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Fix FIFO instances in S10DX example design

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-17 11:05:24 -07:00
parent 2858aaaef7
commit 1be196279f
1 changed files with 4 additions and 4 deletions
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8
example/S10DX_DK/fpga_10g/rtl/fpga_core.v
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@ -498,14 +498,14 @@ axis_async_fifo #(
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(2),
.RAM_PIPELINE(2),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(1)
)
max_rx_fifo (
mac_rx_fifo (
// AXI input
.s_clk(qsfp1_mac_1_rx_clk),
.s_rst(qsfp1_mac_1_rx_rst),
@ -548,14 +548,14 @@ axis_async_fifo #(
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(2),
.RAM_PIPELINE(2),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(0)
)
max_tx_fifo (
mac_tx_fifo (
// AXI input
.s_clk(clk),
.s_rst(rst),