diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
index 0da9f5e23..67893d280 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
@@ -638,8 +638,8 @@ wire [1:0]  axil_cms_rresp_int;
 wire        axil_cms_rvalid_int;
 wire        axil_cms_rready_int;
 
-wire [7:0] hbm_temp_1;
-wire [7:0] hbm_temp_2;
+wire [6:0] hbm_temp_1;
+wire [6:0] hbm_temp_2;
 
 axil_cdc #(
     .DATA_WIDTH(32),
@@ -2958,6 +2958,11 @@ assign m_axi_hbm_rvalid = 0;
 
 assign hbm_status = 0;
 
+assign hbm_cattrip = 1'b0;
+
+assign hbm_temp_1 = 7'd0;
+assign hbm_temp_2 = 7'd0;
+
 end
 
 endgenerate
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
index 0403b86a5..bec48b9a7 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
@@ -645,8 +645,8 @@ wire [1:0]  axil_cms_rresp_int;
 wire        axil_cms_rvalid_int;
 wire        axil_cms_rready_int;
 
-wire [7:0] hbm_temp_1;
-wire [7:0] hbm_temp_2;
+wire [6:0] hbm_temp_1;
+wire [6:0] hbm_temp_2;
 
 axil_cdc #(
     .DATA_WIDTH(32),
@@ -3095,6 +3095,11 @@ assign m_axi_hbm_rvalid = 0;
 
 assign hbm_status = 0;
 
+assign hbm_cattrip = 1'b0;
+
+assign hbm_temp_1 = 7'd0;
+assign hbm_temp_2 = 7'd0;
+
 end
 
 endgenerate
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
index a932e680e..19a5ce281 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
@@ -573,8 +573,8 @@ wire [1:0]  axil_cms_rresp_int;
 wire        axil_cms_rvalid_int;
 wire        axil_cms_rready_int;
 
-wire [7:0] hbm_temp_1;
-wire [7:0] hbm_temp_2;
+wire [6:0] hbm_temp_1;
+wire [6:0] hbm_temp_2;
 
 axil_cdc #(
     .DATA_WIDTH(32),
@@ -2443,6 +2443,11 @@ assign m_axi_hbm_rvalid = 0;
 
 assign hbm_status = 0;
 
+assign hbm_cattrip = 1'b0;
+
+assign hbm_temp_1 = 7'd0;
+assign hbm_temp_2 = 7'd0;
+
 end
 
 endgenerate
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
index 5f4248541..78039533b 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
@@ -583,8 +583,8 @@ wire [1:0]  axil_cms_rresp_int;
 wire        axil_cms_rvalid_int;
 wire        axil_cms_rready_int;
 
-wire [7:0] hbm_temp_1;
-wire [7:0] hbm_temp_2;
+wire [6:0] hbm_temp_1;
+wire [6:0] hbm_temp_2;
 
 axil_cdc #(
     .DATA_WIDTH(32),
@@ -2515,6 +2515,11 @@ assign m_axi_hbm_rvalid = 0;
 
 assign hbm_status = 0;
 
+assign hbm_cattrip = 1'b0;
+
+assign hbm_temp_1 = 7'd0;
+assign hbm_temp_2 = 7'd0;
+
 end
 
 endgenerate