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fpga/mqnic: Fix HBM temp signal width; tie off temp and cattrip signals when HBM is disabled

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-12-17 22:49:38 -08:00
parent bbdb44ce01
commit 1dacc6b1fa
4 changed files with 28 additions and 8 deletions
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9
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
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@ -638,8 +638,8 @@ wire [1:0] axil_cms_rresp_int;
wire axil_cms_rvalid_int; wire axil_cms_rvalid_int;
wire axil_cms_rready_int; wire axil_cms_rready_int;
wire [7:0] hbm_temp_1; wire [6:0] hbm_temp_1;
wire [7:0] hbm_temp_2; wire [6:0] hbm_temp_2;
axil_cdc #( axil_cdc #(
.DATA_WIDTH(32), .DATA_WIDTH(32),
@ -2958,6 +2958,11 @@ assign m_axi_hbm_rvalid = 0;
assign hbm_status = 0; assign hbm_status = 0;
assign hbm_cattrip = 1'b0;
assign hbm_temp_1 = 7'd0;
assign hbm_temp_2 = 7'd0;
end end
endgenerate endgenerate

9
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -645,8 +645,8 @@ wire [1:0] axil_cms_rresp_int;
wire axil_cms_rvalid_int; wire axil_cms_rvalid_int;
wire axil_cms_rready_int; wire axil_cms_rready_int;
wire [7:0] hbm_temp_1; wire [6:0] hbm_temp_1;
wire [7:0] hbm_temp_2; wire [6:0] hbm_temp_2;
axil_cdc #( axil_cdc #(
.DATA_WIDTH(32), .DATA_WIDTH(32),
@ -3095,6 +3095,11 @@ assign m_axi_hbm_rvalid = 0;
assign hbm_status = 0; assign hbm_status = 0;
assign hbm_cattrip = 1'b0;
assign hbm_temp_1 = 7'd0;
assign hbm_temp_2 = 7'd0;
end end
endgenerate endgenerate

9
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -573,8 +573,8 @@ wire [1:0] axil_cms_rresp_int;
wire axil_cms_rvalid_int; wire axil_cms_rvalid_int;
wire axil_cms_rready_int; wire axil_cms_rready_int;
wire [7:0] hbm_temp_1; wire [6:0] hbm_temp_1;
wire [7:0] hbm_temp_2; wire [6:0] hbm_temp_2;
axil_cdc #( axil_cdc #(
.DATA_WIDTH(32), .DATA_WIDTH(32),
@ -2443,6 +2443,11 @@ assign m_axi_hbm_rvalid = 0;
assign hbm_status = 0; assign hbm_status = 0;
assign hbm_cattrip = 1'b0;
assign hbm_temp_1 = 7'd0;
assign hbm_temp_2 = 7'd0;
end end
endgenerate endgenerate

9
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -583,8 +583,8 @@ wire [1:0] axil_cms_rresp_int;
wire axil_cms_rvalid_int; wire axil_cms_rvalid_int;
wire axil_cms_rready_int; wire axil_cms_rready_int;
wire [7:0] hbm_temp_1; wire [6:0] hbm_temp_1;
wire [7:0] hbm_temp_2; wire [6:0] hbm_temp_2;
axil_cdc #( axil_cdc #(
.DATA_WIDTH(32), .DATA_WIDTH(32),
@ -2515,6 +2515,11 @@ assign m_axi_hbm_rvalid = 0;
assign hbm_status = 0; assign hbm_status = 0;
assign hbm_cattrip = 1'b0;
assign hbm_temp_1 = 7'd0;
assign hbm_temp_2 = 7'd0;
end end
endgenerate endgenerate