mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
Add ExaNIC X10 design
This commit is contained in:
Alex Forencich
parent
fcd8b1b8e9
commit
1df012a8d4
25
fpga/mqnic/ExaNIC_X10/fpga/Makefile
Normal file
25
fpga/mqnic/ExaNIC_X10/fpga/Makefile
Normal file
@ -0,0 +1,25 @@
|
||||
# Targets
|
||||
TARGETS:=
|
||||
|
||||
# Subdirectories
|
||||
SUBDIRS = fpga
|
||||
SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
|
||||
|
||||
# Rules
|
||||
.PHONY: all
|
||||
all: $(SUBDIRS) $(TARGETS)
|
||||
|
||||
.PHONY: $(SUBDIRS)
|
||||
$(SUBDIRS):
|
||||
cd $@ && $(MAKE)
|
||||
|
||||
.PHONY: $(SUBDIRS_CLEAN)
|
||||
$(SUBDIRS_CLEAN):
|
||||
cd $(@:.clean=) && $(MAKE) clean
|
||||
|
||||
.PHONY: clean
|
||||
clean: $(SUBDIRS_CLEAN)
|
||||
-rm -rf $(TARGETS)
|
||||
|
||||
program:
|
||||
#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
|
||||
24
fpga/mqnic/ExaNIC_X10/fpga/README.md
Normal file
24
fpga/mqnic/ExaNIC_X10/fpga/README.md
Normal file
@ -0,0 +1,24 @@
|
||||
# Corundum mqnic for ExaNIC X10
|
||||
|
||||
## Introduction
|
||||
|
||||
This design targets the Exablaze ExaNIC X10 FPGA board.
|
||||
|
||||
FPGA: xcku035-fbva676-2-e
|
||||
PHY: 10G BASE-R PHY IP core and internal GTH transceiver
|
||||
|
||||
## How to build
|
||||
|
||||
Run make to build. Ensure that the Xilinx Vivado toolchain components are
|
||||
in PATH.
|
||||
|
||||
Run make to build the driver. Ensure the headers for the running kernel are
|
||||
installed, otherwise the driver cannot be compiled.
|
||||
|
||||
## How to test
|
||||
|
||||
Run make program to program the ExaNIC X10 board with Vivado. Then load the
|
||||
driver with insmod mqnic.ko. Check dmesg for output from driver
|
||||
initialization.
|
||||
|
||||
|
||||
118
fpga/mqnic/ExaNIC_X10/fpga/common/vivado.mk
Normal file
118
fpga/mqnic/ExaNIC_X10/fpga/common/vivado.mk
Normal file
@ -0,0 +1,118 @@
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - space-separated list of source files
|
||||
# INC_FILES - space-separated list of include files
|
||||
# XDC_FILES - space-separated list of timing constraint files
|
||||
# XCI_FILES - space-separated list of IP XCI files
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: clean fpga
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include ../$(CONFIG)
|
||||
|
||||
SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
|
||||
INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
|
||||
XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
|
||||
|
||||
ifdef XDC_FILES
|
||||
XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
|
||||
else
|
||||
XDC_FILES_REL = $(FPGA_TOP).xdc
|
||||
endif
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything
|
||||
# clean: remove output files and project files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(FPGA_TOP).bit
|
||||
|
||||
tmpclean:
|
||||
-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean: tmpclean
|
||||
-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
|
||||
distclean: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
%.xpr: Makefile $(XCI_FILES_REL)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
|
||||
echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
|
||||
for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
|
||||
for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
|
||||
for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
|
||||
echo "exit" >> create_project.tcl
|
||||
vivado -nojournal -nolog -mode batch -source create_project.tcl
|
||||
|
||||
# synthesis run
|
||||
%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
|
||||
echo "open_project $*.xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
echo "exit" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
|
||||
echo "open_project $*.xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "exit" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# bit file
|
||||
%.bit: %.runs/impl_1/%_routed.dcp
|
||||
echo "open_project $*.xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force $*.bit" >> generate_bit.tcl
|
||||
echo "exit" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp $@ rev/$*_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_rev$$COUNT.$$EXT";
|
||||
153
fpga/mqnic/ExaNIC_X10/fpga/fpga.xdc
Normal file
153
fpga/mqnic/ExaNIC_X10/fpga/fpga.xdc
Normal file
@ -0,0 +1,153 @@
|
||||
# XDC constraints for the ExaNIC X10
|
||||
# part: xcku035-fbva676-2-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design]
|
||||
set_property CONFIG_MODE BPI16 [current_design]
|
||||
|
||||
# 100 MHz system clock
|
||||
set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports clk_100mhz_p]
|
||||
set_property -dict {LOC C18 IOSTANDARD LVDS} [get_ports clk_100mhz_n]
|
||||
create_clock -period 10 -name clk_100mhz [get_ports clk_100mhz_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC A25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[1]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[0]}]
|
||||
set_property -dict {LOC D26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[1]}]
|
||||
set_property -dict {LOC C23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
|
||||
set_property -dict {LOC D23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
|
||||
|
||||
# GPIO
|
||||
#set_property -dict {LOC W26 IOSTANDARD LVCMOS18} [get_ports gpio[0]]
|
||||
#set_property -dict {LOC Y26 IOSTANDARD LVCMOS18} [get_ports gpio[1]]
|
||||
#set_property -dict {LOC AB26 IOSTANDARD LVCMOS18} [get_ports gpio[2]]
|
||||
#set_property -dict {LOC AC26 IOSTANDARD LVCMOS18} [get_ports gpio[3]]
|
||||
|
||||
# SMA
|
||||
set_property -dict {LOC B17 IOSTANDARD LVCMOS18} [get_ports sma_in]
|
||||
set_property -dict {LOC B16 IOSTANDARD LVCMOS18} [get_ports sma_out]
|
||||
set_property -dict {LOC B19 IOSTANDARD LVCMOS18} [get_ports sma_out_en]
|
||||
set_property -dict {LOC C16 IOSTANDARD LVCMOS18} [get_ports sma_term_en]
|
||||
|
||||
# SFP+ Interfaces
|
||||
set_property -dict {LOC D2 } [get_ports sfp_1_rx_p] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC D1 } [get_ports sfp_1_rx_n] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||
set_property -dict {LOC E4 } [get_ports sfp_1_tx_p] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC E3 } [get_ports sfp_1_tx_n] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||
set_property -dict {LOC C4 } [get_ports sfp_2_rx_p] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC C3 } [get_ports sfp_2_rx_n] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||
set_property -dict {LOC D6 } [get_ports sfp_2_tx_p] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC D5 } [get_ports sfp_2_tx_n] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||
set_property -dict {LOC H6 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2
|
||||
#set_property -dict {LOC H5 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2
|
||||
set_property -dict {LOC AA12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable]
|
||||
set_property -dict {LOC W14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable]
|
||||
set_property -dict {LOC C24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_npres]
|
||||
set_property -dict {LOC D24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_npres]
|
||||
set_property -dict {LOC W13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los]
|
||||
set_property -dict {LOC AB12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los]
|
||||
set_property -dict {LOC B25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs]
|
||||
set_property -dict {LOC D25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs]
|
||||
set_property -dict {LOC W11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl]
|
||||
set_property -dict {LOC Y11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda]
|
||||
set_property -dict {LOC Y13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
|
||||
|
||||
# I2C interface
|
||||
set_property -dict {LOC B26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
|
||||
set_property -dict {LOC C26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
|
||||
|
||||
# PCIe Interface
|
||||
set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC R4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC R3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC U4 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC U3 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC W4 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC W3 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC AA4 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AA3 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AB6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AB5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AD6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AF6 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF5 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
set_property -dict {LOC T6 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC T5 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
|
||||
set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
|
||||
|
||||
# Flash
|
||||
set_property -dict {LOC AE10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[0]}]
|
||||
set_property -dict {LOC AC8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[1]}]
|
||||
set_property -dict {LOC AD10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[2]}]
|
||||
set_property -dict {LOC AD9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[3]}]
|
||||
set_property -dict {LOC AC11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[4]}]
|
||||
set_property -dict {LOC AF10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[5]}]
|
||||
set_property -dict {LOC AF14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[6]}]
|
||||
set_property -dict {LOC AE12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[7]}]
|
||||
set_property -dict {LOC AD14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[8]}]
|
||||
set_property -dict {LOC AF13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[9]}]
|
||||
set_property -dict {LOC AE13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[10]}]
|
||||
set_property -dict {LOC AD8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[11]}]
|
||||
set_property -dict {LOC AC13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[12]}]
|
||||
set_property -dict {LOC AD13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[13]}]
|
||||
set_property -dict {LOC AA14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[14]}]
|
||||
set_property -dict {LOC AB15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[15]}]
|
||||
set_property -dict {LOC AD11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[0]}]
|
||||
set_property -dict {LOC AE11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[1]}]
|
||||
set_property -dict {LOC AF12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[2]}]
|
||||
set_property -dict {LOC AB11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[3]}]
|
||||
set_property -dict {LOC AB9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[4]}]
|
||||
set_property -dict {LOC AB14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[5]}]
|
||||
set_property -dict {LOC AA10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[6]}]
|
||||
set_property -dict {LOC AA9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[7]}]
|
||||
set_property -dict {LOC W10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[8]}]
|
||||
set_property -dict {LOC AA13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[9]}]
|
||||
set_property -dict {LOC Y15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[10]}]
|
||||
set_property -dict {LOC AC12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[11]}]
|
||||
set_property -dict {LOC V12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[12]}]
|
||||
set_property -dict {LOC V11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[13]}]
|
||||
set_property -dict {LOC Y12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[14]}]
|
||||
set_property -dict {LOC W9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[15]}]
|
||||
set_property -dict {LOC Y8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[16]}]
|
||||
set_property -dict {LOC W8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[17]}]
|
||||
set_property -dict {LOC W15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[18]}]
|
||||
set_property -dict {LOC AA15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[19]}]
|
||||
set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[20]}]
|
||||
set_property -dict {LOC AF15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[21]}]
|
||||
set_property -dict {LOC AE15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[22]}]
|
||||
set_property -dict {LOC AD15 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
|
||||
set_property -dict {LOC AC9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_ce_n}]
|
||||
set_property -dict {LOC AC14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_oe_n}]
|
||||
set_property -dict {LOC AB10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_we_n}]
|
||||
set_property -dict {LOC Y10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_adv_n}]
|
||||
|
||||
136
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
Normal file
136
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
Normal file
@ -0,0 +1,136 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku035-fbva676-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexu
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_reset.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/interface.v
|
||||
SYN_FILES += rtl/common/port.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/eth_interface.v
|
||||
SYN_FILES += rtl/common/event_queue.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axi_dma.v
|
||||
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axi_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axi_ram.v
|
||||
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
|
||||
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
|
||||
SYN_FILES += lib/axi/rtl/axi_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axi_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl
|
||||
|
||||
# IP
|
||||
XCI_FILES = ip/pcie3_ultrascale_0.xci
|
||||
XCI_FILES += ip/gtwizard_ultrascale_0.xci
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {28f256p30t-bpi-x16}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
1406
fpga/mqnic/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.xci
Normal file
1406
fpga/mqnic/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
901
fpga/mqnic/ExaNIC_X10/fpga/ip/pcie3_ultrascale_0.xci
Normal file
901
fpga/mqnic/ExaNIC_X10/fpga/ip/pcie3_ultrascale_0.xci
Normal file
@ -0,0 +1,901 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>pcie3_ultrascale_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_ultrascale" spirit:version="4.4"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.USER_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.USER_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH">85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH">75</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.USER_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH">33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH">60</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ACS_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ACS_EXT_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_PARITY_CHK">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_CLIENT_TAG">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_MSG_ROUTE">0x00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_RX_MSG_INTFC">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_PARITY_CHK">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BMD_PIO_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_CTL_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_EXT_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_MGMT_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_STATUS_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_TX_MSG_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMPLETION_SPACE">16KB</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CORE_CLK_FREQ">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DBG_DESCRAMBLE_EN">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEDICATE_PERST">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEV_PORT_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIS_GT_WIZARD">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_AUTO_RXEQ">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_GT_V1_5">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_IBERT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_JTAG_DBG">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_GT_SELECTION">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_CH_GT_DRP">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_XVC_VSEC_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FREE_RUN_FREQ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GTWIZ_IN_CORE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GT_DRP_CLK_SRC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.INS_LOSS_PROFILE">Add-in_Card</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_ENABLEMENT">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_FPGA_BITSTREAM_VERSION">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSIX_EN">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_EN">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MULT_PF_DES">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE3_DRP">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_CONFIGURATION">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_FAST_CONFIG">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_USE_MODE">2.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PER_FUNC_STATUS_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE">0x11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_CONTROL">0x4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE">0x11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_CONTROL">0x4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CLASS_CODE">0x020000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEVICE_ID">0x1001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_LTR_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0x2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LTR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR">0xC0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PB_CAP_NEXTPTR">0x274</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR">0x90</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_REVISION_ID">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SECONDARY_PCIE_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID">0x1001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">0x1234</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VC_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VENDOR_ID">0x1234</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CLASS_CODE">0x058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEVICE_ID">0x8011</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEV_CAP_MAX_PAYLOAD_SIZE">0x2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_REVISION_ID">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0x0001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PHY_LP_TXPRESET">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_TYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_INTERFACE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_UPSTREAM_FACING">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PM_ENABLE_L23_ENTRY">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RCV_MSG_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RX_DETECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SELECT_QUAD">GTH_Quad_225</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPARE_WORD1">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYS_RESET_POLARITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CD">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CH">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPD">0x028</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPH">0x20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PD">0x198</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PH">0x20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TRANSCEIVER_CTRL_STATUS_PORTS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_FC_IF">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK_FREQ">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.en_msi_per_vec_masking">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y0_xdc">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y1_xdc">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y2_xdc">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y3_xdc">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y4_xdc">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y5_xdc">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_blk_locn">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_revision">Production</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pcie3_ultrascale_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">020000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">1001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">INTA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">32_vectors</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">1001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">1234</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">8011</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHY_LP_TXPRESET">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">8.0_GT/s</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_DETECT">Default</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_PPM_OFFSET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_SSC_PPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.acs_ext_cap_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route_override">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">256_bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bmd_pio_mode">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cc_cq_alignment">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.coreclk_freq">500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dedicate_perst">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dis_gt_wizard">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_gt_loc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_dbg_descramble">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_gt_selection">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_l23_entry">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_parity">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_conf">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pl_ifc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_auto_rxeq">False</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_gt_v1_5">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ibert">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_jtag_dbg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_startup_primitive">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_xvc_vsec_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.free_run_freq">100_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y5">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_drp_clk_src">Internal</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtwiz_in_core">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ins_loss_profile">Add-in_Card</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_enablement">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_fpga_bitstream_version">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Basic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mult_pf_des">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.performance">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Megabytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Megabytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Network_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">02</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Ethernet_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.plltype">QPLL1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rc_rq_alignment">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.select_quad">GTH_Quad_225</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.special_gui">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_reset_polarity">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">1234</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexu</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku035</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbva676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_CLASS_CODE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEVICE_ID" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_DEVICE_ID" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.aspm_support" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.coreclk_freq" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dedicate_perst" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_msi_per_vec_masking" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.extended_tag_field" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gen_x0y0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gen_x0y1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mcap_enablement" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mult_pf_des" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_blk_locn" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_64bit" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_scale" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_size" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_enabled" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_scale" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_size" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_type" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_base_class_menu" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_base" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_interface" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_sub" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_enabled" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_size" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_type" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pipe_sim" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.plltype" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.select_quad" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.vendor_id" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
1
fpga/mqnic/ExaNIC_X10/fpga/lib
Symbolic link
1
fpga/mqnic/ExaNIC_X10/fpga/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
1
fpga/mqnic/ExaNIC_X10/fpga/rtl/common
Symbolic link
1
fpga/mqnic/ExaNIC_X10/fpga/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
89
fpga/mqnic/ExaNIC_X10/fpga/rtl/debounce_switch.v
Normal file
89
fpga/mqnic/ExaNIC_X10/fpga/rtl/debounce_switch.v
Normal file
@ -0,0 +1,89 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes switch and button inputs with a slow sampled shift register
|
||||
*/
|
||||
module debounce_switch #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=3, // length of shift register
|
||||
parameter RATE=125000 // clock division factor
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [23:0] cnt_reg = 24'd0;
|
||||
|
||||
reg [N-1:0] debounce_reg[WIDTH-1:0];
|
||||
|
||||
reg [WIDTH-1:0] state;
|
||||
|
||||
/*
|
||||
* The synchronized output is the state register
|
||||
*/
|
||||
assign out = state;
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
cnt_reg <= 0;
|
||||
state <= 0;
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= 0;
|
||||
end
|
||||
end else begin
|
||||
if (cnt_reg < RATE) begin
|
||||
cnt_reg <= cnt_reg + 24'd1;
|
||||
end else begin
|
||||
cnt_reg <= 24'd0;
|
||||
end
|
||||
|
||||
if (cnt_reg == 24'd0) begin
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
|
||||
end
|
||||
end
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
if (|debounce_reg[k] == 0) begin
|
||||
state[k] <= 0;
|
||||
end else if (&debounce_reg[k] == 1) begin
|
||||
state[k] <= 1;
|
||||
end else begin
|
||||
state[k] <= state[k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
962
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
Normal file
962
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
Normal file
@ -0,0 +1,962 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga (
|
||||
/*
|
||||
* Clock: 100MHz LVDS
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire clk_100mhz_p,
|
||||
input wire clk_100mhz_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire [1:0] sfp_1_led,
|
||||
output wire [1:0] sfp_2_led,
|
||||
output wire [1:0] sma_led,
|
||||
|
||||
input wire sma_in,
|
||||
output wire sma_out,
|
||||
output wire sma_out_en,
|
||||
output wire sma_term_en,
|
||||
|
||||
/*
|
||||
* PCI express
|
||||
*/
|
||||
input wire [7:0] pcie_rx_p,
|
||||
input wire [7:0] pcie_rx_n,
|
||||
output wire [7:0] pcie_tx_p,
|
||||
output wire [7:0] pcie_tx_n,
|
||||
input wire pcie_mgt_refclk_p,
|
||||
input wire pcie_mgt_refclk_n,
|
||||
input wire pcie_reset_n,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
input wire sfp_1_rx_p,
|
||||
input wire sfp_1_rx_n,
|
||||
output wire sfp_1_tx_p,
|
||||
output wire sfp_1_tx_n,
|
||||
input wire sfp_2_rx_p,
|
||||
input wire sfp_2_rx_n,
|
||||
output wire sfp_2_tx_p,
|
||||
output wire sfp_2_tx_n,
|
||||
input wire sfp_mgt_refclk_p,
|
||||
input wire sfp_mgt_refclk_n,
|
||||
output wire sfp_1_tx_disable,
|
||||
output wire sfp_2_tx_disable,
|
||||
input wire sfp_1_npres,
|
||||
input wire sfp_2_npres,
|
||||
input wire sfp_1_los,
|
||||
input wire sfp_2_los,
|
||||
output wire sfp_1_rs,
|
||||
output wire sfp_2_rs,
|
||||
|
||||
inout wire sfp_i2c_scl,
|
||||
inout wire sfp_1_i2c_sda,
|
||||
inout wire sfp_2_i2c_sda,
|
||||
|
||||
inout wire eeprom_i2c_scl,
|
||||
inout wire eeprom_i2c_sda,
|
||||
|
||||
/*
|
||||
* BPI Flash
|
||||
*/
|
||||
inout wire [15:0] flash_dq,
|
||||
output wire [22:0] flash_addr,
|
||||
output wire flash_region,
|
||||
output wire flash_ce_n,
|
||||
output wire flash_oe_n,
|
||||
output wire flash_we_n,
|
||||
output wire flash_adv_n
|
||||
);
|
||||
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 256;
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
wire pcie_user_reset;
|
||||
|
||||
wire clk_100mhz_ibufg;
|
||||
wire clk_125mhz_mmcm_out;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
// Internal 156.25 MHz clock
|
||||
wire clk_156mhz_int;
|
||||
wire rst_156mhz_int;
|
||||
|
||||
wire mmcm_rst = pcie_user_reset;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
clk_100mhz_ibufg_inst (
|
||||
.O (clk_100mhz_ibufg),
|
||||
.I (clk_100mhz_p),
|
||||
.IB (clk_100mhz_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
// 100 MHz in, 125 MHz out
|
||||
// PFD range: 10 MHz to 500 MHz
|
||||
// VCO range: 600 MHz to 1440 MHz
|
||||
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
|
||||
// Divide by 8 to get output frequency of 125 MHz
|
||||
MMCME3_BASE #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKOUT0_DIVIDE_F(8),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
.CLKFBOUT_MULT_F(10),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
.DIVCLK_DIVIDE(1),
|
||||
.REF_JITTER1(0.010),
|
||||
.CLKIN1_PERIOD(10.0),
|
||||
.STARTUP_WAIT("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
.CLKIN1(clk_100mhz_ibufg),
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.RST(mmcm_rst),
|
||||
.PWRDWN(1'b0),
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
.CLKOUT4(),
|
||||
.CLKOUT5(),
|
||||
.CLKOUT6(),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.sync_reset_out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire sfp_i2c_scl_i;
|
||||
wire sfp_i2c_scl_o;
|
||||
wire sfp_i2c_scl_t;
|
||||
wire sfp_1_i2c_sda_i;
|
||||
wire sfp_1_i2c_sda_o;
|
||||
wire sfp_1_i2c_sda_t;
|
||||
wire sfp_2_i2c_sda_i;
|
||||
wire sfp_2_i2c_sda_o;
|
||||
wire sfp_2_i2c_sda_t;
|
||||
wire eeprom_i2c_scl_i;
|
||||
wire eeprom_i2c_scl_o;
|
||||
wire eeprom_i2c_scl_t;
|
||||
wire eeprom_i2c_sda_i;
|
||||
wire eeprom_i2c_sda_o;
|
||||
wire eeprom_i2c_sda_t;
|
||||
|
||||
sync_signal #(
|
||||
.WIDTH(5),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(pcie_user_clk),
|
||||
.in({sfp_i2c_scl, sfp_1_i2c_sda, sfp_2_i2c_sda,
|
||||
eeprom_i2c_scl, eeprom_i2c_sda}),
|
||||
.out({sfp_i2c_scl_i, sfp_1_i2c_sda_i, sfp_2_i2c_sda_i,
|
||||
eeprom_i2c_scl_i, eeprom_i2c_sda_i})
|
||||
);
|
||||
|
||||
assign sfp_i2c_scl = sfp_i2c_scl_t ? 1'bz : sfp_i2c_scl_o;
|
||||
assign sfp_1_i2c_sda = sfp_1_i2c_sda_t ? 1'bz : sfp_1_i2c_sda_o;
|
||||
assign sfp_2_i2c_sda = sfp_2_i2c_sda_t ? 1'bz : sfp_2_i2c_sda_o;
|
||||
assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
|
||||
assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
|
||||
|
||||
// Flash
|
||||
wire [15:0] flash_dq_i_int;
|
||||
wire [15:0] flash_dq_o_int;
|
||||
wire flash_dq_oe_int;
|
||||
wire [22:0] flash_addr_int;
|
||||
wire flash_region_int;
|
||||
wire flash_region_oe_int;
|
||||
wire flash_ce_n_int;
|
||||
wire flash_oe_n_int;
|
||||
wire flash_we_n_int;
|
||||
wire flash_adv_n_int;
|
||||
|
||||
assign flash_dq = flash_dq_oe_int ? flash_dq_o_int : 16'hzzzz;
|
||||
assign flash_addr = flash_addr_int;
|
||||
assign flash_region = flash_region_oe_int ? flash_region_int : 1'bz;
|
||||
assign flash_ce_n = flash_ce_n_int;
|
||||
assign flash_oe_n = flash_oe_n_int;
|
||||
assign flash_we_n = flash_we_n_int;
|
||||
assign flash_adv_n = flash_adv_n_int;
|
||||
|
||||
sync_signal #(
|
||||
.WIDTH(16),
|
||||
.N(2)
|
||||
)
|
||||
flash_sync_signal_inst (
|
||||
.clk(pcie_user_clk),
|
||||
.in(flash_dq),
|
||||
.out(flash_dq_i_int)
|
||||
);
|
||||
|
||||
// PCIe
|
||||
wire pcie_sys_clk;
|
||||
wire pcie_sys_clk_gt;
|
||||
|
||||
IBUFDS_GTE3 #(
|
||||
.REFCLK_HROW_CK_SEL(2'b00)
|
||||
)
|
||||
ibufds_gte3_pcie_mgt_refclk_inst (
|
||||
.I (pcie_mgt_refclk_p),
|
||||
.IB (pcie_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (pcie_sys_clk_gt),
|
||||
.ODIV2 (pcie_sys_clk)
|
||||
);
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
|
||||
wire axis_rq_tlast;
|
||||
wire axis_rq_tready;
|
||||
wire [59:0] axis_rq_tuser;
|
||||
wire axis_rq_tvalid;
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
|
||||
wire axis_rc_tlast;
|
||||
wire axis_rc_tready;
|
||||
wire [74:0] axis_rc_tuser;
|
||||
wire axis_rc_tvalid;
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
|
||||
wire axis_cq_tlast;
|
||||
wire axis_cq_tready;
|
||||
wire [84:0] axis_cq_tuser;
|
||||
wire axis_cq_tvalid;
|
||||
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
|
||||
wire axis_cc_tlast;
|
||||
wire axis_cc_tready;
|
||||
wire [32:0] axis_cc_tuser;
|
||||
wire axis_cc_tvalid;
|
||||
|
||||
wire [1:0] pcie_tfc_nph_av;
|
||||
wire [1:0] pcie_tfc_npd_av;
|
||||
|
||||
wire [2:0] cfg_max_payload;
|
||||
wire [2:0] cfg_max_read_req;
|
||||
|
||||
wire [18:0] cfg_mgmt_addr;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [31:0] cfg_mgmt_read_data;
|
||||
wire cfg_mgmt_read_write_done;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [7:0] cfg_interrupt_msi_vf_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
|
||||
pcie3_ultrascale_0
|
||||
pcie3_ultrascale_inst (
|
||||
.pci_exp_txn(pcie_tx_n),
|
||||
.pci_exp_txp(pcie_tx_p),
|
||||
.pci_exp_rxn(pcie_rx_n),
|
||||
.pci_exp_rxp(pcie_rx_p),
|
||||
.user_clk(pcie_user_clk),
|
||||
.user_reset(pcie_user_reset),
|
||||
.user_lnk_up(),
|
||||
|
||||
.s_axis_rq_tdata(axis_rq_tdata),
|
||||
.s_axis_rq_tkeep(axis_rq_tkeep),
|
||||
.s_axis_rq_tlast(axis_rq_tlast),
|
||||
.s_axis_rq_tready(axis_rq_tready),
|
||||
.s_axis_rq_tuser(axis_rq_tuser),
|
||||
.s_axis_rq_tvalid(axis_rq_tvalid),
|
||||
|
||||
.m_axis_rc_tdata(axis_rc_tdata),
|
||||
.m_axis_rc_tkeep(axis_rc_tkeep),
|
||||
.m_axis_rc_tlast(axis_rc_tlast),
|
||||
.m_axis_rc_tready(axis_rc_tready),
|
||||
.m_axis_rc_tuser(axis_rc_tuser),
|
||||
.m_axis_rc_tvalid(axis_rc_tvalid),
|
||||
|
||||
.m_axis_cq_tdata(axis_cq_tdata),
|
||||
.m_axis_cq_tkeep(axis_cq_tkeep),
|
||||
.m_axis_cq_tlast(axis_cq_tlast),
|
||||
.m_axis_cq_tready(axis_cq_tready),
|
||||
.m_axis_cq_tuser(axis_cq_tuser),
|
||||
.m_axis_cq_tvalid(axis_cq_tvalid),
|
||||
|
||||
.s_axis_cc_tdata(axis_cc_tdata),
|
||||
.s_axis_cc_tkeep(axis_cc_tkeep),
|
||||
.s_axis_cc_tlast(axis_cc_tlast),
|
||||
.s_axis_cc_tready(axis_cc_tready),
|
||||
.s_axis_cc_tuser(axis_cc_tuser),
|
||||
.s_axis_cc_tvalid(axis_cc_tvalid),
|
||||
|
||||
.pcie_rq_seq_num(),
|
||||
.pcie_rq_seq_num_vld(),
|
||||
.pcie_rq_tag(),
|
||||
.pcie_rq_tag_av(),
|
||||
.pcie_rq_tag_vld(),
|
||||
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
|
||||
.pcie_cq_np_req(1'b1),
|
||||
.pcie_cq_np_req_count(),
|
||||
|
||||
.cfg_phy_link_down(),
|
||||
.cfg_phy_link_status(),
|
||||
.cfg_negotiated_width(),
|
||||
.cfg_current_speed(),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_function_status(),
|
||||
.cfg_function_power_state(),
|
||||
.cfg_vf_status(),
|
||||
.cfg_vf_power_state(),
|
||||
.cfg_link_power_state(),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_mgmt_type1_cfg_reg_access(1'b0),
|
||||
|
||||
.cfg_err_cor_out(),
|
||||
.cfg_err_nonfatal_out(),
|
||||
.cfg_err_fatal_out(),
|
||||
.cfg_local_error(),
|
||||
.cfg_ltr_enable(),
|
||||
.cfg_ltssm_state(),
|
||||
.cfg_rcb_status(),
|
||||
.cfg_dpa_substate_change(),
|
||||
.cfg_obff_enable(),
|
||||
.cfg_pl_status_change(),
|
||||
.cfg_tph_requester_enable(),
|
||||
.cfg_tph_st_mode(),
|
||||
.cfg_vf_tph_requester_enable(),
|
||||
.cfg_vf_tph_st_mode(),
|
||||
|
||||
.cfg_msg_received(),
|
||||
.cfg_msg_received_data(),
|
||||
.cfg_msg_received_type(),
|
||||
.cfg_msg_transmit(1'b0),
|
||||
.cfg_msg_transmit_type(3'd0),
|
||||
.cfg_msg_transmit_data(32'd0),
|
||||
.cfg_msg_transmit_done(),
|
||||
|
||||
.cfg_fc_ph(),
|
||||
.cfg_fc_pd(),
|
||||
.cfg_fc_nph(),
|
||||
.cfg_fc_npd(),
|
||||
.cfg_fc_cplh(),
|
||||
.cfg_fc_cpld(),
|
||||
.cfg_fc_sel(3'd0),
|
||||
|
||||
.cfg_per_func_status_control(3'd0),
|
||||
.cfg_per_func_status_data(),
|
||||
.cfg_per_function_number(4'd0),
|
||||
.cfg_per_function_output_request(1'b0),
|
||||
.cfg_per_function_update_done(),
|
||||
|
||||
.cfg_dsn(64'd0),
|
||||
|
||||
.cfg_power_state_change_ack(1'b1),
|
||||
.cfg_power_state_change_interrupt(),
|
||||
|
||||
.cfg_err_cor_in(status_error_cor),
|
||||
.cfg_err_uncor_in(status_error_uncor),
|
||||
.cfg_flr_in_process(),
|
||||
.cfg_flr_done(4'd0),
|
||||
.cfg_vf_flr_in_process(),
|
||||
.cfg_vf_flr_done(8'd0),
|
||||
|
||||
.cfg_link_training_enable(1'b1),
|
||||
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_hot_reset_out(),
|
||||
|
||||
.cfg_config_space_enable(1'b1),
|
||||
.cfg_req_pm_transition_l23_ready(1'b0),
|
||||
.cfg_hot_reset_in(1'b0),
|
||||
|
||||
.cfg_ds_port_number(8'd0),
|
||||
.cfg_ds_bus_number(8'd0),
|
||||
.cfg_ds_device_number(5'd0),
|
||||
.cfg_ds_function_number(3'd0),
|
||||
|
||||
.cfg_subsys_vend_id(16'h1234),
|
||||
|
||||
.sys_clk(pcie_sys_clk),
|
||||
.sys_clk_gt(pcie_sys_clk_gt),
|
||||
.sys_reset(pcie_reset_n),
|
||||
.pcie_perstn1_in(1'b0),
|
||||
.pcie_perstn0_out(),
|
||||
.pcie_perstn1_out(),
|
||||
|
||||
.int_qpll1lock_out(),
|
||||
.int_qpll1outrefclk_out(),
|
||||
.int_qpll1outclk_out(),
|
||||
.phy_rdy_out()
|
||||
);
|
||||
|
||||
// XGMII 10G PHY
|
||||
|
||||
assign sfp_1_tx_disable = 1'b1;
|
||||
assign sfp_2_tx_disable = 1'b1;
|
||||
assign sfp_1_rs = 1'b0;
|
||||
assign sfp_2_rs = 1'b0;
|
||||
|
||||
wire sfp_1_tx_clk_int;
|
||||
wire sfp_1_tx_rst_int;
|
||||
wire [63:0] sfp_1_txd_int;
|
||||
wire [7:0] sfp_1_txc_int;
|
||||
wire sfp_1_rx_clk_int;
|
||||
wire sfp_1_rx_rst_int;
|
||||
wire [63:0] sfp_1_rxd_int;
|
||||
wire [7:0] sfp_1_rxc_int;
|
||||
wire sfp_2_tx_clk_int;
|
||||
wire sfp_2_tx_rst_int;
|
||||
wire [63:0] sfp_2_txd_int;
|
||||
wire [7:0] sfp_2_txc_int;
|
||||
wire sfp_2_rx_clk_int;
|
||||
wire sfp_2_rx_rst_int;
|
||||
wire [63:0] sfp_2_rxd_int;
|
||||
wire [7:0] sfp_2_rxc_int;
|
||||
|
||||
wire sfp_1_rx_block_lock;
|
||||
wire sfp_2_rx_block_lock;
|
||||
|
||||
wire sfp_mgt_refclk;
|
||||
|
||||
wire [1:0] gt_txclkout;
|
||||
wire gt_txusrclk;
|
||||
wire gt_txusrclk2;
|
||||
|
||||
wire [1:0] gt_rxclkout;
|
||||
wire [1:0] gt_rxusrclk;
|
||||
wire [1:0] gt_rxusrclk2;
|
||||
|
||||
wire gt_reset_tx_done;
|
||||
wire gt_reset_rx_done;
|
||||
|
||||
wire [1:0] gt_txprgdivresetdone;
|
||||
wire [1:0] gt_txpmaresetdone;
|
||||
wire [1:0] gt_rxprgdivresetdone;
|
||||
wire [1:0] gt_rxpmaresetdone;
|
||||
|
||||
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
|
||||
wire gt_rx_reset = ~>_rxpmaresetdone;
|
||||
|
||||
reg gt_userclk_tx_active = 1'b0;
|
||||
reg [1:0] gt_userclk_rx_active = 1'b0;
|
||||
|
||||
IBUFDS_GTE3 ibufds_gte3_sfp_mgt_refclk_inst (
|
||||
.I (sfp_mgt_refclk_p),
|
||||
.IB (sfp_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (sfp_mgt_refclk),
|
||||
.ODIV2 ()
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_tx_usrclk_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_tx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_txclkout[0]),
|
||||
.O (gt_txusrclk)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_tx_usrclk2_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_tx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd1),
|
||||
.I (gt_txclkout[0]),
|
||||
.O (gt_txusrclk2)
|
||||
);
|
||||
|
||||
assign clk_156mhz_int = gt_txusrclk2;
|
||||
|
||||
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
|
||||
if (gt_tx_reset) begin
|
||||
gt_userclk_tx_active <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_tx_active <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
|
||||
genvar n;
|
||||
|
||||
for (n = 0 ; n < 2; n = n + 1) begin
|
||||
|
||||
BUFG_GT bufg_gt_rx_usrclk_0_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_rx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_rxclkout[n]),
|
||||
.O (gt_rxusrclk[n])
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_rx_usrclk2_0_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_rx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd1),
|
||||
.I (gt_rxclkout[n]),
|
||||
.O (gt_rxusrclk2[n])
|
||||
);
|
||||
|
||||
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
|
||||
if (gt_rx_reset) begin
|
||||
gt_userclk_rx_active[n] <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_rx_active[n] <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_156mhz_inst (
|
||||
.clk(clk_156mhz_int),
|
||||
.rst(~gt_reset_tx_done),
|
||||
.sync_reset_out(rst_156mhz_int)
|
||||
);
|
||||
|
||||
wire [5:0] sfp_1_gt_txheader;
|
||||
wire [127:0] sfp_1_gt_txdata;
|
||||
wire sfp_1_gt_rxgearboxslip;
|
||||
wire [5:0] sfp_1_gt_rxheader;
|
||||
wire [1:0] sfp_1_gt_rxheadervalid;
|
||||
wire [127:0] sfp_1_gt_rxdata;
|
||||
wire [1:0] sfp_1_gt_rxdatavalid;
|
||||
|
||||
wire [5:0] sfp_2_gt_txheader;
|
||||
wire [127:0] sfp_2_gt_txdata;
|
||||
wire sfp_2_gt_rxgearboxslip;
|
||||
wire [5:0] sfp_2_gt_rxheader;
|
||||
wire [1:0] sfp_2_gt_rxheadervalid;
|
||||
wire [127:0] sfp_2_gt_rxdata;
|
||||
wire [1:0] sfp_2_gt_rxdatavalid;
|
||||
|
||||
gtwizard_ultrascale_0
|
||||
sfp_gth_inst (
|
||||
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
|
||||
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
|
||||
|
||||
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
|
||||
.gtwiz_reset_all_in(rst_125mhz_int),
|
||||
|
||||
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_tx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_rx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_cdr_stable_out(),
|
||||
|
||||
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
||||
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
||||
|
||||
.gtrefclk00_in(sfp_mgt_refclk),
|
||||
|
||||
.qpll0outclk_out(),
|
||||
.qpll0outrefclk_out(),
|
||||
|
||||
.rxpmareset_in(2'd0),
|
||||
|
||||
.gthrxn_in({sfp_2_rx_n, sfp_1_rx_n}),
|
||||
.gthrxp_in({sfp_2_rx_p, sfp_1_rx_p}),
|
||||
|
||||
.rxusrclk_in(gt_rxusrclk),
|
||||
.rxusrclk2_in(gt_rxusrclk2),
|
||||
|
||||
.txdata_in({sfp_2_gt_txdata, sfp_1_gt_txdata}),
|
||||
.txheader_in({sfp_2_gt_txheader, sfp_1_gt_txheader}),
|
||||
.txsequence_in({2{7'b0}}),
|
||||
|
||||
.txusrclk_in({2{gt_txusrclk}}),
|
||||
.txusrclk2_in({2{gt_txusrclk2}}),
|
||||
|
||||
.gtpowergood_out(),
|
||||
|
||||
.gthtxn_out({sfp_2_tx_n, sfp_1_tx_n}),
|
||||
.gthtxp_out({sfp_2_tx_p, sfp_1_tx_p}),
|
||||
|
||||
.txpolarity_in(2'b11),
|
||||
.rxpolarity_in(2'b00),
|
||||
|
||||
.rxgearboxslip_in({sfp_2_gt_rxgearboxslip, sfp_1_gt_rxgearboxslip}),
|
||||
.rxdata_out({sfp_2_gt_rxdata, sfp_1_gt_rxdata}),
|
||||
.rxdatavalid_out({sfp_2_gt_rxdatavalid, sfp_1_gt_rxdatavalid}),
|
||||
.rxheader_out({sfp_2_gt_rxheader, sfp_1_gt_rxheader}),
|
||||
.rxheadervalid_out({sfp_2_gt_rxheadervalid, sfp_1_gt_rxheadervalid}),
|
||||
.rxoutclk_out(gt_rxclkout),
|
||||
.rxpmaresetdone_out(gt_rxpmaresetdone),
|
||||
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
|
||||
.rxstartofseq_out(),
|
||||
|
||||
.txoutclk_out(gt_txclkout),
|
||||
.txpmaresetdone_out(gt_txpmaresetdone),
|
||||
.txprgdivresetdone_out(gt_txprgdivresetdone)
|
||||
);
|
||||
|
||||
assign sfp_1_tx_clk_int = clk_156mhz_int;
|
||||
assign sfp_1_tx_rst_int = rst_156mhz_int;
|
||||
|
||||
assign sfp_1_rx_clk_int = gt_rxusrclk2[0];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sfp_1_rx_rst_reset_sync_inst (
|
||||
.clk(sfp_1_rx_clk_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(sfp_1_rx_rst_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
sfp_1_phy_inst (
|
||||
.tx_clk(sfp_1_tx_clk_int),
|
||||
.tx_rst(sfp_1_tx_rst_int),
|
||||
.rx_clk(sfp_1_rx_clk_int),
|
||||
.rx_rst(sfp_1_rx_rst_int),
|
||||
.xgmii_txd(sfp_1_txd_int),
|
||||
.xgmii_txc(sfp_1_txc_int),
|
||||
.xgmii_rxd(sfp_1_rxd_int),
|
||||
.xgmii_rxc(sfp_1_rxc_int),
|
||||
.serdes_tx_data(sfp_1_gt_txdata),
|
||||
.serdes_tx_hdr(sfp_1_gt_txheader),
|
||||
.serdes_rx_data(sfp_1_gt_rxdata),
|
||||
.serdes_rx_hdr(sfp_1_gt_rxheader),
|
||||
.serdes_rx_bitslip(sfp_1_gt_rxgearboxslip),
|
||||
.rx_block_lock(sfp_1_rx_block_lock),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign sfp_2_tx_clk_int = clk_156mhz_int;
|
||||
assign sfp_2_tx_rst_int = rst_156mhz_int;
|
||||
|
||||
assign sfp_2_rx_clk_int = gt_rxusrclk2[1];
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sfp_2_rx_rst_reset_sync_inst (
|
||||
.clk(sfp_2_rx_clk_int),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(sfp_2_rx_rst_int)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(1)
|
||||
)
|
||||
sfp_2_phy_inst (
|
||||
.tx_clk(sfp_2_tx_clk_int),
|
||||
.tx_rst(sfp_2_tx_rst_int),
|
||||
.rx_clk(sfp_2_rx_clk_int),
|
||||
.rx_rst(sfp_2_rx_rst_int),
|
||||
.xgmii_txd(sfp_2_txd_int),
|
||||
.xgmii_txc(sfp_2_txc_int),
|
||||
.xgmii_rxd(sfp_2_rxd_int),
|
||||
.xgmii_rxc(sfp_2_rxc_int),
|
||||
.serdes_tx_data(sfp_2_gt_txdata),
|
||||
.serdes_tx_hdr(sfp_2_gt_txheader),
|
||||
.serdes_rx_data(sfp_2_gt_rxdata),
|
||||
.serdes_rx_hdr(sfp_2_gt_rxheader),
|
||||
.serdes_rx_bitslip(sfp_2_gt_rxgearboxslip),
|
||||
.rx_block_lock(sfp_2_rx_block_lock),
|
||||
.rx_high_ber()
|
||||
);
|
||||
|
||||
assign sfp_1_led[0] = sfp_1_rx_block_lock;
|
||||
assign sfp_1_led[1] = 1'b0;
|
||||
assign sfp_2_led[0] = sfp_2_rx_block_lock;
|
||||
assign sfp_2_led[1] = 1'b0;
|
||||
|
||||
fpga_core #(
|
||||
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 156.25 MHz, 250 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_156mhz(clk_156mhz_int),
|
||||
.rst_156mhz(rst_156mhz_int),
|
||||
.clk_250mhz(pcie_user_clk),
|
||||
.rst_250mhz(pcie_user_reset),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
//.sfp_1_led(sfp_1_led),
|
||||
//.sfp_2_led(sfp_2_led),
|
||||
.sma_led(sma_led),
|
||||
|
||||
.sma_in(sma_in),
|
||||
.sma_out(sma_out),
|
||||
.sma_out_en(sma_out_en),
|
||||
.sma_term_en(sma_term_en),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
.m_axis_rq_tdata(axis_rq_tdata),
|
||||
.m_axis_rq_tkeep(axis_rq_tkeep),
|
||||
.m_axis_rq_tlast(axis_rq_tlast),
|
||||
.m_axis_rq_tready(axis_rq_tready),
|
||||
.m_axis_rq_tuser(axis_rq_tuser),
|
||||
.m_axis_rq_tvalid(axis_rq_tvalid),
|
||||
|
||||
.s_axis_rc_tdata(axis_rc_tdata),
|
||||
.s_axis_rc_tkeep(axis_rc_tkeep),
|
||||
.s_axis_rc_tlast(axis_rc_tlast),
|
||||
.s_axis_rc_tready(axis_rc_tready),
|
||||
.s_axis_rc_tuser(axis_rc_tuser),
|
||||
.s_axis_rc_tvalid(axis_rc_tvalid),
|
||||
|
||||
.s_axis_cq_tdata(axis_cq_tdata),
|
||||
.s_axis_cq_tkeep(axis_cq_tkeep),
|
||||
.s_axis_cq_tlast(axis_cq_tlast),
|
||||
.s_axis_cq_tready(axis_cq_tready),
|
||||
.s_axis_cq_tuser(axis_cq_tuser),
|
||||
.s_axis_cq_tvalid(axis_cq_tvalid),
|
||||
|
||||
.m_axis_cc_tdata(axis_cc_tdata),
|
||||
.m_axis_cc_tkeep(axis_cc_tkeep),
|
||||
.m_axis_cc_tlast(axis_cc_tlast),
|
||||
.m_axis_cc_tready(axis_cc_tready),
|
||||
.m_axis_cc_tuser(axis_cc_tuser),
|
||||
.m_axis_cc_tvalid(axis_cc_tvalid),
|
||||
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
.status_error_uncor(status_error_uncor),
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
.sfp_1_tx_clk(sfp_1_tx_clk_int),
|
||||
.sfp_1_tx_rst(sfp_1_tx_rst_int),
|
||||
.sfp_1_txd(sfp_1_txd_int),
|
||||
.sfp_1_txc(sfp_1_txc_int),
|
||||
.sfp_1_rx_clk(sfp_1_rx_clk_int),
|
||||
.sfp_1_rx_rst(sfp_1_rx_rst_int),
|
||||
.sfp_1_rxd(sfp_1_rxd_int),
|
||||
.sfp_1_rxc(sfp_1_rxc_int),
|
||||
.sfp_2_tx_clk(sfp_2_tx_clk_int),
|
||||
.sfp_2_tx_rst(sfp_2_tx_rst_int),
|
||||
.sfp_2_txd(sfp_2_txd_int),
|
||||
.sfp_2_txc(sfp_2_txc_int),
|
||||
.sfp_2_rx_clk(sfp_2_rx_clk_int),
|
||||
.sfp_2_rx_rst(sfp_2_rx_rst_int),
|
||||
.sfp_2_rxd(sfp_2_rxd_int),
|
||||
.sfp_2_rxc(sfp_2_rxc_int),
|
||||
|
||||
.sfp_i2c_scl_i(sfp_i2c_scl_i),
|
||||
.sfp_i2c_scl_o(sfp_i2c_scl_o),
|
||||
.sfp_i2c_scl_t(sfp_i2c_scl_t),
|
||||
.sfp_1_i2c_sda_i(sfp_1_i2c_sda_i),
|
||||
.sfp_1_i2c_sda_o(sfp_1_i2c_sda_o),
|
||||
.sfp_1_i2c_sda_t(sfp_1_i2c_sda_t),
|
||||
.sfp_2_i2c_sda_i(sfp_2_i2c_sda_i),
|
||||
.sfp_2_i2c_sda_o(sfp_2_i2c_sda_o),
|
||||
.sfp_2_i2c_sda_t(sfp_2_i2c_sda_t),
|
||||
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_scl_t(eeprom_i2c_scl_t),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
|
||||
|
||||
/*
|
||||
* BPI flash
|
||||
*/
|
||||
.flash_dq_i(flash_dq_i_int),
|
||||
.flash_dq_o(flash_dq_o_int),
|
||||
.flash_dq_oe(flash_dq_oe_int),
|
||||
.flash_addr(flash_addr_int),
|
||||
.flash_region(flash_region_int),
|
||||
.flash_region_oe(flash_region_oe_int),
|
||||
.flash_ce_n(flash_ce_n_int),
|
||||
.flash_oe_n(flash_oe_n_int),
|
||||
.flash_we_n(flash_we_n_int),
|
||||
.flash_adv_n(flash_adv_n_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
2054
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
Normal file
2054
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
52
fpga/mqnic/ExaNIC_X10/fpga/rtl/sync_reset.v
Normal file
52
fpga/mqnic/ExaNIC_X10/fpga/rtl/sync_reset.v
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an active-high asynchronous reset signal to a given clock by
|
||||
* using a pipeline of N registers.
|
||||
*/
|
||||
module sync_reset #(
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
output wire sync_reset_out
|
||||
);
|
||||
|
||||
reg [N-1:0] sync_reg = {N{1'b1}};
|
||||
|
||||
assign sync_reset_out = sync_reg[N-1];
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst)
|
||||
sync_reg <= {N{1'b1}};
|
||||
else
|
||||
sync_reg <= {sync_reg[N-2:0], 1'b0};
|
||||
end
|
||||
|
||||
endmodule
|
||||
58
fpga/mqnic/ExaNIC_X10/fpga/rtl/sync_signal.v
Normal file
58
fpga/mqnic/ExaNIC_X10/fpga/rtl/sync_signal.v
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic/ExaNIC_X10/fpga/tb/axis_ep.py
Symbolic link
1
fpga/mqnic/ExaNIC_X10/fpga/tb/axis_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/axis_ep.py
|
||||
1
fpga/mqnic/ExaNIC_X10/fpga/tb/mqnic.py
Symbolic link
1
fpga/mqnic/ExaNIC_X10/fpga/tb/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/tb/mqnic.py
|
||||
1
fpga/mqnic/ExaNIC_X10/fpga/tb/pcie.py
Symbolic link
1
fpga/mqnic/ExaNIC_X10/fpga/tb/pcie.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie.py
|
||||
1
fpga/mqnic/ExaNIC_X10/fpga/tb/pcie_us.py
Symbolic link
1
fpga/mqnic/ExaNIC_X10/fpga/tb/pcie_us.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie_us.py
|
||||
744
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
Executable file
744
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
Executable file
@ -0,0 +1,744 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
import pcie
|
||||
import pcie_us
|
||||
import xgmii_ep
|
||||
|
||||
import struct
|
||||
|
||||
import mqnic
|
||||
|
||||
module = 'fpga_core'
|
||||
testbench = 'test_%s' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/common/interface.v")
|
||||
srcs.append("../rtl/common/port.v")
|
||||
srcs.append("../rtl/common/queue_manager.v")
|
||||
srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tdma_scheduler.v")
|
||||
srcs.append("../rtl/common/event_queue.v")
|
||||
srcs.append("../rtl/common/event_mux.v")
|
||||
srcs.append("../rtl/common/eth_interface.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/lfsr.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_clock.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_perout.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
|
||||
srcs.append("../lib/axi/rtl/axi_crossbar.v")
|
||||
srcs.append("../lib/axi/rtl/axi_crossbar_addr.v")
|
||||
srcs.append("../lib/axi/rtl/axi_crossbar_rd.v")
|
||||
srcs.append("../lib/axi/rtl/axi_crossbar_wr.v")
|
||||
srcs.append("../lib/axi/rtl/axi_dma.v")
|
||||
srcs.append("../lib/axi/rtl/axi_dma_rd.v")
|
||||
srcs.append("../lib/axi/rtl/axi_dma_wr.v")
|
||||
srcs.append("../lib/axi/rtl/axi_interconnect.v")
|
||||
srcs.append("../lib/axi/rtl/axi_ram.v")
|
||||
srcs.append("../lib/axi/rtl/axi_ram_rd_if.v")
|
||||
srcs.append("../lib/axi/rtl/axi_ram_wr_if.v")
|
||||
srcs.append("../lib/axi/rtl/axi_register_rd.v")
|
||||
srcs.append("../lib/axi/rtl/axi_register_wr.v")
|
||||
srcs.append("../lib/axi/rtl/axil_interconnect.v")
|
||||
srcs.append("../lib/axi/rtl/arbiter.v")
|
||||
srcs.append("../lib/axi/rtl/priority_encoder.v")
|
||||
srcs.append("../lib/axis/rtl/axis_adapter.v")
|
||||
srcs.append("../lib/axis/rtl/axis_arb_mux.v")
|
||||
srcs.append("../lib/axis/rtl/axis_async_fifo.v")
|
||||
srcs.append("../lib/axis/rtl/axis_fifo.v")
|
||||
srcs.append("../lib/axis/rtl/axis_register.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axi_master.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axi_master_rd.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axi_master_wr.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axis_cq_demux.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")
|
||||
srcs.append("../lib/pcie/rtl/pulse_merge.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def frame_checksum(frame):
|
||||
data = frame[14:]
|
||||
|
||||
csum = 0
|
||||
odd = False
|
||||
|
||||
for b in data:
|
||||
if odd:
|
||||
csum += b
|
||||
else:
|
||||
csum += b << 8
|
||||
odd = not odd
|
||||
|
||||
csum = (csum & 0xffff) + (csum >> 16)
|
||||
csum = (csum & 0xffff) + (csum >> 16)
|
||||
|
||||
return csum
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
clk_156mhz = Signal(bool(0))
|
||||
rst_156mhz = Signal(bool(0))
|
||||
clk_250mhz = Signal(bool(0))
|
||||
rst_250mhz = Signal(bool(0))
|
||||
m_axis_rq_tready = Signal(bool(0))
|
||||
s_axis_rc_tdata = Signal(intbv(0)[256:])
|
||||
s_axis_rc_tkeep = Signal(intbv(0)[8:])
|
||||
s_axis_rc_tlast = Signal(bool(0))
|
||||
s_axis_rc_tuser = Signal(intbv(0)[75:])
|
||||
s_axis_rc_tvalid = Signal(bool(0))
|
||||
s_axis_cq_tdata = Signal(intbv(0)[256:])
|
||||
s_axis_cq_tkeep = Signal(intbv(0)[8:])
|
||||
s_axis_cq_tlast = Signal(bool(0))
|
||||
s_axis_cq_tuser = Signal(intbv(0)[85:])
|
||||
s_axis_cq_tvalid = Signal(bool(0))
|
||||
m_axis_cc_tready = Signal(bool(0))
|
||||
pcie_tfc_nph_av = Signal(intbv(0)[2:])
|
||||
pcie_tfc_npd_av = Signal(intbv(0)[2:])
|
||||
cfg_max_payload = Signal(intbv(0)[3:])
|
||||
cfg_max_read_req = Signal(intbv(0)[3:])
|
||||
cfg_mgmt_read_data = Signal(intbv(0)[32:])
|
||||
cfg_mgmt_read_write_done = Signal(bool(0))
|
||||
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
|
||||
cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:])
|
||||
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
|
||||
cfg_interrupt_msi_mask_update = Signal(bool(0))
|
||||
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_sent = Signal(bool(0))
|
||||
cfg_interrupt_msi_fail = Signal(bool(0))
|
||||
sfp_1_tx_clk = Signal(bool(0))
|
||||
sfp_1_tx_rst = Signal(bool(0))
|
||||
sfp_1_rx_clk = Signal(bool(0))
|
||||
sfp_1_rx_rst = Signal(bool(0))
|
||||
sfp_1_rxd = Signal(intbv(0)[64:])
|
||||
sfp_1_rxc = Signal(intbv(0)[8:])
|
||||
sfp_2_tx_clk = Signal(bool(0))
|
||||
sfp_2_tx_rst = Signal(bool(0))
|
||||
sfp_2_rx_clk = Signal(bool(0))
|
||||
sfp_2_rx_rst = Signal(bool(0))
|
||||
sfp_2_rxd = Signal(intbv(0)[64:])
|
||||
sfp_2_rxc = Signal(intbv(0)[8:])
|
||||
sfp_i2c_scl_i = Signal(bool(1))
|
||||
sfp_1_i2c_sda_i = Signal(bool(1))
|
||||
sfp_2_i2c_sda_i = Signal(bool(1))
|
||||
eeprom_i2c_scl_i = Signal(bool(1))
|
||||
eeprom_i2c_sda_i = Signal(bool(1))
|
||||
flash_dq_i = Signal(intbv(0)[16:])
|
||||
|
||||
# Outputs
|
||||
sfp_1_led = Signal(intbv(0)[2:])
|
||||
sfp_2_led = Signal(intbv(0)[2:])
|
||||
sma_led = Signal(intbv(0)[2:])
|
||||
m_axis_rq_tdata = Signal(intbv(0)[256:])
|
||||
m_axis_rq_tkeep = Signal(intbv(0)[8:])
|
||||
m_axis_rq_tlast = Signal(bool(0))
|
||||
m_axis_rq_tuser = Signal(intbv(0)[60:])
|
||||
m_axis_rq_tvalid = Signal(bool(0))
|
||||
s_axis_rc_tready = Signal(bool(0))
|
||||
s_axis_cq_tready = Signal(bool(0))
|
||||
m_axis_cc_tdata = Signal(intbv(0)[256:])
|
||||
m_axis_cc_tkeep = Signal(intbv(0)[8:])
|
||||
m_axis_cc_tlast = Signal(bool(0))
|
||||
m_axis_cc_tuser = Signal(intbv(0)[33:])
|
||||
m_axis_cc_tvalid = Signal(bool(0))
|
||||
status_error_cor = Signal(bool(0))
|
||||
status_error_uncor = Signal(bool(0))
|
||||
cfg_mgmt_addr = Signal(intbv(0)[19:])
|
||||
cfg_mgmt_write = Signal(bool(0))
|
||||
cfg_mgmt_write_data = Signal(intbv(0)[32:])
|
||||
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
|
||||
cfg_mgmt_read = Signal(bool(0))
|
||||
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_select = Signal(intbv(0)[4:])
|
||||
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:])
|
||||
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
|
||||
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
|
||||
cfg_interrupt_msi_tph_present = Signal(bool(0))
|
||||
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
|
||||
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:])
|
||||
cfg_interrupt_msi_function_number = Signal(intbv(0)[4:])
|
||||
sfp_1_txd = Signal(intbv(0)[64:])
|
||||
sfp_1_txc = Signal(intbv(0)[8:])
|
||||
sfp_2_txd = Signal(intbv(0)[64:])
|
||||
sfp_2_txc = Signal(intbv(0)[8:])
|
||||
sfp_i2c_scl_o = Signal(bool(1))
|
||||
sfp_i2c_scl_t = Signal(bool(1))
|
||||
sfp_1_i2c_sda_o = Signal(bool(1))
|
||||
sfp_1_i2c_sda_t = Signal(bool(1))
|
||||
sfp_2_i2c_sda_o = Signal(bool(1))
|
||||
sfp_2_i2c_sda_t = Signal(bool(1))
|
||||
eeprom_i2c_scl_o = Signal(bool(1))
|
||||
eeprom_i2c_scl_t = Signal(bool(1))
|
||||
eeprom_i2c_sda_o = Signal(bool(1))
|
||||
eeprom_i2c_sda_t = Signal(bool(1))
|
||||
flash_dq_o = Signal(intbv(0)[16:])
|
||||
flash_dq_oe = Signal(bool(0))
|
||||
flash_addr = Signal(intbv(0)[23:])
|
||||
flash_region = Signal(bool(0))
|
||||
flash_region_oe = Signal(bool(0))
|
||||
flash_ce_n = Signal(bool(1))
|
||||
flash_oe_n = Signal(bool(1))
|
||||
flash_we_n = Signal(bool(1))
|
||||
flash_adv_n = Signal(bool(1))
|
||||
|
||||
# sources and sinks
|
||||
sfp_1_source = xgmii_ep.XGMIISource()
|
||||
sfp_1_source_logic = sfp_1_source.create_logic(sfp_1_rx_clk, sfp_1_rx_rst, txd=sfp_1_rxd, txc=sfp_1_rxc, name='sfp_1_source')
|
||||
|
||||
sfp_1_sink = xgmii_ep.XGMIISink()
|
||||
sfp_1_sink_logic = sfp_1_sink.create_logic(sfp_1_tx_clk, sfp_1_tx_rst, rxd=sfp_1_txd, rxc=sfp_1_txc, name='sfp_1_sink')
|
||||
|
||||
sfp_2_source = xgmii_ep.XGMIISource()
|
||||
sfp_2_source_logic = sfp_2_source.create_logic(sfp_2_rx_clk, sfp_2_rx_rst, txd=sfp_2_rxd, txc=sfp_2_rxc, name='sfp_2_source')
|
||||
|
||||
sfp_2_sink = xgmii_ep.XGMIISink()
|
||||
sfp_2_sink_logic = sfp_2_sink.create_logic(sfp_2_tx_clk, sfp_2_tx_rst, rxd=sfp_2_txd, rxc=sfp_2_txc, name='sfp_2_sink')
|
||||
|
||||
# Clock and Reset Interface
|
||||
user_clk=Signal(bool(0))
|
||||
user_reset=Signal(bool(0))
|
||||
sys_clk=Signal(bool(0))
|
||||
sys_reset=Signal(bool(0))
|
||||
|
||||
# PCIe devices
|
||||
rc = pcie.RootComplex()
|
||||
|
||||
rc.max_payload_size = 0x1 # 256 bytes
|
||||
rc.max_read_request_size = 0x5 # 4096 bytes
|
||||
|
||||
driver = mqnic.Driver(rc)
|
||||
|
||||
dev = pcie_us.UltrascalePCIe()
|
||||
|
||||
dev.pcie_generation = 3
|
||||
dev.pcie_link_width = 8
|
||||
dev.user_clock_frequency = 256e6
|
||||
|
||||
dev.functions[0].msi_multiple_message_capable = 5
|
||||
|
||||
dev.functions[0].configure_bar(0, 16*1024*1024)
|
||||
dev.functions[0].configure_bar(1, 16*1024*1024)
|
||||
|
||||
rc.make_port().connect(dev)
|
||||
|
||||
pcie_logic = dev.create_logic(
|
||||
# Completer reQuest Interface
|
||||
m_axis_cq_tdata=s_axis_cq_tdata,
|
||||
m_axis_cq_tuser=s_axis_cq_tuser,
|
||||
m_axis_cq_tlast=s_axis_cq_tlast,
|
||||
m_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||
m_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||
m_axis_cq_tready=s_axis_cq_tready,
|
||||
#pcie_cq_np_req=pcie_cq_np_req,
|
||||
pcie_cq_np_req=Signal(bool(1)),
|
||||
#pcie_cq_np_req_count=pcie_cq_np_req_count,
|
||||
|
||||
# Completer Completion Interface
|
||||
s_axis_cc_tdata=m_axis_cc_tdata,
|
||||
s_axis_cc_tuser=m_axis_cc_tuser,
|
||||
s_axis_cc_tlast=m_axis_cc_tlast,
|
||||
s_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||
s_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||
s_axis_cc_tready=m_axis_cc_tready,
|
||||
|
||||
# Requester reQuest Interface
|
||||
s_axis_rq_tdata=m_axis_rq_tdata,
|
||||
s_axis_rq_tuser=m_axis_rq_tuser,
|
||||
s_axis_rq_tlast=m_axis_rq_tlast,
|
||||
s_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||
s_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||
s_axis_rq_tready=m_axis_rq_tready,
|
||||
#pcie_rq_seq_num=pcie_rq_seq_num,
|
||||
#pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
|
||||
#pcie_rq_tag=pcie_rq_tag,
|
||||
#pcie_rq_tag_vld=pcie_rq_tag_vld,
|
||||
|
||||
# Requester Completion Interface
|
||||
m_axis_rc_tdata=s_axis_rc_tdata,
|
||||
m_axis_rc_tuser=s_axis_rc_tuser,
|
||||
m_axis_rc_tlast=s_axis_rc_tlast,
|
||||
m_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||
m_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||
m_axis_rc_tready=s_axis_rc_tready,
|
||||
|
||||
# Transmit Flow Control Interface
|
||||
pcie_tfc_nph_av=pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av=pcie_tfc_npd_av,
|
||||
|
||||
# Configuration Management Interface
|
||||
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||
cfg_mgmt_write=cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||
#cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access,
|
||||
|
||||
# Configuration Status Interface
|
||||
#cfg_phy_link_down=cfg_phy_link_down,
|
||||
#cfg_phy_link_status=cfg_phy_link_status,
|
||||
#cfg_negotiated_width=cfg_negotiated_width,
|
||||
#cfg_current_speed=cfg_current_speed,
|
||||
cfg_max_payload=cfg_max_payload,
|
||||
cfg_max_read_req=cfg_max_read_req,
|
||||
#cfg_function_status=cfg_function_status,
|
||||
#cfg_vf_status=cfg_vf_status,
|
||||
#cfg_function_power_state=cfg_function_power_state,
|
||||
#cfg_vf_power_state=cfg_vf_power_state,
|
||||
#cfg_link_power_state=cfg_link_power_state,
|
||||
#cfg_err_cor_out=cfg_err_cor_out,
|
||||
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
|
||||
#cfg_err_fatal_out=cfg_err_fatal_out,
|
||||
#cfg_ltr_enable=cfg_ltr_enable,
|
||||
#cfg_ltssm_state=cfg_ltssm_state,
|
||||
#cfg_rcb_status=cfg_rcb_status,
|
||||
#cfg_dpa_substate_change=cfg_dpa_substate_change,
|
||||
#cfg_obff_enable=cfg_obff_enable,
|
||||
#cfg_pl_status_change=cfg_pl_status_change,
|
||||
#cfg_tph_requester_enable=cfg_tph_requester_enable,
|
||||
#cfg_tph_st_mode=cfg_tph_st_mode,
|
||||
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
|
||||
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
|
||||
|
||||
# Configuration Received Message Interface
|
||||
#cfg_msg_received=cfg_msg_received,
|
||||
#cfg_msg_received_data=cfg_msg_received_data,
|
||||
#cfg_msg_received_type=cfg_msg_received_type,
|
||||
|
||||
# Configuration Transmit Message Interface
|
||||
#cfg_msg_transmit=cfg_msg_transmit,
|
||||
#cfg_msg_transmit_type=cfg_msg_transmit_type,
|
||||
#cfg_msg_transmit_data=cfg_msg_transmit_data,
|
||||
#cfg_msg_transmit_done=cfg_msg_transmit_done,
|
||||
|
||||
# Configuration Flow Control Interface
|
||||
#cfg_fc_ph=cfg_fc_ph,
|
||||
#cfg_fc_pd=cfg_fc_pd,
|
||||
#cfg_fc_nph=cfg_fc_nph,
|
||||
#cfg_fc_npd=cfg_fc_npd,
|
||||
#cfg_fc_cplh=cfg_fc_cplh,
|
||||
#cfg_fc_cpld=cfg_fc_cpld,
|
||||
#cfg_fc_sel=cfg_fc_sel,
|
||||
|
||||
# Per-Function Status Interface
|
||||
#cfg_per_func_status_control=cfg_per_func_status_control,
|
||||
#cfg_per_func_status_data=cfg_per_func_status_data,
|
||||
|
||||
# Configuration Control Interface
|
||||
#cfg_hot_reset_in=cfg_hot_reset_in,
|
||||
#cfg_hot_reset_out=cfg_hot_reset_out,
|
||||
#cfg_config_space_enable=cfg_config_space_enable,
|
||||
#cfg_per_function_update_done=cfg_per_function_update_done,
|
||||
#cfg_per_function_number=cfg_per_function_number,
|
||||
#cfg_per_function_output_request=cfg_per_function_output_request,
|
||||
#cfg_dsn=cfg_dsn,
|
||||
#cfg_ds_bus_number=cfg_ds_bus_number,
|
||||
#cfg_ds_device_number=cfg_ds_device_number,
|
||||
#cfg_ds_function_number=cfg_ds_function_number,
|
||||
#cfg_power_state_change_ack=cfg_power_state_change_ack,
|
||||
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
|
||||
cfg_err_cor_in=status_error_cor,
|
||||
cfg_err_uncor_in=status_error_uncor,
|
||||
#cfg_flr_done=cfg_flr_done,
|
||||
#cfg_vf_flr_done=cfg_vf_flr_done,
|
||||
#cfg_flr_in_process=cfg_flr_in_process,
|
||||
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
|
||||
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
|
||||
#cfg_link_training_enable=cfg_link_training_enable,
|
||||
|
||||
# Configuration Interrupt Controller Interface
|
||||
#cfg_interrupt_int=cfg_interrupt_int,
|
||||
#cfg_interrupt_sent=cfg_interrupt_sent,
|
||||
#cfg_interrupt_pending=cfg_interrupt_pending,
|
||||
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
|
||||
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
|
||||
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
|
||||
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
|
||||
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
|
||||
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
|
||||
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
|
||||
#cfg_interrupt_msix_sent=cfg_interrupt_msix_sent,
|
||||
#cfg_interrupt_msix_fail=cfg_interrupt_msix_fail,
|
||||
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
#cfg_ext_read_received=cfg_ext_read_received,
|
||||
#cfg_ext_write_received=cfg_ext_write_received,
|
||||
#cfg_ext_register_number=cfg_ext_register_number,
|
||||
#cfg_ext_function_number=cfg_ext_function_number,
|
||||
#cfg_ext_write_data=cfg_ext_write_data,
|
||||
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
|
||||
#cfg_ext_read_data=cfg_ext_read_data,
|
||||
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
|
||||
|
||||
# Clock and Reset Interface
|
||||
user_clk=user_clk,
|
||||
user_reset=user_reset,
|
||||
sys_clk=sys_clk,
|
||||
sys_clk_gt=sys_clk,
|
||||
sys_reset=sys_reset,
|
||||
#pcie_perstn0_out=pcie_perstn0_out,
|
||||
#pcie_perstn1_in=pcie_perstn1_in,
|
||||
#pcie_perstn1_out=pcie_perstn1_out
|
||||
)
|
||||
|
||||
# DUT
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
|
||||
dut = Cosimulation(
|
||||
"vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
clk_156mhz=clk_156mhz,
|
||||
rst_156mhz=rst_156mhz,
|
||||
clk_250mhz=user_clk,
|
||||
rst_250mhz=user_reset,
|
||||
sfp_1_led=sfp_1_led,
|
||||
sfp_2_led=sfp_2_led,
|
||||
sma_led=sma_led,
|
||||
m_axis_rq_tdata=m_axis_rq_tdata,
|
||||
m_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||
m_axis_rq_tlast=m_axis_rq_tlast,
|
||||
m_axis_rq_tready=m_axis_rq_tready,
|
||||
m_axis_rq_tuser=m_axis_rq_tuser,
|
||||
m_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||
s_axis_rc_tdata=s_axis_rc_tdata,
|
||||
s_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||
s_axis_rc_tlast=s_axis_rc_tlast,
|
||||
s_axis_rc_tready=s_axis_rc_tready,
|
||||
s_axis_rc_tuser=s_axis_rc_tuser,
|
||||
s_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||
s_axis_cq_tdata=s_axis_cq_tdata,
|
||||
s_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||
s_axis_cq_tlast=s_axis_cq_tlast,
|
||||
s_axis_cq_tready=s_axis_cq_tready,
|
||||
s_axis_cq_tuser=s_axis_cq_tuser,
|
||||
s_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||
m_axis_cc_tdata=m_axis_cc_tdata,
|
||||
m_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||
m_axis_cc_tlast=m_axis_cc_tlast,
|
||||
m_axis_cc_tready=m_axis_cc_tready,
|
||||
m_axis_cc_tuser=m_axis_cc_tuser,
|
||||
m_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||
pcie_tfc_nph_av=pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av=pcie_tfc_npd_av,
|
||||
cfg_max_payload=cfg_max_payload,
|
||||
cfg_max_read_req=cfg_max_read_req,
|
||||
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||
cfg_mgmt_write=cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||
status_error_cor=status_error_cor,
|
||||
status_error_uncor=status_error_uncor,
|
||||
sfp_1_tx_clk=sfp_1_tx_clk,
|
||||
sfp_1_tx_rst=sfp_1_tx_rst,
|
||||
sfp_1_txd=sfp_1_txd,
|
||||
sfp_1_txc=sfp_1_txc,
|
||||
sfp_1_rx_clk=sfp_1_rx_clk,
|
||||
sfp_1_rx_rst=sfp_1_rx_rst,
|
||||
sfp_1_rxd=sfp_1_rxd,
|
||||
sfp_1_rxc=sfp_1_rxc,
|
||||
sfp_2_tx_clk=sfp_2_tx_clk,
|
||||
sfp_2_tx_rst=sfp_2_tx_rst,
|
||||
sfp_2_txd=sfp_2_txd,
|
||||
sfp_2_txc=sfp_2_txc,
|
||||
sfp_2_rx_clk=sfp_2_rx_clk,
|
||||
sfp_2_rx_rst=sfp_2_rx_rst,
|
||||
sfp_2_rxd=sfp_2_rxd,
|
||||
sfp_2_rxc=sfp_2_rxc,
|
||||
sfp_i2c_scl_i=sfp_i2c_scl_i,
|
||||
sfp_i2c_scl_o=sfp_i2c_scl_o,
|
||||
sfp_i2c_scl_t=sfp_i2c_scl_t,
|
||||
sfp_1_i2c_sda_i=sfp_1_i2c_sda_i,
|
||||
sfp_1_i2c_sda_o=sfp_1_i2c_sda_o,
|
||||
sfp_1_i2c_sda_t=sfp_1_i2c_sda_t,
|
||||
sfp_2_i2c_sda_i=sfp_2_i2c_sda_i,
|
||||
sfp_2_i2c_sda_o=sfp_2_i2c_sda_o,
|
||||
sfp_2_i2c_sda_t=sfp_2_i2c_sda_t,
|
||||
eeprom_i2c_scl_i=eeprom_i2c_scl_i,
|
||||
eeprom_i2c_scl_o=eeprom_i2c_scl_o,
|
||||
eeprom_i2c_scl_t=eeprom_i2c_scl_t,
|
||||
eeprom_i2c_sda_i=eeprom_i2c_sda_i,
|
||||
eeprom_i2c_sda_o=eeprom_i2c_sda_o,
|
||||
eeprom_i2c_sda_t=eeprom_i2c_sda_t,
|
||||
flash_dq_i=flash_dq_i,
|
||||
flash_dq_o=flash_dq_o,
|
||||
flash_dq_oe=flash_dq_oe,
|
||||
flash_addr=flash_addr,
|
||||
flash_region=flash_region,
|
||||
flash_region_oe=flash_region_oe,
|
||||
flash_ce_n=flash_ce_n,
|
||||
flash_oe_n=flash_oe_n,
|
||||
flash_we_n=flash_we_n,
|
||||
flash_adv_n=flash_adv_n
|
||||
)
|
||||
|
||||
@always(delay(5))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
@always_comb
|
||||
def clk_logic():
|
||||
sys_clk.next = clk
|
||||
sys_reset.next = not rst
|
||||
|
||||
sfp_1_tx_clk.next = clk
|
||||
sfp_1_tx_rst.next = rst
|
||||
sfp_1_rx_clk.next = clk
|
||||
sfp_1_rx_rst.next = rst
|
||||
sfp_2_tx_clk.next = clk
|
||||
sfp_2_tx_rst.next = rst
|
||||
sfp_2_rx_clk.next = clk
|
||||
sfp_2_rx_rst.next = rst
|
||||
|
||||
msi_0_sig = Signal(bool(0))
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
current_tag = 1
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: enumeration")
|
||||
current_test.next = 1
|
||||
|
||||
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
|
||||
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
|
||||
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
|
||||
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x270, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x274, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x278, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x27C, 0);
|
||||
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x290, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x294, 1000);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x298, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x29C, 0);
|
||||
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x280, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x284, 2000);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x288, 0);
|
||||
yield from rc.mem_write_dword(dev_pf0_bar0+0x28C, 0);
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: init NIC")
|
||||
current_test.next = 2
|
||||
|
||||
yield from driver.init_dev(dev.functions[0].get_id())
|
||||
yield from driver.interfaces[0].open()
|
||||
|
||||
# enable queues
|
||||
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
|
||||
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
|
||||
|
||||
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: send and receive a packet")
|
||||
current_test.next = 3
|
||||
|
||||
data = bytearray([x%256 for x in range(1024)])
|
||||
|
||||
yield from driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
yield sfp_1_sink.wait()
|
||||
|
||||
pkt = sfp_1_sink.recv()
|
||||
print(pkt)
|
||||
|
||||
sfp_1_source.send(pkt)
|
||||
|
||||
yield driver.interfaces[0].wait()
|
||||
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: multiple small packets")
|
||||
current_test.next = 4
|
||||
|
||||
data = bytearray([x%256 for x in range(64)])
|
||||
|
||||
for k in range(32):
|
||||
yield from driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
for k in range(32):
|
||||
yield sfp_1_sink.wait()
|
||||
|
||||
pkt = sfp_1_sink.recv()
|
||||
print(pkt)
|
||||
|
||||
sfp_1_source.send(pkt)
|
||||
|
||||
for k in range(32):
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
if not pkt:
|
||||
yield driver.interfaces[0].wait()
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
assert pkt.data == data
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: multiple large packets")
|
||||
current_test.next = 5
|
||||
|
||||
data = bytearray([x%256 for x in range(1514)])
|
||||
|
||||
for k in range(16):
|
||||
yield from driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
for k in range(16):
|
||||
yield sfp_1_sink.wait()
|
||||
|
||||
pkt = sfp_1_sink.recv()
|
||||
print(pkt)
|
||||
|
||||
sfp_1_source.send(pkt)
|
||||
|
||||
for k in range(16):
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
if not pkt:
|
||||
yield driver.interfaces[0].wait()
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
assert pkt.data == data
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return instances()
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
376
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v
Normal file
376
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v
Normal file
@ -0,0 +1,376 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for fpga_core
|
||||
*/
|
||||
module test_fpga_core;
|
||||
|
||||
// Parameters
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg clk_156mhz = 0;
|
||||
reg rst_156mhz = 0;
|
||||
reg clk_250mhz = 0;
|
||||
reg rst_250mhz = 0;
|
||||
reg m_axis_rq_tready = 0;
|
||||
reg [255:0] s_axis_rc_tdata = 0;
|
||||
reg [7:0] s_axis_rc_tkeep = 0;
|
||||
reg s_axis_rc_tlast = 0;
|
||||
reg [74:0] s_axis_rc_tuser = 0;
|
||||
reg s_axis_rc_tvalid = 0;
|
||||
reg [255:0] s_axis_cq_tdata = 0;
|
||||
reg [7:0] s_axis_cq_tkeep = 0;
|
||||
reg s_axis_cq_tlast = 0;
|
||||
reg [84:0] s_axis_cq_tuser = 0;
|
||||
reg s_axis_cq_tvalid = 0;
|
||||
reg m_axis_cc_tready = 0;
|
||||
reg [1:0] pcie_tfc_nph_av = 0;
|
||||
reg [1:0] pcie_tfc_npd_av = 0;
|
||||
reg [2:0] cfg_max_payload = 0;
|
||||
reg [2:0] cfg_max_read_req = 0;
|
||||
reg [31:0] cfg_mgmt_read_data = 0;
|
||||
reg cfg_mgmt_read_write_done = 0;
|
||||
reg [3:0] cfg_interrupt_msi_enable = 0;
|
||||
reg [7:0] cfg_interrupt_msi_vf_enable = 0;
|
||||
reg [11:0] cfg_interrupt_msi_mmenable = 0;
|
||||
reg cfg_interrupt_msi_mask_update = 0;
|
||||
reg [31:0] cfg_interrupt_msi_data = 0;
|
||||
reg cfg_interrupt_msi_sent = 0;
|
||||
reg cfg_interrupt_msi_fail = 0;
|
||||
reg sfp_1_tx_clk = 0;
|
||||
reg sfp_1_tx_rst = 0;
|
||||
reg sfp_1_rx_clk = 0;
|
||||
reg sfp_1_rx_rst = 0;
|
||||
reg [63:0] sfp_1_rxd = 0;
|
||||
reg [7:0] sfp_1_rxc = 0;
|
||||
reg sfp_2_tx_clk = 0;
|
||||
reg sfp_2_tx_rst = 0;
|
||||
reg sfp_2_rx_clk = 0;
|
||||
reg sfp_2_rx_rst = 0;
|
||||
reg [63:0] sfp_2_rxd = 0;
|
||||
reg [7:0] sfp_2_rxc = 0;
|
||||
reg sfp_i2c_scl_i = 1;
|
||||
reg sfp_1_i2c_sda_i = 1;
|
||||
reg sfp_2_i2c_sda_i = 1;
|
||||
reg eeprom_i2c_scl_i = 1;
|
||||
reg eeprom_i2c_sda_i = 1;
|
||||
reg [15:0] flash_dq_i = 0;
|
||||
|
||||
// Outputs
|
||||
wire [1:0] sfp_1_led;
|
||||
wire [1:0] sfp_2_led;
|
||||
wire [1:0] sma_led;
|
||||
wire [255:0] m_axis_rq_tdata;
|
||||
wire [7:0] m_axis_rq_tkeep;
|
||||
wire m_axis_rq_tlast;
|
||||
wire [59:0] m_axis_rq_tuser;
|
||||
wire m_axis_rq_tvalid;
|
||||
wire s_axis_rc_tready;
|
||||
wire s_axis_cq_tready;
|
||||
wire [255:0] m_axis_cc_tdata;
|
||||
wire [7:0] m_axis_cc_tkeep;
|
||||
wire m_axis_cc_tlast;
|
||||
wire [32:0] m_axis_cc_tuser;
|
||||
wire m_axis_cc_tvalid;
|
||||
wire [18:0] cfg_mgmt_addr;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
wire [63:0] sfp_1_txd;
|
||||
wire [7:0] sfp_1_txc;
|
||||
wire [63:0] sfp_2_txd;
|
||||
wire [7:0] sfp_2_txc;
|
||||
wire sfp_i2c_scl_o;
|
||||
wire sfp_i2c_scl_t;
|
||||
wire sfp_1_i2c_sda_o;
|
||||
wire sfp_1_i2c_sda_t;
|
||||
wire sfp_2_i2c_sda_o;
|
||||
wire sfp_2_i2c_sda_t;
|
||||
wire eeprom_i2c_scl_o;
|
||||
wire eeprom_i2c_scl_t;
|
||||
wire eeprom_i2c_sda_o;
|
||||
wire eeprom_i2c_sda_t;
|
||||
wire [15:0] flash_dq_o;
|
||||
wire flash_dq_oe;
|
||||
wire [22:0] flash_addr;
|
||||
wire flash_region;
|
||||
wire flash_region_oe;
|
||||
wire flash_ce_n;
|
||||
wire flash_oe_n;
|
||||
wire flash_we_n;
|
||||
wire flash_adv_n;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(
|
||||
clk_156mhz,
|
||||
rst_156mhz,
|
||||
clk_250mhz,
|
||||
rst_250mhz,
|
||||
current_test,
|
||||
m_axis_rq_tready,
|
||||
s_axis_rc_tdata,
|
||||
s_axis_rc_tkeep,
|
||||
s_axis_rc_tlast,
|
||||
s_axis_rc_tuser,
|
||||
s_axis_rc_tvalid,
|
||||
s_axis_cq_tdata,
|
||||
s_axis_cq_tkeep,
|
||||
s_axis_cq_tlast,
|
||||
s_axis_cq_tuser,
|
||||
s_axis_cq_tvalid,
|
||||
m_axis_cc_tready,
|
||||
pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av,
|
||||
cfg_max_payload,
|
||||
cfg_max_read_req,
|
||||
cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done,
|
||||
cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail,
|
||||
sfp_1_tx_clk,
|
||||
sfp_1_tx_rst,
|
||||
sfp_1_rx_clk,
|
||||
sfp_1_rx_rst,
|
||||
sfp_1_rxd,
|
||||
sfp_1_rxc,
|
||||
sfp_2_tx_clk,
|
||||
sfp_2_tx_rst,
|
||||
sfp_2_rx_clk,
|
||||
sfp_2_rx_rst,
|
||||
sfp_2_rxd,
|
||||
sfp_2_rxc,
|
||||
sfp_i2c_scl_i,
|
||||
sfp_1_i2c_sda_i,
|
||||
sfp_2_i2c_sda_i,
|
||||
eeprom_i2c_scl_i,
|
||||
eeprom_i2c_sda_i,
|
||||
flash_dq_i
|
||||
);
|
||||
$to_myhdl(
|
||||
sfp_1_led,
|
||||
sfp_2_led,
|
||||
sma_led,
|
||||
m_axis_rq_tdata,
|
||||
m_axis_rq_tkeep,
|
||||
m_axis_rq_tlast,
|
||||
m_axis_rq_tuser,
|
||||
m_axis_rq_tvalid,
|
||||
s_axis_rc_tready,
|
||||
s_axis_cq_tready,
|
||||
m_axis_cc_tdata,
|
||||
m_axis_cc_tkeep,
|
||||
m_axis_cc_tlast,
|
||||
m_axis_cc_tuser,
|
||||
m_axis_cc_tvalid,
|
||||
cfg_mgmt_addr,
|
||||
cfg_mgmt_write,
|
||||
cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read,
|
||||
cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number,
|
||||
status_error_cor,
|
||||
status_error_uncor,
|
||||
sfp_1_txd,
|
||||
sfp_1_txc,
|
||||
sfp_2_txd,
|
||||
sfp_2_txc,
|
||||
sfp_i2c_scl_o,
|
||||
sfp_i2c_scl_t,
|
||||
sfp_1_i2c_sda_o,
|
||||
sfp_1_i2c_sda_t,
|
||||
sfp_2_i2c_sda_o,
|
||||
sfp_2_i2c_sda_t,
|
||||
eeprom_i2c_scl_o,
|
||||
eeprom_i2c_scl_t,
|
||||
eeprom_i2c_sda_o,
|
||||
eeprom_i2c_sda_t,
|
||||
flash_dq_o,
|
||||
flash_dq_oe,
|
||||
flash_addr,
|
||||
flash_region,
|
||||
flash_region_oe,
|
||||
flash_ce_n,
|
||||
flash_oe_n,
|
||||
flash_we_n,
|
||||
flash_adv_n
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_fpga_core.lxt");
|
||||
$dumpvars(0, test_fpga_core);
|
||||
end
|
||||
|
||||
fpga_core
|
||||
UUT (
|
||||
.clk_156mhz(clk_156mhz),
|
||||
.rst_156mhz(rst_156mhz),
|
||||
.clk_250mhz(clk_250mhz),
|
||||
.rst_250mhz(rst_250mhz),
|
||||
.sfp_1_led(sfp_1_led),
|
||||
.sfp_2_led(sfp_2_led),
|
||||
.sma_led(sma_led),
|
||||
.m_axis_rq_tdata(m_axis_rq_tdata),
|
||||
.m_axis_rq_tkeep(m_axis_rq_tkeep),
|
||||
.m_axis_rq_tlast(m_axis_rq_tlast),
|
||||
.m_axis_rq_tready(m_axis_rq_tready),
|
||||
.m_axis_rq_tuser(m_axis_rq_tuser),
|
||||
.m_axis_rq_tvalid(m_axis_rq_tvalid),
|
||||
.s_axis_rc_tdata(s_axis_rc_tdata),
|
||||
.s_axis_rc_tkeep(s_axis_rc_tkeep),
|
||||
.s_axis_rc_tlast(s_axis_rc_tlast),
|
||||
.s_axis_rc_tready(s_axis_rc_tready),
|
||||
.s_axis_rc_tuser(s_axis_rc_tuser),
|
||||
.s_axis_rc_tvalid(s_axis_rc_tvalid),
|
||||
.s_axis_cq_tdata(s_axis_cq_tdata),
|
||||
.s_axis_cq_tkeep(s_axis_cq_tkeep),
|
||||
.s_axis_cq_tlast(s_axis_cq_tlast),
|
||||
.s_axis_cq_tready(s_axis_cq_tready),
|
||||
.s_axis_cq_tuser(s_axis_cq_tuser),
|
||||
.s_axis_cq_tvalid(s_axis_cq_tvalid),
|
||||
.m_axis_cc_tdata(m_axis_cc_tdata),
|
||||
.m_axis_cc_tkeep(m_axis_cc_tkeep),
|
||||
.m_axis_cc_tlast(m_axis_cc_tlast),
|
||||
.m_axis_cc_tready(m_axis_cc_tready),
|
||||
.m_axis_cc_tuser(m_axis_cc_tuser),
|
||||
.m_axis_cc_tvalid(m_axis_cc_tvalid),
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
.status_error_cor(status_error_cor),
|
||||
.status_error_uncor(status_error_uncor),
|
||||
.sfp_1_tx_clk(sfp_1_tx_clk),
|
||||
.sfp_1_tx_rst(sfp_1_tx_rst),
|
||||
.sfp_1_txd(sfp_1_txd),
|
||||
.sfp_1_txc(sfp_1_txc),
|
||||
.sfp_1_rx_clk(sfp_1_rx_clk),
|
||||
.sfp_1_rx_rst(sfp_1_rx_rst),
|
||||
.sfp_1_rxd(sfp_1_rxd),
|
||||
.sfp_1_rxc(sfp_1_rxc),
|
||||
.sfp_2_tx_clk(sfp_2_tx_clk),
|
||||
.sfp_2_tx_rst(sfp_2_tx_rst),
|
||||
.sfp_2_txd(sfp_2_txd),
|
||||
.sfp_2_txc(sfp_2_txc),
|
||||
.sfp_2_rx_clk(sfp_2_rx_clk),
|
||||
.sfp_2_rx_rst(sfp_2_rx_rst),
|
||||
.sfp_2_rxd(sfp_2_rxd),
|
||||
.sfp_2_rxc(sfp_2_rxc),
|
||||
.sfp_i2c_scl_i(sfp_i2c_scl_i),
|
||||
.sfp_i2c_scl_o(sfp_i2c_scl_o),
|
||||
.sfp_i2c_scl_t(sfp_i2c_scl_t),
|
||||
.sfp_1_i2c_sda_i(sfp_1_i2c_sda_i),
|
||||
.sfp_1_i2c_sda_o(sfp_1_i2c_sda_o),
|
||||
.sfp_1_i2c_sda_t(sfp_1_i2c_sda_t),
|
||||
.sfp_2_i2c_sda_i(sfp_2_i2c_sda_i),
|
||||
.sfp_2_i2c_sda_o(sfp_2_i2c_sda_o),
|
||||
.sfp_2_i2c_sda_t(sfp_2_i2c_sda_t),
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_scl_t(eeprom_i2c_scl_t),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
|
||||
.flash_dq_i(flash_dq_i),
|
||||
.flash_dq_o(flash_dq_o),
|
||||
.flash_dq_oe(flash_dq_oe),
|
||||
.flash_addr(flash_addr),
|
||||
.flash_region(flash_region),
|
||||
.flash_region_oe(flash_region_oe),
|
||||
.flash_ce_n(flash_ce_n),
|
||||
.flash_oe_n(flash_oe_n),
|
||||
.flash_we_n(flash_we_n),
|
||||
.flash_adv_n(flash_adv_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic/ExaNIC_X10/fpga/tb/xgmii_ep.py
Symbolic link
1
fpga/mqnic/ExaNIC_X10/fpga/tb/xgmii_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/xgmii_ep.py
|
||||
Loading…
x
Reference in New Issue
Block a user