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Timing optimization

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-07-31 17:24:03 -07:00
parent b1b82a3f2b
commit 1dfdd8b0e3
2 changed files with 14 additions and 8 deletions
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11
rtl/pcie_tlp_fifo_mux.v
View File

@ -341,13 +341,16 @@ always @* begin
end end
end end
for (port = 0; port < PORTS; port = port + 1) begin for (port = 0; port < PORTS; port = port + 1) begin
if (port_seg_valid[cur_port][0] && !pause[cur_port] && !frame_cyc) begin if (!frame_cyc) begin
// select port, set frame // select port
frame_cyc = 1;
port_cyc = cur_port; port_cyc = cur_port;
seg_offset_cyc = port_seg_offset_cyc[cur_port]; seg_offset_cyc = port_seg_offset_cyc[cur_port];
seg_count_cyc = port_seg_count_cyc[cur_port]; seg_count_cyc = port_seg_count_cyc[cur_port];
sel_tlp_seq_valid_cyc[OUT_TLP_SEG_COUNT*cur_port+seg] = 1'b1; if (port_seg_valid[cur_port][0] && !pause[cur_port]) begin
// set frame
frame_cyc = 1;
sel_tlp_seq_valid_cyc[OUT_TLP_SEG_COUNT*cur_port+seg] = 1'b1;
end
end end
// next port // next port
if (ARB_LSB_HIGH_PRIORITY) begin if (ARB_LSB_HIGH_PRIORITY) begin

11
rtl/pcie_tlp_mux.v
View File

@ -272,12 +272,15 @@ always @* begin
end end
end end
for (port = 0; port < PORTS; port = port + 1) begin for (port = 0; port < PORTS; port = port + 1) begin
if (port_seg_valid[cur_port][0] && !pause[cur_port] && !frame_cyc) begin if (!frame_cyc) begin
// select port, set frame // select port
frame_cyc = 1;
port_cyc = cur_port; port_cyc = cur_port;
seg_offset_cyc = port_seg_offset_next[cur_port]; seg_offset_cyc = port_seg_offset_next[cur_port];
sel_tlp_seq_valid_cyc[TLP_SEG_COUNT*cur_port+seg] = 1'b1; if (port_seg_valid[cur_port][0] && !pause[cur_port]) begin
// set frame
frame_cyc = 1;
sel_tlp_seq_valid_cyc[TLP_SEG_COUNT*cur_port+seg] = 1'b1;
end
end end
// next port // next port
if (ARB_LSB_HIGH_PRIORITY) begin if (ARB_LSB_HIGH_PRIORITY) begin