diff --git a/fpga/lib/pcie/example/common/rtl/example_core.v b/fpga/lib/pcie/example/common/rtl/example_core.v index 4855e980a..a67fb6bcc 100644 --- a/fpga/lib/pcie/example/common/rtl/example_core.v +++ b/fpga/lib/pcie/example/common/rtl/example_core.v @@ -45,18 +45,18 @@ module example_core # parameter DMA_LEN_WIDTH = 16, // DMA Tag field width parameter DMA_TAG_WIDTH = 8, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter RAM_SEG_COUNT = 2, // RAM segment data width parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT, - // RAM segment address width - parameter RAM_SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH) + // RAM segment address width + parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH) ) ( input wire clk, diff --git a/fpga/lib/pcie/example/common/rtl/example_core_pcie.v b/fpga/lib/pcie/example/common/rtl/example_core_pcie.v index 0e4acc3d0..5fa978aed 100644 --- a/fpga/lib/pcie/example/common/rtl/example_core_pcie.v +++ b/fpga/lib/pcie/example/common/rtl/example_core_pcie.v @@ -174,12 +174,12 @@ parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); parameter AXI_ADDR_WIDTH = BAR2_APERTURE; parameter AXI_ID_WIDTH = 8; +parameter RAM_SEL_WIDTH = 2; +parameter RAM_ADDR_WIDTH = 16; parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2; parameter RAM_SEG_DATA_WIDTH = (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH)*2/RAM_SEG_COUNT; -parameter RAM_SEG_ADDR_WIDTH = 10; parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8; -parameter RAM_SEL_WIDTH = 2; -parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH); +parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH); parameter PCIE_ADDR_WIDTH = 64; parameter DMA_LEN_WIDTH = 16; @@ -621,12 +621,12 @@ dma_if_pcie #( .TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE), - .RAM_SEG_COUNT(RAM_SEG_COUNT), - .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), - .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), - .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), .RAM_SEL_WIDTH(RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_SEG_COUNT(RAM_SEG_COUNT), + .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), + .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), + .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), .PCIE_TAG_COUNT(PCIE_TAG_COUNT), .LEN_WIDTH(DMA_LEN_WIDTH), @@ -796,12 +796,12 @@ example_core #( .DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH), .DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_SEL_WIDTH(RAM_SEL_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), .RAM_SEG_COUNT(RAM_SEG_COUNT), .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), - .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), - .RAM_SEL_WIDTH(RAM_SEL_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH) + .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH) ) core_inst ( .clk(clk), diff --git a/fpga/lib/pcie/rtl/dma_client_axis_sink.v b/fpga/lib/pcie/rtl/dma_client_axis_sink.v index 5f5956c80..660c88619 100644 --- a/fpga/lib/pcie/rtl/dma_client_axis_sink.v +++ b/fpga/lib/pcie/rtl/dma_client_axis_sink.v @@ -33,16 +33,16 @@ THE SOFTWARE. */ module dma_client_axis_sink # ( + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter SEG_COUNT = 2, // RAM segment data width parameter SEG_DATA_WIDTH = 64, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, - // RAM address width - parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), + // RAM segment address width + parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH), // Width of AXI stream interfaces in bits parameter AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2, // Use AXI stream tkeep signal diff --git a/fpga/lib/pcie/rtl/dma_client_axis_source.v b/fpga/lib/pcie/rtl/dma_client_axis_source.v index 4ed5777af..6ba11309d 100644 --- a/fpga/lib/pcie/rtl/dma_client_axis_source.v +++ b/fpga/lib/pcie/rtl/dma_client_axis_source.v @@ -33,16 +33,16 @@ THE SOFTWARE. */ module dma_client_axis_source # ( + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter SEG_COUNT = 2, // RAM segment data width parameter SEG_DATA_WIDTH = 64, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, - // RAM address width - parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), + // RAM segment address width + parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH), // Width of AXI stream interfaces in bits parameter AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2, // Use AXI stream tkeep signal diff --git a/fpga/lib/pcie/rtl/dma_if_axi.v b/fpga/lib/pcie/rtl/dma_if_axi.v index 6ec2ee877..1a2dd824d 100644 --- a/fpga/lib/pcie/rtl/dma_if_axi.v +++ b/fpga/lib/pcie/rtl/dma_if_axi.v @@ -43,18 +43,18 @@ module dma_if_axi # parameter AXI_ID_WIDTH = 8, // Maximum AXI burst length to generate parameter AXI_MAX_BURST_LEN = 256, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter RAM_SEG_COUNT = 2, // RAM segment data width parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT, - // RAM segment address width - parameter RAM_SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), + // RAM segment address width + parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), // Length field width parameter LEN_WIDTH = 16, // Tag field width @@ -178,12 +178,12 @@ dma_if_axi_rd #( .AXI_STRB_WIDTH(AXI_STRB_WIDTH), .AXI_ID_WIDTH(AXI_ID_WIDTH), .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN), - .RAM_SEG_COUNT(RAM_SEG_COUNT), - .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), - .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), - .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), .RAM_SEL_WIDTH(RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_SEG_COUNT(RAM_SEG_COUNT), + .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), + .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), + .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(READ_OP_TABLE_SIZE), @@ -254,12 +254,12 @@ dma_if_axi_wr #( .AXI_STRB_WIDTH(AXI_STRB_WIDTH), .AXI_ID_WIDTH(AXI_ID_WIDTH), .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN), - .RAM_SEG_COUNT(RAM_SEG_COUNT), - .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), - .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), - .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), .RAM_SEL_WIDTH(RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_SEG_COUNT(RAM_SEG_COUNT), + .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), + .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), + .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE), diff --git a/fpga/lib/pcie/rtl/dma_if_axi_rd.v b/fpga/lib/pcie/rtl/dma_if_axi_rd.v index 6ba854e79..bbeb97e2d 100644 --- a/fpga/lib/pcie/rtl/dma_if_axi_rd.v +++ b/fpga/lib/pcie/rtl/dma_if_axi_rd.v @@ -43,18 +43,18 @@ module dma_if_axi_rd # parameter AXI_ID_WIDTH = 8, // Maximum AXI burst length to generate parameter AXI_MAX_BURST_LEN = 256, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter RAM_SEG_COUNT = 2, // RAM segment data width parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT, - // RAM segment address width - parameter RAM_SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), + // RAM segment address width + parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), // Length field width parameter LEN_WIDTH = 16, // Tag field width diff --git a/fpga/lib/pcie/rtl/dma_if_axi_wr.v b/fpga/lib/pcie/rtl/dma_if_axi_wr.v index bdf2558f7..1f2de6679 100644 --- a/fpga/lib/pcie/rtl/dma_if_axi_wr.v +++ b/fpga/lib/pcie/rtl/dma_if_axi_wr.v @@ -43,18 +43,18 @@ module dma_if_axi_wr # parameter AXI_ID_WIDTH = 8, // Maximum AXI burst length to generate parameter AXI_MAX_BURST_LEN = 256, - // RAM segment countm_axis_read_desc_status_error - parameter RAM_SEG_COUNT = 2, - // RAM segment data width - parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT, - // RAM segment address width - parameter RAM_SEG_ADDR_WIDTH = 8, - // RAM segment byte enable width - parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, // RAM select width parameter RAM_SEL_WIDTH = 2, // RAM address width - parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), + parameter RAM_ADDR_WIDTH = 16, + // RAM segment count + parameter RAM_SEG_COUNT = 2, + // RAM segment data width + parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT, + // RAM segment byte enable width + parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, + // RAM segment address width + parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), // Length field width parameter LEN_WIDTH = 16, // Tag field width diff --git a/fpga/lib/pcie/rtl/dma_if_pcie.v b/fpga/lib/pcie/rtl/dma_if_pcie.v index 414ae663b..b8a743204 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie.v @@ -47,18 +47,18 @@ module dma_if_pcie # parameter TX_SEQ_NUM_WIDTH = 5, // TX sequence number tracking enable parameter TX_SEQ_NUM_ENABLE = 0, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2, // RAM segment data width parameter RAM_SEG_DATA_WIDTH = (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH)*2/RAM_SEG_COUNT, - // RAM segment address width - parameter RAM_SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), + // RAM segment address width + parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), // PCIe address width parameter PCIE_ADDR_WIDTH = 64, // PCIe tag count @@ -252,12 +252,12 @@ dma_if_pcie_rd #( .TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE), - .RAM_SEG_COUNT(RAM_SEG_COUNT), - .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), - .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), - .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), .RAM_SEL_WIDTH(RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_SEG_COUNT(RAM_SEG_COUNT), + .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), + .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), + .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), .PCIE_TAG_COUNT(PCIE_TAG_COUNT), .LEN_WIDTH(LEN_WIDTH), @@ -378,12 +378,12 @@ dma_if_pcie_wr #( .TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE), - .RAM_SEG_COUNT(RAM_SEG_COUNT), - .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), - .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), - .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), .RAM_SEL_WIDTH(RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_SEG_COUNT(RAM_SEG_COUNT), + .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), + .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH), + .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_rd.v b/fpga/lib/pcie/rtl/dma_if_pcie_rd.v index 680e5af91..b0172e3cd 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_rd.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_rd.v @@ -45,18 +45,18 @@ module dma_if_pcie_rd # parameter TX_SEQ_NUM_WIDTH = 6, // TX sequence number tracking enable parameter TX_SEQ_NUM_ENABLE = 0, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2, // RAM segment data width parameter RAM_SEG_DATA_WIDTH = (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH)*2/RAM_SEG_COUNT, - // RAM segment address width - parameter RAM_SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), + // RAM segment address width + parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), // PCIe address width parameter PCIE_ADDR_WIDTH = 64, // PCIe tag count diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us.v b/fpga/lib/pcie/rtl/dma_if_pcie_us.v index f7b6c2cd7..229df9015 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_us.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_us.v @@ -45,18 +45,18 @@ module dma_if_pcie_us # parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, // RQ sequence number tracking enable parameter RQ_SEQ_NUM_ENABLE = 0, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2, // RAM segment data width parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), + // RAM segment address width + parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH), // PCIe address width parameter PCIE_ADDR_WIDTH = 64, // PCIe tag count @@ -208,12 +208,12 @@ dma_if_pcie_us_rd #( .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), .RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE), - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), .RAM_SEL_WIDTH(RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), .PCIE_TAG_COUNT(PCIE_TAG_COUNT), .LEN_WIDTH(LEN_WIDTH), @@ -310,12 +310,12 @@ dma_if_pcie_us_wr #( .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), .RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE), - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), .RAM_SEL_WIDTH(RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v b/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v index 5f9aeb3de..ae87aa1f1 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v @@ -45,18 +45,18 @@ module dma_if_pcie_us_rd # parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, // RQ sequence number tracking enable parameter RQ_SEQ_NUM_ENABLE = 0, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2, // RAM segment data width parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), + // RAM segment address width + parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH), // PCIe address width parameter PCIE_ADDR_WIDTH = 64, // PCIe tag count diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v b/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v index 7974d6599..3179cbfd7 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v @@ -43,18 +43,18 @@ module dma_if_pcie_us_wr # parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, // RQ sequence number tracking enable parameter RQ_SEQ_NUM_ENABLE = 0, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter SEG_COUNT = AXIS_PCIE_DATA_WIDTH > 64 ? AXIS_PCIE_DATA_WIDTH*2 / 128 : 2, // RAM segment data width parameter SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), + // RAM segment address width + parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH), // PCIe address width parameter PCIE_ADDR_WIDTH = 64, // Length field width diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_wr.v b/fpga/lib/pcie/rtl/dma_if_pcie_wr.v index 03d2f3676..55c9779f9 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_wr.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_wr.v @@ -47,18 +47,18 @@ module dma_if_pcie_wr # parameter TX_SEQ_NUM_WIDTH = 6, // TX sequence number tracking enable parameter TX_SEQ_NUM_ENABLE = 0, + // RAM select width + parameter RAM_SEL_WIDTH = 2, + // RAM address width + parameter RAM_ADDR_WIDTH = 16, // RAM segment count parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2, // RAM segment data width parameter RAM_SEG_DATA_WIDTH = (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH)*2/RAM_SEG_COUNT, - // RAM segment address width - parameter RAM_SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, - // RAM select width - parameter RAM_SEL_WIDTH = 2, - // RAM address width - parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), + // RAM segment address width + parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), // PCIe address width parameter PCIE_ADDR_WIDTH = 64, // Length field width diff --git a/fpga/lib/pcie/rtl/dma_psdpram.v b/fpga/lib/pcie/rtl/dma_psdpram.v index a0f2283af..2f054f8a1 100644 --- a/fpga/lib/pcie/rtl/dma_psdpram.v +++ b/fpga/lib/pcie/rtl/dma_psdpram.v @@ -39,10 +39,10 @@ module dma_psdpram # parameter SEG_COUNT = 2, // RAM segment data width parameter SEG_DATA_WIDTH = 128, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, + // RAM segment address width + parameter SEG_ADDR_WIDTH = $clog2(SIZE/(SEG_COUNT*SEG_BE_WIDTH)), // Read data output pipeline stages parameter PIPELINE = 2 ) diff --git a/fpga/lib/pcie/rtl/dma_psdpram_async.v b/fpga/lib/pcie/rtl/dma_psdpram_async.v index f67c7416c..08fdf5c68 100644 --- a/fpga/lib/pcie/rtl/dma_psdpram_async.v +++ b/fpga/lib/pcie/rtl/dma_psdpram_async.v @@ -39,10 +39,10 @@ module dma_psdpram_async # parameter SEG_COUNT = 2, // RAM segment data width parameter SEG_DATA_WIDTH = 128, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, + // RAM segment address width + parameter SEG_ADDR_WIDTH = $clog2(SIZE/(SEG_COUNT*SEG_BE_WIDTH)), // Read data output pipeline stages parameter PIPELINE = 2 ) diff --git a/fpga/lib/pcie/rtl/dma_ram_demux.v b/fpga/lib/pcie/rtl/dma_ram_demux.v index 9aabccdae..8a125e992 100644 --- a/fpga/lib/pcie/rtl/dma_ram_demux.v +++ b/fpga/lib/pcie/rtl/dma_ram_demux.v @@ -39,10 +39,10 @@ module dma_ram_demux # parameter SEG_COUNT = 2, // RAM segment data width parameter SEG_DATA_WIDTH = 64, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, + // RAM segment address width + parameter SEG_ADDR_WIDTH = 8, // Input RAM segment select width parameter S_RAM_SEL_WIDTH = 2, // Output RAM segment select width @@ -94,8 +94,8 @@ dma_ram_demux_wr #( .PORTS(PORTS), .SEG_COUNT(SEG_COUNT), .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), .SEG_BE_WIDTH(SEG_BE_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), .S_RAM_SEL_WIDTH(S_RAM_SEL_WIDTH), .M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH) ) diff --git a/fpga/lib/pcie/rtl/dma_ram_demux_wr.v b/fpga/lib/pcie/rtl/dma_ram_demux_wr.v index 2d4466b3b..07a33c3d3 100644 --- a/fpga/lib/pcie/rtl/dma_ram_demux_wr.v +++ b/fpga/lib/pcie/rtl/dma_ram_demux_wr.v @@ -39,10 +39,10 @@ module dma_ram_demux_wr # parameter SEG_COUNT = 2, // RAM segment data width parameter SEG_DATA_WIDTH = 64, - // RAM segment address width - parameter SEG_ADDR_WIDTH = 8, // RAM segment byte enable width parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, + // RAM segment address width + parameter SEG_ADDR_WIDTH = 8, // Input RAM segment select width parameter S_RAM_SEL_WIDTH = 2, // Output RAM segment select width diff --git a/fpga/lib/pcie/tb/dma_client_axis_sink/Makefile b/fpga/lib/pcie/tb/dma_client_axis_sink/Makefile index 6fc188d5f..6e2888aa0 100644 --- a/fpga/lib/pcie/tb/dma_client_axis_sink/Makefile +++ b/fpga/lib/pcie/tb/dma_client_axis_sink/Makefile @@ -33,11 +33,11 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_RAM_DATA_WIDTH ?= 128 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_ADDR_WIDTH ?= 12 export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_SEG_ADDR_WIDTH) + ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_AXIS_DATA_WIDTH ?= 64 export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) @@ -55,11 +55,11 @@ ifeq ($(SIM), icarus) PLUSARGS += -fst COMPILE_ARGS += -P $(TOPLEVEL).RAM_DATA_WIDTH=$(PARAM_RAM_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) @@ -81,11 +81,11 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH COMPILE_ARGS += -GRAM_DATA_WIDTH=$(PARAM_RAM_DATA_WIDTH) + COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) - COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) diff --git a/fpga/lib/pcie/tb/dma_client_axis_sink/test_dma_client_axis_sink.py b/fpga/lib/pcie/tb/dma_client_axis_sink/test_dma_client_axis_sink.py index 0c8d5f6e5..7c31e7646 100644 --- a/fpga/lib/pcie/tb/dma_client_axis_sink/test_dma_client_axis_sink.py +++ b/fpga/lib/pcie/tb/dma_client_axis_sink/test_dma_client_axis_sink.py @@ -191,17 +191,17 @@ def test_dma_client_axis_sink(request, ram_data_width, axis_data_width): parameters = {} # segmented interface parameters + ram_addr_width = 16 seg_count = max(2, ram_data_width // 128) seg_data_width = ram_data_width // seg_count - seg_addr_width = 12 seg_be_width = seg_data_width // 8 - ram_addr_width = seg_addr_width + (seg_count*seg_be_width-1).bit_length() + seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length() + parameters['RAM_ADDR_WIDTH'] = ram_addr_width parameters['SEG_COUNT'] = seg_count parameters['SEG_DATA_WIDTH'] = seg_data_width - parameters['SEG_ADDR_WIDTH'] = seg_addr_width parameters['SEG_BE_WIDTH'] = seg_be_width - parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['SEG_ADDR_WIDTH'] = seg_addr_width parameters['AXIS_DATA_WIDTH'] = axis_data_width parameters['AXIS_KEEP_ENABLE'] = int(axis_data_width > 8) parameters['AXIS_KEEP_WIDTH'] = axis_data_width // 8 diff --git a/fpga/lib/pcie/tb/dma_client_axis_source/Makefile b/fpga/lib/pcie/tb/dma_client_axis_source/Makefile index 73a220fc0..f64b35f1a 100644 --- a/fpga/lib/pcie/tb/dma_client_axis_source/Makefile +++ b/fpga/lib/pcie/tb/dma_client_axis_source/Makefile @@ -33,11 +33,11 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_RAM_DATA_WIDTH ?= 128 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_ADDR_WIDTH ?= 12 export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_SEG_ADDR_WIDTH) + ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_AXIS_DATA_WIDTH ?= 64 export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) @@ -55,11 +55,11 @@ ifeq ($(SIM), icarus) PLUSARGS += -fst COMPILE_ARGS += -P $(TOPLEVEL).RAM_DATA_WIDTH=$(PARAM_RAM_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) @@ -81,11 +81,11 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH COMPILE_ARGS += -GRAM_DATA_WIDTH=$(PARAM_RAM_DATA_WIDTH) + COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) - COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH) COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE) COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH) diff --git a/fpga/lib/pcie/tb/dma_client_axis_source/test_dma_client_axis_source.py b/fpga/lib/pcie/tb/dma_client_axis_source/test_dma_client_axis_source.py index 18cba42f3..f90122131 100644 --- a/fpga/lib/pcie/tb/dma_client_axis_source/test_dma_client_axis_source.py +++ b/fpga/lib/pcie/tb/dma_client_axis_source/test_dma_client_axis_source.py @@ -182,17 +182,17 @@ def test_dma_client_axis_source(request, ram_data_width, axis_data_width): parameters = {} # segmented interface parameters + ram_addr_width = 16 seg_count = max(2, ram_data_width // 128) seg_data_width = ram_data_width // seg_count - seg_addr_width = 12 seg_be_width = seg_data_width // 8 - ram_addr_width = seg_addr_width + (seg_count*seg_be_width-1).bit_length() + seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length() + parameters['RAM_ADDR_WIDTH'] = ram_addr_width parameters['SEG_COUNT'] = seg_count parameters['SEG_DATA_WIDTH'] = seg_data_width - parameters['SEG_ADDR_WIDTH'] = seg_addr_width parameters['SEG_BE_WIDTH'] = seg_be_width - parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['SEG_ADDR_WIDTH'] = seg_addr_width parameters['AXIS_DATA_WIDTH'] = axis_data_width parameters['AXIS_KEEP_ENABLE'] = int(axis_data_width > 8) parameters['AXIS_KEEP_WIDTH'] = axis_data_width // 8 diff --git a/fpga/lib/pcie/tb/dma_if_axi/Makefile b/fpga/lib/pcie/tb/dma_if_axi/Makefile index 44f4c988c..83723f504 100644 --- a/fpga/lib/pcie/tb/dma_if_axi/Makefile +++ b/fpga/lib/pcie/tb/dma_if_axi/Makefile @@ -38,12 +38,12 @@ export PARAM_AXI_DATA_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH ?= 16 export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_ID_WIDTH ?= 8 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_SEG_COUNT ?= 2 export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= 12 export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WIDTH) + ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_LEN_WIDTH ?= 16 export PARAM_TAG_WIDTH ?= 8 export PARAM_READ_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") @@ -58,12 +58,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE) @@ -82,12 +82,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH) COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) - COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH) COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE) diff --git a/fpga/lib/pcie/tb/dma_if_axi/test_dma_if_axi.py b/fpga/lib/pcie/tb/dma_if_axi/test_dma_if_axi.py index a94b6c8b2..1aa6c31a5 100644 --- a/fpga/lib/pcie/tb/dma_if_axi/test_dma_if_axi.py +++ b/fpga/lib/pcie/tb/dma_if_axi/test_dma_if_axi.py @@ -246,23 +246,23 @@ def test_dma_if_axi(request, axi_data_width): parameters = {} # segmented interface parameters + ram_sel_width = 2 + ram_addr_width = 16 ram_seg_count = 2 ram_seg_data_width = axi_data_width*2 // ram_seg_count - ram_seg_addr_width = 12 ram_seg_be_width = ram_seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = ram_seg_addr_width + (ram_seg_count*ram_seg_be_width-1).bit_length() + ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length() parameters['AXI_DATA_WIDTH'] = axi_data_width parameters['AXI_ADDR_WIDTH'] = 16 parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8 parameters['AXI_ID_WIDTH'] = 8 - parameters['RAM_SEG_COUNT'] = ram_seg_count - parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width - parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width - parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['RAM_SEG_COUNT'] = ram_seg_count + parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width + parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width + parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width parameters['LEN_WIDTH'] = 16 parameters['TAG_WIDTH'] = 8 parameters['READ_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH'] diff --git a/fpga/lib/pcie/tb/dma_if_axi_rd/Makefile b/fpga/lib/pcie/tb/dma_if_axi_rd/Makefile index 899708914..35b743a76 100644 --- a/fpga/lib/pcie/tb/dma_if_axi_rd/Makefile +++ b/fpga/lib/pcie/tb/dma_if_axi_rd/Makefile @@ -36,12 +36,12 @@ export PARAM_AXI_DATA_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH ?= 16 export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_ID_WIDTH ?= 8 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_SEG_COUNT ?= 2 export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= 12 export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WIDTH) + ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_LEN_WIDTH ?= 16 export PARAM_TAG_WIDTH ?= 8 export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") @@ -54,12 +54,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE) @@ -76,12 +76,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH) COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) - COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH) COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE) diff --git a/fpga/lib/pcie/tb/dma_if_axi_rd/test_dma_if_axi_rd.py b/fpga/lib/pcie/tb/dma_if_axi_rd/test_dma_if_axi_rd.py index f2365c563..734914c6f 100644 --- a/fpga/lib/pcie/tb/dma_if_axi_rd/test_dma_if_axi_rd.py +++ b/fpga/lib/pcie/tb/dma_if_axi_rd/test_dma_if_axi_rd.py @@ -182,23 +182,23 @@ def test_dma_if_axi_rd(request, axi_data_width): parameters = {} # segmented interface parameters + ram_sel_width = 2 + ram_addr_width = 16 ram_seg_count = 2 ram_seg_data_width = axi_data_width*2 // ram_seg_count - ram_seg_addr_width = 12 ram_seg_be_width = ram_seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = ram_seg_addr_width + (ram_seg_count*ram_seg_be_width-1).bit_length() + ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length() parameters['AXI_DATA_WIDTH'] = axi_data_width parameters['AXI_ADDR_WIDTH'] = 16 parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8 parameters['AXI_ID_WIDTH'] = 8 - parameters['RAM_SEG_COUNT'] = ram_seg_count - parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width - parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width - parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['RAM_SEG_COUNT'] = ram_seg_count + parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width + parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width + parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width parameters['LEN_WIDTH'] = 16 parameters['TAG_WIDTH'] = 8 parameters['OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH'] diff --git a/fpga/lib/pcie/tb/dma_if_axi_wr/Makefile b/fpga/lib/pcie/tb/dma_if_axi_wr/Makefile index 43fbefdfc..7f19735db 100644 --- a/fpga/lib/pcie/tb/dma_if_axi_wr/Makefile +++ b/fpga/lib/pcie/tb/dma_if_axi_wr/Makefile @@ -36,12 +36,12 @@ export PARAM_AXI_DATA_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH ?= 16 export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_ID_WIDTH ?= 8 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_SEG_COUNT ?= 2 export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= 12 export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WIDTH) + ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_LEN_WIDTH ?= 16 export PARAM_TAG_WIDTH ?= 8 export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") @@ -54,12 +54,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE) @@ -76,12 +76,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH) COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) - COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH) COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE) diff --git a/fpga/lib/pcie/tb/dma_if_axi_wr/test_dma_if_axi_wr.py b/fpga/lib/pcie/tb/dma_if_axi_wr/test_dma_if_axi_wr.py index 67cae84d6..f26206fe4 100644 --- a/fpga/lib/pcie/tb/dma_if_axi_wr/test_dma_if_axi_wr.py +++ b/fpga/lib/pcie/tb/dma_if_axi_wr/test_dma_if_axi_wr.py @@ -184,23 +184,23 @@ def test_dma_if_axi_wr(request, axi_data_width): parameters = {} # segmented interface parameters + ram_sel_width = 2 + ram_addr_width = 16 ram_seg_count = 2 ram_seg_data_width = axi_data_width*2 // ram_seg_count - ram_seg_addr_width = 12 ram_seg_be_width = ram_seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = ram_seg_addr_width + (ram_seg_count*ram_seg_be_width-1).bit_length() + ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length() parameters['AXI_DATA_WIDTH'] = axi_data_width parameters['AXI_ADDR_WIDTH'] = 16 parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8 parameters['AXI_ID_WIDTH'] = 8 - parameters['RAM_SEG_COUNT'] = ram_seg_count - parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width - parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width - parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['RAM_SEG_COUNT'] = ram_seg_count + parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width + parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width + parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width parameters['LEN_WIDTH'] = 16 parameters['TAG_WIDTH'] = 8 parameters['OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH'] diff --git a/fpga/lib/pcie/tb/dma_if_pcie_rd/Makefile b/fpga/lib/pcie/tb/dma_if_pcie_rd/Makefile index 373770ec2..610ab07f4 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_rd/Makefile +++ b/fpga/lib/pcie/tb/dma_if_pcie_rd/Makefile @@ -38,12 +38,12 @@ export PARAM_TLP_SEG_HDR_WIDTH ?= 128 export PARAM_TX_SEQ_NUM_COUNT ?= 1 export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_ENABLE ?= 1 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= 12 export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WIDTH) + ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_TAG_COUNT ?= 256 export PARAM_LEN_WIDTH ?= 20 @@ -63,12 +63,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) @@ -92,12 +92,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT) COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH) COMPILE_ARGS += -GTX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE) - COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) diff --git a/fpga/lib/pcie/tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py b/fpga/lib/pcie/tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py index 28e5f14a3..8381fe7e8 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py +++ b/fpga/lib/pcie/tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py @@ -310,12 +310,12 @@ def test_dma_if_pcie_rd(request, pcie_data_width, pcie_offset): tlp_seg_count = 1 tlp_seg_data_width = pcie_data_width // tlp_seg_count + ram_sel_width = 2 + ram_addr_width = 16 ram_seg_count = tlp_seg_count*2 ram_seg_data_width = (tlp_seg_count*tlp_seg_data_width)*2 // ram_seg_count - ram_seg_addr_width = 12 ram_seg_be_width = ram_seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = ram_seg_addr_width + (ram_seg_count-1).bit_length() + (ram_seg_be_width-1).bit_length() + ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length() parameters['TLP_SEG_COUNT'] = tlp_seg_count parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width @@ -323,12 +323,12 @@ def test_dma_if_pcie_rd(request, pcie_data_width, pcie_offset): parameters['TX_SEQ_NUM_COUNT'] = 1 parameters['TX_SEQ_NUM_WIDTH'] = 6 parameters['TX_SEQ_NUM_ENABLE'] = 1 - parameters['RAM_SEG_COUNT'] = ram_seg_count - parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width - parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width - parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['RAM_SEG_COUNT'] = ram_seg_count + parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width + parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width + parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width parameters['PCIE_ADDR_WIDTH'] = 64 parameters['PCIE_TAG_COUNT'] = 256 parameters['LEN_WIDTH'] = 20 diff --git a/fpga/lib/pcie/tb/dma_if_pcie_us/Makefile b/fpga/lib/pcie/tb/dma_if_pcie_us/Makefile index 135879c96..789622648 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_us/Makefile +++ b/fpga/lib/pcie/tb/dma_if_pcie_us/Makefile @@ -40,12 +40,12 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_ADDR_WIDTH ?= 12 export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_SEG_ADDR_WIDTH) + ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) export PARAM_LEN_WIDTH ?= 20 @@ -66,12 +66,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) @@ -96,12 +96,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GAXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH) COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH) COMPILE_ARGS += -GRQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE) - COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) - COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) + COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) diff --git a/fpga/lib/pcie/tb/dma_if_pcie_us/test_dma_if_pcie_us.py b/fpga/lib/pcie/tb/dma_if_pcie_us/test_dma_if_pcie_us.py index 271902419..7bf81cedb 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_us/test_dma_if_pcie_us.py +++ b/fpga/lib/pcie/tb/dma_if_pcie_us/test_dma_if_pcie_us.py @@ -381,12 +381,12 @@ def test_dma_if_pcie_us(request, axis_pcie_data_width): parameters = {} # segmented interface parameters + ram_sel_width = 2 + ram_addr_width = 16 seg_count = max(2, axis_pcie_data_width*2 // 128) seg_data_width = axis_pcie_data_width*2 // seg_count - seg_addr_width = 12 seg_be_width = seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = seg_addr_width + (seg_count*seg_be_width-1).bit_length() + seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length() parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32 @@ -394,12 +394,12 @@ def test_dma_if_pcie_us(request, axis_pcie_data_width): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['RQ_SEQ_NUM_WIDTH'] = 4 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 6 parameters['RQ_SEQ_NUM_ENABLE'] = 1 - parameters['SEG_COUNT'] = seg_count - parameters['SEG_DATA_WIDTH'] = seg_data_width - parameters['SEG_ADDR_WIDTH'] = seg_addr_width - parameters['SEG_BE_WIDTH'] = seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['SEG_COUNT'] = seg_count + parameters['SEG_DATA_WIDTH'] = seg_data_width + parameters['SEG_BE_WIDTH'] = seg_be_width + parameters['SEG_ADDR_WIDTH'] = seg_addr_width parameters['PCIE_ADDR_WIDTH'] = 64 parameters['PCIE_TAG_COUNT'] = 64 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 256 parameters['LEN_WIDTH'] = 20 diff --git a/fpga/lib/pcie/tb/dma_if_pcie_us_rd/Makefile b/fpga/lib/pcie/tb/dma_if_pcie_us_rd/Makefile index 863d9fa48..d72504a62 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_us_rd/Makefile +++ b/fpga/lib/pcie/tb/dma_if_pcie_us_rd/Makefile @@ -38,12 +38,12 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_ADDR_WIDTH ?= 12 export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_SEG_ADDR_WIDTH) + ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) export PARAM_LEN_WIDTH ?= 20 @@ -61,12 +61,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) @@ -88,12 +88,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GAXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH) COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH) COMPILE_ARGS += -GRQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE) - COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) - COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) + COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) diff --git a/fpga/lib/pcie/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py b/fpga/lib/pcie/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py index 5014dca8d..a0541515f 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py +++ b/fpga/lib/pcie/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py @@ -317,12 +317,12 @@ def test_dma_if_pcie_us_rd(request, axis_pcie_data_width, pcie_offset): parameters = {} # segmented interface parameters + ram_sel_width = 2 + ram_addr_width = 16 seg_count = max(2, axis_pcie_data_width*2 // 128) seg_data_width = axis_pcie_data_width*2 // seg_count - seg_addr_width = 12 seg_be_width = seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = seg_addr_width + (seg_count-1).bit_length() + (seg_be_width-1).bit_length() + seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length() parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32 @@ -330,12 +330,12 @@ def test_dma_if_pcie_us_rd(request, axis_pcie_data_width, pcie_offset): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['RQ_SEQ_NUM_WIDTH'] = 4 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 6 parameters['RQ_SEQ_NUM_ENABLE'] = 1 - parameters['SEG_COUNT'] = seg_count - parameters['SEG_DATA_WIDTH'] = seg_data_width - parameters['SEG_ADDR_WIDTH'] = seg_addr_width - parameters['SEG_BE_WIDTH'] = seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['SEG_COUNT'] = seg_count + parameters['SEG_DATA_WIDTH'] = seg_data_width + parameters['SEG_BE_WIDTH'] = seg_be_width + parameters['SEG_ADDR_WIDTH'] = seg_addr_width parameters['PCIE_ADDR_WIDTH'] = 64 parameters['PCIE_TAG_COUNT'] = 64 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 256 parameters['LEN_WIDTH'] = 20 diff --git a/fpga/lib/pcie/tb/dma_if_pcie_us_wr/Makefile b/fpga/lib/pcie/tb/dma_if_pcie_us_wr/Makefile index 37a923e19..fb75ef7ca 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_us_wr/Makefile +++ b/fpga/lib/pcie/tb/dma_if_pcie_us_wr/Makefile @@ -37,12 +37,12 @@ export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_ADDR_WIDTH ?= 12 export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_SEG_ADDR_WIDTH) + ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_LEN_WIDTH ?= 20 export PARAM_TAG_WIDTH ?= 8 @@ -58,12 +58,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).SEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH) @@ -83,12 +83,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GAXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH) COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH) COMPILE_ARGS += -GRQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE) - COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) - COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT) + COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GSEG_BE_WIDTH=$(PARAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GSEG_ADDR_WIDTH=$(PARAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH) diff --git a/fpga/lib/pcie/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py b/fpga/lib/pcie/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py index c31f3cc06..e25a43a1f 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py +++ b/fpga/lib/pcie/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py @@ -235,24 +235,24 @@ def test_dma_if_pcie_us_wr(request, axis_pcie_data_width, pcie_offset): parameters = {} # segmented interface parameters + ram_sel_width = 2 + ram_addr_width = 16 seg_count = max(2, axis_pcie_data_width*2 // 128) seg_data_width = axis_pcie_data_width*2 // seg_count - seg_addr_width = 12 seg_be_width = seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = seg_addr_width + (seg_count-1).bit_length() + (seg_be_width-1).bit_length() + seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length() parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32 parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137 parameters['RQ_SEQ_NUM_WIDTH'] = 4 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 6 parameters['RQ_SEQ_NUM_ENABLE'] = 1 - parameters['SEG_COUNT'] = seg_count - parameters['SEG_DATA_WIDTH'] = seg_data_width - parameters['SEG_ADDR_WIDTH'] = seg_addr_width - parameters['SEG_BE_WIDTH'] = seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['SEG_COUNT'] = seg_count + parameters['SEG_DATA_WIDTH'] = seg_data_width + parameters['SEG_BE_WIDTH'] = seg_be_width + parameters['SEG_ADDR_WIDTH'] = seg_addr_width parameters['PCIE_ADDR_WIDTH'] = 64 parameters['LEN_WIDTH'] = 20 parameters['TAG_WIDTH'] = 8 diff --git a/fpga/lib/pcie/tb/dma_if_pcie_wr/Makefile b/fpga/lib/pcie/tb/dma_if_pcie_wr/Makefile index 717166217..74952c3c3 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_wr/Makefile +++ b/fpga/lib/pcie/tb/dma_if_pcie_wr/Makefile @@ -39,12 +39,12 @@ export PARAM_TLP_SEG_HDR_WIDTH ?= 128 export PARAM_TX_SEQ_NUM_COUNT ?= 1 export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_ENABLE ?= 1 +export PARAM_RAM_SEL_WIDTH ?= 2 +export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= 12 export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WIDTH) + ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_LEN_WIDTH ?= 20 export PARAM_TAG_WIDTH ?= 8 @@ -63,12 +63,12 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH) @@ -91,12 +91,12 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GTX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT) COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH) COMPILE_ARGS += -GTX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE) - COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) - COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) - COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) - COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) COMPILE_ARGS += -GRAM_SEL_WIDTH=$(PARAM_RAM_SEL_WIDTH) COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GRAM_SEG_COUNT=$(PARAM_RAM_SEG_COUNT) + COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH) + COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH) + COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH) COMPILE_ARGS += -GPCIE_ADDR_WIDTH=$(PARAM_PCIE_ADDR_WIDTH) COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH) COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH) diff --git a/fpga/lib/pcie/tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py b/fpga/lib/pcie/tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py index 617065b72..8e3fa2cff 100644 --- a/fpga/lib/pcie/tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py +++ b/fpga/lib/pcie/tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py @@ -220,12 +220,12 @@ def test_dma_if_pcie_wr(request, pcie_data_width, pcie_offset): tlp_seg_data_width = pcie_data_width // tlp_seg_count tlp_seg_strb_width = tlp_seg_data_width // 32 + ram_sel_width = 2 + ram_addr_width = 16 ram_seg_count = tlp_seg_count*2 ram_seg_data_width = (tlp_seg_count*tlp_seg_data_width)*2 // ram_seg_count - ram_seg_addr_width = 12 ram_seg_be_width = ram_seg_data_width // 8 - ram_sel_width = 2 - ram_addr_width = ram_seg_addr_width + (ram_seg_count-1).bit_length() + (ram_seg_be_width-1).bit_length() + ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length() parameters['TLP_SEG_COUNT'] = tlp_seg_count parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width @@ -234,12 +234,12 @@ def test_dma_if_pcie_wr(request, pcie_data_width, pcie_offset): parameters['TX_SEQ_NUM_COUNT'] = 1 parameters['TX_SEQ_NUM_WIDTH'] = 6 parameters['TX_SEQ_NUM_ENABLE'] = 1 - parameters['RAM_SEG_COUNT'] = ram_seg_count - parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width - parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width - parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width parameters['RAM_SEL_WIDTH'] = ram_sel_width parameters['RAM_ADDR_WIDTH'] = ram_addr_width + parameters['RAM_SEG_COUNT'] = ram_seg_count + parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width + parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width + parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width parameters['PCIE_ADDR_WIDTH'] = 64 parameters['LEN_WIDTH'] = 20 parameters['TAG_WIDTH'] = 8