mirror of
https://github.com/corundum/corundum.git
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fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
51b9eb251b
commit
1f3b739bb6
@ -18,6 +18,7 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
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// GT type
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parameter GT_GTH = 0,
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parameter GT_USP = 1,
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// PLL parameters
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parameter QPLL0_PD = 1'b0,
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@ -288,6 +289,7 @@ if (COUNT > 0) begin : phy1
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eth_xcvr_phy_10g_gty_wrapper #(
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.HAS_COMMON(1),
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.GT_GTH(GT_GTH),
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.GT_USP(GT_USP),
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// PLL
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.QPLL0_PD(QPLL0_PD),
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.QPLL1_PD(QPLL1_PD),
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@ -397,6 +399,7 @@ if (COUNT > 1) begin : phy2
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eth_xcvr_phy_10g_gty_wrapper #(
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.HAS_COMMON(0),
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.GT_GTH(GT_GTH),
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.GT_USP(GT_USP),
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// GT
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.GT_TX_PD(GT_2_TX_PD),
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.GT_TX_QPLL_SEL(GT_2_TX_QPLL_SEL),
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@ -501,6 +504,7 @@ if (COUNT > 2) begin : phy3
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eth_xcvr_phy_10g_gty_wrapper #(
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.HAS_COMMON(0),
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.GT_GTH(GT_GTH),
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.GT_USP(GT_USP),
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// GT
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.GT_TX_PD(GT_3_TX_PD),
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.GT_TX_QPLL_SEL(GT_3_TX_QPLL_SEL),
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@ -605,6 +609,7 @@ if (COUNT > 3) begin : phy4
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eth_xcvr_phy_10g_gty_wrapper #(
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.HAS_COMMON(0),
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.GT_GTH(GT_GTH),
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.GT_USP(GT_USP),
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// GT
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.GT_TX_PD(GT_4_TX_PD),
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.GT_TX_QPLL_SEL(GT_4_TX_QPLL_SEL),
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@ -19,6 +19,7 @@ module eth_xcvr_phy_10g_gty_wrapper #
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// GT type
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parameter GT_GTH = 0,
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parameter GT_USP = 1,
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// PLL parameters
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parameter QPLL0_PD = 1'b0,
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@ -987,7 +988,7 @@ end
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generate
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if (HAS_COMMON && !GT_GTH) begin : xcvr_gty_com
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if (HAS_COMMON && !GT_GTH && GT_USP) begin : xcvr_gty_com_usp
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eth_xcvr_gty_full
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eth_xcvr_gty_full_inst (
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@ -1123,7 +1124,7 @@ if (HAS_COMMON && !GT_GTH) begin : xcvr_gty_com
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assign xcvr_qpll1clk_out = qpll1_clk;
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assign xcvr_qpll1refclk_out = qpll1_refclk;
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end else if (HAS_COMMON && GT_GTH) begin : xcvr_gth_com
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end else if (HAS_COMMON && GT_GTH && GT_USP) begin : xcvr_gth_com_usp
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eth_xcvr_gth_full
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eth_xcvr_gth_full_inst (
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@ -1259,6 +1260,278 @@ end else if (HAS_COMMON && GT_GTH) begin : xcvr_gth_com
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assign xcvr_qpll1clk_out = qpll1_clk;
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assign xcvr_qpll1refclk_out = qpll1_refclk;
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end else if (HAS_COMMON && !GT_GTH && !GT_USP) begin : xcvr_gty_com_us
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eth_xcvr_gty_full
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eth_xcvr_gty_full_inst (
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// Common
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.gtpowergood_out(xcvr_gtpowergood_out),
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.loopback_in(gt_loopback_reg),
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// DRP
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.drpclk_common_in(drp_clk),
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.drpaddr_common_in(drp_addr_reg),
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.drpdi_common_in(drp_di_reg),
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.drpen_common_in(drp_en_reg_2),
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.drpwe_common_in(drp_we_reg),
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.drpdo_common_out(drp_do_2),
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.drprdy_common_out(drp_rdy_2),
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.drpclk_in(drp_clk),
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.drpaddr_in(drp_addr_reg),
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.drpdi_in(drp_di_reg),
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.drpen_in(drp_en_reg_1),
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.drpwe_in(drp_we_reg),
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.drpdo_out(drp_do_1),
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.drprdy_out(drp_rdy_1),
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// PLL
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.gtrefclk00_in(xcvr_gtrefclk00_in),
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.qpll0lock_out(qpll0_lock),
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.qpll0outclk_out(qpll0_clk),
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.qpll0outrefclk_out(qpll0_refclk),
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.gtrefclk01_in(xcvr_gtrefclk01_in),
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.qpll1lock_out(qpll1_lock),
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.qpll1outclk_out(qpll1_clk),
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.qpll1outrefclk_out(qpll1_refclk),
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.qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg),
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.qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg),
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.qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg),
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.qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg),
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.qpllrsvd2_in(QPLL0_EXT_CTRL ? {2'd0, xcvr_qpll0pcierate_in} : 5'd0), // [2:0] : QPLL0 rate
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.qpllrsvd3_in(QPLL1_EXT_CTRL ? {2'd0, xcvr_qpll1pcierate_in} : 5'd0), // [2:0] : QPLL1 rate
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// Serial data
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.gtytxp_out(xcvr_txp),
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.gtytxn_out(xcvr_txn),
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.gtyrxp_in(xcvr_rxp),
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.gtyrxn_in(xcvr_rxn),
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// Transmit
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.gtwiz_userclk_tx_reset_in(gt_tx_reset_reg),
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.gtwiz_userclk_tx_srcclk_out(),
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.gtwiz_userclk_tx_usrclk_out(),
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.gtwiz_userclk_tx_usrclk2_out(gt_txusrclk2),
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.gtwiz_userclk_tx_active_out(gt_userclk_tx_active),
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.gtwiz_reset_tx_done_in(tx_reset_done_reg),
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.txpdelecidlemode_in(1'b1),
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.txpd_in(gt_tx_pd_reg ? 2'b11 : 2'b00),
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.gttxreset_in(gt_tx_reset_reg),
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.txpmareset_in(gt_tx_pma_reset_reg),
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.txpcsreset_in(gt_tx_pcs_reset_reg),
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.txresetdone_out(gt_tx_reset_done),
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.txpmaresetdone_out(gt_tx_pma_reset_done),
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.txprogdivreset_in(gt_tx_prgdiv_reset_reg),
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.txprgdivresetdone_out(gt_tx_prgdiv_reset_done),
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.txpllclksel_in(gt_tx_qpll_sel_reg ? 2'b10 : 2'b11),
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.txsysclksel_in(gt_tx_qpll_sel_reg ? 2'b11 : 2'b10),
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.txuserrdy_in(gt_tx_userrdy_reg),
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.txpolarity_in(gt_txpolarity_sync_reg),
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.txelecidle_in(gt_txelecidle_reg),
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.txinhibit_in(gt_txinhibit_sync_reg),
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.txdiffctrl_in(gt_txdiffctrl_reg),
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.txmaincursor_in(gt_txmaincursor_reg),
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.txprecursor_in(gt_txprecursor_reg),
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.txpostcursor_in(gt_txpostcursor_reg),
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.txprbsforceerr_in(gt_txprbsforceerr_sync_2_reg ^ gt_txprbsforceerr_sync_3_reg),
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.txprbssel_in(gt_txprbssel_sync_reg),
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.gtwiz_userdata_tx_in(gt_txdata),
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.txheader_in(gt_txheader),
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.txsequence_in(7'b0),
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// Receive
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.gtwiz_userclk_rx_reset_in(gt_rx_reset_reg),
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.gtwiz_userclk_rx_srcclk_out(),
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.gtwiz_userclk_rx_usrclk_out(),
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.gtwiz_userclk_rx_usrclk2_out(gt_rxusrclk2),
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.gtwiz_userclk_rx_active_out(gt_userclk_rx_active),
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.gtwiz_reset_rx_done_in(rx_reset_done_reg),
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.rxpd_in(gt_rx_pd_reg ? 2'b11 : 2'b00),
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.gtrxreset_in(gt_rx_reset_reg),
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.rxpmareset_in(gt_rx_pma_reset_reg),
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.rxdfelpmreset_in(gt_rx_dfe_lpm_reset_reg),
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.eyescanreset_in(gt_eyescan_reset_reg),
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.rxpcsreset_in(gt_rx_pcs_reset_reg),
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.rxresetdone_out(gt_rx_reset_done),
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.rxpmaresetdone_out(gt_rx_pma_reset_done),
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.rxprogdivreset_in(gt_rx_prgdiv_reset_reg),
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.rxprgdivresetdone_out(gt_rx_prgdiv_reset_done),
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.rxpllclksel_in(gt_rx_qpll_sel_reg ? 2'b10 : 2'b11),
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.rxsysclksel_in(gt_rx_qpll_sel_reg ? 2'b11 : 2'b10),
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.rxuserrdy_in(gt_rx_userrdy_reg),
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.rxcdrlock_out(gt_rxcdrlock),
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.rxcdrhold_in(gt_rxcdrhold_reg),
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.rxlpmen_in(gt_rxlpmen_reg),
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.dmonitorout_out(gt_dmonitorout),
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.rxpolarity_in(gt_rxpolarity_sync_reg),
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.rxprbscntreset_in(gt_rxprbscntreset_sync_2_reg ^ gt_rxprbscntreset_sync_3_reg),
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.rxprbssel_in(gt_rxprbssel_sync_reg),
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.rxprbserr_out(gt_rxprbserr),
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.rxprbslocked_out(gt_rxprbslocked),
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.eyescandataerror_out(),
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.rxgearboxslip_in(gt_rxgearboxslip),
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.gtwiz_userdata_rx_out(gt_rxdata),
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.rxdatavalid_out(gt_rxdatavalid),
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.rxheader_out(gt_rxheader),
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.rxheadervalid_out(gt_rxheadervalid),
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.rxstartofseq_out()
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);
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assign xcvr_qpll0lock_out = qpll0_lock;
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assign xcvr_qpll0clk_out = qpll0_clk;
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assign xcvr_qpll0refclk_out = qpll0_refclk;
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assign xcvr_qpll1lock_out = qpll1_lock;
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assign xcvr_qpll1clk_out = qpll1_clk;
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assign xcvr_qpll1refclk_out = qpll1_refclk;
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end else if (HAS_COMMON && GT_GTH && !GT_USP) begin : xcvr_gth_com_us
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eth_xcvr_gth_full
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eth_xcvr_gth_full_inst (
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// Common
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.gtpowergood_out(xcvr_gtpowergood_out),
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.loopback_in(gt_loopback_reg),
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// DRP
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.drpclk_common_in(drp_clk),
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.drpaddr_common_in(drp_addr_reg),
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.drpdi_common_in(drp_di_reg),
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.drpen_common_in(drp_en_reg_2),
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.drpwe_common_in(drp_we_reg),
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.drpdo_common_out(drp_do_2),
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.drprdy_common_out(drp_rdy_2),
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.drpclk_in(drp_clk),
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.drpaddr_in(drp_addr_reg),
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.drpdi_in(drp_di_reg),
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.drpen_in(drp_en_reg_1),
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.drpwe_in(drp_we_reg),
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.drpdo_out(drp_do_1),
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.drprdy_out(drp_rdy_1),
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// PLL
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.gtrefclk00_in(xcvr_gtrefclk00_in),
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.qpll0lock_out(qpll0_lock),
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.qpll0outclk_out(qpll0_clk),
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.qpll0outrefclk_out(qpll0_refclk),
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.gtrefclk01_in(xcvr_gtrefclk01_in),
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.qpll1lock_out(qpll1_lock),
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.qpll1outclk_out(qpll1_clk),
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.qpll1outrefclk_out(qpll1_refclk),
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.qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg),
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.qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg),
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.qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg),
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.qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg),
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.qpllrsvd2_in(QPLL0_EXT_CTRL ? {2'd0, xcvr_qpll0pcierate_in} : 5'd0), // [2:0] : QPLL0 rate
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.qpllrsvd3_in(QPLL1_EXT_CTRL ? {2'd0, xcvr_qpll1pcierate_in} : 5'd0), // [2:0] : QPLL1 rate
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// Serial data
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.gthtxp_out(xcvr_txp),
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.gthtxn_out(xcvr_txn),
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.gthrxp_in(xcvr_rxp),
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.gthrxn_in(xcvr_rxn),
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// Transmit
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.gtwiz_userclk_tx_reset_in(gt_tx_reset_reg),
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.gtwiz_userclk_tx_srcclk_out(),
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.gtwiz_userclk_tx_usrclk_out(),
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.gtwiz_userclk_tx_usrclk2_out(gt_txusrclk2),
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.gtwiz_userclk_tx_active_out(gt_userclk_tx_active),
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.gtwiz_reset_tx_done_in(tx_reset_done_reg),
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.txpdelecidlemode_in(1'b1),
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.txpd_in(gt_tx_pd_reg ? 2'b11 : 2'b00),
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.gttxreset_in(gt_tx_reset_reg),
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.txpmareset_in(gt_tx_pma_reset_reg),
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.txpcsreset_in(gt_tx_pcs_reset_reg),
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.txresetdone_out(gt_tx_reset_done),
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.txpmaresetdone_out(gt_tx_pma_reset_done),
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.txprogdivreset_in(gt_tx_prgdiv_reset_reg),
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.txprgdivresetdone_out(gt_tx_prgdiv_reset_done),
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.txpllclksel_in(gt_tx_qpll_sel_reg ? 2'b10 : 2'b11),
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.txsysclksel_in(gt_tx_qpll_sel_reg ? 2'b11 : 2'b10),
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.txuserrdy_in(gt_tx_userrdy_reg),
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.txpolarity_in(gt_txpolarity_sync_reg),
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.txelecidle_in(gt_txelecidle_reg),
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.txinhibit_in(gt_txinhibit_sync_reg),
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.txdiffctrl_in(gt_txdiffctrl_reg),
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.txmaincursor_in(gt_txmaincursor_reg),
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.txprecursor_in(gt_txprecursor_reg),
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.txpostcursor_in(gt_txpostcursor_reg),
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.txprbsforceerr_in(gt_txprbsforceerr_sync_2_reg ^ gt_txprbsforceerr_sync_3_reg),
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.txprbssel_in(gt_txprbssel_sync_reg),
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.gtwiz_userdata_tx_in(gt_txdata),
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.txheader_in(gt_txheader),
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.txsequence_in(7'b0),
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// Receive
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.gtwiz_userclk_rx_reset_in(gt_rx_reset_reg),
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.gtwiz_userclk_rx_srcclk_out(),
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.gtwiz_userclk_rx_usrclk_out(),
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.gtwiz_userclk_rx_usrclk2_out(gt_rxusrclk2),
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.gtwiz_userclk_rx_active_out(gt_userclk_rx_active),
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.gtwiz_reset_rx_done_in(rx_reset_done_reg),
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.rxpd_in(gt_rx_pd_reg ? 2'b11 : 2'b00),
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.gtrxreset_in(gt_rx_reset_reg),
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.rxpmareset_in(gt_rx_pma_reset_reg),
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.rxdfelpmreset_in(gt_rx_dfe_lpm_reset_reg),
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.eyescanreset_in(gt_eyescan_reset_reg),
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.rxpcsreset_in(gt_rx_pcs_reset_reg),
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.rxresetdone_out(gt_rx_reset_done),
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.rxpmaresetdone_out(gt_rx_pma_reset_done),
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.rxprogdivreset_in(gt_rx_prgdiv_reset_reg),
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.rxprgdivresetdone_out(gt_rx_prgdiv_reset_done),
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.rxpllclksel_in(gt_rx_qpll_sel_reg ? 2'b10 : 2'b11),
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.rxsysclksel_in(gt_rx_qpll_sel_reg ? 2'b11 : 2'b10),
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.rxuserrdy_in(gt_rx_userrdy_reg),
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.rxcdrlock_out(gt_rxcdrlock),
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.rxcdrhold_in(gt_rxcdrhold_reg),
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.rxlpmen_in(gt_rxlpmen_reg),
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.dmonitorout_out(gt_dmonitorout),
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.rxpolarity_in(gt_rxpolarity_sync_reg),
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.rxprbscntreset_in(gt_rxprbscntreset_sync_2_reg ^ gt_rxprbscntreset_sync_3_reg),
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.rxprbssel_in(gt_rxprbssel_sync_reg),
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.rxprbserr_out(gt_rxprbserr),
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.rxprbslocked_out(gt_rxprbslocked),
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.eyescandataerror_out(),
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.rxgearboxslip_in(gt_rxgearboxslip),
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.gtwiz_userdata_rx_out(gt_rxdata),
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.rxdatavalid_out(gt_rxdatavalid),
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.rxheader_out(gt_rxheader),
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.rxheadervalid_out(gt_rxheadervalid),
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.rxstartofseq_out()
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);
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assign xcvr_qpll0lock_out = qpll0_lock;
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assign xcvr_qpll0clk_out = qpll0_clk;
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assign xcvr_qpll0refclk_out = qpll0_refclk;
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assign xcvr_qpll1lock_out = qpll1_lock;
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assign xcvr_qpll1clk_out = qpll1_clk;
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assign xcvr_qpll1refclk_out = qpll1_refclk;
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end else if (!GT_GTH) begin : xcvr_gty
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eth_xcvr_gty_channel
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@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -986,6 +986,7 @@ qsfp0_sync_reset_inst (
|
||||
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.GT_GTH(1),
|
||||
.GT_USP(0),
|
||||
.PRBS31_ENABLE(1),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
@ -1213,6 +1214,7 @@ qsfp1_sync_reset_inst (
|
||||
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.GT_GTH(1),
|
||||
.GT_USP(0),
|
||||
.PRBS31_ENABLE(1),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -908,6 +908,7 @@ sfp_sync_reset_inst (
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.COUNT(2),
|
||||
.GT_GTH(1),
|
||||
.GT_USP(0),
|
||||
.GT_1_TX_POLARITY(1'b1),
|
||||
.GT_2_TX_POLARITY(1'b1)
|
||||
)
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -1000,6 +1000,7 @@ qsfp_sync_reset_inst (
|
||||
);
|
||||
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.GT_USP(0),
|
||||
.PRBS31_ENABLE(1),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -1123,6 +1123,7 @@ qsfp0_sync_reset_inst (
|
||||
);
|
||||
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.GT_USP(0),
|
||||
.PRBS31_ENABLE(1),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
@ -1347,6 +1348,7 @@ qsfp1_sync_reset_inst (
|
||||
);
|
||||
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.GT_USP(0),
|
||||
.PRBS31_ENABLE(1),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
@ -1571,6 +1573,7 @@ qsfp2_sync_reset_inst (
|
||||
);
|
||||
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.GT_USP(0),
|
||||
.PRBS31_ENABLE(1),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
@ -1795,6 +1798,7 @@ qsfp3_sync_reset_inst (
|
||||
);
|
||||
|
||||
eth_xcvr_phy_10g_gty_quad_wrapper #(
|
||||
.GT_USP(0),
|
||||
.PRBS31_ENABLE(1),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user