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Move TDMA registers

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This commit is contained in:
Alex Forencich 2020-05-01 16:55:57 -07:00
parent ded213460d
commit 1f76606667
3 changed files with 67 additions and 66 deletions
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56
fpga/common/rtl/port.v
View File

@ -615,36 +615,36 @@ always @(posedge clk) begin
end end
end end
16'h0080: rss_mask_reg <= axil_ctrl_wdata; // RSS mask 16'h0080: rss_mask_reg <= axil_ctrl_wdata; // RSS mask
16'h0100: begin 16'h1000: begin
// TDMA control // TDMA control
if (axil_ctrl_wstrb[0]) begin if (axil_ctrl_wstrb[0]) begin
tdma_enable_reg <= axil_ctrl_wdata[0]; tdma_enable_reg <= axil_ctrl_wdata[0];
end end
end end
16'h0114: set_tdma_schedule_start_reg[29:0] <= axil_ctrl_wdata; // TDMA schedule start ns 16'h1014: set_tdma_schedule_start_reg[29:0] <= axil_ctrl_wdata; // TDMA schedule start ns
16'h0118: set_tdma_schedule_start_reg[63:32] <= axil_ctrl_wdata; // TDMA schedule start sec l 16'h1018: set_tdma_schedule_start_reg[63:32] <= axil_ctrl_wdata; // TDMA schedule start sec l
16'h011C: begin 16'h101C: begin
// TDMA schedule start sec h // TDMA schedule start sec h
set_tdma_schedule_start_reg[79:64] <= axil_ctrl_wdata; set_tdma_schedule_start_reg[79:64] <= axil_ctrl_wdata;
set_tdma_schedule_start_valid_reg <= 1'b1; set_tdma_schedule_start_valid_reg <= 1'b1;
end end
16'h0124: set_tdma_schedule_period_reg[29:0] <= axil_ctrl_wdata; // TDMA schedule period ns 16'h1024: set_tdma_schedule_period_reg[29:0] <= axil_ctrl_wdata; // TDMA schedule period ns
16'h0128: set_tdma_schedule_period_reg[63:32] <= axil_ctrl_wdata; // TDMA schedule period sec l 16'h1028: set_tdma_schedule_period_reg[63:32] <= axil_ctrl_wdata; // TDMA schedule period sec l
16'h012C: begin 16'h102C: begin
// TDMA schedule period sec h // TDMA schedule period sec h
set_tdma_schedule_period_reg[79:64] <= axil_ctrl_wdata; set_tdma_schedule_period_reg[79:64] <= axil_ctrl_wdata;
set_tdma_schedule_period_valid_reg <= 1'b1; set_tdma_schedule_period_valid_reg <= 1'b1;
end end
16'h0134: set_tdma_timeslot_period_reg[29:0] <= axil_ctrl_wdata; // TDMA timeslot period ns 16'h1034: set_tdma_timeslot_period_reg[29:0] <= axil_ctrl_wdata; // TDMA timeslot period ns
16'h0138: set_tdma_timeslot_period_reg[63:32] <= axil_ctrl_wdata; // TDMA timeslot period sec l 16'h1038: set_tdma_timeslot_period_reg[63:32] <= axil_ctrl_wdata; // TDMA timeslot period sec l
16'h013C: begin 16'h103C: begin
// TDMA timeslot period sec h // TDMA timeslot period sec h
set_tdma_timeslot_period_reg[79:64] <= axil_ctrl_wdata; set_tdma_timeslot_period_reg[79:64] <= axil_ctrl_wdata;
set_tdma_timeslot_period_valid_reg <= 1'b1; set_tdma_timeslot_period_valid_reg <= 1'b1;
end end
16'h0144: set_tdma_active_period_reg[29:0] <= axil_ctrl_wdata; // TDMA active period ns 16'h1044: set_tdma_active_period_reg[29:0] <= axil_ctrl_wdata; // TDMA active period ns
16'h0148: set_tdma_active_period_reg[63:32] <= axil_ctrl_wdata; // TDMA active period sec l 16'h1048: set_tdma_active_period_reg[63:32] <= axil_ctrl_wdata; // TDMA active period sec l
16'h014C: begin 16'h104C: begin
// TDMA active period sec h // TDMA active period sec h
set_tdma_active_period_reg[79:64] <= axil_ctrl_wdata; set_tdma_active_period_reg[79:64] <= axil_ctrl_wdata;
set_tdma_active_period_valid_reg <= 1'b1; set_tdma_active_period_valid_reg <= 1'b1;
@ -678,28 +678,28 @@ always @(posedge clk) begin
axil_ctrl_rdata_reg[0] <= sched_enable_reg; axil_ctrl_rdata_reg[0] <= sched_enable_reg;
end end
16'h0080: axil_ctrl_rdata_reg <= rss_mask_reg; // RSS mask 16'h0080: axil_ctrl_rdata_reg <= rss_mask_reg; // RSS mask
16'h0100: begin 16'h1000: begin
// TDMA control // TDMA control
axil_ctrl_rdata_reg[0] <= tdma_enable_reg; axil_ctrl_rdata_reg[0] <= tdma_enable_reg;
end end
16'h0104: begin 16'h1004: begin
// TDMA status // TDMA status
axil_ctrl_rdata_reg[0] <= tdma_locked; axil_ctrl_rdata_reg[0] <= tdma_locked;
axil_ctrl_rdata_reg[1] <= tdma_error; axil_ctrl_rdata_reg[1] <= tdma_error;
end end
16'h0108: axil_ctrl_rdata_reg <= 2**TDMA_INDEX_WIDTH; // TDMA timeslot count 16'h1008: axil_ctrl_rdata_reg <= 2**TDMA_INDEX_WIDTH; // TDMA timeslot count
16'h0114: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[29:0]; // TDMA schedule start ns 16'h1014: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[29:0]; // TDMA schedule start ns
16'h0118: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[63:32]; // TDMA schedule start sec l 16'h1018: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[63:32]; // TDMA schedule start sec l
16'h011C: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[79:64]; // TDMA schedule start sec h 16'h101C: axil_ctrl_rdata_reg <= set_tdma_schedule_start_reg[79:64]; // TDMA schedule start sec h
16'h0124: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[29:0]; // TDMA schedule period ns 16'h1024: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[29:0]; // TDMA schedule period ns
16'h0128: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[63:32]; // TDMA schedule period sec l 16'h1028: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[63:32]; // TDMA schedule period sec l
16'h012C: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[79:64]; // TDMA schedule period sec h 16'h102C: axil_ctrl_rdata_reg <= set_tdma_schedule_period_reg[79:64]; // TDMA schedule period sec h
16'h0134: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[29:0]; // TDMA timeslot period ns 16'h1034: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[29:0]; // TDMA timeslot period ns
16'h0138: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[63:32]; // TDMA timeslot period sec l 16'h1038: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[63:32]; // TDMA timeslot period sec l
16'h013C: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[79:64]; // TDMA timeslot period sec h 16'h103C: axil_ctrl_rdata_reg <= set_tdma_timeslot_period_reg[79:64]; // TDMA timeslot period sec h
16'h0144: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[29:0]; // TDMA active period ns 16'h1044: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[29:0]; // TDMA active period ns
16'h0148: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[63:32]; // TDMA active period sec l 16'h1048: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[63:32]; // TDMA active period sec l
16'h014C: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[79:64]; // TDMA active period sec h 16'h104C: axil_ctrl_rdata_reg <= set_tdma_active_period_reg[79:64]; // TDMA active period sec h
endcase endcase
end end

39
fpga/common/tb/mqnic.py
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@ -135,25 +135,26 @@ MQNIC_PORT_REG_SCHED_OFFSET = 0x0014
MQNIC_PORT_REG_SCHED_STRIDE = 0x0018 MQNIC_PORT_REG_SCHED_STRIDE = 0x0018
MQNIC_PORT_REG_SCHED_TYPE = 0x001C MQNIC_PORT_REG_SCHED_TYPE = 0x001C
MQNIC_PORT_REG_SCHED_ENABLE = 0x0040 MQNIC_PORT_REG_SCHED_ENABLE = 0x0040
MQNIC_PORT_REG_TDMA_CTRL = 0x0100
MQNIC_PORT_REG_TDMA_STATUS = 0x0104 MQNIC_PORT_REG_TDMA_CTRL = 0x1000
MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT = 0x0108 MQNIC_PORT_REG_TDMA_STATUS = 0x1004
MQNIC_PORT_REG_TDMA_SCHED_START_FNS = 0x0110 MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT = 0x1008
MQNIC_PORT_REG_TDMA_SCHED_START_NS = 0x0114 MQNIC_PORT_REG_TDMA_SCHED_START_FNS = 0x1010
MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L = 0x0118 MQNIC_PORT_REG_TDMA_SCHED_START_NS = 0x1014
MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H = 0x011C MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L = 0x1018
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS = 0x0120 MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H = 0x101C
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS = 0x0124 MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS = 0x1020
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L = 0x0128 MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS = 0x1024
MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H = 0x012C MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L = 0x1028
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS = 0x0130 MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H = 0x102C
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS = 0x0134 MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS = 0x1030
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L = 0x0138 MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS = 0x1034
MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H = 0x013C MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L = 0x1038
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS = 0x0140 MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H = 0x103C
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS = 0x0144 MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS = 0x1040
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L = 0x0148 MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS = 0x1044
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H = 0x014C MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L = 0x1048
MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H = 0x104C
MQNIC_PORT_FEATURE_RSS = (1 << 0) MQNIC_PORT_FEATURE_RSS = (1 << 0)
MQNIC_PORT_FEATURE_PTP_TS = (1 << 4) MQNIC_PORT_FEATURE_PTP_TS = (1 << 4)

38
modules/mqnic/mqnic_hw.h
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@ -152,25 +152,25 @@ either expressed or implied, of The Regents of the University of California.
#define MQNIC_PORT_REG_RSS_MASK 0x0080 #define MQNIC_PORT_REG_RSS_MASK 0x0080
#define MQNIC_PORT_REG_TDMA_CTRL 0x0100 #define MQNIC_PORT_REG_TDMA_CTRL 0x1000
#define MQNIC_PORT_REG_TDMA_STATUS 0x0104 #define MQNIC_PORT_REG_TDMA_STATUS 0x1004
#define MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT 0x0108 #define MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT 0x1008
#define MQNIC_PORT_REG_TDMA_SCHED_START_FNS 0x0110 #define MQNIC_PORT_REG_TDMA_SCHED_START_FNS 0x1010
#define MQNIC_PORT_REG_TDMA_SCHED_START_NS 0x0114 #define MQNIC_PORT_REG_TDMA_SCHED_START_NS 0x1014
#define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L 0x0118 #define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L 0x1018
#define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H 0x011C #define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H 0x101C
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS 0x0120 #define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS 0x1020
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS 0x0124 #define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS 0x1024
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L 0x0128 #define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L 0x1028
#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H 0x012C #define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H 0x102C
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS 0x0130 #define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS 0x1030
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS 0x0134 #define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS 0x1034
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L 0x0138 #define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L 0x1038
#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H 0x013C #define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H 0x103C
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS 0x0140 #define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS 0x1040
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS 0x0144 #define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS 0x1044
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L 0x0148 #define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L 0x1048
#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H 0x014C #define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H 0x104C
#define MQNIC_PORT_FEATURE_RSS (1 << 0) #define MQNIC_PORT_FEATURE_RSS (1 << 0)
#define MQNIC_PORT_FEATURE_PTP_TS (1 << 4) #define MQNIC_PORT_FEATURE_PTP_TS (1 << 4)