mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
Update VCU1525 designs
This commit is contained in:
Alex Forencich
parent
d7e9e91644
commit
200ef77b09
1
fpga/mqnic/VCU1525/fpga_100g/app
Symbolic link
1
fpga/mqnic/VCU1525/fpga_100g/app
Symbolic link
@ -0,0 +1 @@
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../../../app/
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@ -9,26 +9,38 @@ SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/common/mqnic_core_pcie_us.v
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SYN_FILES += rtl/common/mqnic_core_pcie.v
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SYN_FILES += rtl/common/mqnic_core.v
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SYN_FILES += rtl/common/mqnic_interface.v
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SYN_FILES += rtl/common/mqnic_port.v
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SYN_FILES += rtl/common/mqnic_ptp.v
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SYN_FILES += rtl/common/mqnic_ptp_clock.v
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SYN_FILES += rtl/common/mqnic_ptp_perout.v
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SYN_FILES += rtl/common/cpl_write.v
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SYN_FILES += rtl/common/cpl_op_mux.v
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SYN_FILES += rtl/common/desc_fetch.v
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SYN_FILES += rtl/common/desc_op_mux.v
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SYN_FILES += rtl/common/event_mux.v
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SYN_FILES += rtl/common/queue_manager.v
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SYN_FILES += rtl/common/cpl_queue_manager.v
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SYN_FILES += rtl/common/event_mux.v
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SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
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SYN_FILES += rtl/common/tx_scheduler_rr.v
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SYN_FILES += rtl/common/tdma_scheduler.v
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SYN_FILES += rtl/common/tx_engine.v
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SYN_FILES += rtl/common/rx_engine.v
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SYN_FILES += rtl/common/tx_checksum.v
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SYN_FILES += rtl/common/rx_hash.v
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SYN_FILES += rtl/common/rx_checksum.v
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SYN_FILES += rtl/common/stats_counter.v
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SYN_FILES += rtl/common/stats_collect.v
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SYN_FILES += rtl/common/stats_pcie_if.v
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SYN_FILES += rtl/common/stats_pcie_tlp.v
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SYN_FILES += rtl/common/stats_dma_if_pcie.v
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SYN_FILES += rtl/common/stats_dma_latency.v
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SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
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SYN_FILES += rtl/common/tx_scheduler_rr.v
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SYN_FILES += rtl/common/cmac_pad.v
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SYN_FILES += lib/eth/rtl/ptp_clock.v
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SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
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SYN_FILES += lib/eth/rtl/ptp_perout.v
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SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
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SYN_FILES += lib/axi/rtl/axil_interconnect.v
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SYN_FILES += lib/axi/rtl/axil_crossbar.v
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@ -43,17 +55,17 @@ SYN_FILES += lib/axi/rtl/axil_register_wr.v
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SYN_FILES += lib/axi/rtl/arbiter.v
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SYN_FILES += lib/axi/rtl/priority_encoder.v
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SYN_FILES += lib/axis/rtl/axis_adapter.v
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SYN_FILES += lib/axis/rtl/axis_arb_mux.v
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SYN_FILES += lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
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SYN_FILES += lib/axis/rtl/axis_register.v
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SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
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SYN_FILES += lib/axis/rtl/sync_reset.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
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SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
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@ -66,6 +78,11 @@ SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
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SYN_FILES += lib/pcie/rtl/dma_psdpram.v
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SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
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SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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@ -78,13 +95,15 @@ XDC_FILES += boot.xdc
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XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
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XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
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XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
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# IP
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IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_1.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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199
fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
Normal file
199
fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
Normal file
@ -0,0 +1,199 @@
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# Copyright 2021, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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set params [dict create]
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# FW and board IDs
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dict set params FW_ID "32'd0"
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dict set params FW_VER "32'h00000001"
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dict set params BOARD_ID "32'h10ee95f5"
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dict set params BOARD_VER "32'h00000001"
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dict set params FPGA_ID "32'h4B31093"
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# Structural configuration
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# counts QSFP 0 QSFP 1
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# IF PORT 0_1234 1_1234
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# 1 1 0 (0.0)
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# 1 2 0 (0.0) 1 (0.1)
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# 2 1 0 (0.0) 1 (1.0)
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dict set params IF_COUNT "2"
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dict set params PORTS_PER_IF "1"
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# PTP configuration
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dict set params PTP_PEROUT_ENABLE "0"
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dict set params PTP_PEROUT_COUNT "1"
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# Queue manager configuration (interface)
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dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
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dict set params TX_QUEUE_OP_TABLE_SIZE "32"
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dict set params RX_QUEUE_OP_TABLE_SIZE "32"
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dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
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dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
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dict set params TX_QUEUE_INDEX_WIDTH "13"
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dict set params RX_QUEUE_INDEX_WIDTH "8"
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dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
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dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
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dict set params EVENT_QUEUE_PIPELINE "3"
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dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
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dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
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dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
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dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
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# TX and RX engine configuration (port)
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dict set params TX_DESC_TABLE_SIZE "32"
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dict set params RX_DESC_TABLE_SIZE "32"
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# Scheduler configuration (port)
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dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
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dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
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dict set params TDMA_INDEX_WIDTH "6"
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# Timestamping configuration (port)
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dict set params PTP_TS_ENABLE "1"
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dict set params TX_PTP_TS_FIFO_DEPTH "32"
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dict set params RX_PTP_TS_FIFO_DEPTH "32"
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# Interface configuration (port)
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dict set params TX_CHECKSUM_ENABLE "1"
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dict set params RX_RSS_ENABLE "1"
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dict set params RX_HASH_ENABLE "1"
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dict set params RX_CHECKSUM_ENABLE "1"
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dict set params TX_FIFO_DEPTH "32768"
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dict set params RX_FIFO_DEPTH "131072"
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dict set params MAX_TX_SIZE "9214"
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dict set params MAX_RX_SIZE "9214"
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dict set params TX_RAM_SIZE "131072"
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dict set params RX_RAM_SIZE "131072"
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# Application block configuration
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dict set params APP_ENABLE "0"
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dict set params APP_CTRL_ENABLE "1"
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dict set params APP_DMA_ENABLE "1"
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dict set params APP_AXIS_DIRECT_ENABLE "1"
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dict set params APP_AXIS_SYNC_ENABLE "1"
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dict set params APP_AXIS_IF_ENABLE "1"
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dict set params APP_STAT_ENABLE "1"
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# DMA interface configuration
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dict set params DMA_LEN_WIDTH "16"
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dict set params DMA_TAG_WIDTH "16"
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dict set params RAM_PIPELINE "2"
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# PCIe interface configuration
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dict set params PCIE_TAG_COUNT "64"
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dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
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dict set params PCIE_DMA_READ_TX_LIMIT "16"
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dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
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dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
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dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
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dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
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# AXI lite interface configuration (control)
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dict set params AXIL_CTRL_DATA_WIDTH "32"
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dict set params AXIL_CTRL_ADDR_WIDTH "24"
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# AXI lite interface configuration (application control)
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dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
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dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
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# Ethernet interface configuration
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dict set params AXIS_ETH_TX_PIPELINE "4"
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dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
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dict set params AXIS_ETH_TX_TS_PIPELINE "4"
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dict set params AXIS_ETH_RX_PIPELINE "4"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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dict set params STAT_ID_WIDTH "12"
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# PCIe IP core settings
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set pcie [get_ips pcie4_uscale_plus_0]
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# PCIe IDs
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set_property CONFIG.vendor_id {1234} $pcie
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set_property CONFIG.PF0_DEVICE_ID {1001} $pcie
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set_property CONFIG.PF0_CLASS_CODE {020000} $pcie
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set_property CONFIG.PF0_REVISION_ID {00} $pcie
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set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} $pcie
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set_property CONFIG.PF0_SUBSYSTEM_ID {1001} $pcie
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# Internal interface settings
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dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
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dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]
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dict set params AXIS_PCIE_RC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 75 : 161]
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dict set params AXIS_PCIE_RQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 62 : 137]
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dict set params AXIS_PCIE_CQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 85 : 183]
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dict set params AXIS_PCIE_CC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 33 : 81]
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dict set params RQ_SEQ_NUM_WIDTH [expr [dict get $params AXIS_PCIE_RQ_USER_WIDTH] == 60 ? 4 : 6]
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# configure BAR settings
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proc configure_bar {pcie pf bar aperture} {
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set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
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for { set i 0 } { $i < [llength $size_list] } { incr i } {
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set scale [lindex $size_list $i]
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if {$aperture > 0 && $aperture < ($i+1)*10} {
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set size [expr 1 << $aperture - ($i*10)]
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puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
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set_property "CONFIG.pf${pf}_bar${bar}_enabled" {true} $pcie
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set_property "CONFIG.pf${pf}_bar${bar}_type" {Memory} $pcie
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set_property "CONFIG.pf${pf}_bar${bar}_64bit" {true} $pcie
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set_property "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} $pcie
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set_property "CONFIG.pf${pf}_bar${bar}_scale" $scale $pcie
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set_property "CONFIG.pf${pf}_bar${bar}_size" $size $pcie
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return
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}
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}
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puts "${pcie} PF${pf} BAR${bar}: disabled"
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set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
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}
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# Control BAR (BAR 0)
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configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
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# Application BAR (BAR 2)
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configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
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# apply parameters to top-level
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set param_list {}
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dict for {name value} $params {
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lappend param_list $name=$value
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}
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# set_property generic $param_list [current_fileset]
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set_property generic $param_list [get_filesets sources_1]
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@ -1,34 +1,32 @@
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# Placement constraints
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#create_pblock pblock_slr0
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#add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet [list ]]
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#add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet ""]
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#resize_pblock [get_pblocks pblock_slr0] -add {SLR0}
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create_pblock pblock_slr1
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_inst]]
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_ctrl_inst]]
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_data_inst]]
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/iface[0].interface_inst]]
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/iface[1].interface_inst]]
|
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux_inst"]
|
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux.dma_if_mux_ctrl_inst"]
|
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux.dma_if_mux_data_inst"]
|
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst"]
|
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].port[*].tx_fifo_inst"]
|
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add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].port[*].rx_fifo_inst"]
|
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resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
|
||||
|
||||
#create_pblock pblock_slr2
|
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#add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list ]]
|
||||
#add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet ""]
|
||||
#resize_pblock [get_pblocks pblock_slr2] -add {SLR2}
|
||||
|
||||
create_pblock pblock_pcie
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axil_master_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_plus_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
|
||||
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
|
||||
|
||||
create_pblock pblock_eth
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list qsfp0_cmac_pad_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list core_inst/iface[0].mac[0].mac_tx_fifo_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list core_inst/iface[0].mac[0].mac_rx_fifo_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list core_inst/iface[0].mac[0].tx_ptp_ts_fifo]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list qsfp1_cmac_pad_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list core_inst/iface[1].mac[0].mac_tx_fifo_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list core_inst/iface[1].mac[0].mac_rx_fifo_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet [list core_inst/iface[1].mac[0].tx_ptp_ts_fifo]]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].port[*].tx_async_fifo_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].port[*].rx_async_fifo_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].port[*].ptp.tx_ptp_ts_fifo_inst"]
|
||||
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y10:CLOCKREGION_X0Y14}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
Copyright 2019-2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -38,7 +38,120 @@ either expressed or implied, of The Regents of the University of California.
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga (
|
||||
module fpga #
|
||||
(
|
||||
// FW and board IDs
|
||||
parameter FW_ID = 32'd0,
|
||||
parameter FW_VER = {16'd0, 16'd1},
|
||||
parameter BOARD_ID = {16'h10ee, 16'h95f5},
|
||||
parameter BOARD_VER = {16'd0, 16'd1},
|
||||
parameter FPGA_ID = 32'h4B31093,
|
||||
|
||||
// Structural configuration
|
||||
parameter IF_COUNT = 2,
|
||||
parameter PORTS_PER_IF = 1,
|
||||
|
||||
// PTP configuration
|
||||
parameter PTP_PEROUT_ENABLE = 0,
|
||||
parameter PTP_PEROUT_COUNT = 1,
|
||||
|
||||
// Queue manager configuration (interface)
|
||||
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
|
||||
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
|
||||
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
|
||||
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
|
||||
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
|
||||
parameter TX_QUEUE_INDEX_WIDTH = 13,
|
||||
parameter RX_QUEUE_INDEX_WIDTH = 8,
|
||||
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
|
||||
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
|
||||
parameter EVENT_QUEUE_PIPELINE = 3,
|
||||
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
|
||||
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
|
||||
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
|
||||
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
|
||||
|
||||
// TX and RX engine configuration (port)
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
|
||||
// Scheduler configuration (port)
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
|
||||
parameter TDMA_INDEX_WIDTH = 6,
|
||||
|
||||
// Timestamping configuration (port)
|
||||
parameter PTP_TS_ENABLE = 1,
|
||||
parameter TX_PTP_TS_FIFO_DEPTH = 32,
|
||||
parameter RX_PTP_TS_FIFO_DEPTH = 32,
|
||||
|
||||
// Interface configuration (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1,
|
||||
parameter RX_RSS_ENABLE = 1,
|
||||
parameter RX_HASH_ENABLE = 1,
|
||||
parameter RX_CHECKSUM_ENABLE = 1,
|
||||
parameter TX_FIFO_DEPTH = 32768,
|
||||
parameter RX_FIFO_DEPTH = 131072,
|
||||
parameter MAX_TX_SIZE = 9214,
|
||||
parameter MAX_RX_SIZE = 9214,
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ENABLE = 0,
|
||||
parameter APP_CTRL_ENABLE = 1,
|
||||
parameter APP_DMA_ENABLE = 1,
|
||||
parameter APP_AXIS_DIRECT_ENABLE = 1,
|
||||
parameter APP_AXIS_SYNC_ENABLE = 1,
|
||||
parameter APP_AXIS_IF_ENABLE = 1,
|
||||
parameter APP_STAT_ENABLE = 1,
|
||||
|
||||
// DMA interface configuration
|
||||
parameter DMA_LEN_WIDTH = 16,
|
||||
parameter DMA_TAG_WIDTH = 16,
|
||||
parameter RAM_PIPELINE = 2,
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 512,
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
|
||||
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
|
||||
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
|
||||
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
|
||||
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
|
||||
parameter PF_COUNT = 1,
|
||||
parameter VF_COUNT = 0,
|
||||
parameter PCIE_TAG_COUNT = 64,
|
||||
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
|
||||
parameter PCIE_DMA_READ_TX_LIMIT = 16,
|
||||
parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
|
||||
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
|
||||
parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
|
||||
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
parameter AXIL_CTRL_DATA_WIDTH = 32,
|
||||
parameter AXIL_CTRL_ADDR_WIDTH = 24,
|
||||
|
||||
// AXI lite interface configuration (application control)
|
||||
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
|
||||
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter AXIS_ETH_TX_PIPELINE = 4,
|
||||
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
|
||||
parameter AXIS_ETH_TX_TS_PIPELINE = 4,
|
||||
parameter AXIS_ETH_RX_PIPELINE = 4,
|
||||
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
|
||||
|
||||
// Statistics counter subsystem
|
||||
parameter STAT_ENABLE = 1,
|
||||
parameter STAT_DMA_ENABLE = 1,
|
||||
parameter STAT_PCIE_ENABLE = 1,
|
||||
parameter STAT_INC_WIDTH = 24,
|
||||
parameter STAT_ID_WIDTH = 12
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
@ -122,17 +235,25 @@ module fpga (
|
||||
output wire [1:0] qsfp1_fs
|
||||
);
|
||||
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 512;
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = 161;
|
||||
parameter AXIS_PCIE_RQ_USER_WIDTH = 137;
|
||||
parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
|
||||
parameter AXIS_PCIE_CC_USER_WIDTH = 81;
|
||||
parameter RQ_SEQ_NUM_WIDTH = 6;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
// PTP configuration
|
||||
parameter PTP_TS_WIDTH = 96;
|
||||
parameter PTP_TAG_WIDTH = 16;
|
||||
parameter PTP_PERIOD_NS_WIDTH = 4;
|
||||
parameter PTP_OFFSET_NS_WIDTH = 32;
|
||||
parameter PTP_FNS_WIDTH = 32;
|
||||
parameter PTP_PERIOD_NS = 4'd4;
|
||||
parameter PTP_PERIOD_FNS = 32'd0;
|
||||
parameter PTP_USE_SAMPLE_CLOCK = 0;
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter MSI_COUNT = 32;
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter AXIS_ETH_DATA_WIDTH = 512;
|
||||
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
|
||||
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
|
||||
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
|
||||
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -766,17 +887,18 @@ wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep_int;
|
||||
wire qsfp0_tx_axis_tvalid_int;
|
||||
wire qsfp0_tx_axis_tready_int;
|
||||
wire qsfp0_tx_axis_tlast_int;
|
||||
wire qsfp0_tx_axis_tuser_int;
|
||||
wire [16+1-1:0] qsfp0_tx_axis_tuser_int;
|
||||
|
||||
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_mac_tx_axis_tdata;
|
||||
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_mac_tx_axis_tkeep;
|
||||
wire qsfp0_mac_tx_axis_tvalid;
|
||||
wire qsfp0_mac_tx_axis_tready;
|
||||
wire qsfp0_mac_tx_axis_tlast;
|
||||
wire qsfp0_mac_tx_axis_tuser;
|
||||
wire [16+1-1:0] qsfp0_mac_tx_axis_tuser;
|
||||
|
||||
wire [79:0] qsfp0_tx_ptp_time_int;
|
||||
wire [79:0] qsfp0_tx_ptp_ts_int;
|
||||
wire [15:0] qsfp0_tx_ptp_ts_tag_int;
|
||||
wire qsfp0_tx_ptp_ts_valid_int;
|
||||
|
||||
wire qsfp0_rx_clk_int;
|
||||
@ -801,17 +923,18 @@ wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep_int;
|
||||
wire qsfp1_tx_axis_tvalid_int;
|
||||
wire qsfp1_tx_axis_tready_int;
|
||||
wire qsfp1_tx_axis_tlast_int;
|
||||
wire qsfp1_tx_axis_tuser_int;
|
||||
wire [16+1-1:0] qsfp1_tx_axis_tuser_int;
|
||||
|
||||
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_tx_axis_tdata;
|
||||
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_tx_axis_tkeep;
|
||||
wire qsfp1_mac_tx_axis_tvalid;
|
||||
wire qsfp1_mac_tx_axis_tready;
|
||||
wire qsfp1_mac_tx_axis_tlast;
|
||||
wire qsfp1_mac_tx_axis_tuser;
|
||||
wire [16+1-1:0] qsfp1_mac_tx_axis_tuser;
|
||||
|
||||
wire [79:0] qsfp1_tx_ptp_time_int;
|
||||
wire [79:0] qsfp1_tx_ptp_ts_int;
|
||||
wire [15:0] qsfp1_tx_ptp_ts_tag_int;
|
||||
wire qsfp1_tx_ptp_ts_valid_int;
|
||||
|
||||
wire qsfp1_rx_clk_int;
|
||||
@ -841,7 +964,7 @@ assign qsfp1_rx_clk_int = qsfp1_txuserclk2;
|
||||
cmac_pad #(
|
||||
.DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
|
||||
.KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
|
||||
.USER_WIDTH(1)
|
||||
.USER_WIDTH(16+1)
|
||||
)
|
||||
qsfp0_cmac_pad_inst (
|
||||
.clk(qsfp0_tx_clk_int),
|
||||
@ -925,7 +1048,8 @@ qsfp0_cmac_inst (
|
||||
.rx_lane_aligner_fill_9(), // output [6:0]
|
||||
.rx_ptp_tstamp_out(qsfp0_rx_axis_tuser_int[80:1]), // output [79:0]
|
||||
.rx_ptp_pcslane_out(), // output [4:0]
|
||||
.ctl_rx_systemtimerin(qsfp0_rx_ptp_time_int), // input [79:0]
|
||||
// RX fed from TX clock, so use same PTP time source
|
||||
.ctl_rx_systemtimerin(qsfp0_tx_ptp_time_int), // input [79:0]
|
||||
|
||||
.stat_rx_aligned(), // output
|
||||
.stat_rx_aligned_err(), // output
|
||||
@ -1097,10 +1221,10 @@ qsfp0_cmac_inst (
|
||||
|
||||
.tx_ptp_tstamp_valid_out(qsfp0_tx_ptp_ts_valid_int), // output
|
||||
.tx_ptp_pcslane_out(), // output [4:0]
|
||||
.tx_ptp_tstamp_tag_out(), // output [15:0]
|
||||
.tx_ptp_tstamp_tag_out(qsfp0_tx_ptp_ts_tag_int), // output [15:0]
|
||||
.tx_ptp_tstamp_out(qsfp0_tx_ptp_ts_int), // output [79:0]
|
||||
.tx_ptp_1588op_in(2'b10), // input [1:0]
|
||||
.tx_ptp_tag_field_in(16'd0), // input [15:0]
|
||||
.tx_ptp_tag_field_in(qsfp0_mac_tx_axis_tuser[16:1]), // input [15:0]
|
||||
|
||||
.stat_tx_bad_fcs(), // output
|
||||
.stat_tx_broadcast(), // output
|
||||
@ -1141,7 +1265,7 @@ qsfp0_cmac_inst (
|
||||
.tx_axis_tdata(qsfp0_mac_tx_axis_tdata), // input [511:0]
|
||||
.tx_axis_tlast(qsfp0_mac_tx_axis_tlast), // input
|
||||
.tx_axis_tkeep(qsfp0_mac_tx_axis_tkeep), // input [63:0]
|
||||
.tx_axis_tuser(qsfp0_mac_tx_axis_tuser), // input
|
||||
.tx_axis_tuser(qsfp0_mac_tx_axis_tuser[0]), // input
|
||||
|
||||
.tx_ovfout(), // output
|
||||
.tx_unfout(), // output
|
||||
@ -1161,7 +1285,7 @@ qsfp0_cmac_inst (
|
||||
cmac_pad #(
|
||||
.DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
|
||||
.KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
|
||||
.USER_WIDTH(1)
|
||||
.USER_WIDTH(16+1)
|
||||
)
|
||||
qsfp1_cmac_pad_inst (
|
||||
.clk(qsfp1_tx_clk_int),
|
||||
@ -1245,7 +1369,8 @@ qsfp1_cmac_inst (
|
||||
.rx_lane_aligner_fill_9(), // output [6:0]
|
||||
.rx_ptp_tstamp_out(qsfp1_rx_axis_tuser_int[80:1]), // output [79:0]
|
||||
.rx_ptp_pcslane_out(), // output [4:0]
|
||||
.ctl_rx_systemtimerin(qsfp1_rx_ptp_time_int), // input [79:0]
|
||||
// RX fed from TX clock, so use same PTP time source
|
||||
.ctl_rx_systemtimerin(qsfp1_tx_ptp_time_int), // input [79:0]
|
||||
|
||||
.stat_rx_aligned(), // output
|
||||
.stat_rx_aligned_err(), // output
|
||||
@ -1417,10 +1542,10 @@ qsfp1_cmac_inst (
|
||||
|
||||
.tx_ptp_tstamp_valid_out(qsfp1_tx_ptp_ts_valid_int), // output
|
||||
.tx_ptp_pcslane_out(), // output [4:0]
|
||||
.tx_ptp_tstamp_tag_out(), // output [15:0]
|
||||
.tx_ptp_tstamp_tag_out(qsfp1_tx_ptp_ts_tag_int), // output [15:0]
|
||||
.tx_ptp_tstamp_out(qsfp1_tx_ptp_ts_int), // output [79:0]
|
||||
.tx_ptp_1588op_in(2'b10), // input [1:0]
|
||||
.tx_ptp_tag_field_in(16'd0), // input [15:0]
|
||||
.tx_ptp_tag_field_in(qsfp1_mac_tx_axis_tuser[16:1]), // input [15:0]
|
||||
|
||||
.stat_tx_bad_fcs(), // output
|
||||
.stat_tx_broadcast(), // output
|
||||
@ -1461,7 +1586,7 @@ qsfp1_cmac_inst (
|
||||
.tx_axis_tdata(qsfp1_mac_tx_axis_tdata), // input [511:0]
|
||||
.tx_axis_tlast(qsfp1_mac_tx_axis_tlast), // input
|
||||
.tx_axis_tkeep(qsfp1_mac_tx_axis_tkeep), // input [63:0]
|
||||
.tx_axis_tuser(qsfp1_mac_tx_axis_tuser), // input
|
||||
.tx_axis_tuser(qsfp1_mac_tx_axis_tuser[0]), // input
|
||||
|
||||
.tx_ovfout(), // output
|
||||
.tx_unfout(), // output
|
||||
@ -1485,6 +1610,86 @@ assign led[1] = qsfp1_rx_status; // yellow
|
||||
assign led[2] = qsfp0_rx_status; // green
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.FPGA_ID(FPGA_ID),
|
||||
|
||||
// Structural configuration
|
||||
.IF_COUNT(IF_COUNT),
|
||||
.PORTS_PER_IF(PORTS_PER_IF),
|
||||
|
||||
// PTP configuration
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
|
||||
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
|
||||
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
|
||||
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
|
||||
.PTP_PERIOD_NS(PTP_PERIOD_NS),
|
||||
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
|
||||
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
|
||||
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
|
||||
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
|
||||
|
||||
// Queue manager configuration (interface)
|
||||
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
|
||||
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
|
||||
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
|
||||
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
|
||||
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
|
||||
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
|
||||
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
|
||||
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
|
||||
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
|
||||
|
||||
// TX and RX engine configuration (port)
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
|
||||
// Scheduler configuration (port)
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
|
||||
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
|
||||
|
||||
// Timestamping configuration (port)
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
|
||||
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
|
||||
|
||||
// Interface configuration (port)
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
|
||||
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
|
||||
.MAX_TX_SIZE(MAX_TX_SIZE),
|
||||
.MAX_RX_SIZE(MAX_RX_SIZE),
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
|
||||
.APP_DMA_ENABLE(APP_DMA_ENABLE),
|
||||
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
|
||||
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
|
||||
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
|
||||
.APP_STAT_ENABLE(APP_STAT_ENABLE),
|
||||
|
||||
// DMA interface configuration
|
||||
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
|
||||
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
|
||||
// PCIe interface configuration
|
||||
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
||||
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
|
||||
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
|
||||
@ -1492,7 +1697,43 @@ fpga_core #(
|
||||
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
|
||||
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
|
||||
.BAR0_APERTURE(BAR0_APERTURE)
|
||||
.PF_COUNT(PF_COUNT),
|
||||
.VF_COUNT(VF_COUNT),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
|
||||
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
|
||||
.PCIE_DMA_READ_TX_FC_ENABLE(PCIE_DMA_READ_TX_FC_ENABLE),
|
||||
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
|
||||
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
|
||||
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
|
||||
.MSI_COUNT(MSI_COUNT),
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
|
||||
|
||||
// AXI lite interface configuration (application control)
|
||||
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
|
||||
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
|
||||
|
||||
// Ethernet interface configuration
|
||||
.AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
|
||||
.AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
|
||||
.AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
|
||||
.AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
|
||||
.AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
|
||||
.AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
|
||||
.AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
|
||||
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
|
||||
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
|
||||
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
|
||||
|
||||
// Statistics counter subsystem
|
||||
.STAT_ENABLE(STAT_ENABLE),
|
||||
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
|
||||
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
|
||||
.STAT_INC_WIDTH(STAT_INC_WIDTH),
|
||||
.STAT_ID_WIDTH(STAT_ID_WIDTH)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -1610,6 +1851,7 @@ core_inst (
|
||||
.qsfp0_tx_axis_tuser(qsfp0_tx_axis_tuser_int),
|
||||
.qsfp0_tx_ptp_time(qsfp0_tx_ptp_time_int),
|
||||
.qsfp0_tx_ptp_ts(qsfp0_tx_ptp_ts_int),
|
||||
.qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int),
|
||||
.qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int),
|
||||
.qsfp0_rx_clk(qsfp0_rx_clk_int),
|
||||
.qsfp0_rx_rst(qsfp0_rx_rst_int),
|
||||
@ -1635,6 +1877,7 @@ core_inst (
|
||||
.qsfp1_tx_axis_tuser(qsfp1_tx_axis_tuser_int),
|
||||
.qsfp1_tx_ptp_time(qsfp1_tx_ptp_time_int),
|
||||
.qsfp1_tx_ptp_ts(qsfp1_tx_ptp_ts_int),
|
||||
.qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int),
|
||||
.qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int),
|
||||
.qsfp1_rx_clk(qsfp1_rx_clk_int),
|
||||
.qsfp1_rx_rst(qsfp1_rx_rst_int),
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
# Copyright 2020, The Regents of the University of California.
|
||||
# Copyright 2020-2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
@ -39,12 +39,19 @@ DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
|
||||
@ -52,12 +59,14 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
|
||||
@ -79,14 +88,12 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_register.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
@ -99,35 +106,188 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT ?= 2
|
||||
export PARAM_PORTS_PER_IF ?= 1
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_PEROUT_ENABLE ?= 0
|
||||
export PARAM_PTP_PEROUT_COUNT ?= 1
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
|
||||
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
|
||||
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
export PARAM_TX_DESC_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE ?= 32
|
||||
|
||||
# Scheduler configuration (port)
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH ?= 6
|
||||
|
||||
# Timestamping configuration (port)
|
||||
export PARAM_PTP_TS_ENABLE ?= 1
|
||||
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
|
||||
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
|
||||
|
||||
# Interface configuration (port)
|
||||
export PARAM_TX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_RX_RSS_ENABLE ?= 1
|
||||
export PARAM_RX_HASH_ENABLE ?= 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_TX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_RX_FIFO_DEPTH ?= 131072
|
||||
export PARAM_MAX_TX_SIZE ?= 9214
|
||||
export PARAM_MAX_RX_SIZE ?= 9214
|
||||
export PARAM_TX_RAM_SIZE ?= 131072
|
||||
export PARAM_RX_RAM_SIZE ?= 131072
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ENABLE ?= 0
|
||||
export PARAM_APP_CTRL_ENABLE ?= 1
|
||||
export PARAM_APP_DMA_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE ?= 1
|
||||
export PARAM_APP_STAT_ENABLE ?= 1
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_LEN_WIDTH ?= 16
|
||||
export PARAM_DMA_TAG_WIDTH ?= 16
|
||||
export PARAM_RAM_PIPELINE ?= 2
|
||||
|
||||
# PCIe interface configuration
|
||||
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
|
||||
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
|
||||
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
|
||||
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
|
||||
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
|
||||
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
|
||||
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_AXIS_ETH_DATA_WIDTH = 512
|
||||
export PARAM_AXIS_ETH_KEEP_WIDTH = $(shell expr $(PARAM_AXIS_ETH_DATA_WIDTH) / 8 )
|
||||
export PARAM_PF_COUNT ?= 1
|
||||
export PARAM_VF_COUNT ?= 0
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
|
||||
export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
|
||||
export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
|
||||
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
|
||||
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
|
||||
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 4
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE ?= 1
|
||||
export PARAM_STAT_DMA_ENABLE ?= 1
|
||||
export PARAM_STAT_PCIE_ENABLE ?= 1
|
||||
export PARAM_STAT_INC_WIDTH ?= 24
|
||||
export PARAM_STAT_ID_WIDTH ?= 12
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_KEEP_WIDTH=$(PARAM_AXIS_ETH_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -136,16 +296,76 @@ ifeq ($(SIM), icarus)
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
|
||||
COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_KEEP_WIDTH=$(PARAM_AXIS_ETH_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
"""
|
||||
|
||||
Copyright 2020, The Regents of the University of California.
|
||||
Copyright 2020-2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -66,8 +66,6 @@ class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.BAR0_APERTURE = int(os.getenv("PARAM_BAR0_APERTURE"))
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
@ -266,7 +264,9 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True)
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
|
||||
# Ethernet
|
||||
cocotb.fork(Clock(dut.qsfp0_rx_clk, 3.102, units="ns").start())
|
||||
@ -278,6 +278,7 @@ class TB(object):
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp0_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp0_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp0_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp0_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp0_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp0_rx_clk,
|
||||
rx_rst=dut.qsfp0_rx_rst,
|
||||
@ -295,6 +296,7 @@ class TB(object):
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp1_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp1_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp1_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp1_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp1_rx_clk,
|
||||
rx_rst=dut.qsfp1_rx_rst,
|
||||
@ -501,6 +503,7 @@ async def run_test_nic(dut):
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
@ -514,12 +517,19 @@ def test_fpga_core(request):
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_engine.v"),
|
||||
@ -527,12 +537,14 @@ def test_fpga_core(request):
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_perout.v"),
|
||||
@ -554,14 +566,12 @@ def test_fpga_core(request):
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
@ -574,6 +584,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
@ -581,16 +596,103 @@ def test_fpga_core(request):
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = 2
|
||||
parameters['PORTS_PER_IF'] = 1
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_PEROUT_ENABLE'] = 0
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
|
||||
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
|
||||
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
|
||||
parameters['EVENT_QUEUE_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
|
||||
# Scheduler configuration (port)
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Timestamping configuration (port)
|
||||
parameters['PTP_TS_ENABLE'] = 1
|
||||
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
|
||||
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
|
||||
|
||||
# Interface configuration (port)
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_RSS_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 131072
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 131072
|
||||
parameters['RX_RAM_SIZE'] = 131072
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
# PCIe interface configuration
|
||||
parameters['AXIS_PCIE_DATA_WIDTH'] = 512
|
||||
parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
|
||||
parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
|
||||
parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161
|
||||
parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183
|
||||
parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81
|
||||
parameters['RQ_SEQ_NUM_WIDTH'] = 6
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['AXIS_ETH_DATA_WIDTH'] = 512
|
||||
parameters['AXIS_ETH_KEEP_WIDTH'] = parameters['AXIS_ETH_DATA_WIDTH'] // 8
|
||||
parameters['PF_COUNT'] = 1
|
||||
parameters['VF_COUNT'] = 0
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
|
||||
parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
|
||||
parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
|
||||
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
|
||||
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
|
||||
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 1
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_PCIE_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 12
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
1
fpga/mqnic/VCU1525/fpga_10g/app
Symbolic link
1
fpga/mqnic/VCU1525/fpga_10g/app
Symbolic link
@ -0,0 +1 @@
|
||||
../../../app/
|
||||
@ -9,27 +9,38 @@ SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
@ -44,6 +55,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
@ -58,17 +70,17 @@ SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
@ -81,6 +93,11 @@ SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
@ -99,6 +116,9 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
|
||||
216
fpga/mqnic/VCU1525/fpga_10g/fpga/config.tcl
Normal file
216
fpga/mqnic/VCU1525/fpga_10g/fpga/config.tcl
Normal file
@ -0,0 +1,216 @@
|
||||
# Copyright 2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# FW and board IDs
|
||||
dict set params FW_ID "32'd0"
|
||||
dict set params FW_VER "32'h00000001"
|
||||
dict set params BOARD_ID "32'h10ee95f5"
|
||||
dict set params BOARD_VER "32'h00000001"
|
||||
dict set params FPGA_ID "32'h4B31093"
|
||||
|
||||
# Structural configuration
|
||||
|
||||
# counts QSFP 0 QSFP 1
|
||||
# IF PORT 0_1 0_2 0_3 0_4 1_1 1_2 1_3 1_4
|
||||
# 1 1 0 (0.0)
|
||||
# 1 2 0 (0.0) 1 (0.1)
|
||||
# 1 3 0 (0.0) 1 (0.1) 2 (0.2)
|
||||
# 1 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3)
|
||||
# 1 5 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4)
|
||||
# 1 6 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5)
|
||||
# 1 7 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6)
|
||||
# 1 8 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6) 7 (0.7)
|
||||
# 2 1 0 (0.0) 1 (1.0)
|
||||
# 2 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1)
|
||||
# 2 3 0 (0.0) 1 (0.1) 2 (0.2) 3 (1.0) 4 (1.1) 5 (1.2)
|
||||
# 2 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (1.0) 5 (1.1) 6 (1.2) 7 (1.3)
|
||||
# 3 1 0 (0.0) 1 (1.0) 2 (2.0)
|
||||
# 3 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1)
|
||||
# 4 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0)
|
||||
# 4 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1) 6 (3.0) 7 (3.1)
|
||||
# 5 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0)
|
||||
# 6 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0)
|
||||
# 7 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0)
|
||||
# 8 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0) 7 (7.0)
|
||||
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_PEROUT_ENABLE "0"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "13"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration (port)
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Timestamping configuration (port)
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_PTP_TS_FIFO_DEPTH "32"
|
||||
dict set params RX_PTP_TS_FIFO_DEPTH "32"
|
||||
|
||||
# Interface configuration (port)
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params PCIE_TAG_COUNT "64"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_TX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "1"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
# PCIe IDs
|
||||
set_property CONFIG.vendor_id {1234} $pcie
|
||||
set_property CONFIG.PF0_DEVICE_ID {1001} $pcie
|
||||
set_property CONFIG.PF0_CLASS_CODE {020000} $pcie
|
||||
set_property CONFIG.PF0_REVISION_ID {00} $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_ID {1001} $pcie
|
||||
|
||||
# Internal interface settings
|
||||
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
|
||||
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]
|
||||
dict set params AXIS_PCIE_RC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 75 : 161]
|
||||
dict set params AXIS_PCIE_RQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 62 : 137]
|
||||
dict set params AXIS_PCIE_CQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 85 : 183]
|
||||
dict set params AXIS_PCIE_CC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 33 : 81]
|
||||
dict set params RQ_SEQ_NUM_WIDTH [expr [dict get $params AXIS_PCIE_RQ_USER_WIDTH] == 60 ? 4 : 6]
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {pcie pf bar aperture} {
|
||||
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||
set scale [lindex $size_list $i]
|
||||
|
||||
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||
set size [expr 1 << $aperture - ($i*10)]
|
||||
|
||||
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {true} $pcie
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_type" {Memory} $pcie
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_64bit" {true} $pcie
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} $pcie
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_scale" $scale $pcie
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_size" $size $pcie
|
||||
|
||||
return
|
||||
}
|
||||
}
|
||||
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
# set_property generic $param_list [current_fileset]
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
@ -1,23 +1,24 @@
|
||||
# Placement constraints
|
||||
#create_pblock pblock_slr0
|
||||
#add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet [list ]]
|
||||
#add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet ""]
|
||||
#resize_pblock [get_pblocks pblock_slr0] -add {SLR0}
|
||||
|
||||
create_pblock pblock_slr1
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_ctrl_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_data_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/iface[0].interface_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/iface[1].interface_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux.dma_if_mux_ctrl_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux.dma_if_mux_data_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].port[*].tx_fifo_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].port[*].rx_fifo_inst"]
|
||||
resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
|
||||
|
||||
#create_pblock pblock_slr2
|
||||
#add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list ]]
|
||||
#add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet ""]
|
||||
#resize_pblock [get_pblocks pblock_slr2] -add {SLR2}
|
||||
|
||||
create_pblock pblock_pcie
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axil_master_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_plus_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
|
||||
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
Copyright 2019-2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -38,7 +38,120 @@ either expressed or implied, of The Regents of the University of California.
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga (
|
||||
module fpga #
|
||||
(
|
||||
// FW and board IDs
|
||||
parameter FW_ID = 32'd0,
|
||||
parameter FW_VER = {16'd0, 16'd1},
|
||||
parameter BOARD_ID = {16'h10ee, 16'h95f5},
|
||||
parameter BOARD_VER = {16'd0, 16'd1},
|
||||
parameter FPGA_ID = 32'h4B31093,
|
||||
|
||||
// Structural configuration
|
||||
parameter IF_COUNT = 2,
|
||||
parameter PORTS_PER_IF = 1,
|
||||
|
||||
// PTP configuration
|
||||
parameter PTP_PEROUT_ENABLE = 0,
|
||||
parameter PTP_PEROUT_COUNT = 1,
|
||||
|
||||
// Queue manager configuration (interface)
|
||||
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
|
||||
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
|
||||
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
|
||||
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
|
||||
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
|
||||
parameter TX_QUEUE_INDEX_WIDTH = 13,
|
||||
parameter RX_QUEUE_INDEX_WIDTH = 8,
|
||||
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
|
||||
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
|
||||
parameter EVENT_QUEUE_PIPELINE = 3,
|
||||
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
|
||||
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
|
||||
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
|
||||
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
|
||||
|
||||
// TX and RX engine configuration (port)
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
|
||||
// Scheduler configuration (port)
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
|
||||
parameter TDMA_INDEX_WIDTH = 6,
|
||||
|
||||
// Timestamping configuration (port)
|
||||
parameter PTP_TS_ENABLE = 1,
|
||||
parameter TX_PTP_TS_FIFO_DEPTH = 32,
|
||||
parameter RX_PTP_TS_FIFO_DEPTH = 32,
|
||||
|
||||
// Interface configuration (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1,
|
||||
parameter RX_RSS_ENABLE = 1,
|
||||
parameter RX_HASH_ENABLE = 1,
|
||||
parameter RX_CHECKSUM_ENABLE = 1,
|
||||
parameter TX_FIFO_DEPTH = 32768,
|
||||
parameter RX_FIFO_DEPTH = 32768,
|
||||
parameter MAX_TX_SIZE = 9214,
|
||||
parameter MAX_RX_SIZE = 9214,
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ENABLE = 0,
|
||||
parameter APP_CTRL_ENABLE = 1,
|
||||
parameter APP_DMA_ENABLE = 1,
|
||||
parameter APP_AXIS_DIRECT_ENABLE = 1,
|
||||
parameter APP_AXIS_SYNC_ENABLE = 1,
|
||||
parameter APP_AXIS_IF_ENABLE = 1,
|
||||
parameter APP_STAT_ENABLE = 1,
|
||||
|
||||
// DMA interface configuration
|
||||
parameter DMA_LEN_WIDTH = 16,
|
||||
parameter DMA_TAG_WIDTH = 16,
|
||||
parameter RAM_PIPELINE = 2,
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 512,
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
|
||||
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
|
||||
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
|
||||
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
|
||||
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
|
||||
parameter PF_COUNT = 1,
|
||||
parameter VF_COUNT = 0,
|
||||
parameter PCIE_TAG_COUNT = 64,
|
||||
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
|
||||
parameter PCIE_DMA_READ_TX_LIMIT = 16,
|
||||
parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
|
||||
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
|
||||
parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
|
||||
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
parameter AXIL_CTRL_DATA_WIDTH = 32,
|
||||
parameter AXIL_CTRL_ADDR_WIDTH = 24,
|
||||
|
||||
// AXI lite interface configuration (application control)
|
||||
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
|
||||
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter AXIS_ETH_TX_PIPELINE = 4,
|
||||
parameter AXIS_ETH_TX_FIFO_PIPELINE = 4,
|
||||
parameter AXIS_ETH_TX_TS_PIPELINE = 4,
|
||||
parameter AXIS_ETH_RX_PIPELINE = 4,
|
||||
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
|
||||
|
||||
// Statistics counter subsystem
|
||||
parameter STAT_ENABLE = 1,
|
||||
parameter STAT_DMA_ENABLE = 1,
|
||||
parameter STAT_PCIE_ENABLE = 1,
|
||||
parameter STAT_INC_WIDTH = 24,
|
||||
parameter STAT_ID_WIDTH = 12
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
@ -122,14 +235,29 @@ module fpga (
|
||||
output wire [1:0] qsfp1_fs
|
||||
);
|
||||
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 512;
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = 161;
|
||||
parameter AXIS_PCIE_RQ_USER_WIDTH = 137;
|
||||
parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
|
||||
parameter AXIS_PCIE_CC_USER_WIDTH = 81;
|
||||
parameter RQ_SEQ_NUM_WIDTH = 6;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
// PTP configuration
|
||||
parameter PTP_TS_WIDTH = 96;
|
||||
parameter PTP_TAG_WIDTH = 16;
|
||||
parameter PTP_PERIOD_NS_WIDTH = 4;
|
||||
parameter PTP_OFFSET_NS_WIDTH = 32;
|
||||
parameter PTP_FNS_WIDTH = 32;
|
||||
parameter PTP_PERIOD_NS = 4'd4;
|
||||
parameter PTP_PERIOD_FNS = 32'd0;
|
||||
parameter PTP_USE_SAMPLE_CLOCK = 0;
|
||||
parameter IF_PTP_PERIOD_NS = 6'h6;
|
||||
parameter IF_PTP_PERIOD_FNS = 16'h6666;
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter MSI_COUNT = 32;
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter XGMII_DATA_WIDTH = 64;
|
||||
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
|
||||
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
|
||||
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
|
||||
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
|
||||
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
|
||||
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -757,46 +885,46 @@ assign qsfp0_fs = 2'b10;
|
||||
|
||||
wire qsfp0_tx_clk_1_int;
|
||||
wire qsfp0_tx_rst_1_int;
|
||||
wire [63:0] qsfp0_txd_1_int;
|
||||
wire [7:0] qsfp0_txc_1_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
|
||||
wire qsfp0_tx_prbs31_enable_1_int;
|
||||
wire qsfp0_rx_clk_1_int;
|
||||
wire qsfp0_rx_rst_1_int;
|
||||
wire [63:0] qsfp0_rxd_1_int;
|
||||
wire [7:0] qsfp0_rxc_1_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
|
||||
wire qsfp0_rx_prbs31_enable_1_int;
|
||||
wire [6:0] qsfp0_rx_error_count_1_int;
|
||||
wire qsfp0_tx_clk_2_int;
|
||||
wire qsfp0_tx_rst_2_int;
|
||||
wire [63:0] qsfp0_txd_2_int;
|
||||
wire [7:0] qsfp0_txc_2_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
|
||||
wire qsfp0_tx_prbs31_enable_2_int;
|
||||
wire qsfp0_rx_clk_2_int;
|
||||
wire qsfp0_rx_rst_2_int;
|
||||
wire [63:0] qsfp0_rxd_2_int;
|
||||
wire [7:0] qsfp0_rxc_2_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
|
||||
wire qsfp0_rx_prbs31_enable_2_int;
|
||||
wire [6:0] qsfp0_rx_error_count_2_int;
|
||||
wire qsfp0_tx_clk_3_int;
|
||||
wire qsfp0_tx_rst_3_int;
|
||||
wire [63:0] qsfp0_txd_3_int;
|
||||
wire [7:0] qsfp0_txc_3_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
|
||||
wire qsfp0_tx_prbs31_enable_3_int;
|
||||
wire qsfp0_rx_clk_3_int;
|
||||
wire qsfp0_rx_rst_3_int;
|
||||
wire [63:0] qsfp0_rxd_3_int;
|
||||
wire [7:0] qsfp0_rxc_3_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
|
||||
wire qsfp0_rx_prbs31_enable_3_int;
|
||||
wire [6:0] qsfp0_rx_error_count_3_int;
|
||||
wire qsfp0_tx_clk_4_int;
|
||||
wire qsfp0_tx_rst_4_int;
|
||||
wire [63:0] qsfp0_txd_4_int;
|
||||
wire [7:0] qsfp0_txc_4_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
|
||||
wire qsfp0_tx_prbs31_enable_4_int;
|
||||
wire qsfp0_rx_clk_4_int;
|
||||
wire qsfp0_rx_rst_4_int;
|
||||
wire [63:0] qsfp0_rxd_4_int;
|
||||
wire [7:0] qsfp0_rxc_4_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
|
||||
wire qsfp0_rx_prbs31_enable_4_int;
|
||||
wire [6:0] qsfp0_rx_error_count_4_int;
|
||||
|
||||
@ -805,46 +933,46 @@ assign qsfp1_fs = 2'b10;
|
||||
|
||||
wire qsfp1_tx_clk_1_int;
|
||||
wire qsfp1_tx_rst_1_int;
|
||||
wire [63:0] qsfp1_txd_1_int;
|
||||
wire [7:0] qsfp1_txc_1_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
|
||||
wire qsfp1_tx_prbs31_enable_1_int;
|
||||
wire qsfp1_rx_clk_1_int;
|
||||
wire qsfp1_rx_rst_1_int;
|
||||
wire [63:0] qsfp1_rxd_1_int;
|
||||
wire [7:0] qsfp1_rxc_1_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
|
||||
wire qsfp1_rx_prbs31_enable_1_int;
|
||||
wire [6:0] qsfp1_rx_error_count_1_int;
|
||||
wire qsfp1_tx_clk_2_int;
|
||||
wire qsfp1_tx_rst_2_int;
|
||||
wire [63:0] qsfp1_txd_2_int;
|
||||
wire [7:0] qsfp1_txc_2_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
|
||||
wire qsfp1_tx_prbs31_enable_2_int;
|
||||
wire qsfp1_rx_clk_2_int;
|
||||
wire qsfp1_rx_rst_2_int;
|
||||
wire [63:0] qsfp1_rxd_2_int;
|
||||
wire [7:0] qsfp1_rxc_2_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
|
||||
wire qsfp1_rx_prbs31_enable_2_int;
|
||||
wire [6:0] qsfp1_rx_error_count_2_int;
|
||||
wire qsfp1_tx_clk_3_int;
|
||||
wire qsfp1_tx_rst_3_int;
|
||||
wire [63:0] qsfp1_txd_3_int;
|
||||
wire [7:0] qsfp1_txc_3_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
|
||||
wire qsfp1_tx_prbs31_enable_3_int;
|
||||
wire qsfp1_rx_clk_3_int;
|
||||
wire qsfp1_rx_rst_3_int;
|
||||
wire [63:0] qsfp1_rxd_3_int;
|
||||
wire [7:0] qsfp1_rxc_3_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
|
||||
wire qsfp1_rx_prbs31_enable_3_int;
|
||||
wire [6:0] qsfp1_rx_error_count_3_int;
|
||||
wire qsfp1_tx_clk_4_int;
|
||||
wire qsfp1_tx_rst_4_int;
|
||||
wire [63:0] qsfp1_txd_4_int;
|
||||
wire [7:0] qsfp1_txc_4_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
|
||||
wire qsfp1_tx_prbs31_enable_4_int;
|
||||
wire qsfp1_rx_clk_4_int;
|
||||
wire qsfp1_rx_rst_4_int;
|
||||
wire [63:0] qsfp1_rxd_4_int;
|
||||
wire [7:0] qsfp1_rxc_4_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
|
||||
wire qsfp1_rx_prbs31_enable_4_int;
|
||||
wire [6:0] qsfp1_rx_error_count_4_int;
|
||||
|
||||
@ -1395,6 +1523,86 @@ qsfp1_phy_4_inst (
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.FPGA_ID(FPGA_ID),
|
||||
|
||||
// Structural configuration
|
||||
.IF_COUNT(IF_COUNT),
|
||||
.PORTS_PER_IF(PORTS_PER_IF),
|
||||
|
||||
// PTP configuration
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
|
||||
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
|
||||
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
|
||||
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
|
||||
.PTP_PERIOD_NS(PTP_PERIOD_NS),
|
||||
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
|
||||
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
|
||||
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
|
||||
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
|
||||
|
||||
// Queue manager configuration (interface)
|
||||
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
|
||||
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
|
||||
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
|
||||
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
|
||||
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
|
||||
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
|
||||
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
|
||||
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
|
||||
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
|
||||
|
||||
// TX and RX engine configuration (port)
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
|
||||
// Scheduler configuration (port)
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
|
||||
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
|
||||
|
||||
// Timestamping configuration (port)
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
|
||||
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
|
||||
|
||||
// Interface configuration (port)
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
|
||||
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
|
||||
.MAX_TX_SIZE(MAX_TX_SIZE),
|
||||
.MAX_RX_SIZE(MAX_RX_SIZE),
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
|
||||
.APP_DMA_ENABLE(APP_DMA_ENABLE),
|
||||
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
|
||||
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
|
||||
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
|
||||
.APP_STAT_ENABLE(APP_STAT_ENABLE),
|
||||
|
||||
// DMA interface configuration
|
||||
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
|
||||
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
|
||||
// PCIe interface configuration
|
||||
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
||||
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
|
||||
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
|
||||
@ -1402,7 +1610,43 @@ fpga_core #(
|
||||
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
|
||||
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
|
||||
.BAR0_APERTURE(BAR0_APERTURE)
|
||||
.PF_COUNT(PF_COUNT),
|
||||
.VF_COUNT(VF_COUNT),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
|
||||
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
|
||||
.PCIE_DMA_READ_TX_FC_ENABLE(PCIE_DMA_READ_TX_FC_ENABLE),
|
||||
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
|
||||
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
|
||||
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
|
||||
.MSI_COUNT(MSI_COUNT),
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
|
||||
|
||||
// AXI lite interface configuration (application control)
|
||||
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
|
||||
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
|
||||
|
||||
// Ethernet interface configuration
|
||||
.AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
|
||||
.AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
|
||||
.AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
|
||||
.AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
|
||||
.AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
|
||||
.AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
|
||||
.AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
|
||||
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
|
||||
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
|
||||
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
|
||||
|
||||
// Statistics counter subsystem
|
||||
.STAT_ENABLE(STAT_ENABLE),
|
||||
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
|
||||
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
|
||||
.STAT_INC_WIDTH(STAT_INC_WIDTH),
|
||||
.STAT_ID_WIDTH(STAT_ID_WIDTH)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
# Copyright 2020, The Regents of the University of California.
|
||||
# Copyright 2020-2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
@ -39,12 +39,19 @@ DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
|
||||
@ -52,13 +59,17 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
@ -84,13 +95,12 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
@ -103,31 +113,188 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT ?= 2
|
||||
export PARAM_PORTS_PER_IF ?= 1
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_PEROUT_ENABLE ?= 0
|
||||
export PARAM_PTP_PEROUT_COUNT ?= 1
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
|
||||
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
|
||||
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
export PARAM_TX_DESC_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE ?= 32
|
||||
|
||||
# Scheduler configuration (port)
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH ?= 6
|
||||
|
||||
# Timestamping configuration (port)
|
||||
export PARAM_PTP_TS_ENABLE ?= 1
|
||||
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
|
||||
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
|
||||
|
||||
# Interface configuration (port)
|
||||
export PARAM_TX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_RX_RSS_ENABLE ?= 1
|
||||
export PARAM_RX_HASH_ENABLE ?= 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_TX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_RX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_MAX_TX_SIZE ?= 9214
|
||||
export PARAM_MAX_RX_SIZE ?= 9214
|
||||
export PARAM_TX_RAM_SIZE ?= 32768
|
||||
export PARAM_RX_RAM_SIZE ?= 32768
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ENABLE ?= 0
|
||||
export PARAM_APP_CTRL_ENABLE ?= 1
|
||||
export PARAM_APP_DMA_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE ?= 1
|
||||
export PARAM_APP_STAT_ENABLE ?= 1
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_LEN_WIDTH ?= 16
|
||||
export PARAM_DMA_TAG_WIDTH ?= 16
|
||||
export PARAM_RAM_PIPELINE ?= 2
|
||||
|
||||
# PCIe interface configuration
|
||||
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
|
||||
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
|
||||
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
|
||||
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
|
||||
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
|
||||
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
|
||||
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_PF_COUNT ?= 1
|
||||
export PARAM_VF_COUNT ?= 0
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
|
||||
export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
|
||||
export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
|
||||
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
|
||||
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
|
||||
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 4
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE ?= 1
|
||||
export PARAM_STAT_DMA_ENABLE ?= 1
|
||||
export PARAM_STAT_PCIE_ENABLE ?= 1
|
||||
export PARAM_STAT_INC_WIDTH ?= 24
|
||||
export PARAM_STAT_ID_WIDTH ?= 12
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -136,14 +303,76 @@ ifeq ($(SIM), icarus)
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
|
||||
COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
"""
|
||||
|
||||
Copyright 2020, The Regents of the University of California.
|
||||
Copyright 2020-2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -66,8 +66,6 @@ class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.BAR0_APERTURE = int(os.getenv("PARAM_BAR0_APERTURE"))
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
@ -266,7 +264,9 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True)
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
|
||||
# Ethernet
|
||||
cocotb.fork(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start())
|
||||
@ -545,6 +545,7 @@ async def run_test_nic(dut):
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
@ -558,12 +559,19 @@ def test_fpga_core(request):
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_engine.v"),
|
||||
@ -571,13 +579,17 @@ def test_fpga_core(request):
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
|
||||
@ -603,13 +615,12 @@ def test_fpga_core(request):
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
@ -622,6 +633,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
@ -629,14 +645,103 @@ def test_fpga_core(request):
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = 2
|
||||
parameters['PORTS_PER_IF'] = 1
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_PEROUT_ENABLE'] = 0
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
|
||||
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
|
||||
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
|
||||
parameters['EVENT_QUEUE_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
|
||||
# Scheduler configuration (port)
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Timestamping configuration (port)
|
||||
parameters['PTP_TS_ENABLE'] = 1
|
||||
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
|
||||
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
|
||||
|
||||
# Interface configuration (port)
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_RSS_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 32768
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 32768
|
||||
parameters['RX_RAM_SIZE'] = 32768
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
# PCIe interface configuration
|
||||
parameters['AXIS_PCIE_DATA_WIDTH'] = 512
|
||||
parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
|
||||
parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
|
||||
parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161
|
||||
parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183
|
||||
parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81
|
||||
parameters['RQ_SEQ_NUM_WIDTH'] = 6
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['PF_COUNT'] = 1
|
||||
parameters['VF_COUNT'] = 0
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
|
||||
parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
|
||||
parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
|
||||
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
|
||||
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
|
||||
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 1
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_PCIE_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 12
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user