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Code Issues Projects Releases Wiki Activity

Use cfg prefix for configuration signals

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-08-22 17:14:52 -07:00
parent f92a94d278
commit 20c542051d
76 changed files with 163 additions and 159 deletions
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2
example/520N_MX/fpga_10g/rtl/fpga_core.v
View File

@ -497,7 +497,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -419,7 +419,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/ATLYS/fpga/rtl/fpga_core.v
View File

@ -356,7 +356,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -407,7 +407,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -374,7 +374,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/Arty/fpga/rtl/fpga_core.v
View File

@ -363,7 +363,7 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/C10LP/fpga/rtl/fpga_core.v
View File

@ -340,7 +340,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/DE2-115/fpga/rtl/fpga_core.v
View File

@ -448,7 +448,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/DE5-Net/fpga/rtl/fpga_core.v
View File

@ -372,7 +372,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -352,7 +352,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
View File

@ -352,7 +352,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/HTG640/fpga/rtl/fpga_core.v
View File

@ -516,7 +516,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/HTG640/fpga_cxpt16/rtl/fpga_core.v
View File

@ -308,7 +308,7 @@ eth_mac_fifo_inst (
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/HTG9200/fpga_25g/rtl/fpga_core.v
View File

@ -715,7 +715,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v
View File

@ -967,7 +967,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/KC705/fpga_gmii/rtl/fpga_core.v
View File

@ -360,7 +360,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/KC705/fpga_rgmii/rtl/fpga_core.v
View File

@ -357,7 +357,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/KC705/fpga_sgmii/rtl/fpga_core.v
View File

@ -357,7 +357,7 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/ML605/fpga_gmii/rtl/fpga_core.v
View File

@ -369,7 +369,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/ML605/fpga_rgmii/rtl/fpga_core.v
View File

@ -366,7 +366,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/ML605/fpga_sgmii/rtl/fpga_core.v
View File

@ -366,7 +366,7 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -385,7 +385,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/NexysVideo/fpga/rtl/fpga_core.v
View File

@ -355,7 +355,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/RV901T/fpga/rtl/fpga_core.v
View File

@ -344,7 +344,7 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
assign phy_1_tx_clk = 1'b0;

2
example/S10MX_DK/fpga_10g/rtl/fpga_core.v
View File

@ -411,7 +411,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

4
example/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -418,7 +418,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
// 1G interface for debugging
@ -497,7 +497,7 @@ eth_mac_1g_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
axis_adapter #(

2
example/VCU108/fpga_1g/rtl/fpga_core.v
View File

@ -357,7 +357,7 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

2
example/VCU118/fpga_1g/rtl/fpga_core.v
View File

@ -357,7 +357,7 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
eth_axis_rx

4
example/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -459,7 +459,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
// 1G interface for debugging
@ -538,7 +538,7 @@ eth_mac_1g_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
axis_adapter #(

4
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v
View File

@ -709,7 +709,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
// 1G interface for debugging
@ -788,7 +788,7 @@ eth_mac_1g_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
.cfg_ifg(8'd12)
);
axis_adapter #(

2
example/VCU1525/fpga_25g/rtl/fpga_core.v
View File

@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/ZCU102/fpga/rtl/fpga_core.v
View File

@ -384,7 +384,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/ZCU106/fpga/rtl/fpga_core.v
View File

@ -364,7 +364,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

2
example/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -420,7 +420,7 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12)
);
eth_axis_rx #(

4
rtl/axis_baser_tx_64.v
View File

@ -79,7 +79,7 @@ module axis_baser_tx_64 #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire [7:0] cfg_ifg,
/*
* Status
@ -530,7 +530,7 @@ always @* begin
output_data_next = fcs_output_data_0;
output_type_next = fcs_output_type_0;
ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg;
ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg;
if (s_empty_reg <= 4) begin
state_next = STATE_FCS_2;
end else begin

6
rtl/axis_gmii_tx.v
View File

@ -80,7 +80,7 @@ module axis_gmii_tx #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire [7:0] cfg_ifg,
/*
* Status
@ -386,7 +386,7 @@ always @* begin
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = 1'b0;
if (frame_ptr_reg < ifg_delay-1) begin
if (frame_ptr_reg < cfg_ifg-1) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
@ -404,7 +404,7 @@ always @* begin
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 1;
if (frame_ptr_reg < ifg_delay-1) begin
if (frame_ptr_reg < cfg_ifg-1) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;

4
rtl/axis_xgmii_tx_32.v
View File

@ -77,7 +77,7 @@ module axis_xgmii_tx_32 #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire [7:0] cfg_ifg,
/*
* Status
@ -414,7 +414,7 @@ always @* begin
xgmii_txd_next = fcs_output_txd_0;
xgmii_txc_next = fcs_output_txc_0;
ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + deficit_idle_count_reg;
ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + deficit_idle_count_reg;
state_next = STATE_FCS_2;
end
STATE_FCS_2: begin

4
rtl/axis_xgmii_tx_64.v
View File

@ -79,7 +79,7 @@ module axis_xgmii_tx_64 #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire [7:0] cfg_ifg,
/*
* Status
@ -479,7 +479,7 @@ always @* begin
xgmii_txd_next = fcs_output_txd_0;
xgmii_txc_next = fcs_output_txc_0;
ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg;
ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg;
if (s_empty_reg <= 4) begin
state_next = STATE_FCS_2;
end else begin

6
rtl/eth_mac_10g.v
View File

@ -150,7 +150,7 @@ module eth_mac_10g #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire [7:0] cfg_ifg,
input wire [47:0] cfg_mcf_rx_eth_dst_mcast,
input wire cfg_mcf_rx_check_eth_dst_mcast,
input wire [47:0] cfg_mcf_rx_eth_dst_ucast,
@ -274,7 +274,7 @@ axis_xgmii_tx_inst (
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.cfg_ifg(cfg_ifg),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
@ -336,7 +336,7 @@ axis_xgmii_tx_inst (
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.cfg_ifg(cfg_ifg),
.start_packet(tx_start_packet[0]),
.error_underflow(tx_error_underflow)
);

4
rtl/eth_mac_10g_fifo.v
View File

@ -133,7 +133,7 @@ module eth_mac_10g_fifo #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
@ -382,7 +382,7 @@ eth_mac_10g_inst (
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
axis_async_fifo_adapter #(

4
rtl/eth_mac_1g.v
View File

@ -153,7 +153,7 @@ module eth_mac_1g #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire [7:0] cfg_ifg,
input wire [47:0] cfg_mcf_rx_eth_dst_mcast,
input wire cfg_mcf_rx_check_eth_dst_mcast,
input wire [47:0] cfg_mcf_rx_eth_dst_ucast,
@ -253,7 +253,7 @@ axis_gmii_tx_inst (
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.clk_enable(tx_clk_enable),
.mii_select(tx_mii_select),
.ifg_delay(ifg_delay),
.cfg_ifg(cfg_ifg),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);

4
rtl/eth_mac_1g_fifo.v
View File

@ -113,7 +113,7 @@ module eth_mac_1g_fifo #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
wire [7:0] tx_fifo_axis_tdata;
@ -219,7 +219,7 @@ eth_mac_1g_inst (
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
axis_async_fifo_adapter #(

4
rtl/eth_mac_1g_gmii.v
View File

@ -96,7 +96,7 @@ module eth_mac_1g_gmii #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
wire [7:0] mac_gmii_rxd;
@ -244,7 +244,7 @@ eth_mac_1g_inst (
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
endmodule

4
rtl/eth_mac_1g_gmii_fifo.v
View File

@ -118,7 +118,7 @@ module eth_mac_1g_gmii_fifo #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
wire tx_clk;
@ -246,7 +246,7 @@ eth_mac_1g_gmii_inst (
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.speed(speed_int),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
axis_async_fifo_adapter #(

4
rtl/eth_mac_1g_rgmii.v
View File

@ -95,7 +95,7 @@ module eth_mac_1g_rgmii #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
wire [7:0] mac_gmii_rxd;
@ -244,7 +244,7 @@ eth_mac_1g_inst (
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
endmodule

4
rtl/eth_mac_1g_rgmii_fifo.v
View File

@ -117,7 +117,7 @@ module eth_mac_1g_rgmii_fifo #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
wire tx_clk;
@ -244,7 +244,7 @@ eth_mac_1g_rgmii_inst (
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.speed(speed_int),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
axis_async_fifo_adapter #(

4
rtl/eth_mac_mii.v
View File

@ -91,7 +91,7 @@ module eth_mac_mii #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
wire [3:0] mac_mii_rxd;
@ -162,7 +162,7 @@ eth_mac_1g_inst (
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
endmodule

4
rtl/eth_mac_mii_fifo.v
View File

@ -111,7 +111,7 @@ module eth_mac_mii_fifo #
/*
* Configuration
*/
input wire [7:0] ifg_delay
input wire [7:0] cfg_ifg
);
wire tx_clk;
@ -223,7 +223,7 @@ eth_mac_1g_mii_inst (
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
axis_async_fifo_adapter #(

12
rtl/eth_mac_phy_10g.v
View File

@ -120,9 +120,9 @@ module eth_mac_phy_10g #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
input wire [7:0] cfg_ifg,
input wire cfg_tx_prbs31_enable,
input wire cfg_rx_prbs31_enable
);
eth_mac_phy_10g_rx #(
@ -163,7 +163,7 @@ eth_mac_phy_10g_rx_inst (
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
.rx_prbs31_enable(rx_prbs31_enable)
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
eth_mac_phy_10g_tx #(
@ -203,8 +203,8 @@ eth_mac_phy_10g_tx_inst (
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable)
.cfg_ifg(cfg_ifg),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule

12
rtl/eth_mac_phy_10g_fifo.v
View File

@ -147,9 +147,9 @@ module eth_mac_phy_10g_fifo #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
input wire [7:0] cfg_ifg,
input wire cfg_tx_prbs31_enable,
input wire cfg_rx_prbs31_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
@ -425,10 +425,10 @@ eth_mac_phy_10g_inst (
.rx_high_ber(rx_high_ber_int),
.rx_status(rx_status_int),
.ifg_delay(ifg_delay),
.cfg_ifg(cfg_ifg),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
axis_async_fifo_adapter #(

4
rtl/eth_mac_phy_10g_rx.v
View File

@ -90,7 +90,7 @@ module eth_mac_phy_10g_rx #
/*
* Configuration
*/
input wire rx_prbs31_enable
input wire cfg_rx_prbs31_enable
);
// bus width assertions
@ -138,7 +138,7 @@ eth_phy_10g_rx_if_inst (
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
.rx_prbs31_enable(rx_prbs31_enable)
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
axis_baser_rx_64 #(

8
rtl/eth_mac_phy_10g_tx.v
View File

@ -89,8 +89,8 @@ module eth_mac_phy_10g_tx #
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable
input wire [7:0] cfg_ifg,
input wire cfg_tx_prbs31_enable
);
// bus width assertions
@ -147,7 +147,7 @@ axis_baser_tx_inst (
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay)
.cfg_ifg(cfg_ifg)
);
eth_phy_10g_tx_if #(
@ -165,7 +165,7 @@ eth_phy_10g_tx_if_inst (
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule

8
rtl/eth_phy_10g.v
View File

@ -83,8 +83,8 @@ module eth_phy_10g #
/*
* Configuration
*/
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
input wire cfg_tx_prbs31_enable,
input wire cfg_rx_prbs31_enable
);
eth_phy_10g_rx #(
@ -114,7 +114,7 @@ eth_phy_10g_rx_inst (
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
.rx_prbs31_enable(rx_prbs31_enable)
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
eth_phy_10g_tx #(
@ -134,7 +134,7 @@ eth_phy_10g_tx_inst (
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_bad_block(tx_bad_block),
.tx_prbs31_enable(tx_prbs31_enable)
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule

4
rtl/eth_phy_10g_rx.v
View File

@ -75,7 +75,7 @@ module eth_phy_10g_rx #
/*
* Configuration
*/
input wire rx_prbs31_enable
input wire cfg_rx_prbs31_enable
);
// bus width assertions
@ -125,7 +125,7 @@ eth_phy_10g_rx_if_inst (
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
.rx_prbs31_enable(rx_prbs31_enable)
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
xgmii_baser_dec_64 #(

8
rtl/eth_phy_10g_rx_if.v
View File

@ -74,7 +74,7 @@ module eth_phy_10g_rx_if #
/*
* Configuration
*/
input wire rx_prbs31_enable
input wire cfg_rx_prbs31_enable
);
// bus width assertions
@ -206,7 +206,7 @@ always @(posedge clk) begin
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
if (PRBS31_ENABLE && rx_prbs31_enable) begin
if (PRBS31_ENABLE && cfg_rx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
rx_error_count_1_reg <= rx_error_count_1_temp;
@ -222,8 +222,8 @@ assign rx_error_count = rx_error_count_reg;
wire serdes_rx_bitslip_int;
wire serdes_rx_reset_req_int;
assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31_enable);
assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && rx_prbs31_enable);
assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable);
assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable);
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),

4
rtl/eth_phy_10g_tx.v
View File

@ -65,7 +65,7 @@ module eth_phy_10g_tx #
/*
* Configuration
*/
input wire tx_prbs31_enable
input wire cfg_tx_prbs31_enable
);
// bus width assertions
@ -119,7 +119,7 @@ eth_phy_10g_tx_if_inst (
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule

4
rtl/eth_phy_10g_tx_if.v
View File

@ -59,7 +59,7 @@ module eth_phy_10g_tx_if #
/*
* Configuration
*/
input wire tx_prbs31_enable
input wire cfg_tx_prbs31_enable
);
// bus width assertions
@ -167,7 +167,7 @@ prbs31_gen_inst (
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
if (PRBS31_ENABLE && tx_prbs31_enable) begin
if (PRBS31_ENABLE && cfg_tx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
serdes_tx_data_reg <= ~prbs31_data[DATA_WIDTH+HDR_WIDTH-1:HDR_WIDTH];

6
tb/axis_baser_tx_64/test_axis_baser_tx_64.py
View File

@ -73,7 +73,7 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk)
self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -91,7 +91,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -135,7 +135,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

4
tb/axis_gmii_tx/test_axis_gmii_tx.py
View File

@ -67,7 +67,7 @@ class TB:
dut.clk_enable.setimmediatevalue(1)
dut.mii_select.setimmediatevalue(0)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -103,7 +103,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
tb = TB(dut)
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.mii_select.value = mii_sel
if enable_gen is not None:

6
tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py
View File

@ -62,7 +62,7 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk)
self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -120,7 +120,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

6
tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py
View File

@ -62,7 +62,7 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk)
self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -124,7 +124,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

12
tb/eth_mac_10g/test_eth_mac_10g.py
View File

@ -88,7 +88,7 @@ class TB:
dut.tx_lfc_pause_en.setimmediatevalue(0)
dut.tx_pause_req.setimmediatevalue(0)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
@ -141,7 +141,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -185,7 +185,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -230,7 +230,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -313,7 +313,7 @@ async def run_test_lfc(dut, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -456,7 +456,7 @@ async def run_test_pfc(dut, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

8
tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py
View File

@ -75,6 +75,8 @@ class TB:
dut.ptp_sample_clk.setimmediatevalue(0)
dut.ptp_ts_step.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
self.dut.rx_rst.setimmediatevalue(0)
@ -98,7 +100,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -146,7 +148,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -195,7 +197,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.xgmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

10
tb/eth_mac_1g/test_eth_mac_1g.py
View File

@ -95,7 +95,7 @@ class TB:
dut.rx_mii_select.setimmediatevalue(0)
dut.tx_mii_select.setimmediatevalue(0)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
@ -184,7 +184,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -230,7 +230,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -273,7 +273,7 @@ async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -422,7 +422,7 @@ async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel

6
tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py
View File

@ -66,7 +66,7 @@ class TB:
dut.tx_clk_enable.setimmediatevalue(1)
dut.rx_mii_select.setimmediatevalue(0)
dut.tx_mii_select.setimmediatevalue(0)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
@ -127,7 +127,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -160,7 +160,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel

6
tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py
View File

@ -53,7 +53,7 @@ class TB:
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
@ -75,7 +75,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.set_speed(speed)
@ -114,7 +114,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.set_speed(speed)

6
tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py
View File

@ -54,7 +54,7 @@ class TB:
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
@ -79,7 +79,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.set_speed(speed)
@ -118,7 +118,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
tb.set_speed(speed)

6
tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py
View File

@ -50,7 +50,7 @@ class TB:
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.gtx_clk.setimmediatevalue(0)
dut.gtx_clk90.setimmediatevalue(0)
@ -86,7 +86,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -123,7 +123,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

6
tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py
View File

@ -53,7 +53,7 @@ class TB:
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.gtx_clk.setimmediatevalue(0)
dut.gtx_clk90.setimmediatevalue(0)
@ -92,7 +92,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -129,7 +129,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

6
tb/eth_mac_mii/test_eth_mac_mii.py
View File

@ -50,7 +50,7 @@ class TB:
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -69,7 +69,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -96,7 +96,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

6
tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py
View File

@ -53,7 +53,7 @@ class TB:
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst)
dut.ifg_delay.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
@ -72,7 +72,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -99,7 +99,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

11
tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
View File

@ -83,8 +83,9 @@ class TB:
self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk)
self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst)
dut.tx_prbs31_enable.setimmediatevalue(0)
dut.rx_prbs31_enable.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rx_rst.setimmediatevalue(0)
@ -106,7 +107,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -159,7 +160,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -204,7 +205,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

11
tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
View File

@ -86,8 +86,9 @@ class TB:
dut.ptp_sample_clk.setimmediatevalue(0)
dut.ptp_ts_step.setimmediatevalue(0)
dut.tx_prbs31_enable.setimmediatevalue(0)
dut.rx_prbs31_enable.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
@ -112,7 +113,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -167,7 +168,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()
@ -216,7 +217,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
tb.dut.cfg_ifg.value = ifg
await tb.reset()

4
tb/eth_phy_10g/test_eth_phy_10g.py
View File

@ -64,8 +64,8 @@ class TB:
self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk)
dut.tx_prbs31_enable.setimmediatevalue(0)
dut.rx_prbs31_enable.setimmediatevalue(0)
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
async def reset(self):
self.dut.tx_rst.setimmediatevalue(0)