From 20c542051d3112034deb81a02b646e791db03ad5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 22 Aug 2023 17:14:52 -0700 Subject: [PATCH] Use cfg prefix for configuration signals Signed-off-by: Alex Forencich --- example/520N_MX/fpga_10g/rtl/fpga_core.v | 2 +- example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 2 +- example/ATLYS/fpga/rtl/fpga_core.v | 2 +- example/AU200/fpga_25g/rtl/fpga_core.v | 2 +- example/AU250/fpga_25g/rtl/fpga_core.v | 2 +- example/AU280/fpga_25g/rtl/fpga_core.v | 2 +- example/AU50/fpga_25g/rtl/fpga_core.v | 2 +- example/Arty/fpga/rtl/fpga_core.v | 2 +- example/C10LP/fpga/rtl/fpga_core.v | 2 +- example/DE2-115/fpga/rtl/fpga_core.v | 2 +- example/DE5-Net/fpga/rtl/fpga_core.v | 2 +- example/ExaNIC_X10/fpga/rtl/fpga_core.v | 2 +- example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v | 2 +- example/HTG640/fpga/rtl/fpga_core.v | 2 +- example/HTG640/fpga_cxpt16/rtl/fpga_core.v | 2 +- example/HTG9200/fpga_25g/rtl/fpga_core.v | 2 +- .../HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v | 2 +- example/KC705/fpga_gmii/rtl/fpga_core.v | 2 +- example/KC705/fpga_rgmii/rtl/fpga_core.v | 2 +- example/KC705/fpga_sgmii/rtl/fpga_core.v | 2 +- example/ML605/fpga_gmii/rtl/fpga_core.v | 2 +- example/ML605/fpga_rgmii/rtl/fpga_core.v | 2 +- example/ML605/fpga_sgmii/rtl/fpga_core.v | 2 +- example/NetFPGA_SUME/fpga/rtl/fpga_core.v | 2 +- example/NexysVideo/fpga/rtl/fpga_core.v | 2 +- example/RV901T/fpga/rtl/fpga_core.v | 2 +- example/S10MX_DK/fpga_10g/rtl/fpga_core.v | 2 +- example/VCU108/fpga_10g/rtl/fpga_core.v | 4 ++-- example/VCU108/fpga_1g/rtl/fpga_core.v | 2 +- example/VCU118/fpga_1g/rtl/fpga_core.v | 2 +- example/VCU118/fpga_25g/rtl/fpga_core.v | 4 ++-- .../VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v | 4 ++-- example/VCU1525/fpga_25g/rtl/fpga_core.v | 2 +- example/ZCU102/fpga/rtl/fpga_core.v | 2 +- example/ZCU106/fpga/rtl/fpga_core.v | 2 +- example/fb2CG/fpga_25g/rtl/fpga_core.v | 2 +- rtl/axis_baser_tx_64.v | 4 ++-- rtl/axis_gmii_tx.v | 6 +++--- rtl/axis_xgmii_tx_32.v | 4 ++-- rtl/axis_xgmii_tx_64.v | 4 ++-- rtl/eth_mac_10g.v | 6 +++--- rtl/eth_mac_10g_fifo.v | 4 ++-- rtl/eth_mac_1g.v | 4 ++-- rtl/eth_mac_1g_fifo.v | 4 ++-- rtl/eth_mac_1g_gmii.v | 4 ++-- rtl/eth_mac_1g_gmii_fifo.v | 4 ++-- rtl/eth_mac_1g_rgmii.v | 4 ++-- rtl/eth_mac_1g_rgmii_fifo.v | 4 ++-- rtl/eth_mac_mii.v | 4 ++-- rtl/eth_mac_mii_fifo.v | 4 ++-- rtl/eth_mac_phy_10g.v | 12 ++++++------ rtl/eth_mac_phy_10g_fifo.v | 12 ++++++------ rtl/eth_mac_phy_10g_rx.v | 4 ++-- rtl/eth_mac_phy_10g_tx.v | 8 ++++---- rtl/eth_phy_10g.v | 8 ++++---- rtl/eth_phy_10g_rx.v | 4 ++-- rtl/eth_phy_10g_rx_if.v | 8 ++++---- rtl/eth_phy_10g_tx.v | 4 ++-- rtl/eth_phy_10g_tx_if.v | 4 ++-- tb/axis_baser_tx_64/test_axis_baser_tx_64.py | 6 +++--- tb/axis_gmii_tx/test_axis_gmii_tx.py | 4 ++-- tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py | 6 +++--- tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py | 6 +++--- tb/eth_mac_10g/test_eth_mac_10g.py | 12 ++++++------ tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py | 8 +++++--- tb/eth_mac_1g/test_eth_mac_1g.py | 10 +++++----- tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py | 6 +++--- tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py | 6 +++--- tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py | 6 +++--- tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py | 6 +++--- .../test_eth_mac_1g_rgmii_fifo.py | 6 +++--- tb/eth_mac_mii/test_eth_mac_mii.py | 6 +++--- tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py | 6 +++--- tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py | 11 ++++++----- tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py | 11 ++++++----- tb/eth_phy_10g/test_eth_phy_10g.py | 4 ++-- 76 files changed, 163 insertions(+), 159 deletions(-) diff --git a/example/520N_MX/fpga_10g/rtl/fpga_core.v b/example/520N_MX/fpga_10g/rtl/fpga_core.v index edaf3e722..7011d5470 100644 --- a/example/520N_MX/fpga_10g/rtl/fpga_core.v +++ b/example/520N_MX/fpga_10g/rtl/fpga_core.v @@ -497,7 +497,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 670416bba..5cacb65cc 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -419,7 +419,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ATLYS/fpga/rtl/fpga_core.v b/example/ATLYS/fpga/rtl/fpga_core.v index a20960129..5ef8fa732 100644 --- a/example/ATLYS/fpga/rtl/fpga_core.v +++ b/example/ATLYS/fpga/rtl/fpga_core.v @@ -356,7 +356,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/AU200/fpga_25g/rtl/fpga_core.v b/example/AU200/fpga_25g/rtl/fpga_core.v index c8c2c444c..916766566 100644 --- a/example/AU200/fpga_25g/rtl/fpga_core.v +++ b/example/AU200/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/AU250/fpga_25g/rtl/fpga_core.v b/example/AU250/fpga_25g/rtl/fpga_core.v index c8c2c444c..916766566 100644 --- a/example/AU250/fpga_25g/rtl/fpga_core.v +++ b/example/AU250/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/AU280/fpga_25g/rtl/fpga_core.v b/example/AU280/fpga_25g/rtl/fpga_core.v index 3e970d846..1ae8f5fc1 100644 --- a/example/AU280/fpga_25g/rtl/fpga_core.v +++ b/example/AU280/fpga_25g/rtl/fpga_core.v @@ -407,7 +407,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/AU50/fpga_25g/rtl/fpga_core.v b/example/AU50/fpga_25g/rtl/fpga_core.v index a59896f6a..4730761a5 100644 --- a/example/AU50/fpga_25g/rtl/fpga_core.v +++ b/example/AU50/fpga_25g/rtl/fpga_core.v @@ -374,7 +374,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/Arty/fpga/rtl/fpga_core.v b/example/Arty/fpga/rtl/fpga_core.v index 13ba63b7d..e9629f475 100644 --- a/example/Arty/fpga/rtl/fpga_core.v +++ b/example/Arty/fpga/rtl/fpga_core.v @@ -363,7 +363,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/C10LP/fpga/rtl/fpga_core.v b/example/C10LP/fpga/rtl/fpga_core.v index 83fc9401d..ea2f8f3ff 100644 --- a/example/C10LP/fpga/rtl/fpga_core.v +++ b/example/C10LP/fpga/rtl/fpga_core.v @@ -340,7 +340,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/DE2-115/fpga/rtl/fpga_core.v b/example/DE2-115/fpga/rtl/fpga_core.v index 8ce5a6f4e..0934b1ea6 100644 --- a/example/DE2-115/fpga/rtl/fpga_core.v +++ b/example/DE2-115/fpga/rtl/fpga_core.v @@ -448,7 +448,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/DE5-Net/fpga/rtl/fpga_core.v b/example/DE5-Net/fpga/rtl/fpga_core.v index 10e425152..b75ec1009 100644 --- a/example/DE5-Net/fpga/rtl/fpga_core.v +++ b/example/DE5-Net/fpga/rtl/fpga_core.v @@ -372,7 +372,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ExaNIC_X10/fpga/rtl/fpga_core.v b/example/ExaNIC_X10/fpga/rtl/fpga_core.v index ba26330d9..637cf2890 100644 --- a/example/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/example/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -352,7 +352,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v b/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v index ba26330d9..637cf2890 100644 --- a/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v +++ b/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v @@ -352,7 +352,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG640/fpga/rtl/fpga_core.v b/example/HTG640/fpga/rtl/fpga_core.v index d3423eeb3..79bec3ee2 100644 --- a/example/HTG640/fpga/rtl/fpga_core.v +++ b/example/HTG640/fpga/rtl/fpga_core.v @@ -516,7 +516,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG640/fpga_cxpt16/rtl/fpga_core.v b/example/HTG640/fpga_cxpt16/rtl/fpga_core.v index b4a7cf74a..ff3c0ee58 100644 --- a/example/HTG640/fpga_cxpt16/rtl/fpga_core.v +++ b/example/HTG640/fpga_cxpt16/rtl/fpga_core.v @@ -308,7 +308,7 @@ eth_mac_fifo_inst ( .rx_fifo_overflow(), .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG9200/fpga_25g/rtl/fpga_core.v b/example/HTG9200/fpga_25g/rtl/fpga_core.v index 784790234..324804cb4 100644 --- a/example/HTG9200/fpga_25g/rtl/fpga_core.v +++ b/example/HTG9200/fpga_25g/rtl/fpga_core.v @@ -715,7 +715,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v index cfafade3c..a2b77fd0d 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -967,7 +967,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/KC705/fpga_gmii/rtl/fpga_core.v b/example/KC705/fpga_gmii/rtl/fpga_core.v index 0e0b46ff4..5cf47ee7f 100644 --- a/example/KC705/fpga_gmii/rtl/fpga_core.v +++ b/example/KC705/fpga_gmii/rtl/fpga_core.v @@ -360,7 +360,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/KC705/fpga_rgmii/rtl/fpga_core.v b/example/KC705/fpga_rgmii/rtl/fpga_core.v index 1505d3309..78ba7980f 100644 --- a/example/KC705/fpga_rgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_rgmii/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/KC705/fpga_sgmii/rtl/fpga_core.v b/example/KC705/fpga_sgmii/rtl/fpga_core.v index fe73ad5bb..e688c77ec 100644 --- a/example/KC705/fpga_sgmii/rtl/fpga_core.v +++ b/example/KC705/fpga_sgmii/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/ML605/fpga_gmii/rtl/fpga_core.v b/example/ML605/fpga_gmii/rtl/fpga_core.v index 1bae139a1..a9d79878e 100644 --- a/example/ML605/fpga_gmii/rtl/fpga_core.v +++ b/example/ML605/fpga_gmii/rtl/fpga_core.v @@ -369,7 +369,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/ML605/fpga_rgmii/rtl/fpga_core.v b/example/ML605/fpga_rgmii/rtl/fpga_core.v index 1fcb6fa35..44f99672f 100644 --- a/example/ML605/fpga_rgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_rgmii/rtl/fpga_core.v @@ -366,7 +366,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/ML605/fpga_sgmii/rtl/fpga_core.v b/example/ML605/fpga_sgmii/rtl/fpga_core.v index 565a41239..be8a81da5 100644 --- a/example/ML605/fpga_sgmii/rtl/fpga_core.v +++ b/example/ML605/fpga_sgmii/rtl/fpga_core.v @@ -366,7 +366,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v index f80f8a340..5e11592ba 100644 --- a/example/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/example/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -385,7 +385,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/NexysVideo/fpga/rtl/fpga_core.v b/example/NexysVideo/fpga/rtl/fpga_core.v index 5f94b5309..63b5feff5 100644 --- a/example/NexysVideo/fpga/rtl/fpga_core.v +++ b/example/NexysVideo/fpga/rtl/fpga_core.v @@ -355,7 +355,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/RV901T/fpga/rtl/fpga_core.v b/example/RV901T/fpga/rtl/fpga_core.v index 2cac60e2c..0e1242759 100644 --- a/example/RV901T/fpga/rtl/fpga_core.v +++ b/example/RV901T/fpga/rtl/fpga_core.v @@ -344,7 +344,7 @@ eth_mac_inst ( .rx_fifo_good_frame(), .speed(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); assign phy_1_tx_clk = 1'b0; diff --git a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v index 59e53f9c4..496164892 100644 --- a/example/S10MX_DK/fpga_10g/rtl/fpga_core.v +++ b/example/S10MX_DK/fpga_10g/rtl/fpga_core.v @@ -411,7 +411,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v index 2083ae212..63266daa9 100644 --- a/example/VCU108/fpga_10g/rtl/fpga_core.v +++ b/example/VCU108/fpga_10g/rtl/fpga_core.v @@ -418,7 +418,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); // 1G interface for debugging @@ -497,7 +497,7 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); axis_adapter #( diff --git a/example/VCU108/fpga_1g/rtl/fpga_core.v b/example/VCU108/fpga_1g/rtl/fpga_core.v index 8db7f7591..52ad016c8 100644 --- a/example/VCU108/fpga_1g/rtl/fpga_core.v +++ b/example/VCU108/fpga_1g/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/VCU118/fpga_1g/rtl/fpga_core.v b/example/VCU118/fpga_1g/rtl/fpga_core.v index 8db7f7591..52ad016c8 100644 --- a/example/VCU118/fpga_1g/rtl/fpga_core.v +++ b/example/VCU118/fpga_1g/rtl/fpga_core.v @@ -357,7 +357,7 @@ eth_mac_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); eth_axis_rx diff --git a/example/VCU118/fpga_25g/rtl/fpga_core.v b/example/VCU118/fpga_25g/rtl/fpga_core.v index 5521ff960..1d1ea1729 100644 --- a/example/VCU118/fpga_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_25g/rtl/fpga_core.v @@ -459,7 +459,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); // 1G interface for debugging @@ -538,7 +538,7 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); axis_adapter #( diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v index 6d5e2beba..d3b97112a 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -709,7 +709,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); // 1G interface for debugging @@ -788,7 +788,7 @@ eth_mac_1g_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(12) + .cfg_ifg(8'd12) ); axis_adapter #( diff --git a/example/VCU1525/fpga_25g/rtl/fpga_core.v b/example/VCU1525/fpga_25g/rtl/fpga_core.v index c8c2c444c..916766566 100644 --- a/example/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/example/VCU1525/fpga_25g/rtl/fpga_core.v @@ -422,7 +422,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ZCU102/fpga/rtl/fpga_core.v b/example/ZCU102/fpga/rtl/fpga_core.v index 85a8c0bcf..e992b8c05 100644 --- a/example/ZCU102/fpga/rtl/fpga_core.v +++ b/example/ZCU102/fpga/rtl/fpga_core.v @@ -384,7 +384,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/ZCU106/fpga/rtl/fpga_core.v b/example/ZCU106/fpga/rtl/fpga_core.v index 2c6f0193c..a70357d23 100644 --- a/example/ZCU106/fpga/rtl/fpga_core.v +++ b/example/ZCU106/fpga/rtl/fpga_core.v @@ -364,7 +364,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/example/fb2CG/fpga_25g/rtl/fpga_core.v b/example/fb2CG/fpga_25g/rtl/fpga_core.v index 18f1e32f2..560e993dd 100644 --- a/example/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/example/fb2CG/fpga_25g/rtl/fpga_core.v @@ -420,7 +420,7 @@ eth_mac_10g_fifo_inst ( .rx_fifo_bad_frame(), .rx_fifo_good_frame(), - .ifg_delay(8'd12) + .cfg_ifg(8'd12) ); eth_axis_rx #( diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v index 3a2523655..d878db11b 100644 --- a/rtl/axis_baser_tx_64.v +++ b/rtl/axis_baser_tx_64.v @@ -79,7 +79,7 @@ module axis_baser_tx_64 # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -530,7 +530,7 @@ always @* begin output_data_next = fcs_output_data_0; output_type_next = fcs_output_type_0; - ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; if (s_empty_reg <= 4) begin state_next = STATE_FCS_2; end else begin diff --git a/rtl/axis_gmii_tx.v b/rtl/axis_gmii_tx.v index 36c4c210c..d24c81a7d 100644 --- a/rtl/axis_gmii_tx.v +++ b/rtl/axis_gmii_tx.v @@ -80,7 +80,7 @@ module axis_gmii_tx # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -386,7 +386,7 @@ always @* begin if (s_axis_tvalid) begin if (s_axis_tlast) begin s_axis_tready_next = 1'b0; - if (frame_ptr_reg < ifg_delay-1) begin + if (frame_ptr_reg < cfg_ifg-1) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; @@ -404,7 +404,7 @@ always @* begin mii_odd_next = 1'b1; frame_ptr_next = frame_ptr_reg + 1; - if (frame_ptr_reg < ifg_delay-1) begin + if (frame_ptr_reg < cfg_ifg-1) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v index 673438662..ef6781b5a 100644 --- a/rtl/axis_xgmii_tx_32.v +++ b/rtl/axis_xgmii_tx_32.v @@ -77,7 +77,7 @@ module axis_xgmii_tx_32 # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -414,7 +414,7 @@ always @* begin xgmii_txd_next = fcs_output_txd_0; xgmii_txc_next = fcs_output_txc_0; - ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + deficit_idle_count_reg; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + deficit_idle_count_reg; state_next = STATE_FCS_2; end STATE_FCS_2: begin diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v index 060ec412d..0606db81e 100644 --- a/rtl/axis_xgmii_tx_64.v +++ b/rtl/axis_xgmii_tx_64.v @@ -79,7 +79,7 @@ module axis_xgmii_tx_64 # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, /* * Status @@ -479,7 +479,7 @@ always @* begin xgmii_txd_next = fcs_output_txd_0; xgmii_txc_next = fcs_output_txc_0; - ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; if (s_empty_reg <= 4) begin state_next = STATE_FCS_2; end else begin diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v index b34b91d2b..27d330cbb 100644 --- a/rtl/eth_mac_10g.v +++ b/rtl/eth_mac_10g.v @@ -150,7 +150,7 @@ module eth_mac_10g # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, input wire [47:0] cfg_mcf_rx_eth_dst_mcast, input wire cfg_mcf_rx_check_eth_dst_mcast, input wire [47:0] cfg_mcf_rx_eth_dst_ucast, @@ -274,7 +274,7 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts(tx_axis_ptp_ts), .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow) ); @@ -336,7 +336,7 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts(tx_axis_ptp_ts), .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), .start_packet(tx_start_packet[0]), .error_underflow(tx_error_underflow) ); diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index a99b968b8..3acc04edd 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -133,7 +133,7 @@ module eth_mac_10g_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); parameter KEEP_WIDTH = DATA_WIDTH/8; @@ -382,7 +382,7 @@ eth_mac_10g_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index 2f3c3605f..49b8cc7ae 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -153,7 +153,7 @@ module eth_mac_1g # /* * Configuration */ - input wire [7:0] ifg_delay, + input wire [7:0] cfg_ifg, input wire [47:0] cfg_mcf_rx_eth_dst_mcast, input wire cfg_mcf_rx_check_eth_dst_mcast, input wire [47:0] cfg_mcf_rx_eth_dst_ucast, @@ -253,7 +253,7 @@ axis_gmii_tx_inst ( .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .clk_enable(tx_clk_enable), .mii_select(tx_mii_select), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow) ); diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index fc6bf7e0e..e5a629daf 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -113,7 +113,7 @@ module eth_mac_1g_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [7:0] tx_fifo_axis_tdata; @@ -219,7 +219,7 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow_int), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g_gmii.v b/rtl/eth_mac_1g_gmii.v index 6b1196924..bc6912c2b 100644 --- a/rtl/eth_mac_1g_gmii.v +++ b/rtl/eth_mac_1g_gmii.v @@ -96,7 +96,7 @@ module eth_mac_1g_gmii # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [7:0] mac_gmii_rxd; @@ -244,7 +244,7 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); endmodule diff --git a/rtl/eth_mac_1g_gmii_fifo.v b/rtl/eth_mac_1g_gmii_fifo.v index 2c6763047..fa44aae40 100644 --- a/rtl/eth_mac_1g_gmii_fifo.v +++ b/rtl/eth_mac_1g_gmii_fifo.v @@ -118,7 +118,7 @@ module eth_mac_1g_gmii_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire tx_clk; @@ -246,7 +246,7 @@ eth_mac_1g_gmii_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .speed(speed_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_1g_rgmii.v b/rtl/eth_mac_1g_rgmii.v index a6aaaded8..43218a7fa 100644 --- a/rtl/eth_mac_1g_rgmii.v +++ b/rtl/eth_mac_1g_rgmii.v @@ -95,7 +95,7 @@ module eth_mac_1g_rgmii # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [7:0] mac_gmii_rxd; @@ -244,7 +244,7 @@ eth_mac_1g_inst ( .tx_error_underflow(tx_error_underflow), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); endmodule diff --git a/rtl/eth_mac_1g_rgmii_fifo.v b/rtl/eth_mac_1g_rgmii_fifo.v index bf97dc594..e7c2418b8 100644 --- a/rtl/eth_mac_1g_rgmii_fifo.v +++ b/rtl/eth_mac_1g_rgmii_fifo.v @@ -117,7 +117,7 @@ module eth_mac_1g_rgmii_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire tx_clk; @@ -244,7 +244,7 @@ eth_mac_1g_rgmii_inst ( .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), .speed(speed_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_mii.v b/rtl/eth_mac_mii.v index 8c1a47231..f83e223b4 100644 --- a/rtl/eth_mac_mii.v +++ b/rtl/eth_mac_mii.v @@ -91,7 +91,7 @@ module eth_mac_mii # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire [3:0] mac_mii_rxd; @@ -162,7 +162,7 @@ eth_mac_1g_inst ( .rx_start_packet(rx_start_packet), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); endmodule diff --git a/rtl/eth_mac_mii_fifo.v b/rtl/eth_mac_mii_fifo.v index 9384ac149..5f315fd5a 100644 --- a/rtl/eth_mac_mii_fifo.v +++ b/rtl/eth_mac_mii_fifo.v @@ -111,7 +111,7 @@ module eth_mac_mii_fifo # /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] cfg_ifg ); wire tx_clk; @@ -223,7 +223,7 @@ eth_mac_1g_mii_inst ( .tx_error_underflow(tx_error_underflow_int), .rx_error_bad_frame(rx_error_bad_frame_int), .rx_error_bad_fcs(rx_error_bad_fcs_int), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_phy_10g.v b/rtl/eth_mac_phy_10g.v index 46267b7f6..a176ce9f9 100644 --- a/rtl/eth_mac_phy_10g.v +++ b/rtl/eth_mac_phy_10g.v @@ -120,9 +120,9 @@ module eth_mac_phy_10g # /* * Configuration */ - input wire [7:0] ifg_delay, - input wire tx_prbs31_enable, - input wire rx_prbs31_enable + input wire [7:0] cfg_ifg, + input wire cfg_tx_prbs31_enable, + input wire cfg_rx_prbs31_enable ); eth_mac_phy_10g_rx #( @@ -163,7 +163,7 @@ eth_mac_phy_10g_rx_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); eth_mac_phy_10g_tx #( @@ -203,8 +203,8 @@ eth_mac_phy_10g_tx_inst ( .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .tx_start_packet(tx_start_packet), .tx_error_underflow(tx_error_underflow), - .ifg_delay(ifg_delay), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_ifg(cfg_ifg), + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 6205cdca1..220a3396d 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -147,9 +147,9 @@ module eth_mac_phy_10g_fifo # /* * Configuration */ - input wire [7:0] ifg_delay, - input wire tx_prbs31_enable, - input wire rx_prbs31_enable + input wire [7:0] cfg_ifg, + input wire cfg_tx_prbs31_enable, + input wire cfg_rx_prbs31_enable ); parameter KEEP_WIDTH = DATA_WIDTH/8; @@ -425,10 +425,10 @@ eth_mac_phy_10g_inst ( .rx_high_ber(rx_high_ber_int), .rx_status(rx_status_int), - .ifg_delay(ifg_delay), + .cfg_ifg(cfg_ifg), - .tx_prbs31_enable(tx_prbs31_enable), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); axis_async_fifo_adapter #( diff --git a/rtl/eth_mac_phy_10g_rx.v b/rtl/eth_mac_phy_10g_rx.v index fb079ade7..3f498f0bc 100644 --- a/rtl/eth_mac_phy_10g_rx.v +++ b/rtl/eth_mac_phy_10g_rx.v @@ -90,7 +90,7 @@ module eth_mac_phy_10g_rx # /* * Configuration */ - input wire rx_prbs31_enable + input wire cfg_rx_prbs31_enable ); // bus width assertions @@ -138,7 +138,7 @@ eth_phy_10g_rx_if_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); axis_baser_rx_64 #( diff --git a/rtl/eth_mac_phy_10g_tx.v b/rtl/eth_mac_phy_10g_tx.v index 38d39c3db..91c992014 100644 --- a/rtl/eth_mac_phy_10g_tx.v +++ b/rtl/eth_mac_phy_10g_tx.v @@ -89,8 +89,8 @@ module eth_mac_phy_10g_tx # /* * Configuration */ - input wire [7:0] ifg_delay, - input wire tx_prbs31_enable + input wire [7:0] cfg_ifg, + input wire cfg_tx_prbs31_enable ); // bus width assertions @@ -147,7 +147,7 @@ axis_baser_tx_inst ( .m_axis_ptp_ts_valid(m_axis_ptp_ts_valid), .start_packet(tx_start_packet), .error_underflow(tx_error_underflow), - .ifg_delay(ifg_delay) + .cfg_ifg(cfg_ifg) ); eth_phy_10g_tx_if #( @@ -165,7 +165,7 @@ eth_phy_10g_tx_if_inst ( .encoded_tx_hdr(encoded_tx_hdr), .serdes_tx_data(serdes_tx_data), .serdes_tx_hdr(serdes_tx_hdr), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_phy_10g.v b/rtl/eth_phy_10g.v index 7fe6d82e9..c26af2195 100644 --- a/rtl/eth_phy_10g.v +++ b/rtl/eth_phy_10g.v @@ -83,8 +83,8 @@ module eth_phy_10g # /* * Configuration */ - input wire tx_prbs31_enable, - input wire rx_prbs31_enable + input wire cfg_tx_prbs31_enable, + input wire cfg_rx_prbs31_enable ); eth_phy_10g_rx #( @@ -114,7 +114,7 @@ eth_phy_10g_rx_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); eth_phy_10g_tx #( @@ -134,7 +134,7 @@ eth_phy_10g_tx_inst ( .serdes_tx_data(serdes_tx_data), .serdes_tx_hdr(serdes_tx_hdr), .tx_bad_block(tx_bad_block), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_phy_10g_rx.v b/rtl/eth_phy_10g_rx.v index 1b1695e50..f9030dd3e 100644 --- a/rtl/eth_phy_10g_rx.v +++ b/rtl/eth_phy_10g_rx.v @@ -75,7 +75,7 @@ module eth_phy_10g_rx # /* * Configuration */ - input wire rx_prbs31_enable + input wire cfg_rx_prbs31_enable ); // bus width assertions @@ -125,7 +125,7 @@ eth_phy_10g_rx_if_inst ( .rx_block_lock(rx_block_lock), .rx_high_ber(rx_high_ber), .rx_status(rx_status), - .rx_prbs31_enable(rx_prbs31_enable) + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) ); xgmii_baser_dec_64 #( diff --git a/rtl/eth_phy_10g_rx_if.v b/rtl/eth_phy_10g_rx_if.v index 531c197ed..26eb8ed04 100644 --- a/rtl/eth_phy_10g_rx_if.v +++ b/rtl/eth_phy_10g_rx_if.v @@ -74,7 +74,7 @@ module eth_phy_10g_rx_if # /* * Configuration */ - input wire rx_prbs31_enable + input wire cfg_rx_prbs31_enable ); // bus width assertions @@ -206,7 +206,7 @@ always @(posedge clk) begin encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data; encoded_rx_hdr_reg <= serdes_rx_hdr_int; - if (PRBS31_ENABLE && rx_prbs31_enable) begin + if (PRBS31_ENABLE && cfg_rx_prbs31_enable) begin prbs31_state_reg <= prbs31_state; rx_error_count_1_reg <= rx_error_count_1_temp; @@ -222,8 +222,8 @@ assign rx_error_count = rx_error_count_reg; wire serdes_rx_bitslip_int; wire serdes_rx_reset_req_int; -assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31_enable); -assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && rx_prbs31_enable); +assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable); +assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable); eth_phy_10g_rx_frame_sync #( .HDR_WIDTH(HDR_WIDTH), diff --git a/rtl/eth_phy_10g_tx.v b/rtl/eth_phy_10g_tx.v index 692ce4e7d..43d7a6c02 100644 --- a/rtl/eth_phy_10g_tx.v +++ b/rtl/eth_phy_10g_tx.v @@ -65,7 +65,7 @@ module eth_phy_10g_tx # /* * Configuration */ - input wire tx_prbs31_enable + input wire cfg_tx_prbs31_enable ); // bus width assertions @@ -119,7 +119,7 @@ eth_phy_10g_tx_if_inst ( .encoded_tx_hdr(encoded_tx_hdr), .serdes_tx_data(serdes_tx_data), .serdes_tx_hdr(serdes_tx_hdr), - .tx_prbs31_enable(tx_prbs31_enable) + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) ); endmodule diff --git a/rtl/eth_phy_10g_tx_if.v b/rtl/eth_phy_10g_tx_if.v index d61474e7f..2c5314365 100644 --- a/rtl/eth_phy_10g_tx_if.v +++ b/rtl/eth_phy_10g_tx_if.v @@ -59,7 +59,7 @@ module eth_phy_10g_tx_if # /* * Configuration */ - input wire tx_prbs31_enable + input wire cfg_tx_prbs31_enable ); // bus width assertions @@ -167,7 +167,7 @@ prbs31_gen_inst ( always @(posedge clk) begin scrambler_state_reg <= scrambler_state; - if (PRBS31_ENABLE && tx_prbs31_enable) begin + if (PRBS31_ENABLE && cfg_tx_prbs31_enable) begin prbs31_state_reg <= prbs31_state; serdes_tx_data_reg <= ~prbs31_data[DATA_WIDTH+HDR_WIDTH-1:HDR_WIDTH]; diff --git a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py index 7888712a5..4b3cb87ab 100644 --- a/tb/axis_baser_tx_64/test_axis_baser_tx_64.py +++ b/tb/axis_baser_tx_64/test_axis_baser_tx_64.py @@ -73,7 +73,7 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -91,7 +91,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -135,7 +135,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/axis_gmii_tx/test_axis_gmii_tx.py b/tb/axis_gmii_tx/test_axis_gmii_tx.py index 93fad4bd9..7176204a4 100644 --- a/tb/axis_gmii_tx/test_axis_gmii_tx.py +++ b/tb/axis_gmii_tx/test_axis_gmii_tx.py @@ -67,7 +67,7 @@ class TB: dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -103,7 +103,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_ tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.mii_select.value = mii_sel if enable_gen is not None: diff --git a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py index da8c52f3d..790af2da9 100644 --- a/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py +++ b/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py @@ -62,7 +62,7 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -120,7 +120,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py index 29189b382..df6708826 100644 --- a/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py +++ b/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py @@ -62,7 +62,7 @@ class TB: self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -80,7 +80,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -124,7 +124,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): byte_width = tb.source.width // 8 - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_10g/test_eth_mac_10g.py b/tb/eth_mac_10g/test_eth_mac_10g.py index c4363d464..842ecfa9a 100644 --- a/tb/eth_mac_10g/test_eth_mac_10g.py +++ b/tb/eth_mac_10g/test_eth_mac_10g.py @@ -88,7 +88,7 @@ class TB: dut.tx_lfc_pause_en.setimmediatevalue(0) dut.tx_pause_req.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) @@ -141,7 +141,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -185,7 +185,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -230,7 +230,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -313,7 +313,7 @@ async def run_test_lfc(dut, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -456,7 +456,7 @@ async def run_test_pfc(dut, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index eadfe14fa..dc35847f0 100644 --- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -75,6 +75,8 @@ class TB: dut.ptp_sample_clk.setimmediatevalue(0) dut.ptp_ts_step.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) + async def reset(self): self.dut.logic_rst.setimmediatevalue(0) self.dut.rx_rst.setimmediatevalue(0) @@ -98,7 +100,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -146,7 +148,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -195,7 +197,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.xgmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_1g/test_eth_mac_1g.py b/tb/eth_mac_1g/test_eth_mac_1g.py index ab0a48919..1a7a50a07 100644 --- a/tb/eth_mac_1g/test_eth_mac_1g.py +++ b/tb/eth_mac_1g/test_eth_mac_1g.py @@ -95,7 +95,7 @@ class TB: dut.rx_mii_select.setimmediatevalue(0) dut.tx_mii_select.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) @@ -184,7 +184,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -230,7 +230,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -273,7 +273,7 @@ async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True): tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -422,7 +422,7 @@ async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True): tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel diff --git a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py index 8cb333bbb..c37e8c268 100644 --- a/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py +++ b/tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py @@ -66,7 +66,7 @@ class TB: dut.tx_clk_enable.setimmediatevalue(1) dut.rx_mii_select.setimmediatevalue(0) dut.tx_mii_select.setimmediatevalue(0) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -127,7 +127,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel @@ -160,7 +160,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab tb = TB(dut) tb.gmii_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.dut.rx_mii_select.value = mii_sel tb.dut.tx_mii_select.value = mii_sel diff --git a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py index 295427efc..e0e3cd32a 100644 --- a/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py +++ b/tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py @@ -53,7 +53,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.gtx_rst.setimmediatevalue(0) @@ -75,7 +75,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) @@ -114,7 +114,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) diff --git a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py index 7ed984a0a..c080369f5 100644 --- a/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py +++ b/tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py @@ -54,7 +54,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.gtx_rst.setimmediatevalue(0) @@ -79,7 +79,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) @@ -118,7 +118,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.gmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg tb.set_speed(speed) diff --git a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py index 52328b873..c19ad0298 100644 --- a/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py +++ b/tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py @@ -50,7 +50,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.gtx_clk.setimmediatevalue(0) dut.gtx_clk90.setimmediatevalue(0) @@ -86,7 +86,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -123,7 +123,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py index 3e162174f..a6cbcea56 100644 --- a/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py +++ b/tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py @@ -53,7 +53,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) dut.gtx_clk.setimmediatevalue(0) dut.gtx_clk90.setimmediatevalue(0) @@ -92,7 +92,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -129,7 +129,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.rgmii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_mii/test_eth_mac_mii.py b/tb/eth_mac_mii/test_eth_mac_mii.py index b144a509c..f038895ab 100644 --- a/tb/eth_mac_mii/test_eth_mac_mii.py +++ b/tb/eth_mac_mii/test_eth_mac_mii.py @@ -50,7 +50,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -69,7 +69,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -96,7 +96,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py index d154fb859..6da182e21 100644 --- a/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py +++ b/tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py @@ -53,7 +53,7 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst) - dut.ifg_delay.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -72,7 +72,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -99,7 +99,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee tb = TB(dut, speed) tb.mii_phy.rx.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py index bda5fec48..74b07ba94 100644 --- a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py +++ b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py @@ -83,8 +83,9 @@ class TB: self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) - dut.tx_prbs31_enable.setimmediatevalue(0) - dut.rx_prbs31_enable.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) async def reset(self): self.dut.rx_rst.setimmediatevalue(0) @@ -106,7 +107,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -159,7 +160,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -204,7 +205,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index 70abb425b..b470e789e 100644 --- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -86,8 +86,9 @@ class TB: dut.ptp_sample_clk.setimmediatevalue(0) dut.ptp_ts_step.setimmediatevalue(0) - dut.tx_prbs31_enable.setimmediatevalue(0) - dut.rx_prbs31_enable.setimmediatevalue(0) + dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) async def reset(self): self.dut.logic_rst.setimmediatevalue(0) @@ -112,7 +113,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -167,7 +168,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb = TB(dut) tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() @@ -216,7 +217,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): byte_width = tb.axis_source.width // 8 tb.serdes_source.ifg = ifg - tb.dut.ifg_delay.value = ifg + tb.dut.cfg_ifg.value = ifg await tb.reset() diff --git a/tb/eth_phy_10g/test_eth_phy_10g.py b/tb/eth_phy_10g/test_eth_phy_10g.py index 73275f61e..6280adaff 100644 --- a/tb/eth_phy_10g/test_eth_phy_10g.py +++ b/tb/eth_phy_10g/test_eth_phy_10g.py @@ -64,8 +64,8 @@ class TB: self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip) self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk) - dut.tx_prbs31_enable.setimmediatevalue(0) - dut.rx_prbs31_enable.setimmediatevalue(0) + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) async def reset(self): self.dut.tx_rst.setimmediatevalue(0)