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merged changes in axi

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This commit is contained in:
Alex Forencich 2023-01-29 23:00:23 -08:00
commit 2158c4ef9c
29 changed files with 121 additions and 516 deletions
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8
fpga/lib/axi/.github/workflows/regression-tests.yml vendored
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@ -9,14 +9,14 @@ jobs:
strategy:
matrix:
python-version: [3.9]
python-version: ["3.10"]
group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10]
steps:
- uses: actions/checkout@v1
- uses: actions/checkout@v3
- name: Set up Python ${{ matrix.python-version }}
uses: actions/setup-python@v2
uses: actions/setup-python@v4
with:
python-version: ${{ matrix.python-version }}
@ -30,4 +30,4 @@ jobs:
pip install tox tox-gh-actions
- name: Test with tox
run: tox -- --splits 10 --group ${{ matrix.group }} --splitting-algorithm least_duration
run: tox -- -n auto --verbose --splits 10 --group ${{ matrix.group }} --splitting-algorithm least_duration

36
fpga/lib/axi/rtl/axi_adapter_rd.v
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@ -465,11 +465,11 @@ always @* begin
burst_size_next = s_axi_arsize;
if (s_axi_arsize > M_BURST_SIZE) begin
// need to adjust burst size
if ({s_axi_arlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_arsize) > 255) begin
if (s_axi_arlen >> (8+M_BURST_SIZE-s_axi_arsize) != 0) begin
// limit burst length to max
master_burst_next = 8'd255;
master_burst_next = (8'd255 << (s_axi_arsize-M_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> M_BURST_SIZE);
end else begin
master_burst_next = {s_axi_arlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_arsize);
master_burst_next = (s_axi_arlen << (s_axi_arsize-M_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> M_BURST_SIZE);
end
master_burst_size_next = M_BURST_SIZE;
m_axi_arlen_next = master_burst_next;
@ -510,13 +510,22 @@ always @* begin
s_axi_ruser_int = m_axi_ruser;
s_axi_rvalid_int = 1'b0;
master_burst_next = master_burst_reg - 1;
addr_next = addr_reg + (1 << master_burst_size_reg);
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
m_axi_araddr_next = addr_next;
if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
data_next = {DATA_WIDTH{1'b0}};
burst_next = burst_reg - 1;
s_axi_rvalid_int = 1'b1;
end
if (master_burst_reg == 0) begin
if (burst_next >> (8+M_BURST_SIZE-burst_size_reg) != 0) begin
// limit burst length to max
master_burst_next = 8'd255;
end else begin
master_burst_next = (burst_next << (burst_size_reg-M_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> M_BURST_SIZE);
end
m_axi_arlen_next = master_burst_next;
if (burst_reg == 0) begin
m_axi_rready_next = 1'b0;
s_axi_rlast_int = 1'b1;
@ -525,25 +534,6 @@ always @* begin
state_next = STATE_IDLE;
end else begin
// start new burst
m_axi_araddr_next = addr_next;
if (burst_size_reg > M_BURST_SIZE) begin
// need to adjust burst size
if ({burst_next, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg) > 255) begin
// limit burst length to max
master_burst_next = 8'd255;
end else begin
master_burst_next = {burst_next, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg);
end
master_burst_size_next = M_BURST_SIZE;
m_axi_arlen_next = master_burst_next;
m_axi_arsize_next = master_burst_size_next;
end else begin
// pass through narrow (enough) burst
master_burst_next = burst_next;
master_burst_size_next = burst_size_reg;
m_axi_arlen_next = burst_next;
m_axi_arsize_next = burst_size_reg;
end
m_axi_arvalid_next = 1'b1;
m_axi_rready_next = 1'b0;
state_next = STATE_DATA;

40
fpga/lib/axi/rtl/axi_adapter_wr.v
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@ -511,11 +511,11 @@ always @* begin
burst_active_next = 1'b1;
if (s_axi_awsize > M_BURST_SIZE) begin
// need to adjust burst size
if ({s_axi_awlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_awsize) > 255) begin
if (s_axi_awlen >> (8+M_BURST_SIZE-s_axi_awsize) != 0) begin
// limit burst length to max
master_burst_next = 8'd255;
master_burst_next = (8'd255 << (s_axi_awsize-M_BURST_SIZE)) | ((~s_axi_awaddr & (8'hff >> (8-s_axi_awsize))) >> M_BURST_SIZE);
end else begin
master_burst_next = {s_axi_awlen, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-s_axi_awsize);
master_burst_next = (s_axi_awlen << (s_axi_awsize-M_BURST_SIZE)) | ((~s_axi_awaddr & (8'hff >> (8-s_axi_awsize))) >> M_BURST_SIZE);
end
master_burst_size_next = M_BURST_SIZE;
m_axi_awlen_next = master_burst_next;
@ -556,7 +556,7 @@ always @* begin
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
master_burst_next = master_burst_reg - 1;
addr_next = addr_reg + (1 << master_burst_size_reg);
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
if (master_burst_reg == 0) begin
s_axi_wready_next = 1'b0;
m_axi_bready_next = !s_axi_bvalid && !s_axi_awvalid;
@ -582,7 +582,7 @@ always @* begin
m_axi_wuser_int = wuser_reg;
m_axi_wvalid_int = 1'b1;
master_burst_next = master_burst_reg - 1;
addr_next = addr_reg + (1 << master_burst_size_reg);
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
if (master_burst_reg == 0) begin
// burst on master interface finished; transfer response
s_axi_wready_next = 1'b0;
@ -610,27 +610,19 @@ always @* begin
if (first_transfer_reg || m_axi_bresp != 0) begin
s_axi_bresp_next = m_axi_bresp;
end
if (burst_reg >> (8+M_BURST_SIZE-burst_size_reg) != 0) begin
// limit burst length to max
master_burst_next = 8'd255;
end else begin
master_burst_next = (burst_reg << (burst_size_reg-M_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> M_BURST_SIZE);
end
master_burst_size_next = M_BURST_SIZE;
m_axi_awaddr_next = addr_reg;
m_axi_awlen_next = master_burst_next;
m_axi_awsize_next = master_burst_size_next;
if (burst_active_reg) begin
// burst on slave interface still active; start new burst
m_axi_awaddr_next = addr_reg;
if (burst_size_reg > M_BURST_SIZE) begin
// need to adjust burst size
if ({burst_reg, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg) > 255) begin
// limit burst length to max
master_burst_next = 8'd255;
end else begin
master_burst_next = {burst_reg, {S_BURST_SIZE-M_BURST_SIZE{1'b1}}} >> (S_BURST_SIZE-burst_size_reg);
end
master_burst_size_next = M_BURST_SIZE;
m_axi_awlen_next = master_burst_next;
m_axi_awsize_next = master_burst_size_next;
end else begin
// pass through narrow (enough) burst
master_burst_next = burst_reg;
master_burst_size_next = burst_size_reg;
m_axi_awlen_next = burst_reg;
m_axi_awsize_next = burst_size_reg;
end
m_axi_awvalid_next = 1'b1;
state_next = STATE_DATA;
end else begin

33
fpga/lib/axi/rtl/axi_axil_adapter_rd.v
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@ -388,11 +388,11 @@ always @* begin
burst_size_next = s_axi_arsize;
if (s_axi_arsize > AXIL_BURST_SIZE) begin
// need to adjust burst size
if ({s_axi_arlen, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-s_axi_arsize) > 255) begin
if (s_axi_arlen >> (8+AXIL_BURST_SIZE-s_axi_arsize) != 0) begin
// limit burst length to max
master_burst_next = 8'd255;
master_burst_next = (8'd255 << (s_axi_arsize-AXIL_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> AXIL_BURST_SIZE);
end else begin
master_burst_next = {s_axi_arlen, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-s_axi_arsize);
master_burst_next = (s_axi_arlen << (s_axi_arsize-AXIL_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> AXIL_BURST_SIZE);
end
master_burst_size_next = AXIL_BURST_SIZE;
end else begin
@ -422,13 +422,21 @@ always @* begin
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b0;
master_burst_next = master_burst_reg - 1;
addr_next = addr_reg + (1 << master_burst_size_reg);
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
m_axil_araddr_next = addr_next;
if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
data_next = {DATA_WIDTH{1'b0}};
burst_next = burst_reg - 1;
s_axi_rvalid_next = 1'b1;
end
if (master_burst_reg == 0) begin
if (burst_next >> (8+AXIL_BURST_SIZE-burst_size_reg) != 0) begin
// limit burst length to max
master_burst_next = 8'd255;
end else begin
master_burst_next = (burst_next << (burst_size_reg-AXIL_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> AXIL_BURST_SIZE);
end
if (burst_reg == 0) begin
m_axil_rready_next = 1'b0;
s_axi_rlast_next = 1'b1;
@ -436,28 +444,11 @@ always @* begin
s_axi_arready_next = !m_axil_arvalid;
state_next = STATE_IDLE;
end else begin
// start new burst
m_axil_araddr_next = addr_next;
if (burst_size_reg > AXIL_BURST_SIZE) begin
// need to adjust burst size
if ({burst_next, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-burst_size_reg) > 255) begin
// limit burst length to max
master_burst_next = 8'd255;
end else begin
master_burst_next = {burst_next, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-burst_size_reg);
end
master_burst_size_next = AXIL_BURST_SIZE;
end else begin
// pass through narrow (enough) burst
master_burst_next = burst_next;
master_burst_size_next = burst_size_reg;
end
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;

6
fpga/lib/axi/rtl/axi_axil_adapter_wr.v
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@ -456,7 +456,7 @@ always @* begin
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = addr_reg + (1 << master_burst_size_reg);
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
@ -472,7 +472,7 @@ always @* begin
m_axil_wdata_next = data_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
m_axil_wstrb_next = strb_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
m_axil_wvalid_next = 1'b1;
addr_next = addr_reg + (1 << master_burst_size_reg);
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
@ -487,6 +487,7 @@ always @* begin
if (m_axil_bready && m_axil_bvalid) begin
first_transfer_next = 1'b0;
m_axil_awaddr_next = addr_reg;
m_axil_bready_next = 1'b0;
s_axi_bid_next = id_reg;
if (first_transfer_reg || m_axil_bresp != 0) begin
@ -494,7 +495,6 @@ always @* begin
end
if (burst_active_reg || !last_segment_reg) begin
// burst on slave interface still active; start new burst
m_axil_awaddr_next = addr_reg;
m_axil_awvalid_next = 1'b1;
if (last_segment_reg) begin
s_axi_wready_next = !m_axil_wvalid;

10
fpga/lib/axi/rtl/axil_adapter_rd.v
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@ -79,6 +79,8 @@ parameter S_WORD_WIDTH = S_STRB_WIDTH;
parameter M_WORD_WIDTH = M_STRB_WIDTH;
parameter S_WORD_SIZE = S_DATA_WIDTH/S_WORD_WIDTH;
parameter M_WORD_SIZE = M_DATA_WIDTH/M_WORD_WIDTH;
parameter S_ADDR_MASK = {ADDR_WIDTH{1'b1}} << S_ADDR_BIT_OFFSET;
parameter M_ADDR_MASK = {ADDR_WIDTH{1'b1}} << M_ADDR_BIT_OFFSET;
// output bus is wider
parameter EXPAND = M_STRB_WIDTH > S_STRB_WIDTH;
@ -203,12 +205,12 @@ always @* begin
STATE_IDLE: begin
s_axil_arready_next = !m_axil_arvalid;
current_segment_next = 0;
current_segment_next = s_axil_araddr >> M_ADDR_BIT_OFFSET;
s_axil_rresp_next = 2'd0;
if (s_axil_arready && s_axil_arvalid) begin
s_axil_arready_next = 1'b0;
m_axil_araddr_next = s_axil_araddr & ({ADDR_WIDTH{1'b1}} << S_ADDR_BIT_OFFSET);
m_axil_araddr_next = s_axil_araddr;
m_axil_arprot_next = s_axil_arprot;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = !m_axil_rvalid;
@ -222,7 +224,9 @@ always @* begin
if (m_axil_rready && m_axil_rvalid) begin
m_axil_rready_next = 1'b0;
m_axil_araddr_next = (m_axil_araddr_reg & M_ADDR_MASK) + SEGMENT_STRB_WIDTH;
s_axil_rdata_next[current_segment_reg*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
current_segment_next = current_segment_reg + 1;
if (m_axil_rresp) begin
s_axil_rresp_next = m_axil_rresp;
end
@ -231,8 +235,6 @@ always @* begin
s_axil_arready_next = !m_axil_arvalid;
state_next = STATE_IDLE;
end else begin
current_segment_next = current_segment_reg + 1;
m_axil_araddr_next = m_axil_araddr_reg + SEGMENT_STRB_WIDTH;
m_axil_arvalid_next = 1'b1;
state_next = STATE_DATA;
end

21
fpga/lib/axi/rtl/axil_adapter_wr.v
View File

@ -85,6 +85,8 @@ parameter S_WORD_WIDTH = S_STRB_WIDTH;
parameter M_WORD_WIDTH = M_STRB_WIDTH;
parameter S_WORD_SIZE = S_DATA_WIDTH/S_WORD_WIDTH;
parameter M_WORD_SIZE = M_DATA_WIDTH/M_WORD_WIDTH;
parameter S_ADDR_MASK = {ADDR_WIDTH{1'b1}} << S_ADDR_BIT_OFFSET;
parameter M_ADDR_MASK = {ADDR_WIDTH{1'b1}} << M_ADDR_BIT_OFFSET;
// output bus is wider
parameter EXPAND = M_STRB_WIDTH > S_STRB_WIDTH;
@ -239,12 +241,12 @@ always @* begin
STATE_IDLE: begin
s_axil_awready_next = !m_axil_awvalid;
current_segment_next = 0;
current_segment_next = s_axil_awaddr >> M_ADDR_BIT_OFFSET;
s_axil_bresp_next = 2'd0;
if (s_axil_awready && s_axil_awvalid) begin
s_axil_awready_next = 1'b0;
m_axil_awaddr_next = s_axil_awaddr & ({ADDR_WIDTH{1'b1}} << S_ADDR_BIT_OFFSET);
m_axil_awaddr_next = s_axil_awaddr;
m_axil_awprot_next = s_axil_awprot;
m_axil_awvalid_next = 1'b1;
s_axil_wready_next = !m_axil_wvalid;
@ -260,10 +262,11 @@ always @* begin
s_axil_wready_next = 1'b0;
data_next = s_axil_wdata;
strb_next = s_axil_wstrb;
m_axil_wdata_next = s_axil_wdata;
m_axil_wstrb_next = s_axil_wstrb;
m_axil_wdata_next = data_next >> current_segment_reg*SEGMENT_DATA_WIDTH;
m_axil_wstrb_next = strb_next >> current_segment_reg*SEGMENT_STRB_WIDTH;
m_axil_wvalid_next = 1'b1;
m_axil_bready_next = !s_axil_bvalid;
current_segment_next = current_segment_reg + 1;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA;
@ -274,19 +277,19 @@ always @* begin
if (m_axil_bready && m_axil_bvalid) begin
m_axil_bready_next = 1'b0;
m_axil_awaddr_next = (m_axil_awaddr_reg & M_ADDR_MASK) + SEGMENT_STRB_WIDTH;
m_axil_wdata_next = data_next >> current_segment_reg*SEGMENT_DATA_WIDTH;
m_axil_wstrb_next = strb_next >> current_segment_reg*SEGMENT_STRB_WIDTH;
current_segment_next = current_segment_reg + 1;
if (m_axil_bresp != 0) begin
s_axil_bresp_next = m_axil_bresp;
end
if (current_segment_reg == SEGMENT_COUNT-1) begin
if (current_segment_reg == 0) begin
s_axil_bvalid_next = 1'b1;
s_axil_awready_next = !m_axil_awvalid;
state_next = STATE_IDLE;
end else begin
current_segment_next = current_segment_reg + 1;
m_axil_awaddr_next = m_axil_awaddr_reg + SEGMENT_STRB_WIDTH;
m_axil_awvalid_next = 1'b1;
m_axil_wdata_next = data_reg >> (current_segment_reg+1)*SEGMENT_DATA_WIDTH;
m_axil_wstrb_next = strb_reg >> (current_segment_reg+1)*SEGMENT_STRB_WIDTH;
m_axil_wvalid_next = 1'b1;
state_next = STATE_RESP;
end

10
fpga/lib/axi/syn/vivado/axil_cdc.tcl
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@ -24,13 +24,13 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == axil_cdc_rd || REF_NAME
puts "Inserting timing constraints for axil_cdc instance $inst"
# get clock periods
set m_clk [get_clocks -of_objects [get_pins $inst/m_flag_reg_reg/C]]
set s_clk [get_clocks -of_objects [get_pins $inst/s_flag_reg_reg/C]]
set s_clk [get_clocks -of_objects [get_cells "$inst/s_flag_reg_reg"]]
set m_clk [get_clocks -of_objects [get_cells "$inst/m_flag_reg_reg"]]
set m_clk_period [get_property -min PERIOD $m_clk]
set s_clk_period [get_property -min PERIOD $s_clk]
set s_clk_period [if {[llength $s_clk]} {get_property -min PERIOD $s_clk} {expr 1.0}]
set m_clk_period [if {[llength $m_clk]} {get_property -min PERIOD $m_clk} {expr 1.0}]
set min_clk_period [expr $m_clk_period < $s_clk_period ? $m_clk_period : $s_clk_period]
set min_clk_period [expr min($s_clk_period, $m_clk_period)]
set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/m_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]
set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/s_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]

40
fpga/lib/axi/tb/axi_adapter/Makefile
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@ -57,25 +57,7 @@ export PARAM_FORWARD_ID ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).S_STRB_WIDTH=$(PARAM_S_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_STRB_WIDTH=$(PARAM_M_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).CONVERT_BURST=$(PARAM_CONVERT_BURST)
COMPILE_ARGS += -P $(TOPLEVEL).CONVERT_NARROW_BURST=$(PARAM_CONVERT_NARROW_BURST)
COMPILE_ARGS += -P $(TOPLEVEL).FORWARD_ID=$(PARAM_FORWARD_ID)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -84,25 +66,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
COMPILE_ARGS += -GS_STRB_WIDTH=$(PARAM_S_STRB_WIDTH)
COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
COMPILE_ARGS += -GM_STRB_WIDTH=$(PARAM_M_STRB_WIDTH)
COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -GAWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -GAWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -GWUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -GWUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -GBUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -GBUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -GARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -GARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -GRUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -GRUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -GCONVERT_BURST=$(PARAM_CONVERT_BURST)
COMPILE_ARGS += -GCONVERT_NARROW_BURST=$(PARAM_CONVERT_NARROW_BURST)
COMPILE_ARGS += -GFORWARD_ID=$(PARAM_FORWARD_ID)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

18
fpga/lib/axi/tb/axi_axil_adapter/Makefile
View File

@ -46,14 +46,7 @@ export PARAM_CONVERT_NARROW_BURST ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).CONVERT_BURST=$(PARAM_CONVERT_BURST)
COMPILE_ARGS += -P $(TOPLEVEL).CONVERT_NARROW_BURST=$(PARAM_CONVERT_NARROW_BURST)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -62,14 +55,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -GAXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
COMPILE_ARGS += -GCONVERT_BURST=$(PARAM_CONVERT_BURST)
COMPILE_ARGS += -GCONVERT_NARROW_BURST=$(PARAM_CONVERT_NARROW_BURST)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

18
fpga/lib/axi/tb/axi_cdma/Makefile
View File

@ -44,14 +44,7 @@ export PARAM_ENABLE_UNALIGNED = 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -60,14 +53,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -GAXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

34
fpga/lib/axi/tb/axi_crossbar/Makefile
View File

@ -64,22 +64,7 @@ export PARAM_M_REGIONS ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).S_ID_WIDTH=$(PARAM_S_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_ID_WIDTH=$(PARAM_M_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -88,22 +73,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GS_ID_WIDTH=$(PARAM_S_ID_WIDTH)
COMPILE_ARGS += -GM_ID_WIDTH=$(PARAM_M_ID_WIDTH)
COMPILE_ARGS += -GAWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -GAWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -GWUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -GWUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -GBUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -GBUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -GARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -GARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -GRUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -GRUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -GM_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

40
fpga/lib/axi/tb/axi_dma/Makefile
View File

@ -57,25 +57,7 @@ export PARAM_ENABLE_UNALIGNED = 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_LAST_ENABLE=$(PARAM_AXIS_LAST_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ID_ENABLE=$(PARAM_AXIS_ID_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ID_WIDTH=$(PARAM_AXIS_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DEST_ENABLE=$(PARAM_AXIS_DEST_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DEST_WIDTH=$(PARAM_AXIS_DEST_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_USER_ENABLE=$(PARAM_AXIS_USER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_USER_WIDTH=$(PARAM_AXIS_USER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_SG=$(PARAM_ENABLE_SG)
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -84,25 +66,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -GAXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
COMPILE_ARGS += -GAXIS_LAST_ENABLE=$(PARAM_AXIS_LAST_ENABLE)
COMPILE_ARGS += -GAXIS_ID_ENABLE=$(PARAM_AXIS_ID_ENABLE)
COMPILE_ARGS += -GAXIS_ID_WIDTH=$(PARAM_AXIS_ID_WIDTH)
COMPILE_ARGS += -GAXIS_DEST_ENABLE=$(PARAM_AXIS_DEST_ENABLE)
COMPILE_ARGS += -GAXIS_DEST_WIDTH=$(PARAM_AXIS_DEST_WIDTH)
COMPILE_ARGS += -GAXIS_USER_ENABLE=$(PARAM_AXIS_USER_ENABLE)
COMPILE_ARGS += -GAXIS_USER_WIDTH=$(PARAM_AXIS_USER_WIDTH)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GENABLE_SG=$(PARAM_ENABLE_SG)
COMPILE_ARGS += -GENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

40
fpga/lib/axi/tb/axi_dma_rd/Makefile
View File

@ -55,25 +55,7 @@ export PARAM_ENABLE_UNALIGNED = 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_LAST_ENABLE=$(PARAM_AXIS_LAST_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ID_ENABLE=$(PARAM_AXIS_ID_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ID_WIDTH=$(PARAM_AXIS_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DEST_ENABLE=$(PARAM_AXIS_DEST_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DEST_WIDTH=$(PARAM_AXIS_DEST_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_USER_ENABLE=$(PARAM_AXIS_USER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_USER_WIDTH=$(PARAM_AXIS_USER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_SG=$(PARAM_ENABLE_SG)
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -82,25 +64,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -GAXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
COMPILE_ARGS += -GAXIS_LAST_ENABLE=$(PARAM_AXIS_LAST_ENABLE)
COMPILE_ARGS += -GAXIS_ID_ENABLE=$(PARAM_AXIS_ID_ENABLE)
COMPILE_ARGS += -GAXIS_ID_WIDTH=$(PARAM_AXIS_ID_WIDTH)
COMPILE_ARGS += -GAXIS_DEST_ENABLE=$(PARAM_AXIS_DEST_ENABLE)
COMPILE_ARGS += -GAXIS_DEST_WIDTH=$(PARAM_AXIS_DEST_WIDTH)
COMPILE_ARGS += -GAXIS_USER_ENABLE=$(PARAM_AXIS_USER_ENABLE)
COMPILE_ARGS += -GAXIS_USER_WIDTH=$(PARAM_AXIS_USER_WIDTH)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GENABLE_SG=$(PARAM_ENABLE_SG)
COMPILE_ARGS += -GENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

40
fpga/lib/axi/tb/axi_dma_wr/Makefile
View File

@ -55,25 +55,7 @@ export PARAM_ENABLE_UNALIGNED = 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_LAST_ENABLE=$(PARAM_AXIS_LAST_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ID_ENABLE=$(PARAM_AXIS_ID_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ID_WIDTH=$(PARAM_AXIS_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DEST_ENABLE=$(PARAM_AXIS_DEST_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DEST_WIDTH=$(PARAM_AXIS_DEST_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_USER_ENABLE=$(PARAM_AXIS_USER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_USER_WIDTH=$(PARAM_AXIS_USER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_SG=$(PARAM_ENABLE_SG)
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -82,25 +64,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -GAXI_MAX_BURST_LEN=$(PARAM_AXI_MAX_BURST_LEN)
COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
COMPILE_ARGS += -GAXIS_LAST_ENABLE=$(PARAM_AXIS_LAST_ENABLE)
COMPILE_ARGS += -GAXIS_ID_ENABLE=$(PARAM_AXIS_ID_ENABLE)
COMPILE_ARGS += -GAXIS_ID_WIDTH=$(PARAM_AXIS_ID_WIDTH)
COMPILE_ARGS += -GAXIS_DEST_ENABLE=$(PARAM_AXIS_DEST_ENABLE)
COMPILE_ARGS += -GAXIS_DEST_WIDTH=$(PARAM_AXIS_DEST_WIDTH)
COMPILE_ARGS += -GAXIS_USER_ENABLE=$(PARAM_AXIS_USER_ENABLE)
COMPILE_ARGS += -GAXIS_USER_WIDTH=$(PARAM_AXIS_USER_WIDTH)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GENABLE_SG=$(PARAM_ENABLE_SG)
COMPILE_ARGS += -GENABLE_UNALIGNED=$(PARAM_ENABLE_UNALIGNED)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

12
fpga/lib/axi/tb/axi_dp_ram/Makefile
View File

@ -44,11 +44,7 @@ export PARAM_PIPELINE_OUTPUT ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -57,11 +53,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

38
fpga/lib/axi/tb/axi_fifo/Makefile
View File

@ -56,24 +56,7 @@ export PARAM_READ_FIFO_DELAY ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_FIFO_DEPTH=$(PARAM_WRITE_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_FIFO_DEPTH=$(PARAM_READ_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_FIFO_DELAY=$(PARAM_WRITE_FIFO_DELAY)
COMPILE_ARGS += -P $(TOPLEVEL).READ_FIFO_DELAY=$(PARAM_READ_FIFO_DELAY)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -82,24 +65,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -GAWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -GAWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -GWUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -GWUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -GBUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -GBUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -GARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -GARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -GRUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -GRUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -GWRITE_FIFO_DEPTH=$(PARAM_WRITE_FIFO_DEPTH)
COMPILE_ARGS += -GREAD_FIFO_DEPTH=$(PARAM_READ_FIFO_DEPTH)
COMPILE_ARGS += -GWRITE_FIFO_DELAY=$(PARAM_WRITE_FIFO_DELAY)
COMPILE_ARGS += -GREAD_FIFO_DELAY=$(PARAM_READ_FIFO_DELAY)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

34
fpga/lib/axi/tb/axi_interconnect/Makefile
View File

@ -59,22 +59,7 @@ export PARAM_M_REGIONS ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).FORWARD_ID=$(PARAM_FORWARD_ID)
COMPILE_ARGS += -P $(TOPLEVEL).M_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -83,22 +68,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -GAWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -GAWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -GWUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -GWUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -GBUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -GBUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -GARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -GARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -GRUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -GRUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -GFORWARD_ID=$(PARAM_FORWARD_ID)
COMPILE_ARGS += -GM_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

12
fpga/lib/axi/tb/axi_ram/Makefile
View File

@ -41,11 +41,7 @@ export PARAM_PIPELINE_OUTPUT ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -54,11 +50,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

40
fpga/lib/axi/tb/axi_register/Makefile
View File

@ -59,25 +59,7 @@ export PARAM_R_REG_TYPE ?= $(REG_TYPE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).ARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AW_REG_TYPE=$(PARAM_AW_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).W_REG_TYPE=$(PARAM_W_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).B_REG_TYPE=$(PARAM_B_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).AR_REG_TYPE=$(PARAM_AR_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).R_REG_TYPE=$(PARAM_R_REG_TYPE)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -86,25 +68,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
COMPILE_ARGS += -GAWUSER_ENABLE=$(PARAM_AWUSER_ENABLE)
COMPILE_ARGS += -GAWUSER_WIDTH=$(PARAM_AWUSER_WIDTH)
COMPILE_ARGS += -GWUSER_ENABLE=$(PARAM_WUSER_ENABLE)
COMPILE_ARGS += -GWUSER_WIDTH=$(PARAM_WUSER_WIDTH)
COMPILE_ARGS += -GBUSER_ENABLE=$(PARAM_BUSER_ENABLE)
COMPILE_ARGS += -GBUSER_WIDTH=$(PARAM_BUSER_WIDTH)
COMPILE_ARGS += -GARUSER_ENABLE=$(PARAM_ARUSER_ENABLE)
COMPILE_ARGS += -GARUSER_WIDTH=$(PARAM_ARUSER_WIDTH)
COMPILE_ARGS += -GRUSER_ENABLE=$(PARAM_RUSER_ENABLE)
COMPILE_ARGS += -GRUSER_WIDTH=$(PARAM_RUSER_WIDTH)
COMPILE_ARGS += -GAW_REG_TYPE=$(PARAM_AW_REG_TYPE)
COMPILE_ARGS += -GW_REG_TYPE=$(PARAM_W_REG_TYPE)
COMPILE_ARGS += -GB_REG_TYPE=$(PARAM_B_REG_TYPE)
COMPILE_ARGS += -GAR_REG_TYPE=$(PARAM_AR_REG_TYPE)
COMPILE_ARGS += -GR_REG_TYPE=$(PARAM_R_REG_TYPE)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

12
fpga/lib/axi/tb/axil_adapter/Makefile
View File

@ -43,11 +43,7 @@ export PARAM_M_STRB_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).S_STRB_WIDTH=$(PARAM_S_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_STRB_WIDTH=$(PARAM_M_STRB_WIDTH)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -56,11 +52,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
COMPILE_ARGS += -GS_STRB_WIDTH=$(PARAM_S_STRB_WIDTH)
COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
COMPILE_ARGS += -GM_STRB_WIDTH=$(PARAM_M_STRB_WIDTH)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

8
fpga/lib/axi/tb/axil_cdc/Makefile
View File

@ -41,9 +41,7 @@ export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -52,9 +50,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

10
fpga/lib/axi/tb/axil_crossbar/Makefile
View File

@ -52,10 +52,7 @@ export PARAM_M_REGIONS ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -64,10 +61,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GM_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

10
fpga/lib/axi/tb/axil_dp_ram/Makefile
View File

@ -40,10 +40,7 @@ export PARAM_PIPELINE_OUTPUT ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -52,10 +49,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

10
fpga/lib/axi/tb/axil_interconnect/Makefile
View File

@ -47,10 +47,7 @@ export PARAM_M_REGIONS ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).M_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -59,10 +56,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GM_REGIONS=$(PARAM_M_REGIONS)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

10
fpga/lib/axi/tb/axil_ram/Makefile
View File

@ -40,10 +40,7 @@ export PARAM_PIPELINE_OUTPUT ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -52,10 +49,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GPIPELINE_OUTPUT=$(PARAM_PIPELINE_OUTPUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

10
fpga/lib/axi/tb/axil_reg_if/Makefile
View File

@ -43,10 +43,7 @@ export PARAM_TIMEOUT ?= 4
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TIMEOUT=$(PARAM_TIMEOUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -55,10 +52,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GTIMEOUT=$(PARAM_TIMEOUT)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

18
fpga/lib/axi/tb/axil_register/Makefile
View File

@ -48,14 +48,7 @@ export PARAM_R_REG_TYPE ?= $(REG_TYPE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AW_REG_TYPE=$(PARAM_AW_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).W_REG_TYPE=$(PARAM_W_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).B_REG_TYPE=$(PARAM_B_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).AR_REG_TYPE=$(PARAM_AR_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).R_REG_TYPE=$(PARAM_R_REG_TYPE)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -64,14 +57,7 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
COMPILE_ARGS += -GADDR_WIDTH=$(PARAM_ADDR_WIDTH)
COMPILE_ARGS += -GSTRB_WIDTH=$(PARAM_STRB_WIDTH)
COMPILE_ARGS += -GAW_REG_TYPE=$(PARAM_AW_REG_TYPE)
COMPILE_ARGS += -GW_REG_TYPE=$(PARAM_W_REG_TYPE)
COMPILE_ARGS += -GB_REG_TYPE=$(PARAM_B_REG_TYPE)
COMPILE_ARGS += -GAR_REG_TYPE=$(PARAM_AR_REG_TYPE)
COMPILE_ARGS += -GR_REG_TYPE=$(PARAM_R_REG_TYPE)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

19
fpga/lib/axi/tox.ini
View File

@ -7,20 +7,21 @@ requires = virtualenv >= 16.1
[gh-actions]
python =
3.9: py3
3.10: py3
[testenv]
deps =
pytest == 6.2.5
pytest-xdist == 2.4.0
pytest-split == 0.4.0
cocotb == 1.6.1
cocotb-test == 0.2.1
cocotbext-axi == 0.1.16
jinja2 == 3.0.3
pytest == 7.2.1
pytest-xdist == 3.1.0
pytest-split == 0.8.0
cocotb == 1.7.2
cocotb-bus == 0.2.1
cocotb-test == 0.2.4
cocotbext-axi == 0.1.20
jinja2 == 3.1.2
commands =
pytest -n auto {posargs}
pytest {posargs:-n auto --verbose}
# pytest configuration
[pytest]