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Add assert for error_bad_fcs signal
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@ -160,6 +160,13 @@ def bench():
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def clkgen():
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clk.next = not clk
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error_bad_fcs_asserted = Signal(bool(0))
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@always(clk.posedge)
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def monitor():
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if (error_bad_fcs):
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error_bad_fcs_asserted.next = 1
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def wait_normal():
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while input_axis_tvalid or output_axis_tvalid:
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yield clk.posedge
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@ -371,6 +378,8 @@ def bench():
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axis_frame1.data[-1] ^= 0xff
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for wait in wait_normal, wait_pause_source, wait_pause_sink:
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error_bad_fcs_asserted.next = 0
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source_queue.put(axis_frame1)
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source_queue.put(axis_frame2)
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yield clk.posedge
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@ -382,6 +391,8 @@ def bench():
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yield clk.posedge
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yield clk.posedge
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assert error_bad_fcs_asserted
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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@ -405,7 +416,7 @@ def bench():
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raise StopSimulation
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return dut, source, sink, clkgen, check
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return dut, monitor, source, sink, clkgen, check
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def test_bench():
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sim = Simulation(bench())
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