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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-06-02 23:58:29 -07:00
parent 6cda5f857c
commit 21b0f014a5
255 changed files with 4183 additions and 3562 deletions
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13
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -108,6 +108,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -126,7 +127,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -153,6 +153,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -217,7 +218,9 @@ export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16 export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
export PARAM_MSI_COUNT ?= 32
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
@ -265,6 +268,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
@ -317,7 +321,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).MSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
@ -361,6 +365,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GEVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
@ -413,7 +418,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GMSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)

77
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -64,7 +64,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -94,7 +94,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -102,12 +102,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -251,33 +251,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -409,7 +409,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -819,7 +819,7 @@ async def run_test_nic(dut):
lst = [] lst = []
for k in range(64): for k in range(64):
lst.append(await tb.driver.hw_regs.read_dword(0x010000+k*8)) lst.append(await tb.driver.hw_regs.read_dword(0x020000+k*8))
print(lst) print(lst)
@ -925,6 +925,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -943,7 +944,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -971,6 +971,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -1035,7 +1036,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16 parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
parameters['MSI_COUNT'] = 32
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32

12
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -107,6 +107,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -125,7 +126,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -152,7 +152,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -217,7 +217,9 @@ export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16 export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
export PARAM_MSI_COUNT ?= 32
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
@ -318,7 +320,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).MSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
@ -415,7 +417,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GMSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)

78
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -64,7 +64,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -94,7 +94,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -102,12 +102,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -251,33 +251,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -409,7 +409,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -653,7 +653,7 @@ async def run_test_nic(dut):
lst = [] lst = []
for k in range(64): for k in range(64):
lst.append(await tb.driver.hw_regs.read_dword(0x010000+k*8)) lst.append(await tb.driver.hw_regs.read_dword(0x020000+k*8))
print(lst) print(lst)
@ -765,6 +765,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -783,7 +784,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -811,7 +811,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -876,7 +876,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16 parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
parameters['MSI_COUNT'] = 32
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32

151
fpga/common/rtl/mqnic_core.v
View File

@ -140,7 +140,10 @@ module mqnic_core #
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
parameter RAM_PIPELINE = 2, parameter RAM_PIPELINE = 2,
parameter MSI_COUNT = 32, // Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter MSIX_ENABLE = 0,
parameter AXIL_MSIX_ADDR_WIDTH = 16,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -248,6 +251,29 @@ module mqnic_core #
input wire m_axil_csr_rvalid, input wire m_axil_csr_rvalid,
output wire m_axil_csr_rready, output wire m_axil_csr_rready,
/*
* AXI-Lite master interface (MSI-X)
*/
output wire [AXIL_MSIX_ADDR_WIDTH-1:0] m_axil_msix_awaddr,
output wire [2:0] m_axil_msix_awprot,
output wire m_axil_msix_awvalid,
input wire m_axil_msix_awready,
output wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_msix_wdata,
output wire [AXIL_CTRL_STRB_WIDTH-1:0] m_axil_msix_wstrb,
output wire m_axil_msix_wvalid,
input wire m_axil_msix_wready,
input wire [1:0] m_axil_msix_bresp,
input wire m_axil_msix_bvalid,
output wire m_axil_msix_bready,
output wire [AXIL_MSIX_ADDR_WIDTH-1:0] m_axil_msix_araddr,
output wire [2:0] m_axil_msix_arprot,
output wire m_axil_msix_arvalid,
input wire m_axil_msix_arready,
input wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_msix_rdata,
input wire [1:0] m_axil_msix_rresp,
input wire m_axil_msix_rvalid,
output wire m_axil_msix_rready,
/* /*
* Control register interface * Control register interface
*/ */
@ -320,9 +346,11 @@ module mqnic_core #
input wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready, input wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready,
/* /*
* MSI request outputs * Interrupt request output
*/ */
output wire [MSI_COUNT-1:0] msi_irq, output wire [IRQ_INDEX_WIDTH-1:0] irq_index,
output wire irq_valid,
input wire irq_ready,
/* /*
* PTP clock * PTP clock
@ -616,7 +644,7 @@ always @(posedge clk) begin
8'h80: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h0000C006 : 0; // Stats: Type 8'h80: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h0000C006 : 0; // Stats: Type
8'h84: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h00000100 : 0; // Stats: Version 8'h84: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h00000100 : 0; // Stats: Version
8'h88: ctrl_reg_rd_data_reg <= PHC_RB_BASE_ADDR; // Stats: Next header 8'h88: ctrl_reg_rd_data_reg <= PHC_RB_BASE_ADDR; // Stats: Next header
8'h8C: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 2**16 : 0; // Stats: Offset 8'h8C: ctrl_reg_rd_data_reg <= STAT_ENABLE ? (MSIX_ENABLE ? 2 : 1)*2**16 : 0; // Stats: Offset
8'h90: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 2**STAT_ID_WIDTH : 0; // Stats: Count 8'h90: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 2**STAT_ID_WIDTH : 0; // Stats: Count
8'h94: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 8 : 0; // Stats: Stride 8'h94: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 8 : 0; // Stats: Stride
8'h98: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h00000000 : 0; // Stats: Flags 8'h98: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h00000000 : 0; // Stats: Flags
@ -857,13 +885,17 @@ wire [IF_COUNT-1:0] axil_if_csr_rvalid;
wire [IF_COUNT-1:0] axil_if_csr_rready; wire [IF_COUNT-1:0] axil_if_csr_rready;
localparam CSR_XBAR_CSR_OFFSET = 0; localparam CSR_XBAR_CSR_OFFSET = 0;
localparam CSR_XBAR_STAT_OFFSET = CSR_XBAR_CSR_OFFSET + 1; localparam CSR_XBAR_MSIX_OFFSET = CSR_XBAR_CSR_OFFSET + 1;
localparam CSR_XBAR_STAT_OFFSET = CSR_XBAR_MSIX_OFFSET + (MSIX_ENABLE ? 1 : 0);
localparam CSR_XBAR_PASSTHROUGH_OFFSET = CSR_XBAR_STAT_OFFSET + (STAT_ENABLE ? 1 : 0); localparam CSR_XBAR_PASSTHROUGH_OFFSET = CSR_XBAR_STAT_OFFSET + (STAT_ENABLE ? 1 : 0);
localparam CSR_XBAR_M_COUNT = CSR_XBAR_PASSTHROUGH_OFFSET + (AXIL_CSR_PASSTHROUGH_ENABLE ? 1 : 0); localparam CSR_XBAR_M_COUNT = CSR_XBAR_PASSTHROUGH_OFFSET + (AXIL_CSR_PASSTHROUGH_ENABLE ? 1 : 0);
function [CSR_XBAR_M_COUNT*32-1:0] calcCsrXbarWidths(input [31:0] dummy); function [CSR_XBAR_M_COUNT*32-1:0] calcCsrXbarWidths(input [31:0] dummy);
begin begin
calcCsrXbarWidths[CSR_XBAR_CSR_OFFSET*32 +: 32] = 16; calcCsrXbarWidths[CSR_XBAR_CSR_OFFSET*32 +: 32] = 16;
if (MSIX_ENABLE) begin
calcCsrXbarWidths[CSR_XBAR_MSIX_OFFSET*32 +: 32] = 16;
end
if (STAT_ENABLE) begin if (STAT_ENABLE) begin
calcCsrXbarWidths[CSR_XBAR_STAT_OFFSET*32 +: 32] = 16; calcCsrXbarWidths[CSR_XBAR_STAT_OFFSET*32 +: 32] = 16;
end end
@ -915,6 +947,44 @@ assign axil_csr_xbar_rresp[CSR_XBAR_CSR_OFFSET*2 +: 2] = axil_csr_rresp;
assign axil_csr_xbar_rvalid[CSR_XBAR_CSR_OFFSET +: 1] = axil_csr_rvalid; assign axil_csr_xbar_rvalid[CSR_XBAR_CSR_OFFSET +: 1] = axil_csr_rvalid;
assign axil_csr_rready = axil_csr_xbar_rready[CSR_XBAR_CSR_OFFSET +: 1]; assign axil_csr_rready = axil_csr_xbar_rready[CSR_XBAR_CSR_OFFSET +: 1];
if (MSIX_ENABLE) begin
assign m_axil_msix_awaddr = axil_csr_xbar_awaddr[CSR_XBAR_MSIX_OFFSET*AXIL_CSR_ADDR_WIDTH +: AXIL_CSR_ADDR_WIDTH];
assign m_axil_msix_awprot = axil_csr_xbar_awprot[CSR_XBAR_MSIX_OFFSET*3 +: 3];
assign m_axil_msix_awvalid = axil_csr_xbar_awvalid[CSR_XBAR_MSIX_OFFSET +: 1];
assign axil_csr_xbar_awready[CSR_XBAR_MSIX_OFFSET +: 1] = m_axil_msix_awready;
assign m_axil_msix_wdata = axil_csr_xbar_wdata[CSR_XBAR_MSIX_OFFSET*AXIL_CTRL_DATA_WIDTH +: AXIL_CTRL_DATA_WIDTH];
assign m_axil_msix_wstrb = axil_csr_xbar_wstrb[CSR_XBAR_MSIX_OFFSET*AXIL_CTRL_STRB_WIDTH +: AXIL_CTRL_STRB_WIDTH];
assign m_axil_msix_wvalid = axil_csr_xbar_wvalid[CSR_XBAR_MSIX_OFFSET +: 1];
assign axil_csr_xbar_wready[CSR_XBAR_MSIX_OFFSET +: 1] = m_axil_msix_wready;
assign axil_csr_xbar_bresp[CSR_XBAR_MSIX_OFFSET*2 +: 2] = m_axil_msix_bresp;
assign axil_csr_xbar_bvalid[CSR_XBAR_MSIX_OFFSET +: 1] = m_axil_msix_bvalid;
assign m_axil_msix_bready = axil_csr_xbar_bready[CSR_XBAR_MSIX_OFFSET +: 1];
assign m_axil_msix_araddr = axil_csr_xbar_araddr[CSR_XBAR_MSIX_OFFSET*AXIL_CSR_ADDR_WIDTH +: AXIL_CSR_ADDR_WIDTH];
assign m_axil_msix_arprot = axil_csr_xbar_arprot[CSR_XBAR_MSIX_OFFSET*3 +: 3];
assign m_axil_msix_arvalid = axil_csr_xbar_arvalid[CSR_XBAR_MSIX_OFFSET +: 1];
assign axil_csr_xbar_arready[CSR_XBAR_MSIX_OFFSET +: 1] = m_axil_msix_arready;
assign axil_csr_xbar_rdata[CSR_XBAR_MSIX_OFFSET*AXIL_CTRL_DATA_WIDTH +: AXIL_CTRL_DATA_WIDTH] = m_axil_msix_rdata;
assign axil_csr_xbar_rresp[CSR_XBAR_MSIX_OFFSET*2 +: 2] = m_axil_msix_rresp;
assign axil_csr_xbar_rvalid[CSR_XBAR_MSIX_OFFSET +: 1] = m_axil_msix_rvalid;
assign m_axil_msix_rready = axil_csr_xbar_rready[CSR_XBAR_MSIX_OFFSET +: 1];
end else begin
assign m_axil_msix_awaddr = 0;
assign m_axil_msix_awprot = 0;
assign m_axil_msix_awvalid = 0;
assign m_axil_msix_wdata = 0;
assign m_axil_msix_wstrb = 0;
assign m_axil_msix_wvalid = 0;
assign m_axil_msix_bready = 0;
assign m_axil_msix_araddr = 0;
assign m_axil_msix_arprot = 0;
assign m_axil_msix_arvalid = 0;
assign m_axil_msix_rready = 0;
end
if (STAT_ENABLE) begin if (STAT_ENABLE) begin
assign axil_stats_awaddr = axil_csr_xbar_awaddr[CSR_XBAR_STAT_OFFSET*AXIL_CSR_ADDR_WIDTH +: AXIL_CSR_ADDR_WIDTH]; assign axil_stats_awaddr = axil_csr_xbar_awaddr[CSR_XBAR_STAT_OFFSET*AXIL_CSR_ADDR_WIDTH +: AXIL_CSR_ADDR_WIDTH];
@ -2048,20 +2118,64 @@ end
endgenerate endgenerate
wire [MSI_COUNT-1:0] if_msi_irq[IF_COUNT-1:0]; wire [IF_COUNT*IRQ_INDEX_WIDTH-1:0] if_irq_index;
reg [MSI_COUNT-1:0] msi_irq_cmb = 0; wire [IF_COUNT-1:0] if_irq_valid;
wire [IF_COUNT-1:0] if_irq_ready;
assign msi_irq = msi_irq_cmb; generate
integer k; if (IF_COUNT > 1) begin : irq_mux
axis_arb_mux #(
.S_COUNT(IF_COUNT),
.DATA_WIDTH(IRQ_INDEX_WIDTH),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LAST_ENABLE(0),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_LSB_HIGH_PRIORITY(1)
)
axis_irq_mux_inst (
.clk(clk),
.rst(rst),
/*
* AXI Stream inputs
*/
.s_axis_tdata(if_irq_index),
.s_axis_tkeep(0),
.s_axis_tvalid(if_irq_valid),
.s_axis_tready(if_irq_ready),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
/*
* AXI Stream output
*/
.m_axis_tdata(irq_index),
.m_axis_tkeep(),
.m_axis_tvalid(irq_valid),
.m_axis_tready(irq_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
end else begin
assign irq_index = if_irq_index;
assign irq_valid = if_irq_valid;
assign if_irq_ready = irq_ready;
always @* begin
msi_irq_cmb = 0;
for (k = 0; k < IF_COUNT; k = k + 1) begin
msi_irq_cmb = msi_irq_cmb | if_msi_irq[k];
end
end end
endgenerate
// streaming connections to application // streaming connections to application
wire [PORT_COUNT-1:0] app_direct_tx_clk; wire [PORT_COUNT-1:0] app_direct_tx_clk;
wire [PORT_COUNT-1:0] app_direct_tx_rst; wire [PORT_COUNT-1:0] app_direct_tx_rst;
@ -2280,7 +2394,8 @@ generate
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH), .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE), .RAM_PIPELINE(RAM_PIPELINE),
.MSI_COUNT(MSI_COUNT), // Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration // AXI lite interface configuration
.AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -2650,9 +2765,11 @@ generate
.ptp_ts_step(ptp_sync_ts_step), .ptp_ts_step(ptp_sync_ts_step),
/* /*
* MSI interrupts * Interrupt request output
*/ */
.msi_irq(if_msi_irq[n]) .irq_index(if_irq_index[n*IRQ_INDEX_WIDTH +: IRQ_INDEX_WIDTH]),
.irq_valid(if_irq_valid[n +: 1]),
.irq_ready(if_irq_ready[n +: 1])
); );
for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : port for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : port

32
fpga/common/rtl/mqnic_core_axi.v
View File

@ -144,7 +144,7 @@ module mqnic_core_axi #
parameter AXI_DMA_READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH), parameter AXI_DMA_READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
parameter AXI_DMA_WRITE_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH), parameter AXI_DMA_WRITE_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Interrupts // Interrupt configuration
parameter IRQ_COUNT = 32, parameter IRQ_COUNT = 32,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
@ -402,6 +402,8 @@ parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8; parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH); parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH);
parameter IRQ_INDEX_WIDTH = $clog2(IRQ_COUNT);
// DMA connections // DMA connections
wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel; wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be; wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
@ -418,6 +420,24 @@ wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid; wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready; wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Interrupts
wire [IRQ_INDEX_WIDTH-1:0] irq_index;
wire irq_valid;
wire irq_ready;
reg [IRQ_COUNT-1:0] irq_reg;
always @(posedge clk) begin
irq_reg <= 0;
if (irq_valid) begin
irq_reg <= 1 << irq_index;
end
end
assign irq = irq_reg;
assign irq_ready = 1'b1;
// DMA control // DMA control
wire [DMA_ADDR_WIDTH-1:0] dma_read_desc_dma_addr; wire [DMA_ADDR_WIDTH-1:0] dma_read_desc_dma_addr;
wire [RAM_SEL_WIDTH-1:0] dma_read_desc_ram_sel; wire [RAM_SEL_WIDTH-1:0] dma_read_desc_ram_sel;
@ -874,7 +894,9 @@ mqnic_core #(
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE), .RAM_PIPELINE(RAM_PIPELINE),
.MSI_COUNT(IRQ_COUNT), // Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
.MSIX_ENABLE(0),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1054,9 +1076,11 @@ core_inst (
.dma_ram_rd_resp_ready(dma_ram_rd_resp_ready), .dma_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/* /*
* MSI request outputs * Interrupt request output
*/ */
.msi_irq(irq), .irq_index(irq_index),
.irq_valid(irq_valid),
.irq_ready(irq_ready),
/* /*
* PTP clock * PTP clock

146
fpga/common/rtl/mqnic_core_pcie.v
View File

@ -153,7 +153,9 @@ module mqnic_core_pcie #
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 0, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 0,
parameter TLP_FORCE_64_BIT_ADDR = 0, parameter TLP_FORCE_64_BIT_ADDR = 0,
parameter CHECK_BUS_NUMBER = 1, parameter CHECK_BUS_NUMBER = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -261,6 +263,17 @@ module mqnic_core_pcie #
output wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop, output wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop,
input wire pcie_tx_cpl_tlp_ready, input wire pcie_tx_cpl_tlp_ready,
/*
* TLP output (MSI-X write request)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_eop,
input wire pcie_tx_msix_wr_req_tlp_ready,
/* /*
* Flow control credits * Flow control credits
*/ */
@ -275,6 +288,8 @@ module mqnic_core_pcie #
input wire [F_COUNT-1:0] ext_tag_enable, input wire [F_COUNT-1:0] ext_tag_enable,
input wire [F_COUNT*3-1:0] max_read_request_size, input wire [F_COUNT*3-1:0] max_read_request_size,
input wire [F_COUNT*3-1:0] max_payload_size, input wire [F_COUNT*3-1:0] max_payload_size,
input wire [F_COUNT-1:0] msix_enable,
input wire [F_COUNT-1:0] msix_mask,
/* /*
* PCIe error outputs * PCIe error outputs
@ -320,11 +335,6 @@ module mqnic_core_pcie #
input wire ctrl_reg_rd_wait, input wire ctrl_reg_rd_wait,
input wire ctrl_reg_rd_ack, input wire ctrl_reg_rd_ack,
/*
* MSI request outputs
*/
output wire [MSI_COUNT-1:0] msi_irq,
/* /*
* PTP clock * PTP clock
*/ */
@ -413,6 +423,7 @@ parameter RAM_SEG_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8; parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH); parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH);
parameter AXIL_MSIX_ADDR_WIDTH = 16;
parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8); parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8);
// PCIe connections // PCIe connections
@ -471,6 +482,26 @@ wire [1:0] axil_ctrl_rresp;
wire axil_ctrl_rvalid; wire axil_ctrl_rvalid;
wire axil_ctrl_rready; wire axil_ctrl_rready;
wire [AXIL_MSIX_ADDR_WIDTH-1:0] axil_msix_awaddr;
wire [2:0] axil_msix_awprot;
wire axil_msix_awvalid;
wire axil_msix_awready;
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_msix_wdata;
wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_msix_wstrb;
wire axil_msix_wvalid;
wire axil_msix_wready;
wire [1:0] axil_msix_bresp;
wire axil_msix_bvalid;
wire axil_msix_bready;
wire [AXIL_MSIX_ADDR_WIDTH-1:0] axil_msix_araddr;
wire [2:0] axil_msix_arprot;
wire axil_msix_arvalid;
wire axil_msix_arready;
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_msix_rdata;
wire [1:0] axil_msix_rresp;
wire axil_msix_rvalid;
wire axil_msix_rready;
wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] axil_app_ctrl_awaddr; wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] axil_app_ctrl_awaddr;
wire [2:0] axil_app_ctrl_awprot; wire [2:0] axil_app_ctrl_awprot;
wire axil_app_ctrl_awvalid; wire axil_app_ctrl_awvalid;
@ -507,6 +538,11 @@ wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid; wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready; wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// Interrupts
wire [IRQ_INDEX_WIDTH-1:0] irq_index;
wire irq_valid;
wire irq_ready;
// Error handling // Error handling
wire [2:0] pcie_error_uncor_int; wire [2:0] pcie_error_uncor_int;
wire [2:0] pcie_error_cor_int; wire [2:0] pcie_error_cor_int;
@ -1076,6 +1112,70 @@ dma_if_pcie_inst (
.stat_wr_tx_stall(stat_wr_tx_stall) .stat_wr_tx_stall(stat_wr_tx_stall)
); );
pcie_msix #(
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
.AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
)
pcie_msix_inst (
.clk(clk),
.rst(rst),
/*
* AXI lite interface for MSI-X tables
*/
.s_axil_awaddr(axil_msix_awaddr),
.s_axil_awprot(axil_msix_awprot),
.s_axil_awvalid(axil_msix_awvalid),
.s_axil_awready(axil_msix_awready),
.s_axil_wdata(axil_msix_wdata),
.s_axil_wstrb(axil_msix_wstrb),
.s_axil_wvalid(axil_msix_wvalid),
.s_axil_wready(axil_msix_wready),
.s_axil_bresp(axil_msix_bresp),
.s_axil_bvalid(axil_msix_bvalid),
.s_axil_bready(axil_msix_bready),
.s_axil_araddr(axil_msix_araddr),
.s_axil_arprot(axil_msix_arprot),
.s_axil_arvalid(axil_msix_arvalid),
.s_axil_arready(axil_msix_arready),
.s_axil_rdata(axil_msix_rdata),
.s_axil_rresp(axil_msix_rresp),
.s_axil_rvalid(axil_msix_rvalid),
.s_axil_rready(axil_msix_rready),
/*
* Interrupt request input
*/
.irq_index(irq_index),
.irq_valid(irq_valid),
.irq_ready(irq_ready),
/*
* Memory write TLP output
*/
.tx_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
.tx_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
/*
* Configuration
*/
.requester_id({bus_num, 5'd0, 3'd0}),
.msix_enable(msix_enable),
.msix_mask(msix_mask)
);
pulse_merge #( pulse_merge #(
.INPUT_WIDTH(3), .INPUT_WIDTH(3),
.COUNT_WIDTH(4) .COUNT_WIDTH(4)
@ -1425,7 +1525,10 @@ mqnic_core #(
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE), .RAM_PIPELINE(RAM_PIPELINE),
.MSI_COUNT(MSI_COUNT), // Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
.MSIX_ENABLE(1),
.AXIL_MSIX_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1571,6 +1674,29 @@ core_inst (
.m_axil_csr_rvalid(m_axil_csr_rvalid), .m_axil_csr_rvalid(m_axil_csr_rvalid),
.m_axil_csr_rready(m_axil_csr_rready), .m_axil_csr_rready(m_axil_csr_rready),
/*
* AXI-Lite master interface (MSI-X)
*/
.m_axil_msix_awaddr(axil_msix_awaddr),
.m_axil_msix_awprot(axil_msix_awprot),
.m_axil_msix_awvalid(axil_msix_awvalid),
.m_axil_msix_awready(axil_msix_awready),
.m_axil_msix_wdata(axil_msix_wdata),
.m_axil_msix_wstrb(axil_msix_wstrb),
.m_axil_msix_wvalid(axil_msix_wvalid),
.m_axil_msix_wready(axil_msix_wready),
.m_axil_msix_bresp(axil_msix_bresp),
.m_axil_msix_bvalid(axil_msix_bvalid),
.m_axil_msix_bready(axil_msix_bready),
.m_axil_msix_araddr(axil_msix_araddr),
.m_axil_msix_arprot(axil_msix_arprot),
.m_axil_msix_arvalid(axil_msix_arvalid),
.m_axil_msix_arready(axil_msix_arready),
.m_axil_msix_rdata(axil_msix_rdata),
.m_axil_msix_rresp(axil_msix_rresp),
.m_axil_msix_rvalid(axil_msix_rvalid),
.m_axil_msix_rready(axil_msix_rready),
/* /*
* Control register interface * Control register interface
*/ */
@ -1605,9 +1731,11 @@ core_inst (
.dma_ram_rd_resp_ready(dma_ram_rd_resp_ready), .dma_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/* /*
* MSI request outputs * Interrupt request output
*/ */
.msi_irq(msi_irq), .irq_index(irq_index),
.irq_valid(irq_valid),
.irq_ready(irq_ready),
/* /*
* PTP clock * PTP clock

75
fpga/common/rtl/mqnic_core_pcie_s10.v
View File

@ -150,7 +150,9 @@ module mqnic_core_pcie_s10 #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH, parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -228,15 +230,6 @@ module mqnic_core_pcie_s10 #
input wire [SEG_COUNT*2-1:0] tx_cdts_type, input wire [SEG_COUNT*2-1:0] tx_cdts_type,
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value, input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
/*
* H-Tile/L-Tile MSI interrupt interface
*/
output wire app_msi_req,
input wire app_msi_ack,
output wire [2:0] app_msi_tc,
output wire [4:0] app_msi_num,
output wire [1:0] app_msi_func_num,
/* /*
* H-Tile/L-Tile configuration interface * H-Tile/L-Tile configuration interface
*/ */
@ -414,6 +407,14 @@ wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready; wire pcie_tx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av; wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av; wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av; wire [7:0] pcie_tx_fc_nph_av;
@ -422,8 +423,8 @@ wire [F_COUNT-1:0] ext_tag_enable;
wire [7:0] bus_num; wire [7:0] bus_num;
wire [F_COUNT*3-1:0] max_read_request_size; wire [F_COUNT*3-1:0] max_read_request_size;
wire [F_COUNT*3-1:0] max_payload_size; wire [F_COUNT*3-1:0] max_payload_size;
wire [F_COUNT-1:0] msix_enable;
wire [MSI_COUNT-1:0] msi_irq; wire [F_COUNT-1:0] msix_mask;
pcie_s10_if #( pcie_s10_if #(
.SEG_COUNT(SEG_COUNT), .SEG_COUNT(SEG_COUNT),
@ -439,8 +440,7 @@ pcie_s10_if #(
.VF_COUNT(0), .VF_COUNT(0),
.F_COUNT(PF_COUNT+VF_COUNT), .F_COUNT(PF_COUNT+VF_COUNT),
.IO_BAR_INDEX(5), .IO_BAR_INDEX(5),
.MSI_ENABLE(1), .MSI_ENABLE(0)
.MSI_COUNT(MSI_COUNT)
) )
pcie_s10_if_inst ( pcie_s10_if_inst (
.clk(clk), .clk(clk),
@ -487,11 +487,11 @@ pcie_s10_if_inst (
/* /*
* H-Tile/L-Tile MSI interrupt interface * H-Tile/L-Tile MSI interrupt interface
*/ */
.app_msi_req(app_msi_req), .app_msi_req(),
.app_msi_ack(app_msi_ack), .app_msi_ack(1'b0),
.app_msi_tc(app_msi_tc), .app_msi_tc(),
.app_msi_num(app_msi_num), .app_msi_num(),
.app_msi_func_num(app_msi_func_num), .app_msi_func_num(),
/* /*
* H-Tile/L-Tile configuration interface * H-Tile/L-Tile configuration interface
@ -568,6 +568,17 @@ pcie_s10_if_inst (
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP input (write request from MSI)
*/
.tx_msi_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
.tx_msi_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
.tx_msi_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
.tx_msi_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
.tx_msi_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
.tx_msi_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
.tx_msi_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
/* /*
* Flow control * Flow control
*/ */
@ -585,11 +596,13 @@ pcie_s10_if_inst (
.bus_num(bus_num), .bus_num(bus_num),
.max_read_request_size(max_read_request_size), .max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size), .max_payload_size(max_payload_size),
.msix_enable(msix_enable),
.msix_mask(msix_mask),
/* /*
* MSI request inputs * MSI request inputs
*/ */
.msi_irq(msi_irq) .msi_irq(32'd0)
); );
mqnic_core_pcie #( mqnic_core_pcie #(
@ -702,7 +715,9 @@ mqnic_core_pcie #(
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(0), .TLP_FORCE_64_BIT_ADDR(0),
.CHECK_BUS_NUMBER(1), .CHECK_BUS_NUMBER(1),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -810,6 +825,17 @@ core_pcie_inst (
.pcie_tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .pcie_tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.pcie_tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), .pcie_tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP output (MSI-X write request)
*/
.pcie_tx_msix_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
.pcie_tx_msix_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
.pcie_tx_msix_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
.pcie_tx_msix_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
.pcie_tx_msix_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
.pcie_tx_msix_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
.pcie_tx_msix_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
/* /*
* Flow control credits * Flow control credits
*/ */
@ -824,6 +850,8 @@ core_pcie_inst (
.ext_tag_enable(ext_tag_enable), .ext_tag_enable(ext_tag_enable),
.max_read_request_size(max_read_request_size), .max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size), .max_payload_size(max_payload_size),
.msix_enable(msix_enable),
.msix_mask(msix_mask),
/* /*
* PCIe error outputs * PCIe error outputs
@ -869,11 +897,6 @@ core_pcie_inst (
.ctrl_reg_rd_wait(ctrl_reg_rd_wait), .ctrl_reg_rd_wait(ctrl_reg_rd_wait),
.ctrl_reg_rd_ack(ctrl_reg_rd_ack), .ctrl_reg_rd_ack(ctrl_reg_rd_ack),
/*
* MSI request outputs
*/
.msi_irq(msi_irq),
/* /*
* PTP clock * PTP clock
*/ */

128
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -151,7 +151,9 @@ module mqnic_core_pcie_us #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1), parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1),
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), parameter PCIE_DMA_WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 0, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 0,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -271,23 +273,18 @@ module mqnic_core_pcie_us #
/* /*
* Interrupt interface * Interrupt interface
*/ */
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [7:0] cfg_interrupt_msi_vf_enable, input wire [3:0] cfg_interrupt_msix_mask,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_mask,
input wire [31:0] cfg_interrupt_msi_data, output wire [63:0] cfg_interrupt_msix_address,
output wire [3:0] cfg_interrupt_msi_select, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_int, output wire cfg_interrupt_msix_int,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire cfg_interrupt_msi_pending_status_data_enable, input wire cfg_interrupt_msix_vec_pending_status,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_fail,
input wire cfg_interrupt_msi_fail, output wire [7:0] cfg_interrupt_msi_function_number,
output wire [2:0] cfg_interrupt_msi_attr,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
/* /*
* PCIe error outputs * PCIe error outputs
@ -466,12 +463,21 @@ wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready; wire pcie_tx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av; wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av; wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av; wire [7:0] pcie_tx_fc_nph_av;
wire [F_COUNT-1:0] ext_tag_enable; wire [F_COUNT-1:0] ext_tag_enable;
wire [MSI_COUNT-1:0] msi_irq; wire [F_COUNT-1:0] msix_enable;
wire [F_COUNT-1:0] msix_mask;
pcie_us_if #( pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
@ -492,8 +498,8 @@ pcie_us_if #(
.READ_EXT_TAG_ENABLE(1), .READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1), .READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1), .READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1), .MSIX_ENABLE(1),
.MSI_COUNT(MSI_COUNT) .MSI_ENABLE(0)
) )
pcie_if_inst ( pcie_if_inst (
.clk(clk), .clk(clk),
@ -573,22 +579,33 @@ pcie_if_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msi_enable(),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable), .cfg_interrupt_msi_vf_enable(),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msi_mmenable(),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msi_mask_update(),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msi_data(),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msi_select(),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msi_int(),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msi_pending_status(),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msi_pending_status_data_enable(),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msi_pending_status_function_num(),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(),
.cfg_interrupt_msi_tph_present(),
.cfg_interrupt_msi_tph_type(),
.cfg_interrupt_msi_tph_st_tag(),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*
@ -659,6 +676,17 @@ pcie_if_inst (
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP input (write request from MSI)
*/
.tx_msix_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
.tx_msix_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
.tx_msix_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
.tx_msix_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
.tx_msix_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
.tx_msix_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
.tx_msix_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
/* /*
* Flow control * Flow control
*/ */
@ -675,11 +703,13 @@ pcie_if_inst (
.ext_tag_enable(ext_tag_enable), .ext_tag_enable(ext_tag_enable),
.max_read_request_size(), .max_read_request_size(),
.max_payload_size(), .max_payload_size(),
.msix_enable(msix_enable),
.msix_mask(msix_mask),
/* /*
* MSI request inputs * MSI request inputs
*/ */
.msi_irq(msi_irq) .msi_irq(32'd0)
); );
mqnic_core_pcie #( mqnic_core_pcie #(
@ -792,7 +822,9 @@ mqnic_core_pcie #(
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(1), .TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0), .CHECK_BUS_NUMBER(0),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -900,6 +932,17 @@ core_pcie_inst (
.pcie_tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .pcie_tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.pcie_tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), .pcie_tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP output (MSI-X write request)
*/
.pcie_tx_msix_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
.pcie_tx_msix_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
.pcie_tx_msix_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
.pcie_tx_msix_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
.pcie_tx_msix_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
.pcie_tx_msix_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
.pcie_tx_msix_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
/* /*
* Flow control credits * Flow control credits
*/ */
@ -914,6 +957,8 @@ core_pcie_inst (
.ext_tag_enable(ext_tag_enable), .ext_tag_enable(ext_tag_enable),
.max_read_request_size(cfg_max_read_req), .max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload), .max_payload_size(cfg_max_payload),
.msix_enable(msix_enable),
.msix_mask(msix_mask),
/* /*
* PCIe error outputs * PCIe error outputs
@ -959,11 +1004,6 @@ core_pcie_inst (
.ctrl_reg_rd_wait(ctrl_reg_rd_wait), .ctrl_reg_rd_wait(ctrl_reg_rd_wait),
.ctrl_reg_rd_ack(ctrl_reg_rd_ack), .ctrl_reg_rd_ack(ctrl_reg_rd_ack),
/*
* MSI request outputs
*/
.msi_irq(msi_irq),
/* /*
* PTP clock * PTP clock
*/ */

65
fpga/common/rtl/mqnic_interface.v
View File

@ -119,7 +119,8 @@ module mqnic_interface #
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH), parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
parameter RAM_PIPELINE = 2, parameter RAM_PIPELINE = 2,
parameter MSI_COUNT = 32, // Interrupt configuration
parameter IRQ_INDEX_WIDTH = 8,
// AXI lite interface configuration // AXI lite interface configuration
parameter AXIL_DATA_WIDTH = 32, parameter AXIL_DATA_WIDTH = 32,
@ -489,9 +490,11 @@ module mqnic_interface #
input wire ptp_ts_step, input wire ptp_ts_step,
/* /*
* MSI interrupts * Interrupt request output
*/ */
output wire [MSI_COUNT-1:0] msi_irq output wire [IRQ_INDEX_WIDTH-1:0] irq_index,
output wire irq_valid,
input wire irq_ready
); );
parameter DESC_SIZE = 16; parameter DESC_SIZE = 16;
@ -504,8 +507,6 @@ parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8;
parameter EVENT_SOURCE_WIDTH = 16; parameter EVENT_SOURCE_WIDTH = 16;
parameter EVENT_TYPE_WIDTH = 16; parameter EVENT_TYPE_WIDTH = 16;
parameter INT_WIDTH = $clog2(MSI_COUNT);
parameter MAX_DESC_TABLE_SIZE = TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE; parameter MAX_DESC_TABLE_SIZE = TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE;
parameter REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + $clog2(SCHEDULERS); parameter REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + $clog2(SCHEDULERS);
@ -946,20 +947,48 @@ wire [EVENT_SOURCE_WIDTH-1:0] rx_event_source;
wire rx_event_valid; wire rx_event_valid;
// interrupts // interrupts
wire [INT_WIDTH-1:0] event_int; wire [IRQ_INDEX_WIDTH-1:0] event_irq_index;
wire event_int_valid; wire event_irq_valid;
reg [31:0] msi_irq_reg = 0; axis_fifo #(
.DEPTH(128),
.DATA_WIDTH(IRQ_INDEX_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
irq_fifo (
.clk(clk),
.rst(rst),
assign msi_irq = msi_irq_reg; // AXI input
.s_axis_tdata(event_irq_index),
.s_axis_tkeep(0),
.s_axis_tvalid(event_irq_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
always @(posedge clk) begin // AXI output
msi_irq_reg <= 0; .m_axis_tdata(irq_index),
.m_axis_tkeep(),
.m_axis_tvalid(irq_valid),
.m_axis_tready(irq_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
if (event_int_valid) begin // Status
msi_irq_reg <= 1'b1 << event_int; .status_overflow(),
end .status_bad_frame(),
end .status_good_frame()
);
// control registers // control registers
wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr;
@ -1237,7 +1266,7 @@ cpl_queue_manager #(
.OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), .QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.EVENT_WIDTH(INT_WIDTH), .EVENT_WIDTH(IRQ_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
.CPL_SIZE(EVENT_SIZE), .CPL_SIZE(EVENT_SIZE),
@ -1282,9 +1311,9 @@ event_queue_manager_inst (
/* /*
* Event output * Event output
*/ */
.m_axis_event(event_int), .m_axis_event(event_irq_index),
.m_axis_event_source(), .m_axis_event_source(),
.m_axis_event_valid(event_int_valid), .m_axis_event_valid(event_irq_valid),
/* /*
* AXI-Lite slave interface * AXI-Lite slave interface

2
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -202,7 +202,7 @@ export PARAM_AXI_DMA_USE_ID ?= 1
export PARAM_AXI_DMA_READ_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" ) export PARAM_AXI_DMA_READ_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" )
export PARAM_AXI_DMA_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" ) export PARAM_AXI_DMA_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" )
# Interrupts # Interrupt configuration
export PARAM_IRQ_COUNT ?= 32 export PARAM_IRQ_COUNT ?= 32
# AXI lite interface configuration (control) # AXI lite interface configuration (control)

12
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -105,6 +105,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -121,7 +122,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_rx.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_rx.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_tx.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_tx.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -148,7 +148,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -218,7 +218,9 @@ export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
export PARAM_MSI_COUNT ?= 32
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
@ -324,7 +326,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).MSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
@ -426,7 +428,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GMSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)

34
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -64,7 +64,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -86,7 +86,7 @@ class TB(object):
max_payload_size=1024, max_payload_size=1024,
enable_extended_tag=True, enable_extended_tag=True,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -94,12 +94,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -175,11 +175,11 @@ class TB(object):
# app_xfer_pending=dut.app_xfer_pending, # app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface # Interrupt interface
app_msi_req=dut.app_msi_req, # app_msi_req=dut.app_msi_req,
app_msi_ack=dut.app_msi_ack, # app_msi_ack=dut.app_msi_ack,
app_msi_tc=dut.app_msi_tc, # app_msi_tc=dut.app_msi_tc,
app_msi_num=dut.app_msi_num, # app_msi_num=dut.app_msi_num,
app_msi_func_num=dut.app_msi_func_num, # app_msi_func_num=dut.app_msi_func_num,
# app_int_sts=dut.app_int_sts, # app_int_sts=dut.app_int_sts,
# Error interface # Error interface
@ -337,7 +337,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -581,7 +581,7 @@ async def run_test_nic(dut):
lst = [] lst = []
for k in range(64): for k in range(64):
lst.append(await tb.driver.hw_regs.read_dword(0x010000+k*8)) lst.append(await tb.driver.hw_regs.read_dword(0x020000+k*8))
print(lst) print(lst)
@ -685,6 +685,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -701,7 +702,6 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"), os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"),
os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"), os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"),
os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_s10_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -729,7 +729,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -799,7 +799,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH'] parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH'] parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
parameters['MSI_COUNT'] = 32
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32

12
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -105,6 +105,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -123,7 +124,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -150,7 +150,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -215,7 +215,9 @@ export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16 export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
export PARAM_MSI_COUNT ?= 32
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
@ -316,7 +318,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).MSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
@ -413,7 +415,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GMSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)

78
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -64,7 +64,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -94,7 +94,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -102,12 +102,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -251,33 +251,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -409,7 +409,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -653,7 +653,7 @@ async def run_test_nic(dut):
lst = [] lst = []
for k in range(64): for k in range(64):
lst.append(await tb.driver.hw_regs.read_dword(0x010000+k*8)) lst.append(await tb.driver.hw_regs.read_dword(0x020000+k*8))
print(lst) print(lst)
@ -757,6 +757,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -775,7 +776,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -803,7 +803,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -868,7 +868,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16 parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
parameters['MSI_COUNT'] = 32
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32

12
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -107,6 +107,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -125,7 +126,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -152,7 +152,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -217,7 +217,9 @@ export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16 export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
export PARAM_MSI_COUNT ?= 32
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
@ -318,7 +320,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).MSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
@ -415,7 +417,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GMSI_COUNT=$(PARAM_MSI_COUNT) COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE) COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)

78
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -64,7 +64,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -94,7 +94,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -102,12 +102,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -251,33 +251,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -409,7 +409,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -706,7 +706,7 @@ async def run_test_nic(dut):
lst = [] lst = []
for k in range(64): for k in range(64):
lst.append(await tb.driver.hw_regs.read_dword(0x010000+k*8)) lst.append(await tb.driver.hw_regs.read_dword(0x020000+k*8))
print(lst) print(lst)
@ -812,6 +812,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -830,7 +831,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -858,7 +858,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 8 parameters['TX_QUEUE_INDEX_WIDTH'] = 8
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -923,7 +923,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16 parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
parameters['MSI_COUNT'] = 32
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -81,6 +81,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -99,7 +100,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -99,7 +99,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -160,6 +160,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -193,6 +196,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -83,6 +83,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -101,7 +102,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -99,7 +99,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -160,6 +160,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -193,6 +196,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/pcie4_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {9003} \ CONFIG.PF0_SUBSYSTEM_ID {9003} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {4144} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {4144} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/placement.xdc
View File

@ -4,6 +4,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_pl
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}
create_pblock pblock_eth create_pblock pblock_eth

87
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -141,6 +141,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -688,22 +691,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -880,21 +879,17 @@ pcie4_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1860,7 +1855,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1971,21 +1968,17 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),

63
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -146,7 +146,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -257,22 +259,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -930,7 +928,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1049,22 +1049,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -108,6 +108,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -126,7 +127,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -154,7 +154,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -218,6 +218,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -312,6 +315,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -403,6 +407,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -406,7 +406,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -684,6 +684,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -702,7 +703,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -731,7 +731,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -795,6 +795,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -99,6 +99,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -117,7 +118,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -99,6 +99,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -117,7 +118,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -100,6 +100,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -118,7 +119,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/pcie4_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {9003} \ CONFIG.PF0_SUBSYSTEM_ID {9003} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {4144} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {4144} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc
View File

@ -4,6 +4,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_pl
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}
create_pblock pblock_eth create_pblock pblock_eth

90
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -144,6 +144,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -263,9 +266,6 @@ parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter XGMII_DATA_WIDTH = 64; parameter XGMII_DATA_WIDTH = 64;
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
@ -695,22 +695,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -887,21 +883,17 @@ pcie4_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1463,7 +1455,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1574,21 +1568,17 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),

63
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -153,7 +153,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -266,22 +268,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -1202,7 +1200,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1321,22 +1321,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -116,6 +116,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -134,7 +135,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -161,7 +161,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -225,6 +225,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -318,6 +321,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -408,6 +412,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -485,7 +485,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -751,6 +751,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -769,7 +770,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -797,7 +797,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -861,6 +861,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -84,6 +84,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -102,7 +103,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
View File

@ -99,7 +99,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -160,6 +160,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -193,6 +196,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/AU200/fpga_100g/ip/pcie4_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {90c8} \ CONFIG.PF0_SUBSYSTEM_ID {90c8} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

1
fpga/mqnic/AU200/fpga_100g/placement.xdc
View File

@ -22,6 +22,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_pl
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth create_pblock pblock_eth

90
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -141,6 +141,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -260,9 +263,6 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
@ -838,22 +838,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -1002,21 +998,17 @@ pcie4_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1996,7 +1988,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -2115,21 +2109,17 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),

63
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -146,7 +146,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -265,22 +267,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -938,7 +936,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1057,22 +1057,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -108,6 +108,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -126,7 +127,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -154,7 +154,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -218,6 +218,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -312,6 +315,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -403,6 +407,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -406,7 +406,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -684,6 +684,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -702,7 +703,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -731,7 +731,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -795,6 +795,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -120,7 +121,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

2
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -120,7 +121,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {90c8} \ CONFIG.PF0_SUBSYSTEM_ID {90c8} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

1
fpga/mqnic/AU200/fpga_25g/placement.xdc
View File

@ -22,6 +22,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_pl
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth create_pblock pblock_eth

90
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -144,6 +144,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -265,9 +268,6 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter XGMII_DATA_WIDTH = 64; parameter XGMII_DATA_WIDTH = 64;
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
@ -845,22 +845,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -1009,21 +1005,17 @@ pcie4_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1596,7 +1588,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1715,21 +1709,17 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),

63
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -153,7 +153,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -274,22 +276,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -1211,7 +1209,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1330,22 +1330,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -116,6 +116,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -134,7 +135,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -161,7 +161,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -225,6 +225,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -318,6 +321,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -408,6 +412,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -485,7 +485,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -751,6 +751,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -769,7 +770,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -797,7 +797,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -861,6 +861,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -84,6 +84,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -102,7 +103,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
View File

@ -99,7 +99,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -160,6 +160,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -193,6 +196,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {90fa} \ CONFIG.PF0_SUBSYSTEM_ID {90fa} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

1
fpga/mqnic/AU250/fpga_100g/placement.xdc
View File

@ -26,6 +26,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_pl
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}
create_pblock pblock_eth create_pblock pblock_eth

90
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -141,6 +141,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -260,9 +263,6 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
@ -838,22 +838,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -1002,21 +998,17 @@ pcie4_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1996,7 +1988,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -2115,21 +2109,17 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),

63
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -146,7 +146,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -265,22 +267,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -938,7 +936,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1057,22 +1057,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -108,6 +108,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -126,7 +127,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -154,7 +154,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -218,6 +218,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -312,6 +315,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -403,6 +407,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -406,7 +406,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -684,6 +684,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -702,7 +703,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -731,7 +731,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -795,6 +795,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/AU250/fpga_25g/fpga/Makefile
View File

@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -120,7 +121,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

2
fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
View File

@ -102,6 +102,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -120,7 +121,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {90fa} \ CONFIG.PF0_SUBSYSTEM_ID {90fa} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4_uscale_plus_0] ] [get_ips pcie4_uscale_plus_0]

1
fpga/mqnic/AU250/fpga_25g/placement.xdc
View File

@ -26,6 +26,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_pl
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}
create_pblock pblock_eth create_pblock pblock_eth

90
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -144,6 +144,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -265,9 +268,6 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter XGMII_DATA_WIDTH = 64; parameter XGMII_DATA_WIDTH = 64;
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
@ -845,22 +845,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -1009,21 +1005,17 @@ pcie4_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1596,7 +1588,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1715,21 +1709,17 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),

63
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -153,7 +153,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -274,22 +276,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -1211,7 +1209,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1330,22 +1330,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -116,6 +116,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -134,7 +135,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -161,7 +161,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -225,6 +225,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -318,6 +321,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -408,6 +412,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -485,7 +485,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -751,6 +751,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -769,7 +770,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -797,7 +797,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -861,6 +861,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -83,6 +83,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -101,7 +102,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
View File

@ -99,7 +99,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -160,6 +160,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -193,6 +196,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {9118} \ CONFIG.PF0_SUBSYSTEM_ID {9118} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4c_uscale_plus_0] ] [get_ips pcie4c_uscale_plus_0]

1
fpga/mqnic/AU280/fpga_100g/placement.xdc
View File

@ -22,6 +22,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4c_uscale_p
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth create_pblock pblock_eth

90
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -141,6 +141,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -243,9 +246,6 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
@ -727,22 +727,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -891,21 +887,17 @@ pcie4c_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1893,7 +1885,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1996,21 +1990,17 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),

63
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -146,7 +146,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -249,22 +251,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -814,7 +812,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -933,22 +933,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -108,6 +108,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -126,7 +127,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -154,7 +154,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -218,6 +218,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -312,6 +315,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -403,6 +407,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -395,7 +395,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -673,6 +673,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -691,7 +692,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -720,7 +720,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -784,6 +784,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/AU280/fpga_25g/fpga/Makefile
View File

@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -119,7 +120,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

2
fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
View File

@ -101,6 +101,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -119,7 +120,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
View File

@ -111,7 +111,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -172,6 +172,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -206,6 +209,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/AU280/fpga_25g/ip/pcie4c_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {9118} \ CONFIG.PF0_SUBSYSTEM_ID {9118} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4c_uscale_plus_0] ] [get_ips pcie4c_uscale_plus_0]

1
fpga/mqnic/AU280/fpga_25g/placement.xdc
View File

@ -22,6 +22,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4c_uscale_p
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth create_pblock pblock_eth

91
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -144,6 +144,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -248,9 +251,6 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter XGMII_DATA_WIDTH = 64; parameter XGMII_DATA_WIDTH = 64;
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
@ -734,22 +734,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -898,21 +894,17 @@ pcie4c_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1501,7 +1493,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1606,23 +1600,20 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor), .status_error_uncor(status_error_uncor),

63
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -153,7 +153,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -258,22 +260,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -1087,7 +1085,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1206,22 +1206,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -116,6 +116,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -134,7 +135,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -161,7 +161,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -225,6 +225,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -318,6 +321,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -408,6 +412,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

75
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -63,7 +63,7 @@ except ImportError:
class TB(object): class TB(object):
def __init__(self, dut): def __init__(self, dut, msix_count=32):
self.dut = dut self.dut = dut
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
@ -93,7 +93,7 @@ class TB(object):
enable_sriov=False, enable_sriov=False,
enable_extended_configuration=False, enable_extended_configuration=False,
pf0_msi_enable=True, pf0_msi_enable=False,
pf0_msi_count=32, pf0_msi_count=32,
pf1_msi_enable=False, pf1_msi_enable=False,
pf1_msi_count=1, pf1_msi_count=1,
@ -101,12 +101,12 @@ class TB(object):
pf2_msi_count=1, pf2_msi_count=1,
pf3_msi_enable=False, pf3_msi_enable=False,
pf3_msi_count=1, pf3_msi_count=1,
pf0_msix_enable=False, pf0_msix_enable=True,
pf0_msix_table_size=0, pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0, pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000, pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0, pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000, pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False, pf1_msix_enable=False,
pf1_msix_table_size=0, pf1_msix_table_size=0,
pf1_msix_table_bir=0, pf1_msix_table_bir=0,
@ -250,33 +250,33 @@ class TB(object):
# cfg_interrupt_int # cfg_interrupt_int
# cfg_interrupt_sent # cfg_interrupt_sent
# cfg_interrupt_pending # cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, # cfg_interrupt_msi_enable
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, # cfg_interrupt_msi_mmenable
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, # cfg_interrupt_msi_mask_update
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_data
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, # cfg_interrupt_msi_select
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, # cfg_interrupt_msi_int
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, # cfg_interrupt_msi_pending_status
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_data_enable
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, # cfg_interrupt_msi_pending_status_function_num
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, # cfg_interrupt_msi_sent
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msi_fail
# cfg_interrupt_msix_enable cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
# cfg_interrupt_msix_mask cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
# cfg_interrupt_msix_vf_enable cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
# cfg_interrupt_msix_vf_mask cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
# cfg_interrupt_msix_address cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
# cfg_interrupt_msix_data cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
# cfg_interrupt_msix_int cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
# cfg_interrupt_msix_vec_pending cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
# cfg_interrupt_msix_vec_pending_status cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
# cfg_interrupt_msix_sent cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
# cfg_interrupt_msix_fail cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, # cfg_interrupt_msi_attr
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, # cfg_interrupt_msi_tph_present
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_type
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_tph_st_tag
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface # Configuration Extend Interface
# cfg_ext_read_received # cfg_ext_read_received
@ -474,7 +474,7 @@ class TB(object):
@cocotb.test() @cocotb.test()
async def run_test_nic(dut): async def run_test_nic(dut):
tb = TB(dut) tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init() await tb.init()
@ -740,6 +740,7 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
@ -758,7 +759,6 @@ def test_fpga_core(request):
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"), os.path.join(pcie_rtl_dir, "pulse_merge.v"),
] ]
@ -786,7 +786,7 @@ def test_fpga_core(request):
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
@ -850,6 +850,9 @@ def test_fpga_core(request):
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3 parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1 parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32 parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 parameters['AXIL_CTRL_ADDR_WIDTH'] = 24

2
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -83,6 +83,7 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
@ -101,7 +102,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files # XDC files

8
fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
View File

@ -99,7 +99,7 @@ dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5" dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
@ -160,6 +160,9 @@ dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
dict set params PCIE_DMA_WRITE_TX_LIMIT "3" dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32" dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24" dict set params AXIL_CTRL_ADDR_WIDTH "24"
@ -193,6 +196,9 @@ set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
# PCIe IP core configuration
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
# Internal interface settings # Internal interface settings
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]

12
fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
View File

@ -7,16 +7,24 @@ set_property -dict [list \
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
CONFIG.axisten_if_enable_client_tag {true} \ CONFIG.axisten_if_enable_client_tag {true} \
CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_if_width {512_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \ CONFIG.axisten_freq {250} \
CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_CLASS_CODE {020000} \
CONFIG.PF0_DEVICE_ID {1001} \ CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
CONFIG.PF0_SUBSYSTEM_ID {9032} \ CONFIG.PF0_SUBSYSTEM_ID {9032} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
CONFIG.pf0_bar0_64bit {true} \ CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \ CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \ CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
CONFIG.vendor_id {1234} \ CONFIG.vendor_id {1234} \
CONFIG.en_msi_per_vec_masking {true} \
] [get_ips pcie4c_uscale_plus_0] ] [get_ips pcie4c_uscale_plus_0]

1
fpga/mqnic/AU50/fpga_100g/placement.xdc
View File

@ -18,6 +18,7 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4c_uscale_p
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth create_pblock pblock_eth

91
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -141,6 +141,9 @@ module fpga #
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24, parameter AXIL_CTRL_ADDR_WIDTH = 24,
@ -221,9 +224,6 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration // Interface configuration
parameter TX_TAG_WIDTH = 16; parameter TX_TAG_WIDTH = 16;
// PCIe interface configuration
parameter MSI_COUNT = 32;
// Ethernet interface configuration // Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
@ -705,22 +705,18 @@ wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld; wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel; wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable; wire [3:0] cfg_interrupt_msix_enable;
wire [11:0] cfg_interrupt_msi_mmenable; wire [3:0] cfg_interrupt_msix_mask;
wire cfg_interrupt_msi_mask_update; wire [251:0] cfg_interrupt_msix_vf_enable;
wire [31:0] cfg_interrupt_msi_data; wire [251:0] cfg_interrupt_msix_vf_mask;
wire [3:0] cfg_interrupt_msi_select; wire [63:0] cfg_interrupt_msix_address;
wire [31:0] cfg_interrupt_msi_int; wire [31:0] cfg_interrupt_msix_data;
wire [31:0] cfg_interrupt_msi_pending_status; wire cfg_interrupt_msix_int;
wire cfg_interrupt_msi_pending_status_data_enable; wire [1:0] cfg_interrupt_msix_vec_pending;
wire [3:0] cfg_interrupt_msi_pending_status_function_num; wire cfg_interrupt_msix_vec_pending_status;
wire cfg_interrupt_msi_sent; wire cfg_interrupt_msix_sent;
wire cfg_interrupt_msi_fail; wire cfg_interrupt_msix_fail;
wire [2:0] cfg_interrupt_msi_attr; wire [7:0] cfg_interrupt_msi_function_number;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor; wire status_error_cor;
wire status_error_uncor; wire status_error_uncor;
@ -869,21 +865,17 @@ pcie4c_uscale_plus_inst (
.cfg_interrupt_int(4'd0), .cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0), .cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(), .cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0), .cfg_pm_aspm_l1_entry_reject(1'b0),
@ -1458,7 +1450,9 @@ fpga_core #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -1568,23 +1562,20 @@ core_inst (
.cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel), .cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor), .status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor), .status_error_uncor(status_error_uncor),

63
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -146,7 +146,9 @@ module fpga_core #
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16, parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 16,
parameter PCIE_DMA_WRITE_TX_LIMIT = 3, parameter PCIE_DMA_WRITE_TX_LIMIT = 3,
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1, parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
parameter MSI_COUNT = 32,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32, parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -256,22 +258,18 @@ module fpga_core #
input wire [11:0] cfg_fc_cpld, input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel, output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable, input wire [3:0] cfg_interrupt_msix_enable,
input wire [11:0] cfg_interrupt_msi_mmenable, input wire [3:0] cfg_interrupt_msix_mask,
input wire cfg_interrupt_msi_mask_update, input wire [251:0] cfg_interrupt_msix_vf_enable,
input wire [31:0] cfg_interrupt_msi_data, input wire [251:0] cfg_interrupt_msix_vf_mask,
output wire [3:0] cfg_interrupt_msi_select, output wire [63:0] cfg_interrupt_msix_address,
output wire [31:0] cfg_interrupt_msi_int, output wire [31:0] cfg_interrupt_msix_data,
output wire [31:0] cfg_interrupt_msi_pending_status, output wire cfg_interrupt_msix_int,
output wire cfg_interrupt_msi_pending_status_data_enable, output wire [1:0] cfg_interrupt_msix_vec_pending,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num, input wire cfg_interrupt_msix_vec_pending_status,
input wire cfg_interrupt_msi_sent, input wire cfg_interrupt_msix_sent,
input wire cfg_interrupt_msi_fail, input wire cfg_interrupt_msix_fail,
output wire [2:0] cfg_interrupt_msi_attr, output wire [7:0] cfg_interrupt_msi_function_number,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor, output wire status_error_cor,
output wire status_error_uncor, output wire status_error_uncor,
@ -804,7 +802,9 @@ mqnic_core_pcie_us #(
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE), .PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT), .PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE), .PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.MSI_COUNT(MSI_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control) // AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
@ -923,22 +923,17 @@ core_inst (
/* /*
* Interrupt interface * Interrupt interface
*/ */
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
.cfg_interrupt_msi_vf_enable(8'd0), .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data), .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select), .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int), .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/* /*

9
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -108,6 +108,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
@ -126,7 +127,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
@ -154,7 +154,7 @@ export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 5 export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13 export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8 export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
@ -218,6 +218,9 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3 export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1 export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control) # AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
@ -312,6 +315,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
@ -403,6 +407,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE) COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE) COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)

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