merged changes in axis

lib/axis/rtl/axis_async_frame_fifo.v

@@ -55,7 +55,14 @@ module axis_async_frame_fifo #
     output wire [DATA_WIDTH-1:0]  output_axis_tdata,
     output wire                   output_axis_tvalid,
     input  wire                   output_axis_tready,
-    output wire                   output_axis_tlast
+    output wire                   output_axis_tlast,
+
+    /*
+     * Status
+     */
+    output wire                   overflow,
+    output wire                   bad_frame,
+    output wire                   good_frame
 );
 
 reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
@@ -75,14 +82,15 @@ reg output_rst_sync1 = 1;
 reg output_rst_sync2 = 1;
 
 reg drop_frame = 1'b0;
+reg overflow_reg = 1'b0;
+reg bad_frame_reg = 1'b0;
+reg good_frame_reg = 1'b0;
 
 reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, {DATA_WIDTH{1'b0}}};
 
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tdata};
@@ -106,6 +114,10 @@ assign {output_axis_tlast, output_axis_tdata} = data_out_reg;
 assign input_axis_tready = (~full | DROP_WHEN_FULL);
 assign output_axis_tvalid = output_axis_tvalid_reg;
 
+assign overflow = overflow_reg;
+assign bad_frame = bad_frame_reg;
+assign good_frame = good_frame_reg;
+
 // reset synchronization
 always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
     if (input_rst | output_rst) begin
@@ -134,13 +146,20 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
         wr_ptr_cur <= 0;
         wr_ptr_gray <= 0;
         drop_frame <= 0;
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end else if (write) begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
         if (full | full_cur | drop_frame) begin
             // buffer full, hold current pointer, drop packet at end
             drop_frame <= 1;
             if (input_axis_tlast) begin
                 wr_ptr_cur <= wr_ptr;
                 drop_frame <= 0;
+                overflow_reg <= 1;
             end
         end else begin
             mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
@@ -149,14 +168,20 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
                 if (input_axis_tuser) begin
                     // bad packet, reset write pointer
                     wr_ptr_cur <= wr_ptr;
+                    bad_frame_reg <= 1;
                 end else begin
                     // good packet, push new write pointer
                     wr_ptr_next = wr_ptr_cur + 1;
                     wr_ptr <= wr_ptr_next;
                     wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
+                    good_frame_reg <= 1;
                 end
             end
         end
+    end else begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end
 end
 

lib/axis/rtl/axis_async_frame_fifo_64.v

@@ -58,7 +58,14 @@ module axis_async_frame_fifo_64 #
     output wire [KEEP_WIDTH-1:0]  output_axis_tkeep,
     output wire                   output_axis_tvalid,
     input  wire                   output_axis_tready,
-    output wire                   output_axis_tlast
+    output wire                   output_axis_tlast,
+
+    /*
+     * Status
+     */
+    output wire                   overflow,
+    output wire                   bad_frame,
+    output wire                   good_frame
 );
 
 reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
@@ -78,14 +85,15 @@ reg output_rst_sync1 = 1;
 reg output_rst_sync2 = 1;
 
 reg drop_frame = 1'b0;
+reg overflow_reg = 1'b0;
+reg bad_frame_reg = 1'b0;
+reg good_frame_reg = 1'b0;
 
 reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
 
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
@@ -109,6 +117,10 @@ assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
 assign input_axis_tready = (~full | DROP_WHEN_FULL);
 assign output_axis_tvalid = output_axis_tvalid_reg;
 
+assign overflow = overflow_reg;
+assign bad_frame = bad_frame_reg;
+assign good_frame = good_frame_reg;
+
 // reset synchronization
 always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
     if (input_rst | output_rst) begin
@@ -137,13 +149,20 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
         wr_ptr_cur <= 0;
         wr_ptr_gray <= 0;
         drop_frame <= 0;
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end else if (write) begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
         if (full | full_cur | drop_frame) begin
             // buffer full, hold current pointer, drop packet at end
             drop_frame <= 1;
             if (input_axis_tlast) begin
                 wr_ptr_cur <= wr_ptr;
                 drop_frame <= 0;
+                overflow_reg <= 1;
             end
         end else begin
             mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
@@ -152,14 +171,20 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
                 if (input_axis_tuser) begin
                     // bad packet, reset write pointer
                     wr_ptr_cur <= wr_ptr;
+                    bad_frame_reg <= 1;
                 end else begin
                     // good packet, push new write pointer
                     wr_ptr_next = wr_ptr_cur + 1;
                     wr_ptr <= wr_ptr_next;
                     wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
+                    good_frame_reg <= 1;
                 end
             end
         end
+    end else begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end
 end
 

lib/axis/rtl/axis_frame_fifo.v

@@ -54,7 +54,14 @@ module axis_frame_fifo #
     output wire [DATA_WIDTH-1:0]  output_axis_tdata,
     output wire                   output_axis_tvalid,
     input  wire                   output_axis_tready,
-    output wire                   output_axis_tlast
+    output wire                   output_axis_tlast,
+
+    /*
+     * Status
+     */
+    output wire                   overflow,
+    output wire                   bad_frame,
+    output wire                   good_frame
 );
 
 reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
@@ -62,14 +69,15 @@ reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
 
 reg drop_frame = 1'b0;
+reg overflow_reg = 1'b0;
+reg bad_frame_reg = 1'b0;
+reg good_frame_reg = 1'b0;
 
 reg [DATA_WIDTH+1-1:0] data_out_reg = {1'b0, {DATA_WIDTH{1'b0}}};
 
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+1-1:0] data_in = {input_axis_tlast, input_axis_tdata};
@@ -91,19 +99,30 @@ assign {output_axis_tlast, output_axis_tdata} = data_out_reg;
 assign input_axis_tready = (~full | DROP_WHEN_FULL);
 assign output_axis_tvalid = output_axis_tvalid_reg;
 
+assign overflow = overflow_reg;
+assign bad_frame = bad_frame_reg;
+assign good_frame = good_frame_reg;
+
 // write
 always @(posedge clk or posedge rst) begin
     if (rst) begin
         wr_ptr <= 0;
         wr_ptr_cur <= 0;
         drop_frame <= 0;
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end else if (write) begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
         if (full | full_cur | drop_frame) begin
             // buffer full, hold current pointer, drop packet at end
             drop_frame <= 1;
             if (input_axis_tlast) begin
                 wr_ptr_cur <= wr_ptr;
                 drop_frame <= 0;
+                overflow_reg <= 1;
             end
         end else begin
             mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
@@ -112,12 +131,18 @@ always @(posedge clk or posedge rst) begin
                 if (input_axis_tuser) begin
                     // bad packet, reset write pointer
                     wr_ptr_cur <= wr_ptr;
+                    bad_frame_reg <= 1;
                 end else begin
                     // good packet, push new write pointer
                     wr_ptr <= wr_ptr_cur + 1;
+                    good_frame_reg <= 1;
                 end
             end
         end
+    end else begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end
 end
 

lib/axis/rtl/axis_frame_fifo_64.v

@@ -57,7 +57,14 @@ module axis_frame_fifo_64 #
     output wire [KEEP_WIDTH-1:0]  output_axis_tkeep,
     output wire                   output_axis_tvalid,
     input  wire                   output_axis_tready,
-    output wire                   output_axis_tlast
+    output wire                   output_axis_tlast,
+
+    /*
+     * Status
+     */
+    output wire                   overflow,
+    output wire                   bad_frame,
+    output wire                   good_frame
 );
 
 reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
@@ -65,14 +72,15 @@ reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
 
 reg drop_frame = 1'b0;
+reg overflow_reg = 1'b0;
+reg bad_frame_reg = 1'b0;
+reg good_frame_reg = 1'b0;
 
 reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
 
 //(* RAM_STYLE="BLOCK" *)
 reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
 
-reg output_read = 1'b0;
-
 reg output_axis_tvalid_reg = 1'b0;
 
 wire [DATA_WIDTH+KEEP_WIDTH+1-1:0] data_in = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
@@ -94,19 +102,30 @@ assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
 assign input_axis_tready = (~full | DROP_WHEN_FULL);
 assign output_axis_tvalid = output_axis_tvalid_reg;
 
+assign overflow = overflow_reg;
+assign bad_frame = bad_frame_reg;
+assign good_frame = good_frame_reg;
+
 // write
 always @(posedge clk or posedge rst) begin
     if (rst) begin
         wr_ptr <= 0;
         wr_ptr_cur <= 0;
         drop_frame <= 0;
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end else if (write) begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
         if (full | full_cur | drop_frame) begin
             // buffer full, hold current pointer, drop packet at end
             drop_frame <= 1;
             if (input_axis_tlast) begin
                 wr_ptr_cur <= wr_ptr;
                 drop_frame <= 0;
+                overflow_reg <= 1;
             end
         end else begin
             mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
@@ -115,12 +134,18 @@ always @(posedge clk or posedge rst) begin
                 if (input_axis_tuser) begin
                     // bad packet, reset write pointer
                     wr_ptr_cur <= wr_ptr;
+                    bad_frame_reg <= 1;
                 end else begin
                     // good packet, push new write pointer
                     wr_ptr <= wr_ptr_cur + 1;
+                    good_frame_reg <= 1;
                 end
             end
         end
+    end else begin
+        overflow_reg <= 0;
+        bad_frame_reg <= 0;
+        good_frame_reg <= 0;
     end
 end
 

lib/axis/rtl/axis_rate_limit.v

@@ -81,7 +81,7 @@ assign input_axis_tready = input_axis_tready_reg;
 always @* begin
     acc_next = acc_reg;
     pause = 0;
-    frame_next = frame_reg & ~input_axis_tlast;
+    frame_next = frame_reg;
 
     if (acc_reg >= rate_num) begin
         acc_next = acc_reg - rate_num;

lib/axis/rtl/axis_rate_limit_64.v

@@ -85,7 +85,7 @@ assign input_axis_tready = input_axis_tready_reg;
 always @* begin
     acc_next = acc_reg;
     pause = 0;
-    frame_next = frame_reg & ~input_axis_tlast;
+    frame_next = frame_reg;
 
     if (acc_reg >= rate_num) begin
         acc_next = acc_reg - rate_num;

lib/axis/tb/test_axis_async_frame_fifo.py

@@ -59,7 +59,11 @@ def dut_axis_async_frame_fifo(input_clk,
                  output_axis_tdata,
                  output_axis_tvalid,
                  output_axis_tready,
-                 output_axis_tlast):
+                 output_axis_tlast,
+
+                 overflow,
+                 bad_frame,
+                 good_frame):
 
     if os.system(build_cmd):
         raise Exception("Error running build command")
@@ -79,7 +83,11 @@ def dut_axis_async_frame_fifo(input_clk,
                 output_axis_tdata=output_axis_tdata,
                 output_axis_tvalid=output_axis_tvalid,
                 output_axis_tready=output_axis_tready,
-                output_axis_tlast=output_axis_tlast)
+                output_axis_tlast=output_axis_tlast,
+
+                overflow=overflow,
+                bad_frame=bad_frame,
+                good_frame=good_frame)
 
 def bench():
 
@@ -101,6 +109,9 @@ def bench():
     output_axis_tdata = Signal(intbv(0)[8:])
     output_axis_tvalid = Signal(bool(0))
     output_axis_tlast = Signal(bool(0))
+    overflow = Signal(bool(0))
+    bad_frame = Signal(bool(0))
+    good_frame = Signal(bool(0))
 
     # sources and sinks
     source_queue = Queue()
@@ -145,7 +156,11 @@ def bench():
                        output_axis_tdata,
                        output_axis_tvalid,
                        output_axis_tready,
-                       output_axis_tlast)
+                       output_axis_tlast,
+
+                       overflow,
+                       bad_frame,
+                       good_frame)
 
     @always(delay(4))
     def input_clkgen():
@@ -155,6 +170,19 @@ def bench():
     def output_clkgen():
         output_clk.next = not output_clk
 
+    overflow_asserted = Signal(bool(0))
+    bad_frame_asserted = Signal(bool(0))
+    good_frame_asserted = Signal(bool(0))
+
+    @always(input_clk.posedge)
+    def monitor():
+        if (overflow):
+            overflow_asserted.next = 1
+        if (bad_frame):
+            bad_frame_asserted.next = 1
+        if (good_frame):
+            good_frame_asserted.next = 1
+
     @instance
     def check():
         yield delay(100)
@@ -180,6 +208,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -193,6 +226,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -203,6 +240,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256)))
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -216,6 +258,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield input_clk.posedge
         print("test 3: test packet with pauses")
         current_test.next = 3
@@ -224,6 +270,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -251,6 +302,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -265,6 +320,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield input_clk.posedge
@@ -287,6 +347,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -301,6 +365,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield input_clk.posedge
@@ -332,6 +401,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -346,6 +419,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield input_clk.posedge
@@ -373,6 +451,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -384,6 +466,11 @@ def bench():
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
         test_frame.user = 1
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -391,6 +478,10 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert not overflow_asserted
+        assert bad_frame_asserted
+        assert not good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -401,6 +492,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256))*2)
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -408,11 +504,15 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert overflow_asserted
+        assert not bad_frame_asserted
+        assert not good_frame_asserted
+
         yield delay(100)
 
         raise StopSimulation
 
-    return dut, source, sink, input_clkgen, output_clkgen, check
+    return dut, monitor, source, sink, input_clkgen, output_clkgen, check
 
 def test_bench():
     os.chdir(os.path.dirname(os.path.abspath(__file__)))

lib/axis/tb/test_axis_async_frame_fifo.v

@@ -46,6 +46,9 @@ wire input_axis_tready;
 wire [7:0] output_axis_tdata;
 wire output_axis_tvalid;
 wire output_axis_tlast;
+wire overflow;
+wire bad_frame;
+wire good_frame;
 
 initial begin
     // myhdl integration
@@ -62,7 +65,10 @@ initial begin
     $to_myhdl(input_axis_tready,
               output_axis_tdata,
               output_axis_tvalid,
-              output_axis_tlast);
+              output_axis_tlast,
+              overflow,
+              bad_frame,
+              good_frame);
 
     // dump file
     $dumpfile("test_axis_async_frame_fifo.lxt");
@@ -89,7 +95,11 @@ UUT (
     .output_axis_tdata(output_axis_tdata),
     .output_axis_tvalid(output_axis_tvalid),
     .output_axis_tready(output_axis_tready),
-    .output_axis_tlast(output_axis_tlast)
+    .output_axis_tlast(output_axis_tlast),
+    // Status
+    .overflow(overflow),
+    .bad_frame(bad_frame),
+    .good_frame(good_frame)
 );
 
 endmodule

lib/axis/tb/test_axis_async_frame_fifo_64.py

@@ -61,7 +61,11 @@ def dut_axis_async_frame_fifo_64(input_clk,
                  output_axis_tkeep,
                  output_axis_tvalid,
                  output_axis_tready,
-                 output_axis_tlast):
+                 output_axis_tlast,
+
+                 overflow,
+                 bad_frame,
+                 good_frame):
 
     if os.system(build_cmd):
         raise Exception("Error running build command")
@@ -83,7 +87,11 @@ def dut_axis_async_frame_fifo_64(input_clk,
                 output_axis_tkeep=output_axis_tkeep,
                 output_axis_tvalid=output_axis_tvalid,
                 output_axis_tready=output_axis_tready,
-                output_axis_tlast=output_axis_tlast)
+                output_axis_tlast=output_axis_tlast,
+
+                overflow=overflow,
+                bad_frame=bad_frame,
+                good_frame=good_frame)
 
 def bench():
 
@@ -107,6 +115,9 @@ def bench():
     output_axis_tkeep = Signal(intbv(0)[8:])
     output_axis_tvalid = Signal(bool(0))
     output_axis_tlast = Signal(bool(0))
+    overflow = Signal(bool(0))
+    bad_frame = Signal(bool(0))
+    good_frame = Signal(bool(0))
 
     # sources and sinks
     source_queue = Queue()
@@ -155,7 +166,11 @@ def bench():
                        output_axis_tkeep,
                        output_axis_tvalid,
                        output_axis_tready,
-                       output_axis_tlast)
+                       output_axis_tlast,
+
+                       overflow,
+                       bad_frame,
+                       good_frame)
 
     @always(delay(4))
     def input_clkgen():
@@ -165,6 +180,19 @@ def bench():
     def output_clkgen():
         output_clk.next = not output_clk
 
+    overflow_asserted = Signal(bool(0))
+    bad_frame_asserted = Signal(bool(0))
+    good_frame_asserted = Signal(bool(0))
+
+    @always(input_clk.posedge)
+    def monitor():
+        if (overflow):
+            overflow_asserted.next = 1
+        if (bad_frame):
+            bad_frame_asserted.next = 1
+        if (good_frame):
+            good_frame_asserted.next = 1
+
     @instance
     def check():
         yield delay(100)
@@ -190,6 +218,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -203,6 +236,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -213,6 +250,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256)))
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -226,6 +268,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield input_clk.posedge
         print("test 3: test packet with pauses")
         current_test.next = 3
@@ -234,6 +280,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256)))
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -261,6 +312,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -275,6 +330,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield input_clk.posedge
@@ -297,6 +357,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -311,6 +375,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield input_clk.posedge
@@ -342,6 +411,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -356,6 +429,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield input_clk.posedge
@@ -383,6 +461,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -394,6 +476,11 @@ def bench():
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
         test_frame.user = 1
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -401,6 +488,10 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert not overflow_asserted
+        assert bad_frame_asserted
+        assert not good_frame_asserted
+
         yield delay(100)
 
         yield input_clk.posedge
@@ -411,6 +502,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256))*2)
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield input_clk.posedge
 
@@ -418,11 +514,15 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert overflow_asserted
+        assert not bad_frame_asserted
+        assert not good_frame_asserted
+
         yield delay(100)
 
         raise StopSimulation
 
-    return dut, source, sink, input_clkgen, output_clkgen, check
+    return dut, monitor, source, sink, input_clkgen, output_clkgen, check
 
 def test_bench():
     os.chdir(os.path.dirname(os.path.abspath(__file__)))

lib/axis/tb/test_axis_async_frame_fifo_64.v

@@ -48,6 +48,9 @@ wire [63:0] output_axis_tdata;
 wire [7:0] output_axis_tkeep;
 wire output_axis_tvalid;
 wire output_axis_tlast;
+wire overflow;
+wire bad_frame;
+wire good_frame;
 
 initial begin
     // myhdl integration
@@ -66,7 +69,10 @@ initial begin
               output_axis_tdata,
               output_axis_tkeep,
               output_axis_tvalid,
-              output_axis_tlast);
+              output_axis_tlast,
+              overflow,
+              bad_frame,
+              good_frame);
 
     // dump file
     $dumpfile("test_axis_async_frame_fifo_64.lxt");
@@ -95,7 +101,11 @@ UUT (
     .output_axis_tkeep(output_axis_tkeep),
     .output_axis_tvalid(output_axis_tvalid),
     .output_axis_tready(output_axis_tready),
-    .output_axis_tlast(output_axis_tlast)
+    .output_axis_tlast(output_axis_tlast),
+    // Status
+    .overflow(overflow),
+    .bad_frame(bad_frame),
+    .good_frame(good_frame)
 );
 
 endmodule

lib/axis/tb/test_axis_frame_fifo.py

@@ -57,7 +57,11 @@ def dut_axis_frame_fifo(clk,
                  output_axis_tdata,
                  output_axis_tvalid,
                  output_axis_tready,
-                 output_axis_tlast):
+                 output_axis_tlast,
+
+                 overflow,
+                 bad_frame,
+                 good_frame):
 
     if os.system(build_cmd):
         raise Exception("Error running build command")
@@ -75,7 +79,11 @@ def dut_axis_frame_fifo(clk,
                 output_axis_tdata=output_axis_tdata,
                 output_axis_tvalid=output_axis_tvalid,
                 output_axis_tready=output_axis_tready,
-                output_axis_tlast=output_axis_tlast)
+                output_axis_tlast=output_axis_tlast,
+
+                overflow=overflow,
+                bad_frame=bad_frame,
+                good_frame=good_frame)
 
 def bench():
 
@@ -95,6 +103,9 @@ def bench():
     output_axis_tdata = Signal(intbv(0)[8:])
     output_axis_tvalid = Signal(bool(0))
     output_axis_tlast = Signal(bool(0))
+    overflow = Signal(bool(0))
+    bad_frame = Signal(bool(0))
+    good_frame = Signal(bool(0))
 
     # sources and sinks
     source_queue = Queue()
@@ -137,12 +148,29 @@ def bench():
                        output_axis_tdata,
                        output_axis_tvalid,
                        output_axis_tready,
-                       output_axis_tlast)
+                       output_axis_tlast,
+
+                       overflow,
+                       bad_frame,
+                       good_frame)
 
     @always(delay(4))
     def clkgen():
         clk.next = not clk
 
+    overflow_asserted = Signal(bool(0))
+    bad_frame_asserted = Signal(bool(0))
+    good_frame_asserted = Signal(bool(0))
+
+    @always(clk.posedge)
+    def monitor():
+        if (overflow):
+            overflow_asserted.next = 1
+        if (bad_frame):
+            bad_frame_asserted.next = 1
+        if (good_frame):
+            good_frame_asserted.next = 1
+
     @instance
     def check():
         yield delay(100)
@@ -164,6 +192,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -177,6 +210,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -187,6 +224,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256)))
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -200,6 +242,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield clk.posedge
         print("test 3: test packet with pauses")
         current_test.next = 3
@@ -208,6 +254,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -235,6 +286,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -249,6 +304,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield clk.posedge
@@ -271,6 +331,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -285,6 +349,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield clk.posedge
@@ -312,6 +381,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -326,6 +399,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield clk.posedge
@@ -353,6 +431,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -364,6 +446,11 @@ def bench():
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
         test_frame.user = 1
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -371,6 +458,10 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert not overflow_asserted
+        assert bad_frame_asserted
+        assert not good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -381,6 +472,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256))*2)
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -388,11 +484,15 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert overflow_asserted
+        assert not bad_frame_asserted
+        assert not good_frame_asserted
+
         yield delay(100)
 
         raise StopSimulation
 
-    return dut, source, sink, clkgen, check
+    return dut, monitor, source, sink, clkgen, check
 
 def test_bench():
     os.chdir(os.path.dirname(os.path.abspath(__file__)))

lib/axis/tb/test_axis_frame_fifo.v

@@ -44,6 +44,9 @@ wire input_axis_tready;
 wire [7:0] output_axis_tdata;
 wire output_axis_tvalid;
 wire output_axis_tlast;
+wire overflow;
+wire bad_frame;
+wire good_frame;
 
 initial begin
     // myhdl integration
@@ -58,7 +61,10 @@ initial begin
     $to_myhdl(input_axis_tready,
               output_axis_tdata,
               output_axis_tvalid,
-              output_axis_tlast);
+              output_axis_tlast,
+              overflow,
+              bad_frame,
+              good_frame);
 
     // dump file
     $dumpfile("test_axis_frame_fifo.lxt");
@@ -83,7 +89,11 @@ UUT (
     .output_axis_tdata(output_axis_tdata),
     .output_axis_tvalid(output_axis_tvalid),
     .output_axis_tready(output_axis_tready),
-    .output_axis_tlast(output_axis_tlast)
+    .output_axis_tlast(output_axis_tlast),
+    // Status
+    .overflow(overflow),
+    .bad_frame(bad_frame),
+    .good_frame(good_frame)
 );
 
 endmodule

lib/axis/tb/test_axis_frame_fifo_64.py

@@ -60,7 +60,11 @@ def dut_axis_frame_fifo_64(clk,
                  output_axis_tvalid,
                  output_axis_tready,
                  output_axis_tlast,
-                 output_axis_tuser):
+                 output_axis_tuser,
+
+                 overflow,
+                 bad_frame,
+                 good_frame):
 
     if os.system(build_cmd):
         raise Exception("Error running build command")
@@ -81,7 +85,11 @@ def dut_axis_frame_fifo_64(clk,
                 output_axis_tvalid=output_axis_tvalid,
                 output_axis_tready=output_axis_tready,
                 output_axis_tlast=output_axis_tlast,
-                output_axis_tuser=output_axis_tuser)
+                output_axis_tuser=output_axis_tuser,
+
+                overflow=overflow,
+                bad_frame=bad_frame,
+                good_frame=good_frame)
 
 def bench():
 
@@ -104,6 +112,9 @@ def bench():
     output_axis_tvalid = Signal(bool(0))
     output_axis_tlast = Signal(bool(0))
     output_axis_tuser = Signal(bool(0))
+    overflow = Signal(bool(0))
+    bad_frame = Signal(bool(0))
+    good_frame = Signal(bool(0))
 
     # sources and sinks
     source_queue = Queue()
@@ -152,12 +163,29 @@ def bench():
                        output_axis_tvalid,
                        output_axis_tready,
                        output_axis_tlast,
-                       output_axis_tuser)
+                       output_axis_tuser,
+
+                       overflow,
+                       bad_frame,
+                       good_frame)
 
     @always(delay(4))
     def clkgen():
         clk.next = not clk
 
+    overflow_asserted = Signal(bool(0))
+    bad_frame_asserted = Signal(bool(0))
+    good_frame_asserted = Signal(bool(0))
+
+    @always(clk.posedge)
+    def monitor():
+        if (overflow):
+            overflow_asserted.next = 1
+        if (bad_frame):
+            bad_frame_asserted.next = 1
+        if (good_frame):
+            good_frame_asserted.next = 1
+
     @instance
     def check():
         yield delay(100)
@@ -179,6 +207,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -192,6 +225,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -202,6 +239,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256)))
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -215,6 +257,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield clk.posedge
         print("test 3: test packet with pauses")
         current_test.next = 3
@@ -223,6 +269,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256)))
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -250,6 +301,10 @@ def bench():
 
         assert rx_frame == test_frame
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -264,6 +319,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield clk.posedge
@@ -286,6 +346,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -300,6 +364,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield clk.posedge
@@ -327,6 +396,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -341,6 +414,11 @@ def bench():
                                              b'\x5A\x51\x52\x53\x54\x55' +
                                              b'\x80\x00' +
                                              b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame1)
         source_queue.put(test_frame2)
         yield clk.posedge
@@ -368,6 +446,10 @@ def bench():
 
         assert rx_frame == test_frame2
 
+        assert not overflow_asserted
+        assert not bad_frame_asserted
+        assert good_frame_asserted
+
         yield delay(100)
 
         yield clk.posedge
@@ -379,6 +461,11 @@ def bench():
                                             b'\x80\x00' +
                                             b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
         test_frame.user = 1
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -386,6 +473,12 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert not overflow_asserted
+        assert bad_frame_asserted
+        assert not good_frame_asserted
+
+        yield delay(100)
+
         yield clk.posedge
         print("test 8: single packet overflow")
         current_test.next = 8
@@ -394,6 +487,11 @@ def bench():
                                             b'\x5A\x51\x52\x53\x54\x55' +
                                             b'\x80\x00' +
                                             bytearray(range(256))*2)
+
+        overflow_asserted.next = 0
+        bad_frame_asserted.next = 0
+        good_frame_asserted.next = 0
+
         source_queue.put(test_frame)
         yield clk.posedge
 
@@ -401,11 +499,15 @@ def bench():
 
         assert sink_queue.empty()
 
+        assert overflow_asserted
+        assert not bad_frame_asserted
+        assert not good_frame_asserted
+
         yield delay(100)
 
         raise StopSimulation
 
-    return dut, source, sink, clkgen, check
+    return dut, monitor, source, sink, clkgen, check
 
 def test_bench():
     os.chdir(os.path.dirname(os.path.abspath(__file__)))

lib/axis/tb/test_axis_frame_fifo_64.v

@@ -46,6 +46,9 @@ wire [63:0] output_axis_tdata;
 wire [7:0] output_axis_tkeep;
 wire output_axis_tvalid;
 wire output_axis_tlast;
+wire overflow;
+wire bad_frame;
+wire good_frame;
 
 initial begin
     // myhdl integration
@@ -62,7 +65,10 @@ initial begin
               output_axis_tdata,
               output_axis_tkeep,
               output_axis_tvalid,
-              output_axis_tlast);
+              output_axis_tlast,
+              overflow,
+              bad_frame,
+              good_frame);
 
     // dump file
     $dumpfile("test_axis_frame_fifo_64.lxt");
@@ -89,7 +95,11 @@ UUT (
     .output_axis_tkeep(output_axis_tkeep),
     .output_axis_tvalid(output_axis_tvalid),
     .output_axis_tready(output_axis_tready),
-    .output_axis_tlast(output_axis_tlast)
+    .output_axis_tlast(output_axis_tlast),
+    // Status
+    .overflow(overflow),
+    .bad_frame(bad_frame),
+    .good_frame(good_frame)
 );
 
 endmodule

lib/axis/tb/test_axis_stat_counter.v

@@ -28,6 +28,18 @@ THE SOFTWARE.
 
 module test_axis_stat_counter;
 
+// parameters
+parameter DATA_WIDTH = 64;
+parameter KEEP_WIDTH = (DATA_WIDTH/8);
+parameter TAG_ENABLE = 1;
+parameter TAG_WIDTH = 16;
+parameter TICK_COUNT_ENABLE = 1;
+parameter TICK_COUNT_WIDTH = 32;
+parameter BYTE_COUNT_ENABLE = 1;
+parameter BYTE_COUNT_WIDTH = 32;
+parameter FRAME_COUNT_ENABLE = 1;
+parameter FRAME_COUNT_WIDTH = 32;
+
 // Inputs
 reg clk = 0;
 reg rst = 0;
@@ -76,7 +88,16 @@ initial begin
 end
 
 axis_stat_counter #(
-    .DATA_WIDTH(64)
+    .DATA_WIDTH(DATA_WIDTH),
+    .KEEP_WIDTH(KEEP_WIDTH),
+    .TAG_ENABLE(TAG_ENABLE),
+    .TAG_WIDTH(TAG_WIDTH),
+    .TICK_COUNT_ENABLE(TICK_COUNT_ENABLE),
+    .TICK_COUNT_WIDTH(TICK_COUNT_WIDTH),
+    .BYTE_COUNT_ENABLE(BYTE_COUNT_ENABLE),
+    .BYTE_COUNT_WIDTH(BYTE_COUNT_WIDTH),
+    .FRAME_COUNT_ENABLE(FRAME_COUNT_ENABLE),
+    .FRAME_COUNT_WIDTH(FRAME_COUNT_WIDTH)
 )
 UUT (
     .clk(clk),