diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 94fdee880..9db2dc2a2 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -199,6 +199,22 @@ export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 131072 export PARAM_RX_RAM_SIZE := 131072 +# RAM configuration +export PARAM_DDR_CH := 1 +export PARAM_DDR_ENABLE := 0 +export PARAM_DDR_GROUP_SIZE := 1 +export PARAM_AXI_DDR_DATA_WIDTH := 256 +export PARAM_AXI_DDR_ADDR_WIDTH := 32 +export PARAM_AXI_DDR_ID_WIDTH := 8 +export PARAM_AXI_DDR_MAX_BURST_LEN := 256 +export PARAM_HBM_CH := 1 +export PARAM_HBM_ENABLE := 0 +export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH) +export PARAM_AXI_HBM_DATA_WIDTH := 256 +export PARAM_AXI_HBM_ADDR_WIDTH := 32 +export PARAM_AXI_HBM_ID_WIDTH := 6 +export PARAM_AXI_HBM_MAX_BURST_LEN := 16 + # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x12348001)) ) export PARAM_APP_ENABLE := 1 diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 232dbfac5..e1b79c479 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -48,6 +48,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiSlave, AxiBus, SparseMemoryRegion from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice @@ -352,6 +353,38 @@ class TB(object): dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + # DDR + self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value + self.ddr_ram = [] + self.ddr_axi_if = [] + if hasattr(core_inst, 'ddr'): + ram = None + for i, ch in enumerate(core_inst.ddr.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 3.332, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.ddr_group_size == 0: + ram = SparseMemoryRegion() + self.ddr_ram.append(ram) + self.ddr_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + + # HBM + self.hbm_group_size = core_inst.HBM_GROUP_SIZE.value + self.hbm_ram = [] + self.hbm_axi_if = [] + if hasattr(core_inst, 'hbm'): + ram = None + for i, ch in enumerate(core_inst.hbm.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 2.222, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.hbm_group_size == 0: + ram = SparseMemoryRegion() + self.hbm_ram.append(ram) + self.hbm_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) @@ -377,6 +410,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -386,6 +422,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(1) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(1) + await FallingEdge(self.dut.rst) await Timer(100, 'ns') @@ -398,6 +437,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await self.rc.enumerate() async def _run_loopback(self): @@ -1024,6 +1066,22 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # RAM configuration + parameters['DDR_CH'] = 1 + parameters['DDR_ENABLE'] = 0 + parameters['DDR_GROUP_SIZE'] = 1 + parameters['AXI_DDR_DATA_WIDTH'] = 256 + parameters['AXI_DDR_ADDR_WIDTH'] = 32 + parameters['AXI_DDR_ID_WIDTH'] = 8 + parameters['AXI_DDR_MAX_BURST_LEN'] = 256 + parameters['HBM_CH'] = 1 + parameters['HBM_ENABLE'] = 0 + parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH'] + parameters['AXI_HBM_DATA_WIDTH'] = 256 + parameters['AXI_HBM_ADDR_WIDTH'] = 32 + parameters['AXI_HBM_ID_WIDTH'] = 6 + parameters['AXI_HBM_MAX_BURST_LEN'] = 16 + # Application block configuration parameters['APP_ID'] = 0x12348001 parameters['APP_ENABLE'] = 1 diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index 21d305796..b50cfcc41 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -197,6 +197,22 @@ export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 131072 export PARAM_RX_RAM_SIZE := 131072 +# RAM configuration +export PARAM_DDR_CH := 1 +export PARAM_DDR_ENABLE := 0 +export PARAM_DDR_GROUP_SIZE := 1 +export PARAM_AXI_DDR_DATA_WIDTH := 256 +export PARAM_AXI_DDR_ADDR_WIDTH := 32 +export PARAM_AXI_DDR_ID_WIDTH := 8 +export PARAM_AXI_DDR_MAX_BURST_LEN := 256 +export PARAM_HBM_CH := 1 +export PARAM_HBM_ENABLE := 0 +export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH) +export PARAM_AXI_HBM_DATA_WIDTH := 256 +export PARAM_AXI_HBM_ADDR_WIDTH := 32 +export PARAM_AXI_HBM_ID_WIDTH := 6 +export PARAM_AXI_HBM_MAX_BURST_LEN := 16 + # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x12340001)) ) export PARAM_APP_ENABLE := 1 diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index f697c0a2a..aec4a1f12 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -48,6 +48,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiSlave, AxiBus, SparseMemoryRegion from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice @@ -352,6 +353,38 @@ class TB(object): dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + # DDR + self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value + self.ddr_ram = [] + self.ddr_axi_if = [] + if hasattr(core_inst, 'ddr'): + ram = None + for i, ch in enumerate(core_inst.ddr.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 3.332, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.ddr_group_size == 0: + ram = SparseMemoryRegion() + self.ddr_ram.append(ram) + self.ddr_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + + # HBM + self.hbm_group_size = core_inst.HBM_GROUP_SIZE.value + self.hbm_ram = [] + self.hbm_axi_if = [] + if hasattr(core_inst, 'hbm'): + ram = None + for i, ch in enumerate(core_inst.hbm.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 2.222, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.hbm_group_size == 0: + ram = SparseMemoryRegion() + self.hbm_ram.append(ram) + self.hbm_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) @@ -377,6 +410,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -386,6 +422,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(1) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(1) + await FallingEdge(self.dut.rst) await Timer(100, 'ns') @@ -398,6 +437,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await self.rc.enumerate() async def _run_loopback(self): @@ -860,6 +902,22 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # RAM configuration + parameters['DDR_CH'] = 1 + parameters['DDR_ENABLE'] = 0 + parameters['DDR_GROUP_SIZE'] = 1 + parameters['AXI_DDR_DATA_WIDTH'] = 256 + parameters['AXI_DDR_ADDR_WIDTH'] = 32 + parameters['AXI_DDR_ID_WIDTH'] = 8 + parameters['AXI_DDR_MAX_BURST_LEN'] = 256 + parameters['HBM_CH'] = 1 + parameters['HBM_ENABLE'] = 0 + parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH'] + parameters['AXI_HBM_DATA_WIDTH'] = 256 + parameters['AXI_HBM_ADDR_WIDTH'] = 32 + parameters['AXI_HBM_ID_WIDTH'] = 6 + parameters['AXI_HBM_MAX_BURST_LEN'] = 16 + # Application block configuration parameters['APP_ID'] = 0x12340001 parameters['APP_ENABLE'] = 1 diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index 92f1a7aa8..03306f9c9 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -181,6 +181,22 @@ export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 131072 export PARAM_RX_RAM_SIZE := 131072 +# RAM configuration +export PARAM_DDR_CH := 1 +export PARAM_DDR_ENABLE := 0 +export PARAM_DDR_GROUP_SIZE := 1 +export PARAM_AXI_DDR_DATA_WIDTH := 256 +export PARAM_AXI_DDR_ADDR_WIDTH := 32 +export PARAM_AXI_DDR_ID_WIDTH := 8 +export PARAM_AXI_DDR_MAX_BURST_LEN := 256 +export PARAM_HBM_CH := 1 +export PARAM_HBM_ENABLE := 0 +export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH) +export PARAM_AXI_HBM_DATA_WIDTH := 256 +export PARAM_AXI_HBM_ADDR_WIDTH := 32 +export PARAM_AXI_HBM_ID_WIDTH := 6 +export PARAM_AXI_HBM_MAX_BURST_LEN := 16 + # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) export PARAM_APP_ENABLE := 0 diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 9bc2abf4b..f86e0188f 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -50,7 +50,7 @@ from cocotb.triggers import RisingEdge, Timer from cocotbext.axi import AxiStreamBus from cocotbext.axi import AddressSpace from cocotbext.axi import AxiLiteMaster, AxiLiteBus -from cocotbext.axi import AxiSlave, AxiBus +from cocotbext.axi import AxiSlave, AxiBus, SparseMemoryRegion from cocotbext.eth import EthMac try: @@ -135,6 +135,38 @@ class TB(object): dut.tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + # DDR + self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value + self.ddr_ram = [] + self.ddr_axi_if = [] + if hasattr(core_inst, 'ddr'): + ram = None + for i, ch in enumerate(core_inst.ddr.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 3.332, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.ddr_group_size == 0: + ram = SparseMemoryRegion() + self.ddr_ram.append(ram) + self.ddr_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + + # HBM + self.hbm_group_size = core_inst.HBM_GROUP_SIZE.value + self.hbm_ram = [] + self.hbm_axi_if = [] + if hasattr(core_inst, 'hbm'): + ram = None + for i, ch in enumerate(core_inst.hbm.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 2.222, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.hbm_group_size == 0: + ram = SparseMemoryRegion() + self.hbm_ram.append(ram) + self.hbm_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) @@ -164,6 +196,9 @@ class TB(object): await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + self.dut.rst.value = 1 for mac in self.port_mac: mac.rx.reset.value = 1 @@ -171,6 +206,9 @@ class TB(object): self.dut.ptp_rst.value = 1 + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.value = 1 + await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -181,6 +219,9 @@ class TB(object): self.dut.ptp_rst.value = 0 + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.value = 0 + async def _run_loopback(self): while True: await RisingEdge(self.dut.clk) @@ -635,6 +676,22 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # RAM configuration + parameters['DDR_CH'] = 1 + parameters['DDR_ENABLE'] = 0 + parameters['DDR_GROUP_SIZE'] = 1 + parameters['AXI_DDR_DATA_WIDTH'] = 256 + parameters['AXI_DDR_ADDR_WIDTH'] = 32 + parameters['AXI_DDR_ID_WIDTH'] = 8 + parameters['AXI_DDR_MAX_BURST_LEN'] = 256 + parameters['HBM_CH'] = 1 + parameters['HBM_ENABLE'] = 0 + parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH'] + parameters['AXI_HBM_DATA_WIDTH'] = 256 + parameters['AXI_HBM_ADDR_WIDTH'] = 32 + parameters['AXI_HBM_ID_WIDTH'] = 6 + parameters['AXI_HBM_MAX_BURST_LEN'] = 16 + # Application block configuration parameters['APP_ID'] = 0x00000000 parameters['APP_ENABLE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index 3d640648c..17aff3dcf 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -196,6 +196,22 @@ export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 131072 export PARAM_RX_RAM_SIZE := 131072 +# RAM configuration +export PARAM_DDR_CH := 1 +export PARAM_DDR_ENABLE := 0 +export PARAM_DDR_GROUP_SIZE := 1 +export PARAM_AXI_DDR_DATA_WIDTH := 256 +export PARAM_AXI_DDR_ADDR_WIDTH := 32 +export PARAM_AXI_DDR_ID_WIDTH := 8 +export PARAM_AXI_DDR_MAX_BURST_LEN := 256 +export PARAM_HBM_CH := 1 +export PARAM_HBM_ENABLE := 0 +export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH) +export PARAM_AXI_HBM_DATA_WIDTH := 256 +export PARAM_AXI_HBM_ADDR_WIDTH := 32 +export PARAM_AXI_HBM_ID_WIDTH := 6 +export PARAM_AXI_HBM_MAX_BURST_LEN := 16 + # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) export PARAM_APP_ENABLE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index 8c5946319..f80052607 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -48,6 +48,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiSlave, AxiBus, SparseMemoryRegion from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.intel.ptile import PTilePcieDevice, PTileRxBus, PTileTxBus @@ -330,6 +331,38 @@ class TB(object): dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + # DDR + self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value + self.ddr_ram = [] + self.ddr_axi_if = [] + if hasattr(core_inst, 'ddr'): + ram = None + for i, ch in enumerate(core_inst.ddr.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 3.332, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.ddr_group_size == 0: + ram = SparseMemoryRegion() + self.ddr_ram.append(ram) + self.ddr_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + + # HBM + self.hbm_group_size = core_inst.HBM_GROUP_SIZE.value + self.hbm_ram = [] + self.hbm_axi_if = [] + if hasattr(core_inst, 'hbm'): + ram = None + for i, ch in enumerate(core_inst.hbm.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 2.222, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.hbm_group_size == 0: + ram = SparseMemoryRegion() + self.hbm_ram.append(ram) + self.hbm_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) @@ -355,6 +388,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -364,6 +400,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(1) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(1) + await FallingEdge(self.dut.rst) await Timer(100, 'ns') @@ -376,6 +415,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await self.rc.enumerate() async def _run_loopback(self): @@ -850,6 +892,22 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # RAM configuration + parameters['DDR_CH'] = 1 + parameters['DDR_ENABLE'] = 0 + parameters['DDR_GROUP_SIZE'] = 1 + parameters['AXI_DDR_DATA_WIDTH'] = 256 + parameters['AXI_DDR_ADDR_WIDTH'] = 32 + parameters['AXI_DDR_ID_WIDTH'] = 8 + parameters['AXI_DDR_MAX_BURST_LEN'] = 256 + parameters['HBM_CH'] = 1 + parameters['HBM_ENABLE'] = 0 + parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH'] + parameters['AXI_HBM_DATA_WIDTH'] = 256 + parameters['AXI_HBM_ADDR_WIDTH'] = 32 + parameters['AXI_HBM_ID_WIDTH'] = 6 + parameters['AXI_HBM_MAX_BURST_LEN'] = 16 + # Application block configuration parameters['APP_ID'] = 0x00000000 parameters['APP_ENABLE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index e213749ba..1aab9f973 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -195,6 +195,22 @@ export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 131072 export PARAM_RX_RAM_SIZE := 131072 +# RAM configuration +export PARAM_DDR_CH := 1 +export PARAM_DDR_ENABLE := 0 +export PARAM_DDR_GROUP_SIZE := 1 +export PARAM_AXI_DDR_DATA_WIDTH := 256 +export PARAM_AXI_DDR_ADDR_WIDTH := 32 +export PARAM_AXI_DDR_ID_WIDTH := 8 +export PARAM_AXI_DDR_MAX_BURST_LEN := 256 +export PARAM_HBM_CH := 1 +export PARAM_HBM_ENABLE := 0 +export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH) +export PARAM_AXI_HBM_DATA_WIDTH := 256 +export PARAM_AXI_HBM_ADDR_WIDTH := 32 +export PARAM_AXI_HBM_ID_WIDTH := 6 +export PARAM_AXI_HBM_MAX_BURST_LEN := 16 + # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) export PARAM_APP_ENABLE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index d1179a3c0..f30627ccd 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -48,6 +48,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiSlave, AxiBus, SparseMemoryRegion from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus @@ -278,6 +279,38 @@ class TB(object): dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + # DDR + self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value + self.ddr_ram = [] + self.ddr_axi_if = [] + if hasattr(core_inst, 'ddr'): + ram = None + for i, ch in enumerate(core_inst.ddr.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 3.332, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.ddr_group_size == 0: + ram = SparseMemoryRegion() + self.ddr_ram.append(ram) + self.ddr_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + + # HBM + self.hbm_group_size = core_inst.HBM_GROUP_SIZE.value + self.hbm_ram = [] + self.hbm_axi_if = [] + if hasattr(core_inst, 'hbm'): + ram = None + for i, ch in enumerate(core_inst.hbm.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 2.222, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.hbm_group_size == 0: + ram = SparseMemoryRegion() + self.hbm_ram.append(ram) + self.hbm_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) @@ -303,6 +336,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -312,6 +348,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(1) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(1) + await FallingEdge(self.dut.rst) await Timer(100, 'ns') @@ -324,6 +363,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await self.rc.enumerate() async def _run_loopback(self): @@ -797,6 +839,22 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # RAM configuration + parameters['DDR_CH'] = 1 + parameters['DDR_ENABLE'] = 0 + parameters['DDR_GROUP_SIZE'] = 1 + parameters['AXI_DDR_DATA_WIDTH'] = 256 + parameters['AXI_DDR_ADDR_WIDTH'] = 32 + parameters['AXI_DDR_ID_WIDTH'] = 8 + parameters['AXI_DDR_MAX_BURST_LEN'] = 256 + parameters['HBM_CH'] = 1 + parameters['HBM_ENABLE'] = 0 + parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH'] + parameters['AXI_HBM_DATA_WIDTH'] = 256 + parameters['AXI_HBM_ADDR_WIDTH'] = 32 + parameters['AXI_HBM_ID_WIDTH'] = 6 + parameters['AXI_HBM_MAX_BURST_LEN'] = 16 + # Application block configuration parameters['APP_ID'] = 0x00000000 parameters['APP_ENABLE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index 5e05ebc10..9fcd90d10 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -195,6 +195,22 @@ export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 131072 export PARAM_RX_RAM_SIZE := 131072 +# RAM configuration +export PARAM_DDR_CH := 1 +export PARAM_DDR_ENABLE := 0 +export PARAM_DDR_GROUP_SIZE := 1 +export PARAM_AXI_DDR_DATA_WIDTH := 256 +export PARAM_AXI_DDR_ADDR_WIDTH := 32 +export PARAM_AXI_DDR_ID_WIDTH := 8 +export PARAM_AXI_DDR_MAX_BURST_LEN := 256 +export PARAM_HBM_CH := 1 +export PARAM_HBM_ENABLE := 0 +export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH) +export PARAM_AXI_HBM_DATA_WIDTH := 256 +export PARAM_AXI_HBM_ADDR_WIDTH := 32 +export PARAM_AXI_HBM_ID_WIDTH := 6 +export PARAM_AXI_HBM_MAX_BURST_LEN := 16 + # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) export PARAM_APP_ENABLE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index fe29d5376..95a131628 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -48,6 +48,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiSlave, AxiBus, SparseMemoryRegion from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice @@ -352,6 +353,38 @@ class TB(object): dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + # DDR + self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value + self.ddr_ram = [] + self.ddr_axi_if = [] + if hasattr(core_inst, 'ddr'): + ram = None + for i, ch in enumerate(core_inst.ddr.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 3.332, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.ddr_group_size == 0: + ram = SparseMemoryRegion() + self.ddr_ram.append(ram) + self.ddr_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + + # HBM + self.hbm_group_size = core_inst.HBM_GROUP_SIZE.value + self.hbm_ram = [] + self.hbm_axi_if = [] + if hasattr(core_inst, 'hbm'): + ram = None + for i, ch in enumerate(core_inst.hbm.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 2.222, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.hbm_group_size == 0: + ram = SparseMemoryRegion() + self.hbm_ram.append(ram) + self.hbm_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) @@ -377,6 +410,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -386,6 +422,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(1) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(1) + await FallingEdge(self.dut.rst) await Timer(100, 'ns') @@ -398,6 +437,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await self.rc.enumerate() async def _run_loopback(self): @@ -871,6 +913,22 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # RAM configuration + parameters['DDR_CH'] = 1 + parameters['DDR_ENABLE'] = 0 + parameters['DDR_GROUP_SIZE'] = 1 + parameters['AXI_DDR_DATA_WIDTH'] = 256 + parameters['AXI_DDR_ADDR_WIDTH'] = 32 + parameters['AXI_DDR_ID_WIDTH'] = 8 + parameters['AXI_DDR_MAX_BURST_LEN'] = 256 + parameters['HBM_CH'] = 1 + parameters['HBM_ENABLE'] = 0 + parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH'] + parameters['AXI_HBM_DATA_WIDTH'] = 256 + parameters['AXI_HBM_ADDR_WIDTH'] = 32 + parameters['AXI_HBM_ID_WIDTH'] = 6 + parameters['AXI_HBM_MAX_BURST_LEN'] = 16 + # Application block configuration parameters['APP_ID'] = 0x00000000 parameters['APP_ENABLE'] = 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index d81b37254..63c728a2e 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -197,6 +197,22 @@ export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 131072 export PARAM_RX_RAM_SIZE := 131072 +# RAM configuration +export PARAM_DDR_CH := 1 +export PARAM_DDR_ENABLE := 0 +export PARAM_DDR_GROUP_SIZE := 1 +export PARAM_AXI_DDR_DATA_WIDTH := 256 +export PARAM_AXI_DDR_ADDR_WIDTH := 32 +export PARAM_AXI_DDR_ID_WIDTH := 8 +export PARAM_AXI_DDR_MAX_BURST_LEN := 256 +export PARAM_HBM_CH := 1 +export PARAM_HBM_ENABLE := 0 +export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH) +export PARAM_AXI_HBM_DATA_WIDTH := 256 +export PARAM_AXI_HBM_ADDR_WIDTH := 32 +export PARAM_AXI_HBM_ID_WIDTH := 6 +export PARAM_AXI_HBM_MAX_BURST_LEN := 16 + # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) export PARAM_APP_ENABLE := 0 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index 0059be10e..04f92aa31 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -48,6 +48,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiSlave, AxiBus, SparseMemoryRegion from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice @@ -352,6 +353,38 @@ class TB(object): dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + # DDR + self.ddr_group_size = core_inst.DDR_GROUP_SIZE.value + self.ddr_ram = [] + self.ddr_axi_if = [] + if hasattr(core_inst, 'ddr'): + ram = None + for i, ch in enumerate(core_inst.ddr.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 3.332, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.ddr_group_size == 0: + ram = SparseMemoryRegion() + self.ddr_ram.append(ram) + self.ddr_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + + # HBM + self.hbm_group_size = core_inst.HBM_GROUP_SIZE.value + self.hbm_ram = [] + self.hbm_axi_if = [] + if hasattr(core_inst, 'hbm'): + ram = None + for i, ch in enumerate(core_inst.hbm.dram_if_inst.ch): + cocotb.start_soon(Clock(ch.ch_clk, 2.222, units="ns").start()) + ch.ch_rst.setimmediatevalue(0) + ch.ch_status.setimmediatevalue(1) + + if i % self.hbm_group_size == 0: + ram = SparseMemoryRegion() + self.hbm_ram.append(ram) + self.hbm_axi_if.append(AxiSlave(AxiBus.from_prefix(ch, "axi_ch"), ch.ch_clk, ch.ch_rst, target=ram)) + dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) @@ -377,6 +410,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) @@ -386,6 +422,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(1) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(1) + await FallingEdge(self.dut.rst) await Timer(100, 'ns') @@ -398,6 +437,9 @@ class TB(object): self.dut.ptp_rst.setimmediatevalue(0) + for ram in self.ddr_axi_if + self.ddr_axi_if: + ram.write_if.reset.setimmediatevalue(0) + await self.rc.enumerate() async def _run_loopback(self): @@ -926,6 +968,22 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['TX_RAM_SIZE'] = 131072 parameters['RX_RAM_SIZE'] = 131072 + # RAM configuration + parameters['DDR_CH'] = 1 + parameters['DDR_ENABLE'] = 0 + parameters['DDR_GROUP_SIZE'] = 1 + parameters['AXI_DDR_DATA_WIDTH'] = 256 + parameters['AXI_DDR_ADDR_WIDTH'] = 32 + parameters['AXI_DDR_ID_WIDTH'] = 8 + parameters['AXI_DDR_MAX_BURST_LEN'] = 256 + parameters['HBM_CH'] = 1 + parameters['HBM_ENABLE'] = 0 + parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH'] + parameters['AXI_HBM_DATA_WIDTH'] = 256 + parameters['AXI_HBM_ADDR_WIDTH'] = 32 + parameters['AXI_HBM_ID_WIDTH'] = 6 + parameters['AXI_HBM_MAX_BURST_LEN'] = 16 + # Application block configuration parameters['APP_ID'] = 0x00000000 parameters['APP_ENABLE'] = 0