From 22850707a623ba75da44bb2bce0c1b9937182e54 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Mon, 15 Oct 2018 13:51:43 -0700
Subject: [PATCH] Address is relative to beginning of region

---
 tb/pcie.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tb/pcie.py b/tb/pcie.py
index 11b610ee3..02edd5b83 100644
--- a/tb/pcie.py
+++ b/tb/pcie.py
@@ -3596,7 +3596,7 @@ class RootComplex(Switch):
         return b'\x00'*length
 
     def msi_region_write(self, addr, data):
-        assert addr == self.msi_addr
+        assert addr == 0
         assert len(data) == 4
         number = struct.unpack('<L', data)[0]
         print("MSI interrupt: 0x%08x, 0x%04x" % (addr, number))