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Address is relative to beginning of region

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This commit is contained in:
Alex Forencich 2018-10-15 13:51:43 -07:00
parent be8ef351ce
commit 22850707a6
1 changed files with 1 additions and 1 deletions
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2
tb/pcie.py
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@ -3596,7 +3596,7 @@ class RootComplex(Switch):
return b'\x00'*length
def msi_region_write(self, addr, data):
assert addr == self.msi_addr
assert addr == 0
assert len(data) == 4
number = struct.unpack('<L', data)[0]
print("MSI interrupt: 0x%08x, 0x%04x" % (addr, number))