FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity

Update readme

Browse Source
This commit is contained in:
Alex Forencich 2019-01-31 18:20:31 -08:00
parent c1fe89db62
commit 22b3d05954
1 changed files with 24 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
README.md
View File

@ -10,15 +10,16 @@ Collection of Ethernet-related components for both gigabit and 10G packet
processing (8 bit and 64 bit datapaths). Includes modules for handling processing (8 bit and 64 bit datapaths). Includes modules for handling
Ethernet frames as well as IP, UDP, and ARP and the components for Ethernet frames as well as IP, UDP, and ARP and the components for
constructing a complete UDP/IP stack. Includes MAC modules for gigabit and constructing a complete UDP/IP stack. Includes MAC modules for gigabit and
10G and a 10G PCS/PMA PHY module. Also includes full MyHDL testbench with 10G, a 10G PCS/PMA PHY module, and a 10G combination MAC/PCS/PMA module. Also
intelligent bus cosimulation endpoints. includes full MyHDL testbench with intelligent bus cosimulation endpoints.
For IP and ARP support only, use ip_complete (1G) or ip_complete_64 (10G). For IP and ARP support only, use ip_complete (1G) or ip_complete_64 (10G).
For UDP, IP, and ARP support, use udp_complete (1G) or udp_complete_64 (10G). For UDP, IP, and ARP support, use udp_complete (1G) or udp_complete_64 (10G).
Top level gigabit and 10G MAC modules are eth_mac_*, with various interfaces Top level gigabit and 10G MAC modules are eth_mac_*, with various interfaces
and with/without FIFOs. Top level 10G PCS/PMA PHY module is eth_phy_10g. and with/without FIFOs. Top level 10G PCS/PMA PHY module is eth_phy_10g. Top
level 10G MAC/PCS/PMA combination module is eth_mac_phy_10g.
## Documentation ## Documentation
@ -155,6 +156,22 @@ bits.
10G Ethernet MAC with XGMII interface and FIFOs. Datapath selectable between 10G Ethernet MAC with XGMII interface and FIFOs. Datapath selectable between
32 and 64 bits. 32 and 64 bits.
### eth_mac_phy_10g module
10G Ethernet MAC/PHY combination module with SERDES interface.
### eth_mac_phy_10g_fifo module
10G Ethernet MAC/PHY combination module with SERDES interface and FIFOs.
### eth_mac_phy_10g_rx module
10G Ethernet MAC/PHY combination module with SERDES interface, RX path.
### eth_mac_phy_10g_tx module
10G Ethernet MAC/PHY combination module with SERDES interface, TX path.
### eth_mux module ### eth_mux module
Ethernet frame muliplexer with parametrizable data width and port count. Ethernet frame muliplexer with parametrizable data width and port count.
@ -370,6 +387,10 @@ and data lines.
rtl/eth_mac_1g_rgmii_fifo.v : Tri-mode Ethernet RGMII MAC with FIFO rtl/eth_mac_1g_rgmii_fifo.v : Tri-mode Ethernet RGMII MAC with FIFO
rtl/eth_mac_10g.v : 10G Etherent XGMII MAC rtl/eth_mac_10g.v : 10G Etherent XGMII MAC
rtl/eth_mac_10g_fifo.v : 10G Etherent XGMII MAC with FIFO rtl/eth_mac_10g_fifo.v : 10G Etherent XGMII MAC with FIFO
rtl/eth_mac_phy_10g.v : 10G Etherent XGMII MAC/PHY
rtl/eth_mac_phy_10g_fifo.v : 10G Etherent XGMII MAC/PHY with FIFO
rtl/eth_mac_phy_10g_rx.v : 10G Etherent XGMII MAC/PHY RX with FIFO
rtl/eth_mac_phy_10g_tx.v : 10G Etherent XGMII MAC/PHY TX with FIFO
rtl/eth_mux.v : Ethernet frame multiplexer rtl/eth_mux.v : Ethernet frame multiplexer
rtl/gmii_phy_if.v : GMII PHY interface rtl/gmii_phy_if.v : GMII PHY interface
rtl/iddr.v : Generic DDR input register rtl/iddr.v : Generic DDR input register