From 2306e515223729819f1105099b46c66de5c3f7f8 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 22 Jun 2023 18:08:44 -0700 Subject: [PATCH] Example design parameter clean-up Signed-off-by: Alex Forencich --- .../fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/AU200/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/AU250/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/AU280/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/AU50/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - .../ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - .../ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/VCU108/fpga_axi/rtl/fpga.v | 59 ++++---- example/VCU108/fpga_axi/rtl/fpga_core.v | 128 +++++++++--------- .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/VCU118/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - .../VCU1525/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/ZCU106/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - example/fb2CG/fpga_axi/tb/fpga_core/Makefile | 1 - .../fpga_axi/tb/fpga_core/test_fpga_core.py | 1 - 25 files changed, 100 insertions(+), 110 deletions(-) diff --git a/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile +++ b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py index 80b4057a8..ee8e602bc 100644 --- a/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -396,7 +396,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/AU200/fpga_axi/tb/fpga_core/Makefile b/example/AU200/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/AU200/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU200/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py index f662d6cf6..8e67c0332 100644 --- a/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -398,7 +398,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/AU250/fpga_axi/tb/fpga_core/Makefile b/example/AU250/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/AU250/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU250/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py index f662d6cf6..8e67c0332 100644 --- a/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -398,7 +398,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/AU280/fpga_axi/tb/fpga_core/Makefile b/example/AU280/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/AU280/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU280/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py index 80b4057a8..ee8e602bc 100644 --- a/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -396,7 +396,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/AU50/fpga_axi/tb/fpga_core/Makefile b/example/AU50/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/AU50/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU50/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py index 80b4057a8..ee8e602bc 100644 --- a/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -396,7 +396,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile index 83abb0568..ebdba6e8f 100644 --- a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile +++ b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60 export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75 export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85 export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33 -export PARAM_RQ_SEQ_NUM_WIDTH := 4 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py index 942cda074..8a8449e2c 100644 --- a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -370,7 +370,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 85 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 - parameters['RQ_SEQ_NUM_WIDTH'] = 4 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile index 8df1050af..09f0cec0e 100644 --- a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile +++ b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py index 0d0d0c5b1..9fbce2122 100644 --- a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -396,7 +396,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/VCU108/fpga_axi/rtl/fpga.v b/example/VCU108/fpga_axi/rtl/fpga.v index 93ddb1620..125e8a0b6 100644 --- a/example/VCU108/fpga_axi/rtl/fpga.v +++ b/example/VCU108/fpga_axi/rtl/fpga.v @@ -57,6 +57,10 @@ module fpga ( parameter AXIS_PCIE_DATA_WIDTH = 256; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = 75; +parameter AXIS_PCIE_RQ_USER_WIDTH = 60; +parameter AXIS_PCIE_CQ_USER_WIDTH = 85; +parameter AXIS_PCIE_CC_USER_WIDTH = 33; // Clock and reset wire pcie_user_clk; @@ -107,33 +111,33 @@ ibufds_gte3_pcie_mgt_refclk_inst ( .ODIV2 (pcie_sys_clk) ); -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [59:0] axis_rq_tuser; -wire axis_rq_tvalid; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; +wire axis_rq_tlast; +wire axis_rq_tready; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; +wire axis_rq_tvalid; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [74:0] axis_rc_tuser; -wire axis_rc_tvalid; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; +wire axis_rc_tlast; +wire axis_rc_tready; +wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; +wire axis_rc_tvalid; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [84:0] axis_cq_tuser; -wire axis_cq_tvalid; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; +wire axis_cq_tlast; +wire axis_cq_tready; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; +wire axis_cq_tvalid; -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [32:0] axis_cc_tuser; -wire axis_cc_tvalid; +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; +wire axis_cc_tlast; +wire axis_cc_tready; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; +wire axis_cc_tvalid; // ila_0 rq_ila ( // .clk(pcie_user_clk), @@ -357,7 +361,12 @@ pcie3_ultrascale_inst ( ); fpga_core #( - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH) + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH) ) core_inst ( /* diff --git a/example/VCU108/fpga_axi/rtl/fpga_core.v b/example/VCU108/fpga_axi/rtl/fpga_core.v index c5819b9d5..742db0bc5 100644 --- a/example/VCU108/fpga_axi/rtl/fpga_core.v +++ b/example/VCU108/fpga_axi/rtl/fpga_core.v @@ -34,89 +34,93 @@ THE SOFTWARE. module fpga_core # ( parameter AXIS_PCIE_DATA_WIDTH = 256, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + parameter AXIS_PCIE_RC_USER_WIDTH = 75, + parameter AXIS_PCIE_RQ_USER_WIDTH = 60, + parameter AXIS_PCIE_CQ_USER_WIDTH = 85, + parameter AXIS_PCIE_CC_USER_WIDTH = 33 ) ( /* * Clock: 250 MHz * Synchronous reset */ - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * GPIO */ - input wire btnu, - input wire btnl, - input wire btnd, - input wire btnr, - input wire btnc, - input wire [3:0] sw, - output wire [7:0] led, + input wire btnu, + input wire btnl, + input wire btnd, + input wire btnr, + input wire btnc, + input wire [3:0] sw, + output wire [7:0] led, /* * PCIe */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [59:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tlast, + input wire m_axis_rq_tready, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, + output wire m_axis_rq_tvalid, - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [74:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tlast, + output wire s_axis_rc_tready, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, + input wire s_axis_rc_tvalid, - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [84:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tlast, + output wire s_axis_cq_tready, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, + input wire s_axis_cq_tvalid, - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [32:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tlast, + input wire m_axis_cc_tready, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, + output wire m_axis_cc_tvalid, - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, - output wire [18:0] cfg_mgmt_addr, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, + output wire [18:0] cfg_mgmt_addr, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + input wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, - input wire [3:0] cfg_interrupt_msi_enable, - input wire [7:0] cfg_interrupt_msi_vf_enable, - input wire [11:0] cfg_interrupt_msi_mmenable, - input wire cfg_interrupt_msi_mask_update, - input wire [31:0] cfg_interrupt_msi_data, - output wire [3:0] cfg_interrupt_msi_select, - output wire [31:0] cfg_interrupt_msi_int, - output wire [31:0] cfg_interrupt_msi_pending_status, - output wire cfg_interrupt_msi_pending_status_data_enable, - output wire [3:0] cfg_interrupt_msi_pending_status_function_num, - input wire cfg_interrupt_msi_sent, - input wire cfg_interrupt_msi_fail, - output wire [2:0] cfg_interrupt_msi_attr, - output wire cfg_interrupt_msi_tph_present, - output wire [1:0] cfg_interrupt_msi_tph_type, - output wire [8:0] cfg_interrupt_msi_tph_st_tag, - output wire [3:0] cfg_interrupt_msi_function_number, + input wire [3:0] cfg_interrupt_msi_enable, + input wire [7:0] cfg_interrupt_msi_vf_enable, + input wire [11:0] cfg_interrupt_msi_mmenable, + input wire cfg_interrupt_msi_mask_update, + input wire [31:0] cfg_interrupt_msi_data, + output wire [3:0] cfg_interrupt_msi_select, + output wire [31:0] cfg_interrupt_msi_int, + output wire [31:0] cfg_interrupt_msi_pending_status, + output wire cfg_interrupt_msi_pending_status_data_enable, + output wire [3:0] cfg_interrupt_msi_pending_status_function_num, + input wire cfg_interrupt_msi_sent, + input wire cfg_interrupt_msi_fail, + output wire [2:0] cfg_interrupt_msi_attr, + output wire cfg_interrupt_msi_tph_present, + output wire [1:0] cfg_interrupt_msi_tph_type, + output wire [8:0] cfg_interrupt_msi_tph_st_tag, + output wire [3:0] cfg_interrupt_msi_function_number, - output wire status_error_cor, - output wire status_error_uncor + output wire status_error_cor, + output wire status_error_uncor ); parameter PCIE_ADDR_WIDTH = 64; diff --git a/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py index b292bc974..562568c0b 100644 --- a/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -377,7 +377,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 85 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 - parameters['RQ_SEQ_NUM_WIDTH'] = 4 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/VCU118/fpga_axi/tb/fpga_core/Makefile b/example/VCU118/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/VCU118/fpga_axi/tb/fpga_core/Makefile +++ b/example/VCU118/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU118/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga_axi/tb/fpga_core/test_fpga_core.py index 74ef95548..a2de697b6 100644 --- a/example/VCU118/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/VCU118/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -403,7 +403,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/VCU1525/fpga_axi/tb/fpga_core/Makefile b/example/VCU1525/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/VCU1525/fpga_axi/tb/fpga_core/Makefile +++ b/example/VCU1525/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py index f662d6cf6..8e67c0332 100644 --- a/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -398,7 +398,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/ZCU106/fpga_axi/tb/fpga_core/Makefile b/example/ZCU106/fpga_axi/tb/fpga_core/Makefile index 6d78bf572..55ed40bff 100644 --- a/example/ZCU106/fpga_axi/tb/fpga_core/Makefile +++ b/example/ZCU106/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py index e27299f62..3e1712a8e 100644 --- a/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -403,7 +403,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/example/fb2CG/fpga_axi/tb/fpga_core/Makefile b/example/fb2CG/fpga_axi/tb/fpga_core/Makefile index e730af529..b09d0d3bf 100644 --- a/example/fb2CG/fpga_axi/tb/fpga_core/Makefile +++ b/example/fb2CG/fpga_axi/tb/fpga_core/Makefile @@ -54,7 +54,6 @@ export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_ export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py index 80b4057a8..ee8e602bc 100644 --- a/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -396,7 +396,6 @@ def test_fpga_core(request): parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161 parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183 parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81 - parameters['RQ_SEQ_NUM_WIDTH'] = 6 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}