diff --git a/fpga/common/rtl/interface.v b/fpga/common/rtl/interface.v
index 25a01d77f..38945637a 100644
--- a/fpga/common/rtl/interface.v
+++ b/fpga/common/rtl/interface.v
@@ -50,6 +50,8 @@ module interface #
     parameter PCIE_DMA_TAG_WIDTH = 8,
     // Request tag field width
     parameter REQ_TAG_WIDTH = 8,
+    // Descriptor request tag field width
+    parameter DESC_REQ_TAG_WIDTH = 8,
     // Number of outstanding operations (event queue)
     parameter EVENT_QUEUE_OP_TABLE_SIZE = 16,
     // Number of outstanding operations (transmit queue)
@@ -305,6 +307,11 @@ parameter EVENT_TYPE_WIDTH = 16;
 
 parameter PCIE_DMA_TAG_WIDTH_INT = PCIE_DMA_TAG_WIDTH - $clog2(PORTS+1);
 
+parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH;
+parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH;
+
+parameter PORT_DESC_REQ_TAG_WIDTH = DESC_REQ_TAG_WIDTH - $clog2(PORTS+1);
+
 // AXI lite connections
 wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
 wire [2:0]                 axil_ctrl_awprot;
@@ -447,52 +454,62 @@ wire [PORTS-1:0]                 axil_port_rvalid;
 wire [PORTS-1:0]                 axil_port_rready;
 
 // AXI connections
-wire [AXI_ID_WIDTH-1:0]    axi_event_awid;
-wire [AXI_ADDR_WIDTH-1:0]  axi_event_awaddr;
-wire [7:0]                 axi_event_awlen;
-wire [2:0]                 axi_event_awsize;
-wire [1:0]                 axi_event_awburst;
-wire                       axi_event_awlock;
-wire [3:0]                 axi_event_awcache;
-wire [2:0]                 axi_event_awprot;
-wire                       axi_event_awvalid;
-wire                       axi_event_awready;
-wire [AXI_DATA_WIDTH-1:0]  axi_event_wdata;
-wire [AXI_STRB_WIDTH-1:0]  axi_event_wstrb;
-wire                       axi_event_wlast;
-wire                       axi_event_wvalid;
-wire                       axi_event_wready;
-wire [AXI_ID_WIDTH-1:0]    axi_event_bid;
-wire [1:0]                 axi_event_bresp;
-wire                       axi_event_bvalid;
-wire                       axi_event_bready;
-wire [AXI_ID_WIDTH-1:0]    axi_event_arid;
-wire [AXI_ADDR_WIDTH-1:0]  axi_event_araddr;
-wire [7:0]                 axi_event_arlen;
-wire [2:0]                 axi_event_arsize;
-wire [1:0]                 axi_event_arburst;
-wire                       axi_event_arlock;
-wire [3:0]                 axi_event_arcache;
-wire [2:0]                 axi_event_arprot;
-wire                       axi_event_arvalid;
-wire                       axi_event_arready;
-wire [AXI_ID_WIDTH-1:0]    axi_event_rid;
-wire [AXI_DATA_WIDTH-1:0]  axi_event_rdata;
-wire [1:0]                 axi_event_rresp;
-wire                       axi_event_rlast;
-wire                       axi_event_rvalid;
-wire                       axi_event_rready;
+wire [AXI_ID_WIDTH-1:0]    axi_desc_awid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_desc_awaddr;
+wire [7:0]                 axi_desc_awlen;
+wire [2:0]                 axi_desc_awsize;
+wire [1:0]                 axi_desc_awburst;
+wire                       axi_desc_awlock;
+wire [3:0]                 axi_desc_awcache;
+wire [2:0]                 axi_desc_awprot;
+wire                       axi_desc_awvalid;
+wire                       axi_desc_awready;
+wire [AXI_DATA_WIDTH-1:0]  axi_desc_wdata;
+wire [AXI_STRB_WIDTH-1:0]  axi_desc_wstrb;
+wire                       axi_desc_wlast;
+wire                       axi_desc_wvalid;
+wire                       axi_desc_wready;
+wire [AXI_ID_WIDTH-1:0]    axi_desc_bid;
+wire [1:0]                 axi_desc_bresp;
+wire                       axi_desc_bvalid;
+wire                       axi_desc_bready;
+wire [AXI_ID_WIDTH-1:0]    axi_desc_arid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_desc_araddr;
+wire [7:0]                 axi_desc_arlen;
+wire [2:0]                 axi_desc_arsize;
+wire [1:0]                 axi_desc_arburst;
+wire                       axi_desc_arlock;
+wire [3:0]                 axi_desc_arcache;
+wire [2:0]                 axi_desc_arprot;
+wire                       axi_desc_arvalid;
+wire                       axi_desc_arready;
+wire [AXI_ID_WIDTH-1:0]    axi_desc_rid;
+wire [AXI_DATA_WIDTH-1:0]  axi_desc_rdata;
+wire [1:0]                 axi_desc_rresp;
+wire                       axi_desc_rlast;
+wire                       axi_desc_rvalid;
+wire                       axi_desc_rready;
 
 // PCIe DMA
-wire [PCIE_ADDR_WIDTH-1:0]        event_pcie_axi_dma_write_desc_pcie_addr;
-wire [AXI_ADDR_WIDTH-1:0]         event_pcie_axi_dma_write_desc_axi_addr;
-wire [PCIE_DMA_LEN_WIDTH-1:0]     event_pcie_axi_dma_write_desc_len;
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] event_pcie_axi_dma_write_desc_tag;
-wire                              event_pcie_axi_dma_write_desc_valid;
-wire                              event_pcie_axi_dma_write_desc_ready;
+wire [PCIE_ADDR_WIDTH-1:0]        desc_pcie_axi_dma_write_desc_pcie_addr;
+wire [AXI_ADDR_WIDTH-1:0]         desc_pcie_axi_dma_write_desc_axi_addr;
+wire [PCIE_DMA_LEN_WIDTH-1:0]     desc_pcie_axi_dma_write_desc_len;
+wire [PCIE_DMA_TAG_WIDTH_INT-1:0] desc_pcie_axi_dma_write_desc_tag;
+wire                              desc_pcie_axi_dma_write_desc_valid;
+wire                              desc_pcie_axi_dma_write_desc_ready;
 
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] event_pcie_axi_dma_write_desc_status_tag;
-wire                              event_pcie_axi_dma_write_desc_status_valid;
+wire [PCIE_DMA_TAG_WIDTH_INT-1:0] desc_pcie_axi_dma_write_desc_status_tag;
+wire                              desc_pcie_axi_dma_write_desc_status_valid;
+
+wire [PCIE_ADDR_WIDTH-1:0]        cpl_pcie_axi_dma_write_desc_pcie_addr;
+wire [AXI_ADDR_WIDTH-1:0]         cpl_pcie_axi_dma_write_desc_axi_addr;
+wire [PCIE_DMA_LEN_WIDTH-1:0]     cpl_pcie_axi_dma_write_desc_len;
+wire [PCIE_DMA_TAG_WIDTH_INT-1:0] cpl_pcie_axi_dma_write_desc_tag;
+wire                              cpl_pcie_axi_dma_write_desc_valid;
+wire                              cpl_pcie_axi_dma_write_desc_ready;
+
+wire [PCIE_DMA_TAG_WIDTH_INT-1:0] cpl_pcie_axi_dma_write_desc_status_tag;
+wire                              cpl_pcie_axi_dma_write_desc_status_valid;
 
 wire [PORTS*PCIE_ADDR_WIDTH-1:0]        port_pcie_axi_dma_read_desc_pcie_addr;
 wire [PORTS*AXI_ADDR_WIDTH-1:0]         port_pcie_axi_dma_read_desc_axi_addr;
@@ -555,26 +572,6 @@ wire                                tx_desc_dequeue_commit_ready;
 wire [TX_QUEUE_INDEX_WIDTH-1:0]     tx_doorbell_queue;
 wire                                tx_doorbell_valid;
 
-wire [PORTS*TX_QUEUE_INDEX_WIDTH-1:0]     tx_port_desc_dequeue_req_queue;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      tx_port_desc_dequeue_req_tag;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_req_valid;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_req_ready;
-
-wire [PORTS*TX_QUEUE_INDEX_WIDTH-1:0]     tx_port_desc_dequeue_resp_queue;
-wire [PORTS*QUEUE_PTR_WIDTH-1:0]          tx_port_desc_dequeue_resp_ptr;
-wire [PORTS*PCIE_ADDR_WIDTH-1:0]          tx_port_desc_dequeue_resp_addr;
-wire [PORTS*TX_CPL_QUEUE_INDEX_WIDTH-1:0] tx_port_desc_dequeue_resp_cpl;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      tx_port_desc_dequeue_resp_tag;
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       tx_port_desc_dequeue_resp_op_tag;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_resp_empty;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_resp_error;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_resp_valid;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_resp_ready;
-
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       tx_port_desc_dequeue_commit_op_tag;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_commit_valid;
-wire [PORTS-1:0]                          tx_port_desc_dequeue_commit_ready;
-
 wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0] tx_cpl_enqueue_req_queue;
 wire [QUEUE_REQ_TAG_WIDTH-1:0]      tx_cpl_enqueue_req_tag;
 wire                                tx_cpl_enqueue_req_valid;
@@ -592,23 +589,6 @@ wire [QUEUE_OP_TAG_WIDTH-1:0]       tx_cpl_enqueue_commit_op_tag;
 wire                                tx_cpl_enqueue_commit_valid;
 wire                                tx_cpl_enqueue_commit_ready;
 
-wire [PORTS*TX_CPL_QUEUE_INDEX_WIDTH-1:0] tx_port_cpl_enqueue_req_queue;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      tx_port_cpl_enqueue_req_tag;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_req_valid;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_req_ready;
-
-wire [PORTS*PCIE_ADDR_WIDTH-1:0]          tx_port_cpl_enqueue_resp_addr;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      tx_port_cpl_enqueue_resp_tag;
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       tx_port_cpl_enqueue_resp_op_tag;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_resp_full;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_resp_error;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_resp_valid;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_resp_ready;
-
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       tx_port_cpl_enqueue_commit_op_tag;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_commit_valid;
-wire [PORTS-1:0]                          tx_port_cpl_enqueue_commit_ready;
-
 wire [TX_QUEUE_INDEX_WIDTH-1:0]     rx_desc_dequeue_req_queue;
 wire [QUEUE_REQ_TAG_WIDTH-1:0]      rx_desc_dequeue_req_tag;
 wire                                rx_desc_dequeue_req_valid;
@@ -629,26 +609,6 @@ wire [QUEUE_OP_TAG_WIDTH-1:0]       rx_desc_dequeue_commit_op_tag;
 wire                                rx_desc_dequeue_commit_valid;
 wire                                rx_desc_dequeue_commit_ready;
 
-wire [PORTS*RX_QUEUE_INDEX_WIDTH-1:0]     rx_port_desc_dequeue_req_queue;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      rx_port_desc_dequeue_req_tag;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_req_valid;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_req_ready;
-
-wire [PORTS*RX_QUEUE_INDEX_WIDTH-1:0]     rx_port_desc_dequeue_resp_queue;
-wire [PORTS*QUEUE_PTR_WIDTH-1:0]          rx_port_desc_dequeue_resp_ptr;
-wire [PORTS*PCIE_ADDR_WIDTH-1:0]          rx_port_desc_dequeue_resp_addr;
-wire [PORTS*RX_CPL_QUEUE_INDEX_WIDTH-1:0] rx_port_desc_dequeue_resp_cpl;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      rx_port_desc_dequeue_resp_tag;
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       rx_port_desc_dequeue_resp_op_tag;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_resp_empty;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_resp_error;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_resp_valid;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_resp_ready;
-
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       rx_port_desc_dequeue_commit_op_tag;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_commit_valid;
-wire [PORTS-1:0]                          rx_port_desc_dequeue_commit_ready;
-
 wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0] rx_cpl_enqueue_req_queue;
 wire [QUEUE_REQ_TAG_WIDTH-1:0]      rx_cpl_enqueue_req_tag;
 wire                                rx_cpl_enqueue_req_valid;
@@ -666,22 +626,86 @@ wire [QUEUE_OP_TAG_WIDTH-1:0]       rx_cpl_enqueue_commit_op_tag;
 wire                                rx_cpl_enqueue_commit_valid;
 wire                                rx_cpl_enqueue_commit_ready;
 
-wire [PORTS*RX_CPL_QUEUE_INDEX_WIDTH-1:0] rx_port_cpl_enqueue_req_queue;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      rx_port_cpl_enqueue_req_tag;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_req_valid;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_req_ready;
+// descriptor and completion
+wire [0:0]                               desc_req_sel;
+wire [QUEUE_INDEX_WIDTH-1:0]             desc_req_queue;
+wire [DESC_REQ_TAG_WIDTH-1:0]            desc_req_tag;
+wire                                     desc_req_valid;
+wire                                     desc_req_ready;
 
-wire [PORTS*PCIE_ADDR_WIDTH-1:0]          rx_port_cpl_enqueue_resp_addr;
-wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0]      rx_port_cpl_enqueue_resp_tag;
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       rx_port_cpl_enqueue_resp_op_tag;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_resp_full;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_resp_error;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_resp_valid;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_resp_ready;
+wire [QUEUE_INDEX_WIDTH-1:0]             desc_req_status_queue;
+wire [QUEUE_PTR_WIDTH-1:0]               desc_req_status_ptr;
+wire [CPL_QUEUE_INDEX_WIDTH-1:0]         desc_req_status_cpl;
+wire [DESC_REQ_TAG_WIDTH-1:0]            desc_req_status_tag;
+wire                                     desc_req_status_empty;
+wire                                     desc_req_status_error;
+wire                                     desc_req_status_valid;
 
-wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0]       rx_port_cpl_enqueue_commit_op_tag;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_commit_valid;
-wire [PORTS-1:0]                          rx_port_cpl_enqueue_commit_ready;
+wire [AXIS_DATA_WIDTH-1:0]               desc_tdata;
+wire [AXIS_KEEP_WIDTH-1:0]               desc_tkeep;
+wire                                     desc_tvalid;
+wire                                     desc_tready;
+wire                                     desc_tlast;
+wire [DESC_REQ_TAG_WIDTH-1:0]            desc_tid;
+wire                                     desc_tuser;
+
+wire [PORTS*1-1:0]                       port_desc_req_sel;
+wire [PORTS*QUEUE_INDEX_WIDTH-1:0]       port_desc_req_queue;
+wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_desc_req_tag;
+wire [PORTS-1:0]                         port_desc_req_valid;
+wire [PORTS-1:0]                         port_desc_req_ready;
+
+wire [PORTS*QUEUE_INDEX_WIDTH-1:0]       port_desc_req_status_queue;
+wire [PORTS*QUEUE_PTR_WIDTH-1:0]         port_desc_req_status_ptr;
+wire [PORTS*CPL_QUEUE_INDEX_WIDTH-1:0]   port_desc_req_status_cpl;
+wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_desc_req_status_tag;
+wire [PORTS-1:0]                         port_desc_req_status_empty;
+wire [PORTS-1:0]                         port_desc_req_status_error;
+wire [PORTS-1:0]                         port_desc_req_status_valid;
+
+wire [PORTS*AXIS_DATA_WIDTH-1:0]         port_desc_tdata;
+wire [PORTS*AXIS_KEEP_WIDTH-1:0]         port_desc_tkeep;
+wire [PORTS-1:0]                         port_desc_tvalid;
+wire [PORTS-1:0]                         port_desc_tready;
+wire [PORTS-1:0]                         port_desc_tlast;
+wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_desc_tid;
+wire [PORTS-1:0]                         port_desc_tuser;
+
+wire [1:0]                               cpl_req_sel;
+wire [QUEUE_INDEX_WIDTH-1:0]             cpl_req_queue;
+wire [DESC_REQ_TAG_WIDTH-1:0]            cpl_req_tag;
+wire [CPL_SIZE*8-1:0]                    cpl_req_data;
+wire                                     cpl_req_valid;
+wire                                     cpl_req_ready;
+
+wire [DESC_REQ_TAG_WIDTH-1:0]            cpl_req_status_tag;
+wire                                     cpl_req_status_full;
+wire                                     cpl_req_status_error;
+wire                                     cpl_req_status_valid;
+
+wire [1:0]                               event_cpl_req_sel = 2'd2;
+wire [QUEUE_INDEX_WIDTH-1:0]             event_cpl_req_queue;
+wire [PORT_DESC_REQ_TAG_WIDTH-1:0]       event_cpl_req_tag;
+wire [CPL_SIZE*8-1:0]                    event_cpl_req_data;
+wire                                     event_cpl_req_valid;
+wire                                     event_cpl_req_ready;
+
+wire [PORT_DESC_REQ_TAG_WIDTH-1:0]       event_cpl_req_status_tag;
+wire                                     event_cpl_req_status_full;
+wire                                     event_cpl_req_status_error;
+wire                                     event_cpl_req_status_valid;
+
+wire [PORTS*2-1:0]                       port_cpl_req_sel;
+wire [PORTS*QUEUE_INDEX_WIDTH-1:0]       port_cpl_req_queue;
+wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_cpl_req_tag;
+wire [PORTS*CPL_SIZE*8-1:0]              port_cpl_req_data;
+wire [PORTS-1:0]                         port_cpl_req_valid;
+wire [PORTS-1:0]                         port_cpl_req_ready;
+
+wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_cpl_req_status_tag;
+wire [PORTS-1:0]                         port_cpl_req_status_full;
+wire [PORTS-1:0]                         port_cpl_req_status_error;
+wire [PORTS-1:0]                         port_cpl_req_status_valid;
 
 // events
 wire [EVENT_QUEUE_INDEX_WIDTH-1:0]  axis_event_queue;
@@ -942,107 +966,6 @@ event_queue_manager_inst (
     .enable(1'b1)
 );
 
-if (PORTS > 1) begin
-
-    queue_op_mux #(
-        .PORTS(PORTS),
-        .ADDR_WIDTH(PCIE_ADDR_WIDTH),
-        .S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
-        .M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
-        .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
-        .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
-        .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
-        .CPL_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
-        .ARB_TYPE("ROUND_ROBIN"),
-        .LSB_PRIORITY("HIGH")
-    )
-    tx_queue_op_mux_inst (
-        .clk(clk),
-        .rst(rst),
-
-        /*
-         * Dequeue request output
-         */
-        .m_axis_dequeue_req_queue(tx_desc_dequeue_req_queue),
-        .m_axis_dequeue_req_tag(tx_desc_dequeue_req_tag),
-        .m_axis_dequeue_req_valid(tx_desc_dequeue_req_valid),
-        .m_axis_dequeue_req_ready(tx_desc_dequeue_req_ready),
-
-        /*
-         * Dequeue response input
-         */
-        .s_axis_enqueue_resp_queue(tx_desc_dequeue_resp_queue),
-        .s_axis_dequeue_resp_ptr(tx_desc_dequeue_resp_ptr),
-        .s_axis_dequeue_resp_addr(tx_desc_dequeue_resp_addr),
-        .s_axis_dequeue_resp_cpl(tx_desc_dequeue_resp_cpl),
-        .s_axis_dequeue_resp_tag(tx_desc_dequeue_resp_tag),
-        .s_axis_dequeue_resp_op_tag(tx_desc_dequeue_resp_op_tag),
-        .s_axis_dequeue_resp_empty(tx_desc_dequeue_resp_empty),
-        .s_axis_dequeue_resp_error(tx_desc_dequeue_resp_error),
-        .s_axis_dequeue_resp_valid(tx_desc_dequeue_resp_valid),
-        .s_axis_dequeue_resp_ready(tx_desc_dequeue_resp_ready),
-
-        /*
-         * Dequeue commit output
-         */
-        .m_axis_dequeue_commit_op_tag(tx_desc_dequeue_commit_op_tag),
-        .m_axis_dequeue_commit_valid(tx_desc_dequeue_commit_valid),
-        .m_axis_dequeue_commit_ready(tx_desc_dequeue_commit_ready),
-
-        /*
-         * Dequeue request input
-         */
-        .s_axis_dequeue_req_queue(tx_port_desc_dequeue_req_queue),
-        .s_axis_dequeue_req_tag(tx_port_desc_dequeue_req_tag),
-        .s_axis_dequeue_req_valid(tx_port_desc_dequeue_req_valid),
-        .s_axis_dequeue_req_ready(tx_port_desc_dequeue_req_ready),
-
-        /*
-         * Dequeue response output
-         */
-        .m_axis_enqueue_resp_queue(tx_port_desc_dequeue_resp_queue),
-        .m_axis_dequeue_resp_ptr(tx_port_desc_dequeue_resp_ptr),
-        .m_axis_dequeue_resp_addr(tx_port_desc_dequeue_resp_addr),
-        .m_axis_dequeue_resp_cpl(tx_port_desc_dequeue_resp_cpl),
-        .m_axis_dequeue_resp_tag(tx_port_desc_dequeue_resp_tag),
-        .m_axis_dequeue_resp_op_tag(tx_port_desc_dequeue_resp_op_tag),
-        .m_axis_dequeue_resp_empty(tx_port_desc_dequeue_resp_empty),
-        .m_axis_dequeue_resp_error(tx_port_desc_dequeue_resp_error),
-        .m_axis_dequeue_resp_valid(tx_port_desc_dequeue_resp_valid),
-        .m_axis_dequeue_resp_ready(tx_port_desc_dequeue_resp_ready),
-
-        /*
-         * Dequeue commit input
-         */
-        .s_axis_dequeue_commit_op_tag(tx_port_desc_dequeue_commit_op_tag),
-        .s_axis_dequeue_commit_valid(tx_port_desc_dequeue_commit_valid),
-        .s_axis_dequeue_commit_ready(tx_port_desc_dequeue_commit_ready)
-    );
-
-end else begin
-
-    assign tx_desc_dequeue_req_queue = tx_port_desc_dequeue_req_queue;
-    assign tx_desc_dequeue_req_tag = tx_port_desc_dequeue_req_tag;
-    assign tx_desc_dequeue_req_valid = tx_port_desc_dequeue_req_valid;
-    assign tx_port_desc_dequeue_req_ready = tx_desc_dequeue_req_ready;
-
-    assign tx_port_desc_dequeue_resp_queue = tx_desc_dequeue_resp_queue;
-    assign tx_port_desc_dequeue_resp_ptr = tx_desc_dequeue_resp_ptr;
-    assign tx_port_desc_dequeue_resp_addr = tx_desc_dequeue_resp_addr;
-    assign tx_port_desc_dequeue_resp_cpl = tx_desc_dequeue_resp_cpl;
-    assign tx_port_desc_dequeue_resp_tag = tx_desc_dequeue_resp_tag;
-    assign tx_port_desc_dequeue_resp_op_tag = tx_desc_dequeue_resp_op_tag;
-    assign tx_port_desc_dequeue_resp_empty = tx_desc_dequeue_resp_empty;
-    assign tx_port_desc_dequeue_resp_error = tx_desc_dequeue_resp_error;
-    assign tx_port_desc_dequeue_resp_valid = tx_desc_dequeue_resp_valid;
-    assign tx_desc_dequeue_resp_ready = tx_port_desc_dequeue_resp_ready;
-
-    assign tx_desc_dequeue_commit_op_tag = tx_port_desc_dequeue_commit_op_tag;
-    assign tx_desc_dequeue_commit_valid = tx_port_desc_dequeue_commit_valid;
-    assign tx_port_desc_dequeue_commit_ready = tx_desc_dequeue_commit_ready;
-
-end
-
 queue_manager #(
     .ADDR_WIDTH(PCIE_ADDR_WIDTH),
     .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
@@ -1126,104 +1049,6 @@ tx_queue_manager_inst (
     .enable(1'b1)
 );
 
-if (PORTS > 1) begin
-
-    queue_op_mux #(
-        .PORTS(PORTS),
-        .ADDR_WIDTH(PCIE_ADDR_WIDTH),
-        .S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
-        .M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
-        .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
-        .QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
-        .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
-        .CPL_INDEX_WIDTH(0),
-        .ARB_TYPE("ROUND_ROBIN"),
-        .LSB_PRIORITY("HIGH")
-    )
-    tx_cpl_queue_op_mux_inst (
-        .clk(clk),
-        .rst(rst),
-
-        /*
-         * Dequeue request output
-         */
-        .m_axis_dequeue_req_queue(tx_cpl_enqueue_req_queue),
-        .m_axis_dequeue_req_tag(tx_cpl_enqueue_req_tag),
-        .m_axis_dequeue_req_valid(tx_cpl_enqueue_req_valid),
-        .m_axis_dequeue_req_ready(tx_cpl_enqueue_req_ready),
-
-        /*
-         * Dequeue response input
-         */
-        .s_axis_enqueue_resp_queue(0),
-        .s_axis_dequeue_resp_ptr(0),
-        .s_axis_dequeue_resp_addr(tx_cpl_enqueue_resp_addr),
-        .s_axis_dequeue_resp_cpl(0),
-        .s_axis_dequeue_resp_tag(tx_cpl_enqueue_resp_tag),
-        .s_axis_dequeue_resp_op_tag(tx_cpl_enqueue_resp_op_tag),
-        .s_axis_dequeue_resp_empty(tx_cpl_enqueue_resp_full),
-        .s_axis_dequeue_resp_error(tx_cpl_enqueue_resp_error),
-        .s_axis_dequeue_resp_valid(tx_cpl_enqueue_resp_valid),
-        .s_axis_dequeue_resp_ready(tx_cpl_enqueue_resp_ready),
-
-        /*
-         * Dequeue commit output
-         */
-        .m_axis_dequeue_commit_op_tag(tx_cpl_enqueue_commit_op_tag),
-        .m_axis_dequeue_commit_valid(tx_cpl_enqueue_commit_valid),
-        .m_axis_dequeue_commit_ready(tx_cpl_enqueue_commit_ready),
-
-        /*
-         * Dequeue request input
-         */
-        .s_axis_dequeue_req_queue(tx_port_cpl_enqueue_req_queue),
-        .s_axis_dequeue_req_tag(tx_port_cpl_enqueue_req_tag),
-        .s_axis_dequeue_req_valid(tx_port_cpl_enqueue_req_valid),
-        .s_axis_dequeue_req_ready(tx_port_cpl_enqueue_req_ready),
-
-        /*
-         * Dequeue response output
-         */
-        .m_axis_enqueue_resp_queue(),
-        .m_axis_dequeue_resp_ptr(),
-        .m_axis_dequeue_resp_addr(tx_port_cpl_enqueue_resp_addr),
-        .m_axis_dequeue_resp_cpl(),
-        .m_axis_dequeue_resp_tag(tx_port_cpl_enqueue_resp_tag),
-        .m_axis_dequeue_resp_op_tag(tx_port_cpl_enqueue_resp_op_tag),
-        .m_axis_dequeue_resp_empty(tx_port_cpl_enqueue_resp_full),
-        .m_axis_dequeue_resp_error(tx_port_cpl_enqueue_resp_error),
-        .m_axis_dequeue_resp_valid(tx_port_cpl_enqueue_resp_valid),
-        .m_axis_dequeue_resp_ready(tx_port_cpl_enqueue_resp_ready),
-
-        /*
-         * Dequeue commit input
-         */
-        .s_axis_dequeue_commit_op_tag(tx_port_cpl_enqueue_commit_op_tag),
-        .s_axis_dequeue_commit_valid(tx_port_cpl_enqueue_commit_valid),
-        .s_axis_dequeue_commit_ready(tx_port_cpl_enqueue_commit_ready)
-    );
-
-end else begin
-
-    assign tx_cpl_enqueue_req_queue = tx_port_cpl_enqueue_req_queue;
-    assign tx_cpl_enqueue_req_tag = tx_port_cpl_enqueue_req_tag;
-    assign tx_cpl_enqueue_req_valid = tx_port_cpl_enqueue_req_valid;
-    assign tx_port_cpl_enqueue_req_ready = tx_cpl_enqueue_req_ready;
-
-    assign tx_port_cpl_enqueue_resp_addr = tx_cpl_enqueue_resp_addr;
-    assign tx_port_cpl_enqueue_resp_tag = tx_cpl_enqueue_resp_tag;
-    assign tx_port_cpl_enqueue_resp_op_tag = tx_cpl_enqueue_resp_op_tag;
-    assign tx_port_cpl_enqueue_resp_full = tx_cpl_enqueue_resp_full;
-    assign tx_port_cpl_enqueue_resp_error = tx_cpl_enqueue_resp_error;
-    assign tx_port_cpl_enqueue_resp_valid = tx_cpl_enqueue_resp_valid;
-    assign tx_cpl_enqueue_resp_ready = tx_port_cpl_enqueue_resp_ready;
-
-    assign tx_cpl_enqueue_commit_op_tag = tx_port_cpl_enqueue_commit_op_tag;
-    assign tx_cpl_enqueue_commit_valid = tx_port_cpl_enqueue_commit_valid;
-    assign tx_port_cpl_enqueue_commit_ready = tx_cpl_enqueue_commit_ready;
-
-end
-
 cpl_queue_manager #(
     .ADDR_WIDTH(PCIE_ADDR_WIDTH),
     .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
@@ -1308,108 +1133,6 @@ tx_cpl_queue_manager_inst (
     .enable(1'b1)
 );
 
-
-if (PORTS > 1) begin
-
-    queue_op_mux #(
-        .PORTS(PORTS),
-        .ADDR_WIDTH(PCIE_ADDR_WIDTH),
-        .S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
-        .M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
-        .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
-        .QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
-        .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
-        .CPL_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
-        .ARB_TYPE("ROUND_ROBIN"),
-        .LSB_PRIORITY("HIGH")
-    )
-    rx_queue_op_mux_inst (
-        .clk(clk),
-        .rst(rst),
-
-        /*
-         * Dequeue request output
-         */
-        .m_axis_dequeue_req_queue(rx_desc_dequeue_req_queue),
-        .m_axis_dequeue_req_tag(rx_desc_dequeue_req_tag),
-        .m_axis_dequeue_req_valid(rx_desc_dequeue_req_valid),
-        .m_axis_dequeue_req_ready(rx_desc_dequeue_req_ready),
-
-        /*
-         * Dequeue response input
-         */
-        .s_axis_enqueue_resp_queue(rx_desc_dequeue_resp_queue),
-        .s_axis_dequeue_resp_ptr(rx_desc_dequeue_resp_ptr),
-        .s_axis_dequeue_resp_addr(rx_desc_dequeue_resp_addr),
-        .s_axis_dequeue_resp_cpl(rx_desc_dequeue_resp_cpl),
-        .s_axis_dequeue_resp_tag(rx_desc_dequeue_resp_tag),
-        .s_axis_dequeue_resp_op_tag(rx_desc_dequeue_resp_op_tag),
-        .s_axis_dequeue_resp_empty(rx_desc_dequeue_resp_empty),
-        .s_axis_dequeue_resp_error(rx_desc_dequeue_resp_error),
-        .s_axis_dequeue_resp_valid(rx_desc_dequeue_resp_valid),
-        .s_axis_dequeue_resp_ready(rx_desc_dequeue_resp_ready),
-
-        /*
-         * Dequeue commit output
-         */
-        .m_axis_dequeue_commit_op_tag(rx_desc_dequeue_commit_op_tag),
-        .m_axis_dequeue_commit_valid(rx_desc_dequeue_commit_valid),
-        .m_axis_dequeue_commit_ready(rx_desc_dequeue_commit_ready),
-
-        /*
-         * Dequeue request input
-         */
-        .s_axis_dequeue_req_queue(rx_port_desc_dequeue_req_queue),
-        .s_axis_dequeue_req_tag(rx_port_desc_dequeue_req_tag),
-        .s_axis_dequeue_req_valid(rx_port_desc_dequeue_req_valid),
-        .s_axis_dequeue_req_ready(rx_port_desc_dequeue_req_ready),
-
-        /*
-         * Dequeue response output
-         */
-        .m_axis_enqueue_resp_queue(rx_port_desc_dequeue_resp_queue),
-        .m_axis_dequeue_resp_ptr(rx_port_desc_dequeue_resp_ptr),
-        .m_axis_dequeue_resp_addr(rx_port_desc_dequeue_resp_addr),
-        .m_axis_dequeue_resp_cpl(rx_port_desc_dequeue_resp_cpl),
-        .m_axis_dequeue_resp_tag(rx_port_desc_dequeue_resp_tag),
-        .m_axis_dequeue_resp_op_tag(rx_port_desc_dequeue_resp_op_tag),
-        .m_axis_dequeue_resp_empty(rx_port_desc_dequeue_resp_empty),
-        .m_axis_dequeue_resp_error(rx_port_desc_dequeue_resp_error),
-        .m_axis_dequeue_resp_valid(rx_port_desc_dequeue_resp_valid),
-        .m_axis_dequeue_resp_ready(rx_port_desc_dequeue_resp_ready),
-
-        /*
-         * Dequeue commit input
-         */
-        .s_axis_dequeue_commit_op_tag(rx_port_desc_dequeue_commit_op_tag),
-        .s_axis_dequeue_commit_valid(rx_port_desc_dequeue_commit_valid),
-        .s_axis_dequeue_commit_ready(rx_port_desc_dequeue_commit_ready)
-    );
-
-end else begin
-
-    assign rx_desc_dequeue_req_queue = rx_port_desc_dequeue_req_queue;
-    assign rx_desc_dequeue_req_tag = rx_port_desc_dequeue_req_tag;
-    assign rx_desc_dequeue_req_valid = rx_port_desc_dequeue_req_valid;
-    assign rx_port_desc_dequeue_req_ready = rx_desc_dequeue_req_ready;
-
-    assign rx_port_desc_dequeue_resp_queue = rx_desc_dequeue_resp_queue;
-    assign rx_port_desc_dequeue_resp_ptr = rx_desc_dequeue_resp_ptr;
-    assign rx_port_desc_dequeue_resp_addr = rx_desc_dequeue_resp_addr;
-    assign rx_port_desc_dequeue_resp_cpl = rx_desc_dequeue_resp_cpl;
-    assign rx_port_desc_dequeue_resp_tag = rx_desc_dequeue_resp_tag;
-    assign rx_port_desc_dequeue_resp_op_tag = rx_desc_dequeue_resp_op_tag;
-    assign rx_port_desc_dequeue_resp_empty = rx_desc_dequeue_resp_empty;
-    assign rx_port_desc_dequeue_resp_error = rx_desc_dequeue_resp_error;
-    assign rx_port_desc_dequeue_resp_valid = rx_desc_dequeue_resp_valid;
-    assign rx_desc_dequeue_resp_ready = rx_port_desc_dequeue_resp_ready;
-
-    assign rx_desc_dequeue_commit_op_tag = rx_port_desc_dequeue_commit_op_tag;
-    assign rx_desc_dequeue_commit_valid = rx_port_desc_dequeue_commit_valid;
-    assign rx_port_desc_dequeue_commit_ready = rx_desc_dequeue_commit_ready;
-
-end
-
 queue_manager #(
     .ADDR_WIDTH(PCIE_ADDR_WIDTH),
     .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
@@ -1440,7 +1163,7 @@ rx_queue_manager_inst (
     /*
      * Dequeue response output
      */
-    .m_axis_dequeue_resp_queue(),
+    .m_axis_dequeue_resp_queue(rx_desc_dequeue_resp_queue),
     .m_axis_dequeue_resp_ptr(rx_desc_dequeue_resp_ptr),
     .m_axis_dequeue_resp_addr(rx_desc_dequeue_resp_addr),
     .m_axis_dequeue_resp_cpl(rx_desc_dequeue_resp_cpl),
@@ -1493,104 +1216,6 @@ rx_queue_manager_inst (
     .enable(1'b1)
 );
 
-if (PORTS > 1) begin
-
-    queue_op_mux #(
-        .PORTS(PORTS),
-        .ADDR_WIDTH(PCIE_ADDR_WIDTH),
-        .S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
-        .M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
-        .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
-        .QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
-        .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
-        .CPL_INDEX_WIDTH(0),
-        .ARB_TYPE("ROUND_ROBIN"),
-        .LSB_PRIORITY("HIGH")
-    )
-    rx_cpl_queue_op_mux_inst (
-        .clk(clk),
-        .rst(rst),
-
-        /*
-         * Dequeue request output
-         */
-        .m_axis_dequeue_req_queue(rx_cpl_enqueue_req_queue),
-        .m_axis_dequeue_req_tag(rx_cpl_enqueue_req_tag),
-        .m_axis_dequeue_req_valid(rx_cpl_enqueue_req_valid),
-        .m_axis_dequeue_req_ready(rx_cpl_enqueue_req_ready),
-
-        /*
-         * Dequeue response input
-         */
-        .m_axis_enqueue_resp_queue(0),
-        .s_axis_dequeue_resp_ptr(0),
-        .s_axis_dequeue_resp_addr(rx_cpl_enqueue_resp_addr),
-        .s_axis_dequeue_resp_cpl(0),
-        .s_axis_dequeue_resp_tag(rx_cpl_enqueue_resp_tag),
-        .s_axis_dequeue_resp_op_tag(rx_cpl_enqueue_resp_op_tag),
-        .s_axis_dequeue_resp_empty(rx_cpl_enqueue_resp_full),
-        .s_axis_dequeue_resp_error(rx_cpl_enqueue_resp_error),
-        .s_axis_dequeue_resp_valid(rx_cpl_enqueue_resp_valid),
-        .s_axis_dequeue_resp_ready(rx_cpl_enqueue_resp_ready),
-
-        /*
-         * Dequeue commit output
-         */
-        .m_axis_dequeue_commit_op_tag(rx_cpl_enqueue_commit_op_tag),
-        .m_axis_dequeue_commit_valid(rx_cpl_enqueue_commit_valid),
-        .m_axis_dequeue_commit_ready(rx_cpl_enqueue_commit_ready),
-
-        /*
-         * Dequeue request input
-         */
-        .s_axis_dequeue_req_queue(rx_port_cpl_enqueue_req_queue),
-        .s_axis_dequeue_req_tag(rx_port_cpl_enqueue_req_tag),
-        .s_axis_dequeue_req_valid(rx_port_cpl_enqueue_req_valid),
-        .s_axis_dequeue_req_ready(rx_port_cpl_enqueue_req_ready),
-
-        /*
-         * Dequeue response output
-         */
-        .m_axis_enqueue_resp_queue(),
-        .m_axis_dequeue_resp_ptr(),
-        .m_axis_dequeue_resp_addr(rx_port_cpl_enqueue_resp_addr),
-        .m_axis_dequeue_resp_cpl(),
-        .m_axis_dequeue_resp_tag(rx_port_cpl_enqueue_resp_tag),
-        .m_axis_dequeue_resp_op_tag(rx_port_cpl_enqueue_resp_op_tag),
-        .m_axis_dequeue_resp_empty(rx_port_cpl_enqueue_resp_full),
-        .m_axis_dequeue_resp_error(rx_port_cpl_enqueue_resp_error),
-        .m_axis_dequeue_resp_valid(rx_port_cpl_enqueue_resp_valid),
-        .m_axis_dequeue_resp_ready(rx_port_cpl_enqueue_resp_ready),
-
-        /*
-         * Dequeue commit input
-         */
-        .s_axis_dequeue_commit_op_tag(rx_port_cpl_enqueue_commit_op_tag),
-        .s_axis_dequeue_commit_valid(rx_port_cpl_enqueue_commit_valid),
-        .s_axis_dequeue_commit_ready(rx_port_cpl_enqueue_commit_ready)
-    );
-
-end else begin
-
-    assign rx_cpl_enqueue_req_queue = rx_port_cpl_enqueue_req_queue;
-    assign rx_cpl_enqueue_req_tag = rx_port_cpl_enqueue_req_tag;
-    assign rx_cpl_enqueue_req_valid = rx_port_cpl_enqueue_req_valid;
-    assign rx_port_cpl_enqueue_req_ready = rx_cpl_enqueue_req_ready;
-
-    assign rx_port_cpl_enqueue_resp_addr = rx_cpl_enqueue_resp_addr;
-    assign rx_port_cpl_enqueue_resp_tag = rx_cpl_enqueue_resp_tag;
-    assign rx_port_cpl_enqueue_resp_op_tag = rx_cpl_enqueue_resp_op_tag;
-    assign rx_port_cpl_enqueue_resp_full = rx_cpl_enqueue_resp_full;
-    assign rx_port_cpl_enqueue_resp_error = rx_cpl_enqueue_resp_error;
-    assign rx_port_cpl_enqueue_resp_valid = rx_cpl_enqueue_resp_valid;
-    assign rx_cpl_enqueue_resp_ready = rx_port_cpl_enqueue_resp_ready;
-
-    assign rx_cpl_enqueue_commit_op_tag = rx_port_cpl_enqueue_commit_op_tag;
-    assign rx_cpl_enqueue_commit_valid = rx_port_cpl_enqueue_commit_valid;
-    assign rx_port_cpl_enqueue_commit_ready = rx_cpl_enqueue_commit_ready;
-
-end
-
 cpl_queue_manager #(
     .ADDR_WIDTH(PCIE_ADDR_WIDTH),
     .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
@@ -1675,72 +1300,450 @@ rx_cpl_queue_manager_inst (
     .enable(1'b1)
 );
 
-generate
-
 if (PORTS > 1) begin
 
-    pcie_axi_dma_desc_mux #(
+    desc_op_mux #(
         .PORTS(PORTS),
-        .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
-        .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
-        .LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
-        .S_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
-        .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
+        .SELECT_WIDTH(1),
+        .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
+        .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
+        .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH),
+        .S_REQ_TAG_WIDTH(PORT_DESC_REQ_TAG_WIDTH),
+        .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
+        .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+        .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
         .ARB_TYPE("ROUND_ROBIN"),
         .LSB_PRIORITY("HIGH")
     )
-    pcie_axi_dma_read_desc_mux_inst (
+    desc_op_mux_inst (
         .clk(clk),
         .rst(rst),
 
         /*
-         * Descriptor output
+         * Descriptor request output
          */
-        .m_axis_desc_pcie_addr(m_axis_pcie_axi_dma_read_desc_pcie_addr),
-        .m_axis_desc_axi_addr(m_axis_pcie_axi_dma_read_desc_axi_addr),
-        .m_axis_desc_len(m_axis_pcie_axi_dma_read_desc_len),
-        .m_axis_desc_tag(m_axis_pcie_axi_dma_read_desc_tag),
-        .m_axis_desc_valid(m_axis_pcie_axi_dma_read_desc_valid),
-        .m_axis_desc_ready(m_axis_pcie_axi_dma_read_desc_ready),
+        .m_axis_req_sel(desc_req_sel),
+        .m_axis_req_queue(desc_req_queue),
+        .m_axis_req_tag(desc_req_tag),
+        .m_axis_req_valid(desc_req_valid),
+        .m_axis_req_ready(desc_req_ready),
 
         /*
-         * Descriptor status input
+         * Descriptor request status input
          */
-        .s_axis_desc_status_tag(s_axis_pcie_axi_dma_read_desc_status_tag),
-        .s_axis_desc_status_valid(s_axis_pcie_axi_dma_read_desc_status_valid),
+        .s_axis_req_status_queue(desc_req_status_queue),
+        .s_axis_req_status_ptr(desc_req_status_ptr),
+        .s_axis_req_status_cpl(desc_req_status_cpl),
+        .s_axis_req_status_tag(desc_req_status_tag),
+        .s_axis_req_status_empty(desc_req_status_empty),
+        .s_axis_req_status_error(desc_req_status_error),
+        .s_axis_req_status_valid(desc_req_status_valid),
 
         /*
-         * Descriptor input
+         * Descriptor data input
          */
-        .s_axis_desc_pcie_addr(port_pcie_axi_dma_read_desc_pcie_addr),
-        .s_axis_desc_axi_addr(port_pcie_axi_dma_read_desc_axi_addr),
-        .s_axis_desc_len(port_pcie_axi_dma_read_desc_len),
-        .s_axis_desc_tag(port_pcie_axi_dma_read_desc_tag),
-        .s_axis_desc_valid(port_pcie_axi_dma_read_desc_valid),
-        .s_axis_desc_ready(port_pcie_axi_dma_read_desc_ready),
+        .s_axis_desc_tdata(desc_tdata),
+        .s_axis_desc_tkeep(desc_tkeep),
+        .s_axis_desc_tvalid(desc_tvalid),
+        .s_axis_desc_tready(desc_tready),
+        .s_axis_desc_tlast(desc_tlast),
+        .s_axis_desc_tid(desc_tid),
+        .s_axis_desc_tuser(desc_tuser),
 
         /*
-         * Descriptor status output
+         * Descriptor request input
          */
-        .m_axis_desc_status_tag(port_pcie_axi_dma_read_desc_status_tag),
-        .m_axis_desc_status_valid(port_pcie_axi_dma_read_desc_status_valid)
+        .s_axis_req_sel(port_desc_req_sel),
+        .s_axis_req_queue(port_desc_req_queue),
+        .s_axis_req_tag(port_desc_req_tag),
+        .s_axis_req_valid(port_desc_req_valid),
+        .s_axis_req_ready(port_desc_req_ready),
+
+        /*
+         * Descriptor response output
+         */
+        .m_axis_req_status_queue(port_desc_req_status_queue),
+        .m_axis_req_status_ptr(port_desc_req_status_ptr),
+        .m_axis_req_status_cpl(port_desc_req_status_cpl),
+        .m_axis_req_status_tag(port_desc_req_status_tag),
+        .m_axis_req_status_empty(port_desc_req_status_empty),
+        .m_axis_req_status_error(port_desc_req_status_error),
+        .m_axis_req_status_valid(port_desc_req_status_valid),
+
+        /*
+         * Descriptor commit output
+         */
+        .m_axis_desc_tdata(port_desc_tdata),
+        .m_axis_desc_tkeep(port_desc_tkeep),
+        .m_axis_desc_tvalid(port_desc_tvalid),
+        .m_axis_desc_tready(port_desc_tready),
+        .m_axis_desc_tlast(port_desc_tlast),
+        .m_axis_desc_tid(port_desc_tid),
+        .m_axis_desc_tuser(port_desc_tuser)
     );
 
 end else begin
-    
-    assign m_axis_pcie_axi_dma_read_desc_pcie_addr = port_pcie_axi_dma_read_desc_pcie_addr;
-    assign m_axis_pcie_axi_dma_read_desc_axi_addr = port_pcie_axi_dma_read_desc_axi_addr;
-    assign m_axis_pcie_axi_dma_read_desc_len = port_pcie_axi_dma_read_desc_len;
-    assign m_axis_pcie_axi_dma_read_desc_tag = port_pcie_axi_dma_read_desc_tag;
-    assign m_axis_pcie_axi_dma_read_desc_valid = port_pcie_axi_dma_read_desc_valid;
-    assign port_pcie_axi_dma_read_desc_ready = m_axis_pcie_axi_dma_read_desc_ready;
 
-    assign port_pcie_axi_dma_read_desc_status_tag = s_axis_pcie_axi_dma_read_desc_status_tag;
-    assign port_pcie_axi_dma_read_desc_status_valid = s_axis_pcie_axi_dma_read_desc_status_valid;
+    assign desc_req_sel = port_desc_req_sel;
+    assign desc_req_queue = port_desc_req_queue;
+    assign desc_req_tag = port_desc_req_tag;
+    assign desc_req_valid = port_desc_req_valid;
+    assign port_desc_req_ready = desc_req_ready;
+
+    assign port_desc_req_status_queue = desc_req_status_queue;
+    assign port_desc_req_status_ptr = desc_req_status_ptr;
+    assign port_desc_req_status_cpl = desc_req_status_cpl;
+    assign port_desc_req_status_tag = desc_req_status_tag;
+    assign port_desc_req_status_empty = desc_req_status_empty;
+    assign port_desc_req_status_error = desc_req_status_error;
+    assign port_desc_req_status_valid = desc_req_status_valid;
+
+    assign port_desc_tdata = desc_tdata;
+    assign port_desc_tkeep = desc_tkeep;
+    assign port_desc_tvalid = desc_tvalid;
+    assign desc_tready = port_desc_tready;
+    assign port_desc_tlast = desc_tlast;
+    assign port_desc_tid = desc_tid;
+    assign port_desc_tuser = desc_tuser;
 
 end
 
-endgenerate
+desc_fetch #(
+    .PORTS(2),
+    .SELECT_WIDTH(1),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+    .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+    .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+    .PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
+    .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
+    .REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
+    .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
+    .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
+    .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
+    .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH),
+    .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
+    .DESC_SIZE(DESC_SIZE),
+    .DESC_TABLE_SIZE(32),
+    .AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h000000)
+)
+desc_fetch_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Descriptor read request input
+     */
+    .s_axis_req_sel(desc_req_sel),
+    .s_axis_req_queue(desc_req_queue),
+    .s_axis_req_tag(desc_req_tag),
+    .s_axis_req_valid(desc_req_valid),
+    .s_axis_req_ready(desc_req_ready),
+
+    /*
+     * Descriptor read request status output
+     */
+    .m_axis_req_status_queue(desc_req_status_queue),
+    .m_axis_req_status_ptr(desc_req_status_ptr),
+    .m_axis_req_status_cpl(desc_req_status_cpl),
+    .m_axis_req_status_tag(desc_req_status_tag),
+    .m_axis_req_status_empty(desc_req_status_empty),
+    .m_axis_req_status_error(desc_req_status_error),
+    .m_axis_req_status_valid(desc_req_status_valid),
+
+    /*
+     * Descriptor data output
+     */
+    .m_axis_desc_tdata(desc_tdata),
+    .m_axis_desc_tkeep(desc_tkeep),
+    .m_axis_desc_tvalid(desc_tvalid),
+    .m_axis_desc_tready(desc_tready),
+    .m_axis_desc_tlast(desc_tlast),
+    .m_axis_desc_tid(desc_tid),
+    .m_axis_desc_tuser(desc_tuser),
+
+    /*
+     * Descriptor dequeue request output
+     */
+    .m_axis_desc_dequeue_req_queue({rx_desc_dequeue_req_queue, tx_desc_dequeue_req_queue}),
+    .m_axis_desc_dequeue_req_tag({rx_desc_dequeue_req_tag, tx_desc_dequeue_req_tag}),
+    .m_axis_desc_dequeue_req_valid({rx_desc_dequeue_req_valid, tx_desc_dequeue_req_valid}),
+    .m_axis_desc_dequeue_req_ready({rx_desc_dequeue_req_ready, tx_desc_dequeue_req_ready}),
+
+    /*
+     * Descriptor dequeue response input
+     */
+    .s_axis_desc_dequeue_resp_queue({rx_desc_dequeue_resp_queue, tx_desc_dequeue_resp_queue}),
+    .s_axis_desc_dequeue_resp_ptr({rx_desc_dequeue_resp_ptr, tx_desc_dequeue_resp_ptr}),
+    .s_axis_desc_dequeue_resp_addr({rx_desc_dequeue_resp_addr, tx_desc_dequeue_resp_addr}),
+    .s_axis_desc_dequeue_resp_cpl({rx_desc_dequeue_resp_cpl, tx_desc_dequeue_resp_cpl}),
+    .s_axis_desc_dequeue_resp_tag({rx_desc_dequeue_resp_tag, tx_desc_dequeue_resp_tag}),
+    .s_axis_desc_dequeue_resp_op_tag({rx_desc_dequeue_resp_op_tag, tx_desc_dequeue_resp_op_tag}),
+    .s_axis_desc_dequeue_resp_empty({rx_desc_dequeue_resp_empty, tx_desc_dequeue_resp_empty}),
+    .s_axis_desc_dequeue_resp_error({rx_desc_dequeue_resp_error, tx_desc_dequeue_resp_error}),
+    .s_axis_desc_dequeue_resp_valid({rx_desc_dequeue_resp_valid, tx_desc_dequeue_resp_valid}),
+    .s_axis_desc_dequeue_resp_ready({rx_desc_dequeue_resp_ready, tx_desc_dequeue_resp_ready}),
+
+    /*
+     * Descriptor dequeue commit output
+     */
+    .m_axis_desc_dequeue_commit_op_tag({rx_desc_dequeue_commit_op_tag, tx_desc_dequeue_commit_op_tag}),
+    .m_axis_desc_dequeue_commit_valid({rx_desc_dequeue_commit_valid, tx_desc_dequeue_commit_valid}),
+    .m_axis_desc_dequeue_commit_ready({rx_desc_dequeue_commit_ready, tx_desc_dequeue_commit_ready}),
+
+    /*
+     * PCIe AXI DMA read descriptor output
+     */
+    .m_axis_pcie_axi_dma_read_desc_pcie_addr(desc_pcie_axi_dma_write_desc_pcie_addr),
+    .m_axis_pcie_axi_dma_read_desc_axi_addr(desc_pcie_axi_dma_write_desc_axi_addr),
+    .m_axis_pcie_axi_dma_read_desc_len(desc_pcie_axi_dma_write_desc_len),
+    .m_axis_pcie_axi_dma_read_desc_tag(desc_pcie_axi_dma_write_desc_tag),
+    .m_axis_pcie_axi_dma_read_desc_valid(desc_pcie_axi_dma_write_desc_valid),
+    .m_axis_pcie_axi_dma_read_desc_ready(desc_pcie_axi_dma_write_desc_ready),
+
+    /*
+     * PCIe AXI DMA read descriptor status input
+     */
+    .s_axis_pcie_axi_dma_read_desc_status_tag(desc_pcie_axi_dma_write_desc_status_tag),
+    .s_axis_pcie_axi_dma_read_desc_status_valid(desc_pcie_axi_dma_write_desc_status_valid),
+
+    /*
+     * AXI slave interface (write)
+     */
+    .s_axi_awid(axi_desc_awid),
+    .s_axi_awaddr(axi_desc_awaddr),
+    .s_axi_awlen(axi_desc_awlen),
+    .s_axi_awsize(axi_desc_awsize),
+    .s_axi_awburst(axi_desc_awburst),
+    .s_axi_awlock(axi_desc_awlock),
+    .s_axi_awcache(axi_desc_awcache),
+    .s_axi_awprot(axi_desc_awprot),
+    .s_axi_awvalid(axi_desc_awvalid),
+    .s_axi_awready(axi_desc_awready),
+    .s_axi_wdata(axi_desc_wdata),
+    .s_axi_wstrb(axi_desc_wstrb),
+    .s_axi_wlast(axi_desc_wlast),
+    .s_axi_wvalid(axi_desc_wvalid),
+    .s_axi_wready(axi_desc_wready),
+    .s_axi_bid(axi_desc_bid),
+    .s_axi_bresp(axi_desc_bresp),
+    .s_axi_bvalid(axi_desc_bvalid),
+    .s_axi_bready(axi_desc_bready),
+
+    /*
+     * Configuration
+     */
+    .enable(1'b1)
+);
+
+cpl_op_mux #(
+    .PORTS(PORTS+1),
+    .SELECT_WIDTH(2),
+    .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
+    .S_REQ_TAG_WIDTH(PORT_DESC_REQ_TAG_WIDTH),
+    .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
+    .CPL_SIZE(CPL_SIZE),
+    .ARB_TYPE("ROUND_ROBIN"),
+    .LSB_PRIORITY("HIGH")
+)
+cpl_op_mux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Completion request output
+     */
+    .m_axis_req_sel(cpl_req_sel),
+    .m_axis_req_queue(cpl_req_queue),
+    .m_axis_req_tag(cpl_req_tag),
+    .m_axis_req_data(cpl_req_data),
+    .m_axis_req_valid(cpl_req_valid),
+    .m_axis_req_ready(cpl_req_ready),
+
+    /*
+     * Completion request status input
+     */
+    .s_axis_req_status_tag(cpl_req_status_tag),
+    .s_axis_req_status_full(cpl_req_status_full),
+    .s_axis_req_status_error(cpl_req_status_error),
+    .s_axis_req_status_valid(cpl_req_status_valid),
+
+    /*
+     * Completion request input
+     */
+    .s_axis_req_sel({port_cpl_req_sel, event_cpl_req_sel}),
+    .s_axis_req_queue({port_cpl_req_queue, event_cpl_req_queue}),
+    .s_axis_req_tag({port_cpl_req_tag, event_cpl_req_tag}),
+    .s_axis_req_data({port_cpl_req_data, event_cpl_req_data}),
+    .s_axis_req_valid({port_cpl_req_valid, event_cpl_req_valid}),
+    .s_axis_req_ready({port_cpl_req_ready, event_cpl_req_ready}),
+
+    /*
+     * Completion response output
+     */
+    .m_axis_req_status_tag({port_cpl_req_status_tag, event_cpl_req_status_tag}),
+    .m_axis_req_status_full({port_cpl_req_status_full, event_cpl_req_status_full}),
+    .m_axis_req_status_error({port_cpl_req_status_error, event_cpl_req_status_error}),
+    .m_axis_req_status_valid({port_cpl_req_status_valid, event_cpl_req_status_valid})
+);
+
+cpl_write #(
+    .PORTS(3),
+    .SELECT_WIDTH(2),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+    .PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
+    .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
+    .REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
+    .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
+    .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
+    .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
+    .CPL_SIZE(CPL_SIZE),
+    .DESC_TABLE_SIZE(32),
+    .AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h000000)
+)
+cpl_write_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Completion read request input
+     */
+    .s_axis_req_sel(cpl_req_sel),
+    .s_axis_req_queue(cpl_req_queue),
+    .s_axis_req_tag(cpl_req_tag),
+    .s_axis_req_data(cpl_req_data),
+    .s_axis_req_valid(cpl_req_valid),
+    .s_axis_req_ready(cpl_req_ready),
+
+    /*
+     * Completion read request status output
+     */
+    .m_axis_req_status_tag(cpl_req_status_tag),
+    .m_axis_req_status_full(cpl_req_status_full),
+    .m_axis_req_status_error(cpl_req_status_error),
+    .m_axis_req_status_valid(cpl_req_status_valid),
+
+    /*
+     * Completion enqueue request output
+     */
+    .m_axis_cpl_enqueue_req_queue({event_enqueue_req_queue, rx_cpl_enqueue_req_queue, tx_cpl_enqueue_req_queue}),
+    .m_axis_cpl_enqueue_req_tag({event_enqueue_req_tag, rx_cpl_enqueue_req_tag, tx_cpl_enqueue_req_tag}),
+    .m_axis_cpl_enqueue_req_valid({event_enqueue_req_valid, rx_cpl_enqueue_req_valid, tx_cpl_enqueue_req_valid}),
+    .m_axis_cpl_enqueue_req_ready({event_enqueue_req_ready, rx_cpl_enqueue_req_ready, tx_cpl_enqueue_req_ready}),
+
+    /*
+     * Completion enqueue response input
+     */
+    .s_axis_cpl_enqueue_resp_addr({event_enqueue_resp_addr, rx_cpl_enqueue_resp_addr, tx_cpl_enqueue_resp_addr}),
+    .s_axis_cpl_enqueue_resp_tag({event_enqueue_resp_tag, rx_cpl_enqueue_resp_tag, tx_cpl_enqueue_resp_tag}),
+    .s_axis_cpl_enqueue_resp_op_tag({event_enqueue_resp_op_tag, rx_cpl_enqueue_resp_op_tag, tx_cpl_enqueue_resp_op_tag}),
+    .s_axis_cpl_enqueue_resp_full({event_enqueue_resp_full, rx_cpl_enqueue_resp_full, tx_cpl_enqueue_resp_full}),
+    .s_axis_cpl_enqueue_resp_error({event_enqueue_resp_error, rx_cpl_enqueue_resp_error, tx_cpl_enqueue_resp_error}),
+    .s_axis_cpl_enqueue_resp_valid({event_enqueue_resp_valid, rx_cpl_enqueue_resp_valid, tx_cpl_enqueue_resp_valid}),
+    .s_axis_cpl_enqueue_resp_ready({event_enqueue_resp_ready, rx_cpl_enqueue_resp_ready, tx_cpl_enqueue_resp_ready}),
+
+    /*
+     * Completion enqueue commit output
+     */
+    .m_axis_cpl_enqueue_commit_op_tag({event_enqueue_commit_op_tag, rx_cpl_enqueue_commit_op_tag, tx_cpl_enqueue_commit_op_tag}),
+    .m_axis_cpl_enqueue_commit_valid({event_enqueue_commit_valid, rx_cpl_enqueue_commit_valid, tx_cpl_enqueue_commit_valid}),
+    .m_axis_cpl_enqueue_commit_ready({event_enqueue_commit_ready, rx_cpl_enqueue_commit_ready, tx_cpl_enqueue_commit_ready}),
+
+    /*
+     * PCIe AXI DMA write descriptor output
+     */
+    .m_axis_pcie_axi_dma_write_desc_pcie_addr(cpl_pcie_axi_dma_write_desc_pcie_addr),
+    .m_axis_pcie_axi_dma_write_desc_axi_addr(cpl_pcie_axi_dma_write_desc_axi_addr),
+    .m_axis_pcie_axi_dma_write_desc_len(cpl_pcie_axi_dma_write_desc_len),
+    .m_axis_pcie_axi_dma_write_desc_tag(cpl_pcie_axi_dma_write_desc_tag),
+    .m_axis_pcie_axi_dma_write_desc_valid(cpl_pcie_axi_dma_write_desc_valid),
+    .m_axis_pcie_axi_dma_write_desc_ready(cpl_pcie_axi_dma_write_desc_ready),
+
+    /*
+     * PCIe AXI DMA write descriptor status input
+     */
+    .s_axis_pcie_axi_dma_write_desc_status_tag(cpl_pcie_axi_dma_write_desc_status_tag),
+    .s_axis_pcie_axi_dma_write_desc_status_valid(cpl_pcie_axi_dma_write_desc_status_valid),
+
+    /*
+     * AXI slave interface (read)
+     */
+    .s_axi_arid(axi_desc_arid),
+    .s_axi_araddr(axi_desc_araddr),
+    .s_axi_arlen(axi_desc_arlen),
+    .s_axi_arsize(axi_desc_arsize),
+    .s_axi_arburst(axi_desc_arburst),
+    .s_axi_arlock(axi_desc_arlock),
+    .s_axi_arcache(axi_desc_arcache),
+    .s_axi_arprot(axi_desc_arprot),
+    .s_axi_arvalid(axi_desc_arvalid),
+    .s_axi_arready(axi_desc_arready),
+    .s_axi_rid(axi_desc_rid),
+    .s_axi_rdata(axi_desc_rdata),
+    .s_axi_rresp(axi_desc_rresp),
+    .s_axi_rlast(axi_desc_rlast),
+    .s_axi_rvalid(axi_desc_rvalid),
+    .s_axi_rready(axi_desc_rready),
+
+    /*
+     * Configuration
+     */
+    .enable(1'b1)
+);
+
+pcie_axi_dma_desc_mux #(
+    .PORTS(PORTS+1),
+    .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+    .LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
+    .S_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
+    .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
+    .ARB_TYPE("ROUND_ROBIN"),
+    .LSB_PRIORITY("HIGH")
+)
+pcie_axi_dma_read_desc_mux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Descriptor output
+     */
+    .m_axis_desc_pcie_addr(m_axis_pcie_axi_dma_read_desc_pcie_addr),
+    .m_axis_desc_axi_addr(m_axis_pcie_axi_dma_read_desc_axi_addr),
+    .m_axis_desc_len(m_axis_pcie_axi_dma_read_desc_len),
+    .m_axis_desc_tag(m_axis_pcie_axi_dma_read_desc_tag),
+    .m_axis_desc_valid(m_axis_pcie_axi_dma_read_desc_valid),
+    .m_axis_desc_ready(m_axis_pcie_axi_dma_read_desc_ready),
+
+    /*
+     * Descriptor status input
+     */
+    .s_axis_desc_status_tag(s_axis_pcie_axi_dma_read_desc_status_tag),
+    .s_axis_desc_status_valid(s_axis_pcie_axi_dma_read_desc_status_valid),
+
+    /*
+     * Descriptor input
+     */
+    .s_axis_desc_pcie_addr({port_pcie_axi_dma_read_desc_pcie_addr, desc_pcie_axi_dma_write_desc_pcie_addr}),
+    .s_axis_desc_axi_addr({port_pcie_axi_dma_read_desc_axi_addr, desc_pcie_axi_dma_write_desc_axi_addr}),
+    .s_axis_desc_len({port_pcie_axi_dma_read_desc_len, desc_pcie_axi_dma_write_desc_len}),
+    .s_axis_desc_tag({port_pcie_axi_dma_read_desc_tag, desc_pcie_axi_dma_write_desc_tag}),
+    .s_axis_desc_valid({port_pcie_axi_dma_read_desc_valid, desc_pcie_axi_dma_write_desc_valid}),
+    .s_axis_desc_ready({port_pcie_axi_dma_read_desc_ready, desc_pcie_axi_dma_write_desc_ready}),
+
+    /*
+     * Descriptor status output
+     */
+    .m_axis_desc_status_tag({port_pcie_axi_dma_read_desc_status_tag, desc_pcie_axi_dma_write_desc_status_tag}),
+    .m_axis_desc_status_valid({port_pcie_axi_dma_read_desc_status_valid, desc_pcie_axi_dma_write_desc_status_valid})
+);
 
 pcie_axi_dma_desc_mux #(
     .PORTS(PORTS+1),
@@ -1775,18 +1778,18 @@ pcie_axi_dma_write_desc_mux_inst (
     /*
      * Descriptor input
      */
-    .s_axis_desc_pcie_addr({port_pcie_axi_dma_write_desc_pcie_addr, event_pcie_axi_dma_write_desc_pcie_addr}),
-    .s_axis_desc_axi_addr({port_pcie_axi_dma_write_desc_axi_addr, event_pcie_axi_dma_write_desc_axi_addr}),
-    .s_axis_desc_len({port_pcie_axi_dma_write_desc_len, event_pcie_axi_dma_write_desc_len}),
-    .s_axis_desc_tag({port_pcie_axi_dma_write_desc_tag, event_pcie_axi_dma_write_desc_tag}),
-    .s_axis_desc_valid({port_pcie_axi_dma_write_desc_valid, event_pcie_axi_dma_write_desc_valid}),
-    .s_axis_desc_ready({port_pcie_axi_dma_write_desc_ready, event_pcie_axi_dma_write_desc_ready}),
+    .s_axis_desc_pcie_addr({port_pcie_axi_dma_write_desc_pcie_addr, cpl_pcie_axi_dma_write_desc_pcie_addr}),
+    .s_axis_desc_axi_addr({port_pcie_axi_dma_write_desc_axi_addr, cpl_pcie_axi_dma_write_desc_axi_addr}),
+    .s_axis_desc_len({port_pcie_axi_dma_write_desc_len, cpl_pcie_axi_dma_write_desc_len}),
+    .s_axis_desc_tag({port_pcie_axi_dma_write_desc_tag, cpl_pcie_axi_dma_write_desc_tag}),
+    .s_axis_desc_valid({port_pcie_axi_dma_write_desc_valid, cpl_pcie_axi_dma_write_desc_valid}),
+    .s_axis_desc_ready({port_pcie_axi_dma_write_desc_ready, cpl_pcie_axi_dma_write_desc_ready}),
 
     /*
      * Descriptor status output
      */
-    .m_axis_desc_status_tag({port_pcie_axi_dma_write_desc_status_tag, event_pcie_axi_dma_write_desc_status_tag}),
-    .m_axis_desc_status_valid({port_pcie_axi_dma_write_desc_status_valid, event_pcie_axi_dma_write_desc_status_valid})
+    .m_axis_desc_status_tag({port_pcie_axi_dma_write_desc_status_tag, cpl_pcie_axi_dma_write_desc_status_tag}),
+    .m_axis_desc_status_valid({port_pcie_axi_dma_write_desc_status_valid, cpl_pcie_axi_dma_write_desc_status_valid})
 );
 
 event_mux #(
@@ -1820,6 +1823,14 @@ event_mux_inst (
     .s_axis_event_ready({rx_fifo_event_ready, tx_fifo_event_ready})
 );
 
+assign event_cpl_req_queue = axis_event_queue;
+assign event_cpl_req_tag = 0;
+assign event_cpl_req_data[15:0] = axis_event_type;
+assign event_cpl_req_data[31:16] = axis_event_source;
+assign event_cpl_req_data[255:32] = 0;
+assign event_cpl_req_valid = axis_event_valid;
+assign axis_event_ready = event_cpl_req_ready;
+
 axis_fifo #(
     .DEPTH(16),
     .DATA_WIDTH(EVENT_SOURCE_WIDTH+EVENT_TYPE_WIDTH+EVENT_QUEUE_INDEX_WIDTH),
@@ -1900,120 +1911,6 @@ rx_event_fifo (
     .status_good_frame()
 );
 
-event_queue #(
-    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
-    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .AXI_ID_WIDTH(AXI_ID_WIDTH),
-    .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
-    .PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
-    .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
-    .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
-    .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
-    .QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
-    .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
-    .EVENT_TABLE_SIZE(16),
-    .AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h000000)
-)
-event_queue_inst (
-    .clk(clk),
-    .rst(rst),
-
-    /*
-     * Event input
-     */
-    .s_axis_event_queue(axis_event_queue),
-    .s_axis_event_type(axis_event_type),
-    .s_axis_event_source(axis_event_source),
-    .s_axis_event_valid(axis_event_valid),
-    .s_axis_event_ready(axis_event_ready),
-
-    /*
-     * Completion enqueue request output
-     */
-    .m_axis_event_enqueue_req_queue(event_enqueue_req_queue),
-    .m_axis_event_enqueue_req_tag(event_enqueue_req_tag),
-    .m_axis_event_enqueue_req_valid(event_enqueue_req_valid),
-    .m_axis_event_enqueue_req_ready(event_enqueue_req_ready),
-
-    /*
-     * Completion enqueue response input
-     */
-    .s_axis_event_enqueue_resp_addr(event_enqueue_resp_addr),
-    .s_axis_event_enqueue_resp_tag(event_enqueue_resp_tag),
-    .s_axis_event_enqueue_resp_op_tag(event_enqueue_resp_op_tag),
-    .s_axis_event_enqueue_resp_full(event_enqueue_resp_full),
-    .s_axis_event_enqueue_resp_error(event_enqueue_resp_error),
-    .s_axis_event_enqueue_resp_valid(event_enqueue_resp_valid),
-    .s_axis_event_enqueue_resp_ready(event_enqueue_resp_ready),
-
-    /*
-     * Completion enqueue commit output
-     */
-    .m_axis_event_enqueue_commit_op_tag(event_enqueue_commit_op_tag),
-    .m_axis_event_enqueue_commit_valid(event_enqueue_commit_valid),
-    .m_axis_event_enqueue_commit_ready(event_enqueue_commit_ready),
-
-    /*
-     * PCIe DMA write descriptor output
-     */
-    .m_axis_pcie_axi_dma_write_desc_pcie_addr(event_pcie_axi_dma_write_desc_pcie_addr),
-    .m_axis_pcie_axi_dma_write_desc_axi_addr(event_pcie_axi_dma_write_desc_axi_addr),
-    .m_axis_pcie_axi_dma_write_desc_len(event_pcie_axi_dma_write_desc_len),
-    .m_axis_pcie_axi_dma_write_desc_tag(event_pcie_axi_dma_write_desc_tag),
-    .m_axis_pcie_axi_dma_write_desc_valid(event_pcie_axi_dma_write_desc_valid),
-    .m_axis_pcie_axi_dma_write_desc_ready(event_pcie_axi_dma_write_desc_ready),
-
-    /*
-     * PCIe DMA write descriptor status input
-     */
-    .s_axis_pcie_axi_dma_write_desc_status_tag(event_pcie_axi_dma_write_desc_status_tag),
-    .s_axis_pcie_axi_dma_write_desc_status_valid(event_pcie_axi_dma_write_desc_status_valid),
-
-    /*
-     * AXI slave interface
-     */
-    .s_axi_awid(axi_event_awid),
-    .s_axi_awaddr(axi_event_awaddr),
-    .s_axi_awlen(axi_event_awlen),
-    .s_axi_awsize(axi_event_awsize),
-    .s_axi_awburst(axi_event_awburst),
-    .s_axi_awlock(axi_event_awlock),
-    .s_axi_awcache(axi_event_awcache),
-    .s_axi_awprot(axi_event_awprot),
-    .s_axi_awvalid(axi_event_awvalid),
-    .s_axi_awready(axi_event_awready),
-    .s_axi_wdata(axi_event_wdata),
-    .s_axi_wstrb(axi_event_wstrb),
-    .s_axi_wlast(axi_event_wlast),
-    .s_axi_wvalid(axi_event_wvalid),
-    .s_axi_wready(axi_event_wready),
-    .s_axi_bid(axi_event_bid),
-    .s_axi_bresp(axi_event_bresp),
-    .s_axi_bvalid(axi_event_bvalid),
-    .s_axi_bready(axi_event_bready),
-    .s_axi_arid(axi_event_arid),
-    .s_axi_araddr(axi_event_araddr),
-    .s_axi_arlen(axi_event_arlen),
-    .s_axi_arsize(axi_event_arsize),
-    .s_axi_arburst(axi_event_arburst),
-    .s_axi_arlock(axi_event_arlock),
-    .s_axi_arcache(axi_event_arcache),
-    .s_axi_arprot(axi_event_arprot),
-    .s_axi_arvalid(axi_event_arvalid),
-    .s_axi_arready(axi_event_arready),
-    .s_axi_rid(axi_event_rid),
-    .s_axi_rdata(axi_event_rdata),
-    .s_axi_rresp(axi_event_rresp),
-    .s_axi_rlast(axi_event_rlast),
-    .s_axi_rvalid(axi_event_rvalid),
-    .s_axi_rready(axi_event_rready),
-
-    /*
-     * Configuration
-     */
-    .enable(1'b1)
-);
-
 parameter RAM_COUNT = PORTS*2+1;
 parameter RAM_BASE_ADDR_WIDTH = RAM_COUNT*AXI_ADDR_WIDTH;
 parameter RAM_BASE_ADDR = calcRAMBaseAddrs(RAM_ADDR_WIDTH);
@@ -2106,42 +2003,6 @@ wire [RAM_COUNT-1:0]                axi_ram_rlast;
 wire [RAM_COUNT-1:0]                axi_ram_rvalid;
 wire [RAM_COUNT-1:0]                axi_ram_rready;
 
-wire [PORTS*RAM_ID_WIDTH-1:0]    axi_port_desc_awid;
-wire [PORTS*AXI_ADDR_WIDTH-1:0]  axi_port_desc_awaddr;
-wire [PORTS*8-1:0]               axi_port_desc_awlen;
-wire [PORTS*3-1:0]               axi_port_desc_awsize;
-wire [PORTS*2-1:0]               axi_port_desc_awburst;
-wire [PORTS-1:0]                 axi_port_desc_awlock;
-wire [PORTS*4-1:0]               axi_port_desc_awcache;
-wire [PORTS*3-1:0]               axi_port_desc_awprot;
-wire [PORTS-1:0]                 axi_port_desc_awvalid;
-wire [PORTS-1:0]                 axi_port_desc_awready;
-wire [PORTS*AXI_DATA_WIDTH-1:0]  axi_port_desc_wdata;
-wire [PORTS*AXI_STRB_WIDTH-1:0]  axi_port_desc_wstrb;
-wire [PORTS-1:0]                 axi_port_desc_wlast;
-wire [PORTS-1:0]                 axi_port_desc_wvalid;
-wire [PORTS-1:0]                 axi_port_desc_wready;
-wire [PORTS*RAM_ID_WIDTH-1:0]    axi_port_desc_bid;
-wire [PORTS*2-1:0]               axi_port_desc_bresp;
-wire [PORTS-1:0]                 axi_port_desc_bvalid;
-wire [PORTS-1:0]                 axi_port_desc_bready;
-wire [PORTS*RAM_ID_WIDTH-1:0]    axi_port_desc_arid;
-wire [PORTS*AXI_ADDR_WIDTH-1:0]  axi_port_desc_araddr;
-wire [PORTS*8-1:0]               axi_port_desc_arlen;
-wire [PORTS*3-1:0]               axi_port_desc_arsize;
-wire [PORTS*2-1:0]               axi_port_desc_arburst;
-wire [PORTS-1:0]                 axi_port_desc_arlock;
-wire [PORTS*4-1:0]               axi_port_desc_arcache;
-wire [PORTS*3-1:0]               axi_port_desc_arprot;
-wire [PORTS-1:0]                 axi_port_desc_arvalid;
-wire [PORTS-1:0]                 axi_port_desc_arready;
-wire [PORTS*RAM_ID_WIDTH-1:0]    axi_port_desc_rid;
-wire [PORTS*AXI_DATA_WIDTH-1:0]  axi_port_desc_rdata;
-wire [PORTS*2-1:0]               axi_port_desc_rresp;
-wire [PORTS-1:0]                 axi_port_desc_rlast;
-wire [PORTS-1:0]                 axi_port_desc_rvalid;
-wire [PORTS-1:0]                 axi_port_desc_rready;
-
 axi_crossbar #(
     .S_COUNT(AXI_S_COUNT),
     .M_COUNT(RAM_COUNT),
@@ -2257,131 +2118,63 @@ axi_crossbar_inst (
     .m_axi_rready(   {axi_ram_rready})
 );
 
-axi_interconnect #(
-    .S_COUNT(1),
-    .M_COUNT(2),
-    .DATA_WIDTH(AXI_DATA_WIDTH),
-    .ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .STRB_WIDTH(AXI_STRB_WIDTH),
-    .ID_WIDTH(RAM_ID_WIDTH),
-    .AWUSER_ENABLE(0),
-    .WUSER_ENABLE(0),
-    .BUSER_ENABLE(0),
-    .ARUSER_ENABLE(0),
-    .RUSER_ENABLE(0),
-    .FORWARD_ID(0),
-    .M_REGIONS(1),
-    .M_BASE_ADDR({23'h004000, 23'h000000}),
-    .M_ADDR_WIDTH({2{32'd14}}),
-    .M_CONNECT_READ({2{{1{1'b1}}}}),
-    .M_CONNECT_WRITE({2{{1{1'b1}}}})
-)
-axi_interconnect_inst (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_awid(     {axi_ram_awid[RAM_ID_WIDTH-1:0]}),
-    .s_axi_awaddr(   {axi_ram_awaddr[AXI_ADDR_WIDTH-1:0]}),
-    .s_axi_awlen(    {axi_ram_awlen[7:0]}),
-    .s_axi_awsize(   {axi_ram_awsize[2:0]}),
-    .s_axi_awburst(  {axi_ram_awburst[1:0]}),
-    .s_axi_awlock(   {axi_ram_awlock[0]}),
-    .s_axi_awcache(  {axi_ram_awcache[3:0]}),
-    .s_axi_awprot(   {axi_ram_awprot[2:0]}),
-    .s_axi_awqos(0),
-    .s_axi_awuser(0),
-    .s_axi_awvalid(  {axi_ram_awvalid[0]}),
-    .s_axi_awready(  {axi_ram_awready[0]}),
-    .s_axi_wdata(    {axi_ram_wdata[AXI_DATA_WIDTH-1:0]}),
-    .s_axi_wstrb(    {axi_ram_wstrb[AXI_STRB_WIDTH-1:0]}),
-    .s_axi_wlast(    {axi_ram_wlast[0]}),
-    .s_axi_wuser(0),
-    .s_axi_wvalid(   {axi_ram_wvalid[0]}),
-    .s_axi_wready(   {axi_ram_wready[0]}),
-    .s_axi_bid(      {axi_ram_bid[RAM_ID_WIDTH-1:0]}),
-    .s_axi_bresp(    {axi_ram_bresp[1:0]}),
-    .s_axi_buser(),
-    .s_axi_bvalid(   {axi_ram_bvalid[0]}),
-    .s_axi_bready(   {axi_ram_bready[0]}),
-    .s_axi_arid(     {axi_ram_arid[RAM_ID_WIDTH-1:0]}),
-    .s_axi_araddr(   {axi_ram_araddr[AXI_ADDR_WIDTH-1:0]}),
-    .s_axi_arlen(    {axi_ram_arlen[7:0]}),
-    .s_axi_arsize(   {axi_ram_arsize[2:0]}),
-    .s_axi_arburst(  {axi_ram_arburst[1:0]}),
-    .s_axi_arlock(   {axi_ram_arlock[0]}),
-    .s_axi_arcache(  {axi_ram_arcache[3:0]}),
-    .s_axi_arprot(   {axi_ram_arprot[2:0]}),
-    .s_axi_arqos(0),
-    .s_axi_aruser(0),
-    .s_axi_arvalid(  {axi_ram_arvalid[0]}),
-    .s_axi_arready(  {axi_ram_arready[0]}),
-    .s_axi_rid(      {axi_ram_rid[RAM_ID_WIDTH-1:0]}),
-    .s_axi_rdata(    {axi_ram_rdata[AXI_DATA_WIDTH-1:0]}),
-    .s_axi_rresp(    {axi_ram_rresp[1:0]}),
-    .s_axi_rlast(    {axi_ram_rlast[0]}),
-    .s_axi_ruser(),
-    .s_axi_rvalid(   {axi_ram_rvalid[0]}),
-    .s_axi_rready(   {axi_ram_rready[0]}),
-
-    .m_axi_awid(     {axi_port_desc_awid,     axi_event_awid}),
-    .m_axi_awaddr(   {axi_port_desc_awaddr,   axi_event_awaddr}),
-    .m_axi_awlen(    {axi_port_desc_awlen,    axi_event_awlen}),
-    .m_axi_awsize(   {axi_port_desc_awsize,   axi_event_awsize}),
-    .m_axi_awburst(  {axi_port_desc_awburst,  axi_event_awburst}),
-    .m_axi_awlock(   {axi_port_desc_awlock,   axi_event_awlock}),
-    .m_axi_awcache(  {axi_port_desc_awcache,  axi_event_awcache}),
-    .m_axi_awprot(   {axi_port_desc_awprot,   axi_event_awprot}),
-    .m_axi_awqos(),
-    .m_axi_awuser(),
-    .m_axi_awvalid(  {axi_port_desc_awvalid,  axi_event_awvalid}),
-    .m_axi_awready(  {axi_port_desc_awready,  axi_event_awready}),
-    .m_axi_wdata(    {axi_port_desc_wdata,    axi_event_wdata}),
-    .m_axi_wstrb(    {axi_port_desc_wstrb,    axi_event_wstrb}),
-    .m_axi_wlast(    {axi_port_desc_wlast,    axi_event_wlast}),
-    .m_axi_wuser(),
-    .m_axi_wvalid(   {axi_port_desc_wvalid,   axi_event_wvalid}),
-    .m_axi_wready(   {axi_port_desc_wready,   axi_event_wready}),
-    .m_axi_bid(      {axi_port_desc_bid,      axi_event_bid}),
-    .m_axi_bresp(    {axi_port_desc_bresp,    axi_event_bresp}),
-    .m_axi_buser(0),
-    .m_axi_bvalid(   {axi_port_desc_bvalid,   axi_event_bvalid}),
-    .m_axi_bready(   {axi_port_desc_bready,   axi_event_bready}),
-    .m_axi_arid(     {axi_port_desc_arid,     axi_event_arid}),
-    .m_axi_araddr(   {axi_port_desc_araddr,   axi_event_araddr}),
-    .m_axi_arlen(    {axi_port_desc_arlen,    axi_event_arlen}),
-    .m_axi_arsize(   {axi_port_desc_arsize,   axi_event_arsize}),
-    .m_axi_arburst(  {axi_port_desc_arburst,  axi_event_arburst}),
-    .m_axi_arlock(   {axi_port_desc_arlock,   axi_event_arlock}),
-    .m_axi_arcache(  {axi_port_desc_arcache,  axi_event_arcache}),
-    .m_axi_arprot(   {axi_port_desc_arprot,   axi_event_arprot}),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(  {axi_port_desc_arvalid,  axi_event_arvalid}),
-    .m_axi_arready(  {axi_port_desc_arready,  axi_event_arready}),
-    .m_axi_rid(      {axi_port_desc_rid,      axi_event_rid}),
-    .m_axi_rdata(    {axi_port_desc_rdata,    axi_event_rdata}),
-    .m_axi_rresp(    {axi_port_desc_rresp,    axi_event_rresp}),
-    .m_axi_rlast(    {axi_port_desc_rlast,    axi_event_rlast}),
-    .m_axi_ruser(0),
-    .m_axi_rvalid(   {axi_port_desc_rvalid,   axi_event_rvalid}),
-    .m_axi_rready(   {axi_port_desc_rready,   axi_event_rready})
-);
+assign axi_desc_awid = axi_ram_awid[RAM_ID_WIDTH-1:0];
+assign axi_desc_awaddr = axi_ram_awaddr[AXI_ADDR_WIDTH-1:0];
+assign axi_desc_awlen = axi_ram_awlen[7:0];
+assign axi_desc_awsize = axi_ram_awsize[2:0];
+assign axi_desc_awburst = axi_ram_awburst[1:0];
+assign axi_desc_awlock = axi_ram_awlock[0];
+assign axi_desc_awcache = axi_ram_awcache[3:0];
+assign axi_desc_awprot = axi_ram_awprot[2:0];
+assign axi_desc_awvalid = axi_ram_awvalid[0];
+assign axi_ram_awready[0] = axi_desc_awready;
+assign axi_desc_wdata = axi_ram_wdata[AXI_DATA_WIDTH-1:0];
+assign axi_desc_wstrb = axi_ram_wstrb[AXI_STRB_WIDTH-1:0];
+assign axi_desc_wlast = axi_ram_wlast[0];
+assign axi_desc_wvalid = axi_ram_wvalid[0];
+assign axi_ram_wready[0] = axi_desc_wready;
+assign axi_ram_bid[RAM_ID_WIDTH-1:0] = axi_desc_bid;
+assign axi_ram_bresp[1:0] = axi_desc_bresp;
+assign axi_ram_bvalid[0] = axi_desc_bvalid;
+assign axi_desc_bready = axi_ram_bready[0];
+assign axi_desc_arid = axi_ram_arid[RAM_ID_WIDTH-1:0];
+assign axi_desc_araddr = axi_ram_araddr[AXI_ADDR_WIDTH-1:0];
+assign axi_desc_arlen = axi_ram_arlen[7:0];
+assign axi_desc_arsize = axi_ram_arsize[2:0];
+assign axi_desc_arburst = axi_ram_arburst[1:0];
+assign axi_desc_arlock = axi_ram_arlock[0];
+assign axi_desc_arcache = axi_ram_arcache[3:0];
+assign axi_desc_arprot = axi_ram_arprot[2:0];
+assign axi_desc_arvalid = axi_ram_arvalid[0];
+assign axi_ram_arready[0] = axi_desc_arready;
+assign axi_ram_rid[RAM_ID_WIDTH-1:0] = axi_desc_rid;
+assign axi_ram_rdata[AXI_DATA_WIDTH-1:0] = axi_desc_rdata;
+assign axi_ram_rresp[1:0] = axi_desc_rresp;
+assign axi_ram_rlast[0] = axi_desc_rlast;
+assign axi_ram_rvalid[0] = axi_desc_rvalid;
+assign axi_desc_rready = axi_ram_rready[0];
 
 generate
     genvar n;
 
     for (n = 0; n < PORTS; n = n + 1) begin : port
 
+        assign port_cpl_req_sel[n*2+1 +: 1] = 1'b0;
+
         port #(
             .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
             .PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
             .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
             .REQ_TAG_WIDTH(REQ_TAG_WIDTH),
+            .DESC_REQ_TAG_WIDTH(PORT_DESC_REQ_TAG_WIDTH),
             .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
             .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
             .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
             .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
+            .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
             .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
             .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
+            .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH),
             .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
             .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
             .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
@@ -2406,40 +2199,62 @@ generate
             .TX_RAM_AXI_BASE_ADDR(23'h000000 + 23'h010000),
             .RX_RAM_AXI_BASE_ADDR(23'h000000 + 23'h020000),
             .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
-            .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
+            .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+            .DESC_SIZE(DESC_SIZE),
+            .CPL_SIZE(CPL_SIZE)
         )
         port_inst (
             .clk(clk),
             .rst(rst),
 
             /*
-             * TX descriptor dequeue request output
+             * Descriptor request output
              */
-            .m_axis_tx_desc_dequeue_req_queue(tx_port_desc_dequeue_req_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]),
-            .m_axis_tx_desc_dequeue_req_tag(tx_port_desc_dequeue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .m_axis_tx_desc_dequeue_req_valid(tx_port_desc_dequeue_req_valid[n +: 1]),
-            .m_axis_tx_desc_dequeue_req_ready(tx_port_desc_dequeue_req_ready[n +: 1]),
+            .m_axis_desc_req_sel(port_desc_req_sel[n*1 +: 1]),
+            .m_axis_desc_req_queue(port_desc_req_queue[n*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH]),
+            .m_axis_desc_req_tag(port_desc_req_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]),
+            .m_axis_desc_req_valid(port_desc_req_valid[n +: 1]),
+            .m_axis_desc_req_ready(port_desc_req_ready[n +: 1]),
 
             /*
-             * TX descriptor dequeue response input
+             * Descriptor response input
              */
-            .s_axis_tx_desc_dequeue_resp_queue(tx_port_desc_dequeue_resp_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]),
-            .s_axis_tx_desc_dequeue_resp_ptr(tx_port_desc_dequeue_resp_ptr[n*QUEUE_PTR_WIDTH +: QUEUE_PTR_WIDTH]),
-            .s_axis_tx_desc_dequeue_resp_addr(tx_port_desc_dequeue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
-            .s_axis_tx_desc_dequeue_resp_cpl(tx_port_desc_dequeue_resp_cpl[n*TX_CPL_QUEUE_INDEX_WIDTH +: TX_CPL_QUEUE_INDEX_WIDTH]),
-            .s_axis_tx_desc_dequeue_resp_tag(tx_port_desc_dequeue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .s_axis_tx_desc_dequeue_resp_op_tag(tx_port_desc_dequeue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .s_axis_tx_desc_dequeue_resp_empty(tx_port_desc_dequeue_resp_empty[n +: 1]),
-            .s_axis_tx_desc_dequeue_resp_error(tx_port_desc_dequeue_resp_error[n +: 1]),
-            .s_axis_tx_desc_dequeue_resp_valid(tx_port_desc_dequeue_resp_valid[n +: 1]),
-            .s_axis_tx_desc_dequeue_resp_ready(tx_port_desc_dequeue_resp_ready[n +: 1]),
+            .s_axis_desc_req_status_queue(port_desc_req_status_queue[n*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH]),
+            .s_axis_desc_req_status_ptr(port_desc_req_status_ptr[n*QUEUE_PTR_WIDTH +: QUEUE_PTR_WIDTH]),
+            .s_axis_desc_req_status_cpl(port_desc_req_status_cpl[n*CPL_QUEUE_INDEX_WIDTH +: CPL_QUEUE_INDEX_WIDTH]),
+            .s_axis_desc_req_status_tag(port_desc_req_status_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]),
+            .s_axis_desc_req_status_empty(port_desc_req_status_empty[n +: 1]),
+            .s_axis_desc_req_status_error(port_desc_req_status_error[n +: 1]),
+            .s_axis_desc_req_status_valid(port_desc_req_status_valid[n +: 1]),
 
             /*
-             * TX descriptor dequeue commit output
+             * Descriptor data input
              */
-            .m_axis_tx_desc_dequeue_commit_op_tag(tx_port_desc_dequeue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .m_axis_tx_desc_dequeue_commit_valid(tx_port_desc_dequeue_commit_valid[n +: 1]),
-            .m_axis_tx_desc_dequeue_commit_ready(tx_port_desc_dequeue_commit_ready[n +: 1]),
+            .s_axis_desc_tdata(port_desc_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
+            .s_axis_desc_tkeep(port_desc_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
+            .s_axis_desc_tvalid(port_desc_tvalid[n +: 1]),
+            .s_axis_desc_tready(port_desc_tready[n +: 1]),
+            .s_axis_desc_tlast(port_desc_tlast[n +: 1]),
+            .s_axis_desc_tid(port_desc_tid[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]),
+            .s_axis_desc_tuser(port_desc_tuser[n +: 1]),
+
+            /*
+             * Completion request output
+             */
+            .m_axis_cpl_req_sel(port_cpl_req_sel[n*2 +: 1]),
+            .m_axis_cpl_req_queue(port_cpl_req_queue[n*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH]),
+            .m_axis_cpl_req_tag(port_cpl_req_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]),
+            .m_axis_cpl_req_data(port_cpl_req_data[n*CPL_SIZE*8 +: CPL_SIZE*8]),
+            .m_axis_cpl_req_valid(port_cpl_req_valid[n +: 1]),
+            .m_axis_cpl_req_ready(port_cpl_req_ready[n +: 1]),
+
+            /*
+             * Completion response input
+             */
+            .s_axis_cpl_req_status_tag(port_cpl_req_status_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]),
+            .s_axis_cpl_req_status_full(port_cpl_req_status_full[n +: 1]),
+            .s_axis_cpl_req_status_error(port_cpl_req_status_error[n +: 1]),
+            .s_axis_cpl_req_status_valid(port_cpl_req_status_valid[n +: 1]),
 
             /*
              * TX doorbell input
@@ -2447,91 +2262,6 @@ generate
             .s_axis_tx_doorbell_queue(tx_doorbell_queue),
             .s_axis_tx_doorbell_valid(tx_doorbell_valid),
 
-            /*
-             * TX completion enqueue request output
-             */
-            .m_axis_tx_cpl_enqueue_req_queue(tx_port_cpl_enqueue_req_queue[n*TX_CPL_QUEUE_INDEX_WIDTH +: TX_CPL_QUEUE_INDEX_WIDTH]),
-            .m_axis_tx_cpl_enqueue_req_tag(tx_port_cpl_enqueue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .m_axis_tx_cpl_enqueue_req_valid(tx_port_cpl_enqueue_req_valid[n +: 1]),
-            .m_axis_tx_cpl_enqueue_req_ready(tx_port_cpl_enqueue_req_ready[n +: 1]),
-
-            /*
-             * TX completion enqueue response input
-             */
-            //.s_axis_tx_cpl_enqueue_resp_ptr(),
-            .s_axis_tx_cpl_enqueue_resp_addr(tx_port_cpl_enqueue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
-            //.s_axis_tx_cpl_enqueue_resp_event(),
-            .s_axis_tx_cpl_enqueue_resp_tag(tx_port_cpl_enqueue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .s_axis_tx_cpl_enqueue_resp_op_tag(tx_port_cpl_enqueue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .s_axis_tx_cpl_enqueue_resp_full(tx_port_cpl_enqueue_resp_full[n +: 1]),
-            .s_axis_tx_cpl_enqueue_resp_error(tx_port_cpl_enqueue_resp_error[n +: 1]),
-            .s_axis_tx_cpl_enqueue_resp_valid(tx_port_cpl_enqueue_resp_valid[n +: 1]),
-            .s_axis_tx_cpl_enqueue_resp_ready(tx_port_cpl_enqueue_resp_ready[n +: 1]),
-
-            /*
-             * TX completion enqueue commit output
-             */
-            .m_axis_tx_cpl_enqueue_commit_op_tag(tx_port_cpl_enqueue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .m_axis_tx_cpl_enqueue_commit_valid(tx_port_cpl_enqueue_commit_valid[n +: 1]),
-            .m_axis_tx_cpl_enqueue_commit_ready(tx_port_cpl_enqueue_commit_ready[n +: 1]),
-
-            /*
-             * RX descriptor dequeue request output
-             */
-            .m_axis_rx_desc_dequeue_req_queue(rx_port_desc_dequeue_req_queue[n*RX_QUEUE_INDEX_WIDTH +: RX_QUEUE_INDEX_WIDTH]),
-            .m_axis_rx_desc_dequeue_req_tag(rx_port_desc_dequeue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .m_axis_rx_desc_dequeue_req_valid(rx_port_desc_dequeue_req_valid[n +: 1]),
-            .m_axis_rx_desc_dequeue_req_ready(rx_port_desc_dequeue_req_ready[n +: 1]),
-
-            /*
-             * RX descriptor dequeue response input
-             */
-            .s_axis_rx_desc_dequeue_resp_queue(rx_port_desc_dequeue_resp_queue[n*RX_QUEUE_INDEX_WIDTH +: RX_QUEUE_INDEX_WIDTH]),
-            .s_axis_rx_desc_dequeue_resp_ptr(rx_port_desc_dequeue_resp_ptr[n*QUEUE_PTR_WIDTH +: QUEUE_PTR_WIDTH]),
-            .s_axis_rx_desc_dequeue_resp_addr(rx_port_desc_dequeue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
-            .s_axis_rx_desc_dequeue_resp_cpl(rx_port_desc_dequeue_resp_cpl[n*RX_CPL_QUEUE_INDEX_WIDTH +: RX_CPL_QUEUE_INDEX_WIDTH]),
-            .s_axis_rx_desc_dequeue_resp_tag(rx_port_desc_dequeue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .s_axis_rx_desc_dequeue_resp_op_tag(rx_port_desc_dequeue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .s_axis_rx_desc_dequeue_resp_empty(rx_port_desc_dequeue_resp_empty[n +: 1]),
-            .s_axis_rx_desc_dequeue_resp_error(rx_port_desc_dequeue_resp_error[n +: 1]),
-            .s_axis_rx_desc_dequeue_resp_valid(rx_port_desc_dequeue_resp_valid[n +: 1]),
-            .s_axis_rx_desc_dequeue_resp_ready(rx_port_desc_dequeue_resp_ready[n +: 1]),
-
-            /*
-             * RX descriptor dequeue commit output
-             */
-            .m_axis_rx_desc_dequeue_commit_op_tag(rx_port_desc_dequeue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .m_axis_rx_desc_dequeue_commit_valid(rx_port_desc_dequeue_commit_valid[n +: 1]),
-            .m_axis_rx_desc_dequeue_commit_ready(rx_port_desc_dequeue_commit_ready[n +: 1]),
-
-            /*
-             * RX completion enqueue request output
-             */
-            .m_axis_rx_cpl_enqueue_req_queue(rx_port_cpl_enqueue_req_queue[n*RX_CPL_QUEUE_INDEX_WIDTH +: RX_CPL_QUEUE_INDEX_WIDTH]),
-            .m_axis_rx_cpl_enqueue_req_tag(rx_port_cpl_enqueue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .m_axis_rx_cpl_enqueue_req_valid(rx_port_cpl_enqueue_req_valid[n +: 1]),
-            .m_axis_rx_cpl_enqueue_req_ready(rx_port_cpl_enqueue_req_ready[n +: 1]),
-
-            /*
-             * RX completion enqueue response input
-             */
-            //.s_axis_rx_cpl_enqueue_resp_ptr(),
-            .s_axis_rx_cpl_enqueue_resp_addr(rx_port_cpl_enqueue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
-            //.s_axis_rx_cpl_enqueue_resp_event(),
-            .s_axis_rx_cpl_enqueue_resp_tag(rx_port_cpl_enqueue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
-            .s_axis_rx_cpl_enqueue_resp_op_tag(rx_port_cpl_enqueue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .s_axis_rx_cpl_enqueue_resp_full(rx_port_cpl_enqueue_resp_full[n +: 1]),
-            .s_axis_rx_cpl_enqueue_resp_error(rx_port_cpl_enqueue_resp_error[n +: 1]),
-            .s_axis_rx_cpl_enqueue_resp_valid(rx_port_cpl_enqueue_resp_valid[n +: 1]),
-            .s_axis_rx_cpl_enqueue_resp_ready(rx_port_cpl_enqueue_resp_ready[n +: 1]),
-
-            /*
-             * RX completion enqueue commit output
-             */
-            .m_axis_rx_cpl_enqueue_commit_op_tag(rx_port_cpl_enqueue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
-            .m_axis_rx_cpl_enqueue_commit_valid(rx_port_cpl_enqueue_commit_valid[n +: 1]),
-            .m_axis_rx_cpl_enqueue_commit_ready(rx_port_cpl_enqueue_commit_ready[n +: 1]),
-
             /*
              * PCIe read descriptor output
              */
@@ -2626,45 +2356,6 @@ generate
             .m_axi_rvalid(axi_port_dma_rvalid[n +: 1]),
             .m_axi_rready(axi_port_dma_rready[n +: 1]),
 
-            /*
-             * AXI slave inteface
-             */
-            .s_axi_awid(axi_port_desc_awid[n*RAM_ID_WIDTH +: RAM_ID_WIDTH]),
-            .s_axi_awaddr(axi_port_desc_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
-            .s_axi_awlen(axi_port_desc_awlen[n*8 +: 8]),
-            .s_axi_awsize(axi_port_desc_awsize[n*3 +: 3]),
-            .s_axi_awburst(axi_port_desc_awburst[n*2 +: 2]),
-            .s_axi_awlock(axi_port_desc_awlock[n +: 1]),
-            .s_axi_awcache(axi_port_desc_awcache[n*4 +: 4]),
-            .s_axi_awprot(axi_port_desc_awprot[n*3 +: 3]),
-            .s_axi_awvalid(axi_port_desc_awvalid[n +: 1]),
-            .s_axi_awready(axi_port_desc_awready[n +: 1]),
-            .s_axi_wdata(axi_port_desc_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
-            .s_axi_wstrb(axi_port_desc_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]),
-            .s_axi_wlast(axi_port_desc_wlast[n +: 1]),
-            .s_axi_wvalid(axi_port_desc_wvalid[n +: 1]),
-            .s_axi_wready(axi_port_desc_wready[n +: 1]),
-            .s_axi_bid(axi_port_desc_bid[n*RAM_ID_WIDTH +: RAM_ID_WIDTH]),
-            .s_axi_bresp(axi_port_desc_bresp[n*2 +: 2]),
-            .s_axi_bvalid(axi_port_desc_bvalid[n +: 1]),
-            .s_axi_bready(axi_port_desc_bready[n +: 1]),
-            .s_axi_arid(axi_port_desc_arid[n*RAM_ID_WIDTH +: RAM_ID_WIDTH]),
-            .s_axi_araddr(axi_port_desc_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]),
-            .s_axi_arlen(axi_port_desc_arlen[n*8 +: 8]),
-            .s_axi_arsize(axi_port_desc_arsize[n*3 +: 3]),
-            .s_axi_arburst(axi_port_desc_arburst[n*2 +: 2]),
-            .s_axi_arlock(axi_port_desc_arlock[n +: 1]),
-            .s_axi_arcache(axi_port_desc_arcache[n*4 +: 4]),
-            .s_axi_arprot(axi_port_desc_arprot[n*3 +: 3]),
-            .s_axi_arvalid(axi_port_desc_arvalid[n +: 1]),
-            .s_axi_arready(axi_port_desc_arready[n +: 1]),
-            .s_axi_rid(axi_port_desc_rid[n*RAM_ID_WIDTH +: RAM_ID_WIDTH]),
-            .s_axi_rdata(axi_port_desc_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]),
-            .s_axi_rresp(axi_port_desc_rresp[n*2 +: 2]),
-            .s_axi_rlast(axi_port_desc_rlast[n +: 1]),
-            .s_axi_rvalid(axi_port_desc_rvalid[n +: 1]),
-            .s_axi_rready(axi_port_desc_rready[n +: 1]),
-
             /*
              * Transmit data output
              */
diff --git a/fpga/common/rtl/port.v b/fpga/common/rtl/port.v
index 6a931417b..1a8bd69ae 100644
--- a/fpga/common/rtl/port.v
+++ b/fpga/common/rtl/port.v
@@ -48,6 +48,8 @@ module port #
     parameter PCIE_DMA_TAG_WIDTH = 8,
     // Request tag field width
     parameter REQ_TAG_WIDTH = 8,
+    // Descriptor request tag field width
+    parameter DESC_REQ_TAG_WIDTH = 8,
     // Queue request tag field width
     parameter QUEUE_REQ_TAG_WIDTH = 8,
     // Queue operation tag field width
@@ -56,10 +58,14 @@ module port #
     parameter TX_QUEUE_INDEX_WIDTH = 8,
     // Receive queue index width
     parameter RX_QUEUE_INDEX_WIDTH = 8,
+    // Max queue index width
+    parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH,
     // Transmit completion queue index width
     parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
     // Receive completion queue index width
     parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
+    // Max completion queue index width
+    parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH,
     // Transmit descriptor table size (number of in-flight operations)
     parameter TX_DESC_TABLE_SIZE = 16,
     // Transmit packet table size (number of in-progress packets)
@@ -109,40 +115,64 @@ module port #
     // Width of AXI stream interfaces in bits
     parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
     // AXI stream tkeep signal width (words per cycle)
-    parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH
+    parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
+    // Descriptor size (in bytes)
+    parameter DESC_SIZE = 16,
+    // Descriptor size (in bytes)
+    parameter CPL_SIZE = 32
 )
 (
     input  wire                                 clk,
     input  wire                                 rst,
 
     /*
-     * TX descriptor dequeue request output
+     * Descriptor request output
      */
-    output wire [TX_QUEUE_INDEX_WIDTH-1:0]      m_axis_tx_desc_dequeue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]       m_axis_tx_desc_dequeue_req_tag,
-    output wire                                 m_axis_tx_desc_dequeue_req_valid,
-    input  wire                                 m_axis_tx_desc_dequeue_req_ready,
+    output wire [0:0]                           m_axis_desc_req_sel,
+    output wire [QUEUE_INDEX_WIDTH-1:0]         m_axis_desc_req_queue,
+    output wire [DESC_REQ_TAG_WIDTH-1:0]        m_axis_desc_req_tag,
+    output wire                                 m_axis_desc_req_valid,
+    input  wire                                 m_axis_desc_req_ready,
 
     /*
-     * TX descriptor dequeue response input
+     * Descriptor request status input
      */
-    input  wire [TX_QUEUE_INDEX_WIDTH-1:0]      s_axis_tx_desc_dequeue_resp_queue,
-    input  wire [QUEUE_PTR_WIDTH-1:0]           s_axis_tx_desc_dequeue_resp_ptr,
-    input  wire [PCIE_ADDR_WIDTH-1:0]           s_axis_tx_desc_dequeue_resp_addr,
-    input  wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0]  s_axis_tx_desc_dequeue_resp_cpl,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]       s_axis_tx_desc_dequeue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]        s_axis_tx_desc_dequeue_resp_op_tag,
-    input  wire                                 s_axis_tx_desc_dequeue_resp_empty,
-    input  wire                                 s_axis_tx_desc_dequeue_resp_error,
-    input  wire                                 s_axis_tx_desc_dequeue_resp_valid,
-    output wire                                 s_axis_tx_desc_dequeue_resp_ready,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]         s_axis_desc_req_status_queue,
+    input  wire [QUEUE_PTR_WIDTH-1:0]           s_axis_desc_req_status_ptr,
+    input  wire [CPL_QUEUE_INDEX_WIDTH-1:0]     s_axis_desc_req_status_cpl,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]        s_axis_desc_req_status_tag,
+    input  wire                                 s_axis_desc_req_status_empty,
+    input  wire                                 s_axis_desc_req_status_error,
+    input  wire                                 s_axis_desc_req_status_valid,
 
     /*
-     * TX descriptor dequeue commit output
+     * Descriptor data input
      */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]        m_axis_tx_desc_dequeue_commit_op_tag,
-    output wire                                 m_axis_tx_desc_dequeue_commit_valid,
-    input  wire                                 m_axis_tx_desc_dequeue_commit_ready,
+    input  wire [AXIS_DATA_WIDTH-1:0]           s_axis_desc_tdata,
+    input  wire [AXIS_KEEP_WIDTH-1:0]           s_axis_desc_tkeep,
+    input  wire                                 s_axis_desc_tvalid,
+    output wire                                 s_axis_desc_tready,
+    input  wire                                 s_axis_desc_tlast,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]        s_axis_desc_tid,
+    input  wire                                 s_axis_desc_tuser,
+
+    /*
+     * Completion request output
+     */
+    output wire [0:0]                           m_axis_cpl_req_sel,
+    output wire [QUEUE_INDEX_WIDTH-1:0]         m_axis_cpl_req_queue,
+    output wire [DESC_REQ_TAG_WIDTH-1:0]        m_axis_cpl_req_tag,
+    output wire [CPL_SIZE*8-1:0]                m_axis_cpl_req_data,
+    output wire                                 m_axis_cpl_req_valid,
+    input  wire                                 m_axis_cpl_req_ready,
+
+    /*
+     * Completion request status input
+     */
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]        s_axis_cpl_req_status_tag,
+    input  wire                                 s_axis_cpl_req_status_full,
+    input  wire                                 s_axis_cpl_req_status_error,
+    input  wire                                 s_axis_cpl_req_status_valid,
 
     /*
      * TX doorbell input
@@ -150,91 +180,6 @@ module port #
     input  wire [TX_QUEUE_INDEX_WIDTH-1:0]      s_axis_tx_doorbell_queue,
     input  wire                                 s_axis_tx_doorbell_valid,
 
-    /*
-     * TX completion enqueue request output
-     */
-    output wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0]  m_axis_tx_cpl_enqueue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]       m_axis_tx_cpl_enqueue_req_tag,
-    output wire                                 m_axis_tx_cpl_enqueue_req_valid,
-    input  wire                                 m_axis_tx_cpl_enqueue_req_ready,
-
-    /*
-     * TX completion enqueue response input
-     */
-    //input  wire [QUEUE_PTR_WIDTH-1:0]           s_axis_tx_cpl_enqueue_resp_ptr,
-    input  wire [PCIE_ADDR_WIDTH-1:0]           s_axis_tx_cpl_enqueue_resp_addr,
-    //input  wire [EVENT_WIDTH-1:0]               s_axis_tx_cpl_enqueue_resp_event,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]       s_axis_tx_cpl_enqueue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]        s_axis_tx_cpl_enqueue_resp_op_tag,
-    input  wire                                 s_axis_tx_cpl_enqueue_resp_full,
-    input  wire                                 s_axis_tx_cpl_enqueue_resp_error,
-    input  wire                                 s_axis_tx_cpl_enqueue_resp_valid,
-    output wire                                 s_axis_tx_cpl_enqueue_resp_ready,
-
-    /*
-     * TX completion enqueue commit output
-     */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]        m_axis_tx_cpl_enqueue_commit_op_tag,
-    output wire                                 m_axis_tx_cpl_enqueue_commit_valid,
-    input  wire                                 m_axis_tx_cpl_enqueue_commit_ready,
-
-    /*
-     * RX descriptor dequeue request output
-     */
-    output wire [RX_QUEUE_INDEX_WIDTH-1:0]      m_axis_rx_desc_dequeue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]       m_axis_rx_desc_dequeue_req_tag,
-    output wire                                 m_axis_rx_desc_dequeue_req_valid,
-    input  wire                                 m_axis_rx_desc_dequeue_req_ready,
-
-    /*
-     * RX descriptor dequeue response input
-     */
-    input  wire [RX_QUEUE_INDEX_WIDTH-1:0]      s_axis_rx_desc_dequeue_resp_queue,
-    input  wire [QUEUE_PTR_WIDTH-1:0]           s_axis_rx_desc_dequeue_resp_ptr,
-    input  wire [PCIE_ADDR_WIDTH-1:0]           s_axis_rx_desc_dequeue_resp_addr,
-    input  wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0]  s_axis_rx_desc_dequeue_resp_cpl,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]       s_axis_rx_desc_dequeue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]        s_axis_rx_desc_dequeue_resp_op_tag,
-    input  wire                                 s_axis_rx_desc_dequeue_resp_empty,
-    input  wire                                 s_axis_rx_desc_dequeue_resp_error,
-    input  wire                                 s_axis_rx_desc_dequeue_resp_valid,
-    output wire                                 s_axis_rx_desc_dequeue_resp_ready,
-
-    /*
-     * RX descriptor dequeue commit output
-     */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]        m_axis_rx_desc_dequeue_commit_op_tag,
-    output wire                                 m_axis_rx_desc_dequeue_commit_valid,
-    input  wire                                 m_axis_rx_desc_dequeue_commit_ready,
-
-    /*
-     * RX completion enqueue request output
-     */
-    output wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0]  m_axis_rx_cpl_enqueue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]       m_axis_rx_cpl_enqueue_req_tag,
-    output wire                                 m_axis_rx_cpl_enqueue_req_valid,
-    input  wire                                 m_axis_rx_cpl_enqueue_req_ready,
-
-    /*
-     * RX completion enqueue response input
-     */
-    //input  wire [QUEUE_PTR_WIDTH-1:0]           s_axis_rx_cpl_enqueue_resp_ptr,
-    input  wire [PCIE_ADDR_WIDTH-1:0]           s_axis_rx_cpl_enqueue_resp_addr,
-    //input  wire [EVENT_WIDTH-1:0]               s_axis_rx_cpl_enqueue_resp_event,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]       s_axis_rx_cpl_enqueue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]        s_axis_rx_cpl_enqueue_resp_op_tag,
-    input  wire                                 s_axis_rx_cpl_enqueue_resp_full,
-    input  wire                                 s_axis_rx_cpl_enqueue_resp_error,
-    input  wire                                 s_axis_rx_cpl_enqueue_resp_valid,
-    output wire                                 s_axis_rx_cpl_enqueue_resp_ready,
-
-    /*
-     * RX completion enqueue commit output
-     */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]        m_axis_rx_cpl_enqueue_commit_op_tag,
-    output wire                                 m_axis_rx_cpl_enqueue_commit_valid,
-    input  wire                                 m_axis_rx_cpl_enqueue_commit_ready,
-
     /*
      * PCIe read descriptor output
      */
@@ -329,45 +274,6 @@ module port #
     input  wire                                 m_axi_rvalid,
     output wire                                 m_axi_rready,
 
-    /*
-     * AXI slave inteface
-     */
-    input  wire [AXI_ID_WIDTH-1:0]              s_axi_awid,
-    input  wire [AXI_ADDR_WIDTH-1:0]            s_axi_awaddr,
-    input  wire [7:0]                           s_axi_awlen,
-    input  wire [2:0]                           s_axi_awsize,
-    input  wire [1:0]                           s_axi_awburst,
-    input  wire                                 s_axi_awlock,
-    input  wire [3:0]                           s_axi_awcache,
-    input  wire [2:0]                           s_axi_awprot,
-    input  wire                                 s_axi_awvalid,
-    output wire                                 s_axi_awready,
-    input  wire [AXI_DATA_WIDTH-1:0]            s_axi_wdata,
-    input  wire [AXI_STRB_WIDTH-1:0]            s_axi_wstrb,
-    input  wire                                 s_axi_wlast,
-    input  wire                                 s_axi_wvalid,
-    output wire                                 s_axi_wready,
-    output wire [AXI_ID_WIDTH-1:0]              s_axi_bid,
-    output wire [1:0]                           s_axi_bresp,
-    output wire                                 s_axi_bvalid,
-    input  wire                                 s_axi_bready,
-    input  wire [AXI_ID_WIDTH-1:0]              s_axi_arid,
-    input  wire [AXI_ADDR_WIDTH-1:0]            s_axi_araddr,
-    input  wire [7:0]                           s_axi_arlen,
-    input  wire [2:0]                           s_axi_arsize,
-    input  wire [1:0]                           s_axi_arburst,
-    input  wire                                 s_axi_arlock,
-    input  wire [3:0]                           s_axi_arcache,
-    input  wire [2:0]                           s_axi_arprot,
-    input  wire                                 s_axi_arvalid,
-    output wire                                 s_axi_arready,
-    output wire [AXI_ID_WIDTH-1:0]              s_axi_rid,
-    output wire [AXI_DATA_WIDTH-1:0]            s_axi_rdata,
-    output wire [1:0]                           s_axi_rresp,
-    output wire                                 s_axi_rlast,
-    output wire                                 s_axi_rvalid,
-    input  wire                                 s_axi_rready,
-
     /*
      * Transmit data output
      */
@@ -409,13 +315,10 @@ module port #
     input  wire                                 ptp_ts_step
 );
 
-parameter DESC_SIZE = 16;
-parameter CPL_SIZE = 32;
-
 parameter AXI_DMA_TAG_WIDTH = 8;
 parameter AXI_DMA_LEN_WIDTH = 16;
 
-parameter PCIE_DMA_TAG_WIDTH_INT = PCIE_DMA_TAG_WIDTH - $clog2(2);
+parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(2);
 
 // AXI lite connections
 wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
@@ -458,79 +361,6 @@ wire [1:0]                 axil_sched_rresp;
 wire                       axil_sched_rvalid;
 wire                       axil_sched_rready;
 
-// AXI connections
-wire [AXI_ID_WIDTH-1:0]    axi_tx_awid;
-wire [AXI_ADDR_WIDTH-1:0]  axi_tx_awaddr;
-wire [7:0]                 axi_tx_awlen;
-wire [2:0]                 axi_tx_awsize;
-wire [1:0]                 axi_tx_awburst;
-wire                       axi_tx_awlock;
-wire [3:0]                 axi_tx_awcache;
-wire [2:0]                 axi_tx_awprot;
-wire                       axi_tx_awvalid;
-wire                       axi_tx_awready;
-wire [AXI_DATA_WIDTH-1:0]  axi_tx_wdata;
-wire [AXI_STRB_WIDTH-1:0]  axi_tx_wstrb;
-wire                       axi_tx_wlast;
-wire                       axi_tx_wvalid;
-wire                       axi_tx_wready;
-wire [AXI_ID_WIDTH-1:0]    axi_tx_bid;
-wire [1:0]                 axi_tx_bresp;
-wire                       axi_tx_bvalid;
-wire                       axi_tx_bready;
-wire [AXI_ID_WIDTH-1:0]    axi_tx_arid;
-wire [AXI_ADDR_WIDTH-1:0]  axi_tx_araddr;
-wire [7:0]                 axi_tx_arlen;
-wire [2:0]                 axi_tx_arsize;
-wire [1:0]                 axi_tx_arburst;
-wire                       axi_tx_arlock;
-wire [3:0]                 axi_tx_arcache;
-wire [2:0]                 axi_tx_arprot;
-wire                       axi_tx_arvalid;
-wire                       axi_tx_arready;
-wire [AXI_ID_WIDTH-1:0]    axi_tx_rid;
-wire [AXI_DATA_WIDTH-1:0]  axi_tx_rdata;
-wire [1:0]                 axi_tx_rresp;
-wire                       axi_tx_rlast;
-wire                       axi_tx_rvalid;
-wire                       axi_tx_rready;
-
-wire [AXI_ID_WIDTH-1:0]    axi_rx_awid;
-wire [AXI_ADDR_WIDTH-1:0]  axi_rx_awaddr;
-wire [7:0]                 axi_rx_awlen;
-wire [2:0]                 axi_rx_awsize;
-wire [1:0]                 axi_rx_awburst;
-wire                       axi_rx_awlock;
-wire [3:0]                 axi_rx_awcache;
-wire [2:0]                 axi_rx_awprot;
-wire                       axi_rx_awvalid;
-wire                       axi_rx_awready;
-wire [AXI_DATA_WIDTH-1:0]  axi_rx_wdata;
-wire [AXI_STRB_WIDTH-1:0]  axi_rx_wstrb;
-wire                       axi_rx_wlast;
-wire                       axi_rx_wvalid;
-wire                       axi_rx_wready;
-wire [AXI_ID_WIDTH-1:0]    axi_rx_bid;
-wire [1:0]                 axi_rx_bresp;
-wire                       axi_rx_bvalid;
-wire                       axi_rx_bready;
-wire [AXI_ID_WIDTH-1:0]    axi_rx_arid;
-wire [AXI_ADDR_WIDTH-1:0]  axi_rx_araddr;
-wire [7:0]                 axi_rx_arlen;
-wire [2:0]                 axi_rx_arsize;
-wire [1:0]                 axi_rx_arburst;
-wire                       axi_rx_arlock;
-wire [3:0]                 axi_rx_arcache;
-wire [2:0]                 axi_rx_arprot;
-wire                       axi_rx_arvalid;
-wire                       axi_rx_arready;
-wire [AXI_ID_WIDTH-1:0]    axi_rx_rid;
-wire [AXI_DATA_WIDTH-1:0]  axi_rx_rdata;
-wire [1:0]                 axi_rx_rresp;
-wire                       axi_rx_rlast;
-wire                       axi_rx_rvalid;
-wire                       axi_rx_rready;
-
 // Checksumming
 wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
 wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
@@ -539,46 +369,74 @@ wire                       tx_axis_tready_int;
 wire                       tx_axis_tlast_int;
 wire                       tx_axis_tuser_int;
 
-// PCIe DMA
-wire [PCIE_ADDR_WIDTH-1:0]        tx_pcie_axi_dma_read_desc_pcie_addr;
-wire [AXI_ADDR_WIDTH-1:0]         tx_pcie_axi_dma_read_desc_axi_addr;
-wire [PCIE_DMA_LEN_WIDTH-1:0]     tx_pcie_axi_dma_read_desc_len;
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_read_desc_tag;
-wire                              tx_pcie_axi_dma_read_desc_valid;
-wire                              tx_pcie_axi_dma_read_desc_ready;
+// Descriptor and completion
+wire [0:0]                           rx_desc_req_sel = 1'b1;
+wire [QUEUE_INDEX_WIDTH-1:0]         rx_desc_req_queue;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    rx_desc_req_tag;
+wire                                 rx_desc_req_valid;
+wire                                 rx_desc_req_ready;
 
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_read_desc_status_tag;
-wire                              tx_pcie_axi_dma_read_desc_status_valid;
+wire [QUEUE_INDEX_WIDTH-1:0]         rx_desc_req_status_queue;
+wire [QUEUE_PTR_WIDTH-1:0]           rx_desc_req_status_ptr;
+wire [CPL_QUEUE_INDEX_WIDTH-1:0]     rx_desc_req_status_cpl;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    rx_desc_req_status_tag;
+wire                                 rx_desc_req_status_empty;
+wire                                 rx_desc_req_status_error;
+wire                                 rx_desc_req_status_valid;
 
-wire [PCIE_ADDR_WIDTH-1:0]        tx_pcie_axi_dma_write_desc_pcie_addr;
-wire [AXI_ADDR_WIDTH-1:0]         tx_pcie_axi_dma_write_desc_axi_addr;
-wire [PCIE_DMA_LEN_WIDTH-1:0]     tx_pcie_axi_dma_write_desc_len;
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_write_desc_tag;
-wire                              tx_pcie_axi_dma_write_desc_valid;
-wire                              tx_pcie_axi_dma_write_desc_ready;
+wire [AXIS_DATA_WIDTH-1:0]           rx_desc_tdata;
+wire [AXIS_KEEP_WIDTH-1:0]           rx_desc_tkeep;
+wire                                 rx_desc_tvalid;
+wire                                 rx_desc_tready;
+wire                                 rx_desc_tlast;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    rx_desc_tid;
+wire                                 rx_desc_tuser;
 
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_write_desc_status_tag;
-wire                              tx_pcie_axi_dma_write_desc_status_valid;
+wire [0:0]                           tx_desc_req_sel = 1'b0;
+wire [QUEUE_INDEX_WIDTH-1:0]         tx_desc_req_queue;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    tx_desc_req_tag;
+wire                                 tx_desc_req_valid;
+wire                                 tx_desc_req_ready;
 
-wire [PCIE_ADDR_WIDTH-1:0]        rx_pcie_axi_dma_read_desc_pcie_addr;
-wire [AXI_ADDR_WIDTH-1:0]         rx_pcie_axi_dma_read_desc_axi_addr;
-wire [PCIE_DMA_LEN_WIDTH-1:0]     rx_pcie_axi_dma_read_desc_len;
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_read_desc_tag;
-wire                              rx_pcie_axi_dma_read_desc_valid;
-wire                              rx_pcie_axi_dma_read_desc_ready;
+wire [QUEUE_INDEX_WIDTH-1:0]         tx_desc_req_status_queue;
+wire [QUEUE_PTR_WIDTH-1:0]           tx_desc_req_status_ptr;
+wire [CPL_QUEUE_INDEX_WIDTH-1:0]     tx_desc_req_status_cpl;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    tx_desc_req_status_tag;
+wire                                 tx_desc_req_status_empty;
+wire                                 tx_desc_req_status_error;
+wire                                 tx_desc_req_status_valid;
 
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_read_desc_status_tag;
-wire                              rx_pcie_axi_dma_read_desc_status_valid;
+wire [AXIS_DATA_WIDTH-1:0]           tx_desc_tdata;
+wire [AXIS_KEEP_WIDTH-1:0]           tx_desc_tkeep;
+wire                                 tx_desc_tvalid;
+wire                                 tx_desc_tready;
+wire                                 tx_desc_tlast;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    tx_desc_tid;
+wire                                 tx_desc_tuser;
 
-wire [PCIE_ADDR_WIDTH-1:0]        rx_pcie_axi_dma_write_desc_pcie_addr;
-wire [AXI_ADDR_WIDTH-1:0]         rx_pcie_axi_dma_write_desc_axi_addr;
-wire [PCIE_DMA_LEN_WIDTH-1:0]     rx_pcie_axi_dma_write_desc_len;
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_write_desc_tag;
-wire                              rx_pcie_axi_dma_write_desc_valid;
-wire                              rx_pcie_axi_dma_write_desc_ready;
+wire [0:0]                           rx_cpl_req_sel = 1'b1;
+wire [QUEUE_INDEX_WIDTH-1:0]         rx_cpl_req_queue;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    rx_cpl_req_tag;
+wire [CPL_SIZE*8-1:0]                rx_cpl_req_data;
+wire                                 rx_cpl_req_valid;
+wire                                 rx_cpl_req_ready;
 
-wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_write_desc_status_tag;
-wire                              rx_pcie_axi_dma_write_desc_status_valid;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    rx_cpl_req_status_tag;
+wire                                 rx_cpl_req_status_full;
+wire                                 rx_cpl_req_status_error;
+wire                                 rx_cpl_req_status_valid;
+
+wire [0:0]                           tx_cpl_req_sel = 1'b0;
+wire [QUEUE_INDEX_WIDTH-1:0]         tx_cpl_req_queue;
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    tx_cpl_req_tag;
+wire [CPL_SIZE*8-1:0]                tx_cpl_req_data;
+wire                                 tx_cpl_req_valid;
+wire                                 tx_cpl_req_ready;
+
+wire [DESC_REQ_TAG_WIDTH_INT-1:0]    tx_cpl_req_status_tag;
+wire                                 tx_cpl_req_status_full;
+wire                                 tx_cpl_req_status_error;
+wire                                 tx_cpl_req_status_valid;
 
 // TX engine
 wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_req_queue;
@@ -1129,7 +987,8 @@ tx_engine #(
     .PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
     .AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
     .REQ_TAG_WIDTH(REQ_TAG_WIDTH),
-    .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
+    .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
+    .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
     .AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
     .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
     .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
@@ -1138,7 +997,6 @@ tx_engine #(
     .CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
     .DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
     .PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
-    .AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h004000),
     .SCRATCH_PKT_AXI_ADDR(TX_RAM_AXI_BASE_ADDR),
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE)
@@ -1163,91 +1021,67 @@ tx_engine_inst (
     .m_axis_tx_req_status_valid(tx_req_status_valid),
 
     /*
-     * Descriptor dequeue request output
+     * Descriptor request output
      */
-    .m_axis_desc_dequeue_req_queue(m_axis_tx_desc_dequeue_req_queue),
-    .m_axis_desc_dequeue_req_tag(m_axis_tx_desc_dequeue_req_tag),
-    .m_axis_desc_dequeue_req_valid(m_axis_tx_desc_dequeue_req_valid),
-    .m_axis_desc_dequeue_req_ready(m_axis_tx_desc_dequeue_req_ready),
+    .m_axis_desc_req_queue(tx_desc_req_queue),
+    .m_axis_desc_req_tag(tx_desc_req_tag),
+    .m_axis_desc_req_valid(tx_desc_req_valid),
+    .m_axis_desc_req_ready(tx_desc_req_ready),
 
     /*
-     * Descriptor dequeue response input
+     * Descriptor request status input
      */
-    .s_axis_desc_dequeue_resp_queue(s_axis_tx_desc_dequeue_resp_queue),
-    .s_axis_desc_dequeue_resp_ptr(s_axis_tx_desc_dequeue_resp_ptr),
-    .s_axis_desc_dequeue_resp_addr(s_axis_tx_desc_dequeue_resp_addr),
-    .s_axis_desc_dequeue_resp_cpl(s_axis_tx_desc_dequeue_resp_cpl),
-    .s_axis_desc_dequeue_resp_tag(s_axis_tx_desc_dequeue_resp_tag),
-    .s_axis_desc_dequeue_resp_op_tag(s_axis_tx_desc_dequeue_resp_op_tag),
-    .s_axis_desc_dequeue_resp_empty(s_axis_tx_desc_dequeue_resp_empty),
-    .s_axis_desc_dequeue_resp_error(s_axis_tx_desc_dequeue_resp_error),
-    .s_axis_desc_dequeue_resp_valid(s_axis_tx_desc_dequeue_resp_valid),
-    .s_axis_desc_dequeue_resp_ready(s_axis_tx_desc_dequeue_resp_ready),
+    .s_axis_desc_req_status_queue(tx_desc_req_status_queue),
+    .s_axis_desc_req_status_ptr(tx_desc_req_status_ptr),
+    .s_axis_desc_req_status_cpl(tx_desc_req_status_cpl),
+    .s_axis_desc_req_status_tag(tx_desc_req_status_tag),
+    .s_axis_desc_req_status_empty(tx_desc_req_status_empty),
+    .s_axis_desc_req_status_error(tx_desc_req_status_error),
+    .s_axis_desc_req_status_valid(tx_desc_req_status_valid),
 
     /*
-     * Descriptor dequeue commit output
+     * Descriptor data input
      */
-    .m_axis_desc_dequeue_commit_op_tag(m_axis_tx_desc_dequeue_commit_op_tag),
-    .m_axis_desc_dequeue_commit_valid(m_axis_tx_desc_dequeue_commit_valid),
-    .m_axis_desc_dequeue_commit_ready(m_axis_tx_desc_dequeue_commit_ready),
+    .s_axis_desc_tdata(tx_desc_tdata),
+    .s_axis_desc_tkeep(tx_desc_tkeep),
+    .s_axis_desc_tvalid(tx_desc_tvalid),
+    .s_axis_desc_tready(tx_desc_tready),
+    .s_axis_desc_tlast(tx_desc_tlast),
+    .s_axis_desc_tid(tx_desc_tid),
+    .s_axis_desc_tuser(tx_desc_tuser),
 
     /*
-     * Completion enqueue request output
+     * Completion request output
      */
-    .m_axis_cpl_enqueue_req_queue(m_axis_tx_cpl_enqueue_req_queue),
-    .m_axis_cpl_enqueue_req_tag(m_axis_tx_cpl_enqueue_req_tag),
-    .m_axis_cpl_enqueue_req_valid(m_axis_tx_cpl_enqueue_req_valid),
-    .m_axis_cpl_enqueue_req_ready(m_axis_tx_cpl_enqueue_req_ready),
+    .m_axis_cpl_req_queue(tx_cpl_req_queue),
+    .m_axis_cpl_req_tag(tx_cpl_req_tag),
+    .m_axis_cpl_req_data(tx_cpl_req_data),
+    .m_axis_cpl_req_valid(tx_cpl_req_valid),
+    .m_axis_cpl_req_ready(tx_cpl_req_ready),
 
     /*
-     * Completion enqueue response input
+     * Completion request status input
      */
-    .s_axis_cpl_enqueue_resp_addr(s_axis_tx_cpl_enqueue_resp_addr),
-    .s_axis_cpl_enqueue_resp_tag(s_axis_tx_cpl_enqueue_resp_tag),
-    .s_axis_cpl_enqueue_resp_op_tag(s_axis_tx_cpl_enqueue_resp_op_tag),
-    .s_axis_cpl_enqueue_resp_full(s_axis_tx_cpl_enqueue_resp_full),
-    .s_axis_cpl_enqueue_resp_error(s_axis_tx_cpl_enqueue_resp_error),
-    .s_axis_cpl_enqueue_resp_valid(s_axis_tx_cpl_enqueue_resp_valid),
-    .s_axis_cpl_enqueue_resp_ready(s_axis_tx_cpl_enqueue_resp_ready),
-
-    /*
-     * Completion enqueue commit output
-     */
-    .m_axis_cpl_enqueue_commit_op_tag(m_axis_tx_cpl_enqueue_commit_op_tag),
-    .m_axis_cpl_enqueue_commit_valid(m_axis_tx_cpl_enqueue_commit_valid),
-    .m_axis_cpl_enqueue_commit_ready(m_axis_tx_cpl_enqueue_commit_ready),
+    .s_axis_cpl_req_status_tag(tx_cpl_req_status_tag),
+    .s_axis_cpl_req_status_full(tx_cpl_req_status_full),
+    .s_axis_cpl_req_status_error(tx_cpl_req_status_error),
+    .s_axis_cpl_req_status_valid(tx_cpl_req_status_valid),
 
     /*
      * PCIe DMA read descriptor output
      */
-    .m_axis_pcie_axi_dma_read_desc_pcie_addr(tx_pcie_axi_dma_read_desc_pcie_addr),
-    .m_axis_pcie_axi_dma_read_desc_axi_addr(tx_pcie_axi_dma_read_desc_axi_addr),
-    .m_axis_pcie_axi_dma_read_desc_len(tx_pcie_axi_dma_read_desc_len),
-    .m_axis_pcie_axi_dma_read_desc_tag(tx_pcie_axi_dma_read_desc_tag),
-    .m_axis_pcie_axi_dma_read_desc_valid(tx_pcie_axi_dma_read_desc_valid),
-    .m_axis_pcie_axi_dma_read_desc_ready(tx_pcie_axi_dma_read_desc_ready),
+    .m_axis_pcie_axi_dma_read_desc_pcie_addr(m_axis_pcie_axi_dma_read_desc_pcie_addr),
+    .m_axis_pcie_axi_dma_read_desc_axi_addr(m_axis_pcie_axi_dma_read_desc_axi_addr),
+    .m_axis_pcie_axi_dma_read_desc_len(m_axis_pcie_axi_dma_read_desc_len),
+    .m_axis_pcie_axi_dma_read_desc_tag(m_axis_pcie_axi_dma_read_desc_tag),
+    .m_axis_pcie_axi_dma_read_desc_valid(m_axis_pcie_axi_dma_read_desc_valid),
+    .m_axis_pcie_axi_dma_read_desc_ready(m_axis_pcie_axi_dma_read_desc_ready),
 
     /*
      * PCIe DMA read descriptor status input
      */
-    .s_axis_pcie_axi_dma_read_desc_status_tag(tx_pcie_axi_dma_read_desc_status_tag),
-    .s_axis_pcie_axi_dma_read_desc_status_valid(tx_pcie_axi_dma_read_desc_status_valid),
-
-    /*
-     * PCIe DMA write descriptor output
-     */
-    .m_axis_pcie_axi_dma_write_desc_pcie_addr(tx_pcie_axi_dma_write_desc_pcie_addr),
-    .m_axis_pcie_axi_dma_write_desc_axi_addr(tx_pcie_axi_dma_write_desc_axi_addr),
-    .m_axis_pcie_axi_dma_write_desc_len(tx_pcie_axi_dma_write_desc_len),
-    .m_axis_pcie_axi_dma_write_desc_tag(tx_pcie_axi_dma_write_desc_tag),
-    .m_axis_pcie_axi_dma_write_desc_valid(tx_pcie_axi_dma_write_desc_valid),
-    .m_axis_pcie_axi_dma_write_desc_ready(tx_pcie_axi_dma_write_desc_ready),
-
-    /*
-     * PCIe DMA write descriptor status input
-     */
-    .s_axis_pcie_axi_dma_write_desc_status_tag(tx_pcie_axi_dma_write_desc_status_tag),
-    .s_axis_pcie_axi_dma_write_desc_status_valid(tx_pcie_axi_dma_write_desc_status_valid),
+    .s_axis_pcie_axi_dma_read_desc_status_tag(s_axis_pcie_axi_dma_read_desc_status_tag),
+    .s_axis_pcie_axi_dma_read_desc_status_valid(s_axis_pcie_axi_dma_read_desc_status_valid),
 
     /*
      * Transmit descriptor output
@@ -1281,45 +1115,6 @@ tx_engine_inst (
     .s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
     .s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
 
-    /*
-     * AXI slave interface
-     */
-    .s_axi_awid(axi_tx_awid),
-    .s_axi_awaddr(axi_tx_awaddr),
-    .s_axi_awlen(axi_tx_awlen),
-    .s_axi_awsize(axi_tx_awsize),
-    .s_axi_awburst(axi_tx_awburst),
-    .s_axi_awlock(axi_tx_awlock),
-    .s_axi_awcache(axi_tx_awcache),
-    .s_axi_awprot(axi_tx_awprot),
-    .s_axi_awvalid(axi_tx_awvalid),
-    .s_axi_awready(axi_tx_awready),
-    .s_axi_wdata(axi_tx_wdata),
-    .s_axi_wstrb(axi_tx_wstrb),
-    .s_axi_wlast(axi_tx_wlast),
-    .s_axi_wvalid(axi_tx_wvalid),
-    .s_axi_wready(axi_tx_wready),
-    .s_axi_bid(axi_tx_bid),
-    .s_axi_bresp(axi_tx_bresp),
-    .s_axi_bvalid(axi_tx_bvalid),
-    .s_axi_bready(axi_tx_bready),
-    .s_axi_arid(axi_tx_arid),
-    .s_axi_araddr(axi_tx_araddr),
-    .s_axi_arlen(axi_tx_arlen),
-    .s_axi_arsize(axi_tx_arsize),
-    .s_axi_arburst(axi_tx_arburst),
-    .s_axi_arlock(axi_tx_arlock),
-    .s_axi_arcache(axi_tx_arcache),
-    .s_axi_arprot(axi_tx_arprot),
-    .s_axi_arvalid(axi_tx_arvalid),
-    .s_axi_arready(axi_tx_arready),
-    .s_axi_rid(axi_tx_rid),
-    .s_axi_rdata(axi_tx_rdata),
-    .s_axi_rresp(axi_tx_rresp),
-    .s_axi_rlast(axi_tx_rlast),
-    .s_axi_rvalid(axi_tx_rvalid),
-    .s_axi_rready(axi_tx_rready),
-
     /*
      * Configuration
      */
@@ -1334,7 +1129,8 @@ rx_engine #(
     .PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
     .AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
     .REQ_TAG_WIDTH(REQ_TAG_WIDTH),
-    .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
+    .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
+    .PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
     .AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
     .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
     .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
@@ -1343,7 +1139,6 @@ rx_engine #(
     .CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
     .DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
     .PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
-    .AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h006000),
     .SCRATCH_PKT_AXI_ADDR(RX_RAM_AXI_BASE_ADDR),
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
     .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE)
@@ -1367,91 +1162,67 @@ rx_engine_inst (
     .m_axis_rx_req_status_valid(rx_req_status_valid),
 
     /*
-     * Descriptor dequeue request output
+     * Descriptor request output
      */
-    .m_axis_desc_dequeue_req_queue(m_axis_rx_desc_dequeue_req_queue),
-    .m_axis_desc_dequeue_req_tag(m_axis_rx_desc_dequeue_req_tag),
-    .m_axis_desc_dequeue_req_valid(m_axis_rx_desc_dequeue_req_valid),
-    .m_axis_desc_dequeue_req_ready(m_axis_rx_desc_dequeue_req_ready),
+    .m_axis_desc_req_queue(rx_desc_req_queue),
+    .m_axis_desc_req_tag(rx_desc_req_tag),
+    .m_axis_desc_req_valid(rx_desc_req_valid),
+    .m_axis_desc_req_ready(rx_desc_req_ready),
 
     /*
-     * Descriptor dequeue response input
+     * Descriptor request status input
      */
-    .s_axis_desc_dequeue_resp_queue(s_axis_rx_desc_dequeue_resp_queue),
-    .s_axis_desc_dequeue_resp_ptr(s_axis_rx_desc_dequeue_resp_ptr),
-    .s_axis_desc_dequeue_resp_addr(s_axis_rx_desc_dequeue_resp_addr),
-    .s_axis_desc_dequeue_resp_cpl(s_axis_rx_desc_dequeue_resp_cpl),
-    .s_axis_desc_dequeue_resp_tag(s_axis_rx_desc_dequeue_resp_tag),
-    .s_axis_desc_dequeue_resp_op_tag(s_axis_rx_desc_dequeue_resp_op_tag),
-    .s_axis_desc_dequeue_resp_empty(s_axis_rx_desc_dequeue_resp_empty),
-    .s_axis_desc_dequeue_resp_error(s_axis_rx_desc_dequeue_resp_error),
-    .s_axis_desc_dequeue_resp_valid(s_axis_rx_desc_dequeue_resp_valid),
-    .s_axis_desc_dequeue_resp_ready(s_axis_rx_desc_dequeue_resp_ready),
+    .s_axis_desc_req_status_queue(rx_desc_req_status_queue),
+    .s_axis_desc_req_status_ptr(rx_desc_req_status_ptr),
+    .s_axis_desc_req_status_cpl(rx_desc_req_status_cpl),
+    .s_axis_desc_req_status_tag(rx_desc_req_status_tag),
+    .s_axis_desc_req_status_empty(rx_desc_req_status_empty),
+    .s_axis_desc_req_status_error(rx_desc_req_status_error),
+    .s_axis_desc_req_status_valid(rx_desc_req_status_valid),
 
     /*
-     * Descriptor dequeue commit output
+     * Descriptor data input
      */
-    .m_axis_desc_dequeue_commit_op_tag(m_axis_rx_desc_dequeue_commit_op_tag),
-    .m_axis_desc_dequeue_commit_valid(m_axis_rx_desc_dequeue_commit_valid),
-    .m_axis_desc_dequeue_commit_ready(m_axis_rx_desc_dequeue_commit_ready),
+    .s_axis_desc_tdata(rx_desc_tdata),
+    .s_axis_desc_tkeep(rx_desc_tkeep),
+    .s_axis_desc_tvalid(rx_desc_tvalid),
+    .s_axis_desc_tready(rx_desc_tready),
+    .s_axis_desc_tlast(rx_desc_tlast),
+    .s_axis_desc_tid(rx_desc_tid),
+    .s_axis_desc_tuser(rx_desc_tuser),
 
     /*
-     * Completion enqueue request output
+     * Completion request output
      */
-    .m_axis_cpl_enqueue_req_queue(m_axis_rx_cpl_enqueue_req_queue),
-    .m_axis_cpl_enqueue_req_tag(m_axis_rx_cpl_enqueue_req_tag),
-    .m_axis_cpl_enqueue_req_valid(m_axis_rx_cpl_enqueue_req_valid),
-    .m_axis_cpl_enqueue_req_ready(m_axis_rx_cpl_enqueue_req_ready),
+    .m_axis_cpl_req_queue(rx_cpl_req_queue),
+    .m_axis_cpl_req_tag(rx_cpl_req_tag),
+    .m_axis_cpl_req_data(rx_cpl_req_data),
+    .m_axis_cpl_req_valid(rx_cpl_req_valid),
+    .m_axis_cpl_req_ready(rx_cpl_req_ready),
 
     /*
-     * Completion enqueue response input
+     * Completion request status input
      */
-    .s_axis_cpl_enqueue_resp_addr(s_axis_rx_cpl_enqueue_resp_addr),
-    .s_axis_cpl_enqueue_resp_tag(s_axis_rx_cpl_enqueue_resp_tag),
-    .s_axis_cpl_enqueue_resp_op_tag(s_axis_rx_cpl_enqueue_resp_op_tag),
-    .s_axis_cpl_enqueue_resp_full(s_axis_rx_cpl_enqueue_resp_full),
-    .s_axis_cpl_enqueue_resp_error(s_axis_rx_cpl_enqueue_resp_error),
-    .s_axis_cpl_enqueue_resp_valid(s_axis_rx_cpl_enqueue_resp_valid),
-    .s_axis_cpl_enqueue_resp_ready(s_axis_rx_cpl_enqueue_resp_ready),
-
-    /*
-     * Completion enqueue commit output
-     */
-    .m_axis_cpl_enqueue_commit_op_tag(m_axis_rx_cpl_enqueue_commit_op_tag),
-    .m_axis_cpl_enqueue_commit_valid(m_axis_rx_cpl_enqueue_commit_valid),
-    .m_axis_cpl_enqueue_commit_ready(m_axis_rx_cpl_enqueue_commit_ready),
-
-    /*
-     * PCIe DMA read descriptor output
-     */
-    .m_axis_pcie_axi_dma_read_desc_pcie_addr(rx_pcie_axi_dma_read_desc_pcie_addr),
-    .m_axis_pcie_axi_dma_read_desc_axi_addr(rx_pcie_axi_dma_read_desc_axi_addr),
-    .m_axis_pcie_axi_dma_read_desc_len(rx_pcie_axi_dma_read_desc_len),
-    .m_axis_pcie_axi_dma_read_desc_tag(rx_pcie_axi_dma_read_desc_tag),
-    .m_axis_pcie_axi_dma_read_desc_valid(rx_pcie_axi_dma_read_desc_valid),
-    .m_axis_pcie_axi_dma_read_desc_ready(rx_pcie_axi_dma_read_desc_ready),
-
-    /*
-     * PCIe DMA read descriptor status input
-     */
-    .s_axis_pcie_axi_dma_read_desc_status_tag(rx_pcie_axi_dma_read_desc_status_tag),
-    .s_axis_pcie_axi_dma_read_desc_status_valid(rx_pcie_axi_dma_read_desc_status_valid),
+    .s_axis_cpl_req_status_tag(rx_cpl_req_status_tag),
+    .s_axis_cpl_req_status_full(rx_cpl_req_status_full),
+    .s_axis_cpl_req_status_error(rx_cpl_req_status_error),
+    .s_axis_cpl_req_status_valid(rx_cpl_req_status_valid),
 
     /*
      * PCIe DMA write descriptor output
      */
-    .m_axis_pcie_axi_dma_write_desc_pcie_addr(rx_pcie_axi_dma_write_desc_pcie_addr),
-    .m_axis_pcie_axi_dma_write_desc_axi_addr(rx_pcie_axi_dma_write_desc_axi_addr),
-    .m_axis_pcie_axi_dma_write_desc_len(rx_pcie_axi_dma_write_desc_len),
-    .m_axis_pcie_axi_dma_write_desc_tag(rx_pcie_axi_dma_write_desc_tag),
-    .m_axis_pcie_axi_dma_write_desc_valid(rx_pcie_axi_dma_write_desc_valid),
-    .m_axis_pcie_axi_dma_write_desc_ready(rx_pcie_axi_dma_write_desc_ready),
+    .m_axis_pcie_axi_dma_write_desc_pcie_addr(m_axis_pcie_axi_dma_write_desc_pcie_addr),
+    .m_axis_pcie_axi_dma_write_desc_axi_addr(m_axis_pcie_axi_dma_write_desc_axi_addr),
+    .m_axis_pcie_axi_dma_write_desc_len(m_axis_pcie_axi_dma_write_desc_len),
+    .m_axis_pcie_axi_dma_write_desc_tag(m_axis_pcie_axi_dma_write_desc_tag),
+    .m_axis_pcie_axi_dma_write_desc_valid(m_axis_pcie_axi_dma_write_desc_valid),
+    .m_axis_pcie_axi_dma_write_desc_ready(m_axis_pcie_axi_dma_write_desc_ready),
 
     /*
      * PCIe DMA write descriptor status input
      */
-    .s_axis_pcie_axi_dma_write_desc_status_tag(rx_pcie_axi_dma_write_desc_status_tag),
-    .s_axis_pcie_axi_dma_write_desc_status_valid(rx_pcie_axi_dma_write_desc_status_valid),
+    .s_axis_pcie_axi_dma_write_desc_status_tag(s_axis_pcie_axi_dma_write_desc_status_tag),
+    .s_axis_pcie_axi_dma_write_desc_status_valid(s_axis_pcie_axi_dma_write_desc_status_valid),
 
     /*
      * Receive descriptor output
@@ -1484,45 +1255,6 @@ rx_engine_inst (
     .s_axis_rx_csum_valid(rx_fifo_csum_valid),
     .s_axis_rx_csum_ready(rx_fifo_csum_ready),
 
-    /*
-     * AXI slave interface
-     */
-    .s_axi_awid(axi_rx_awid),
-    .s_axi_awaddr(axi_rx_awaddr),
-    .s_axi_awlen(axi_rx_awlen),
-    .s_axi_awsize(axi_rx_awsize),
-    .s_axi_awburst(axi_rx_awburst),
-    .s_axi_awlock(axi_rx_awlock),
-    .s_axi_awcache(axi_rx_awcache),
-    .s_axi_awprot(axi_rx_awprot),
-    .s_axi_awvalid(axi_rx_awvalid),
-    .s_axi_awready(axi_rx_awready),
-    .s_axi_wdata(axi_rx_wdata),
-    .s_axi_wstrb(axi_rx_wstrb),
-    .s_axi_wlast(axi_rx_wlast),
-    .s_axi_wvalid(axi_rx_wvalid),
-    .s_axi_wready(axi_rx_wready),
-    .s_axi_bid(axi_rx_bid),
-    .s_axi_bresp(axi_rx_bresp),
-    .s_axi_bvalid(axi_rx_bvalid),
-    .s_axi_bready(axi_rx_bready),
-    .s_axi_arid(axi_rx_arid),
-    .s_axi_araddr(axi_rx_araddr),
-    .s_axi_arlen(axi_rx_arlen),
-    .s_axi_arsize(axi_rx_arsize),
-    .s_axi_arburst(axi_rx_arburst),
-    .s_axi_arlock(axi_rx_arlock),
-    .s_axi_arcache(axi_rx_arcache),
-    .s_axi_arprot(axi_rx_arprot),
-    .s_axi_arvalid(axi_rx_arvalid),
-    .s_axi_arready(axi_rx_arready),
-    .s_axi_rid(axi_rx_rid),
-    .s_axi_rdata(axi_rx_rdata),
-    .s_axi_rresp(axi_rx_rresp),
-    .s_axi_rlast(axi_rx_rlast),
-    .s_axi_rvalid(axi_rx_rvalid),
-    .s_axi_rready(axi_rx_rready),
-
     /*
      * Configuration
      */
@@ -1807,134 +1539,4 @@ axi_dma_inst (
     .write_abort(1'b0)
 );
 
-parameter RAM_COUNT = 3;
-parameter RAM_SIZE = 2**16;
-parameter RAM_ADDR_WIDTH = $clog2(RAM_SIZE);
-parameter RAM_BASE_ADDR_WIDTH = RAM_COUNT*AXI_ADDR_WIDTH;
-parameter RAM_BASE_ADDR = calcRAMBaseAddrs(RAM_ADDR_WIDTH);
-
-function [RAM_BASE_ADDR_WIDTH-1:0] calcRAMBaseAddrs(input [31:0] ram_width);
-    integer i;
-    begin
-        calcRAMBaseAddrs = {RAM_BASE_ADDR_WIDTH{1'b0}};
-        for (i = 0; i < RAM_COUNT; i = i + 1) begin
-            calcRAMBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**ram_width);
-        end
-    end
-endfunction
-
-parameter AXI_S_COUNT = 2;
-parameter AXI_M_COUNT = RAM_COUNT+1;
-
-parameter RAM_ID_WIDTH = AXI_ID_WIDTH+$clog2(AXI_S_COUNT);
-
-axi_interconnect #(
-    .S_COUNT(1),
-    .M_COUNT(2),
-    .DATA_WIDTH(AXI_DATA_WIDTH),
-    .ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .STRB_WIDTH(AXI_STRB_WIDTH),
-    .ID_WIDTH(RAM_ID_WIDTH),
-    .AWUSER_ENABLE(0),
-    .WUSER_ENABLE(0),
-    .BUSER_ENABLE(0),
-    .ARUSER_ENABLE(0),
-    .RUSER_ENABLE(0),
-    .FORWARD_ID(0),
-    .M_REGIONS(1),
-    .M_BASE_ADDR({23'h006000, 23'h004000}),
-    .M_ADDR_WIDTH({2{32'd13}}),
-    .M_CONNECT_READ({2{{1{1'b1}}}}),
-    .M_CONNECT_WRITE({2{{1{1'b1}}}})
-)
-axi_interconnect_inst (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awqos(0),
-    .s_axi_awuser(0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arqos(0),
-    .s_axi_aruser(0),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-
-    .m_axi_awid(     {axi_rx_awid,     axi_tx_awid}),
-    .m_axi_awaddr(   {axi_rx_awaddr,   axi_tx_awaddr}),
-    .m_axi_awlen(    {axi_rx_awlen,    axi_tx_awlen}),
-    .m_axi_awsize(   {axi_rx_awsize,   axi_tx_awsize}),
-    .m_axi_awburst(  {axi_rx_awburst,  axi_tx_awburst}),
-    .m_axi_awlock(   {axi_rx_awlock,   axi_tx_awlock}),
-    .m_axi_awcache(  {axi_rx_awcache,  axi_tx_awcache}),
-    .m_axi_awprot(   {axi_rx_awprot,   axi_tx_awprot}),
-    .m_axi_awqos(),
-    .m_axi_awuser(),
-    .m_axi_awvalid(  {axi_rx_awvalid,  axi_tx_awvalid}),
-    .m_axi_awready(  {axi_rx_awready,  axi_tx_awready}),
-    .m_axi_wdata(    {axi_rx_wdata,    axi_tx_wdata}),
-    .m_axi_wstrb(    {axi_rx_wstrb,    axi_tx_wstrb}),
-    .m_axi_wlast(    {axi_rx_wlast,    axi_tx_wlast}),
-    .m_axi_wuser(),
-    .m_axi_wvalid(   {axi_rx_wvalid,   axi_tx_wvalid}),
-    .m_axi_wready(   {axi_rx_wready,   axi_tx_wready}),
-    .m_axi_bid(      {axi_rx_bid,      axi_tx_bid}),
-    .m_axi_bresp(    {axi_rx_bresp,    axi_tx_bresp}),
-    .m_axi_buser(0),
-    .m_axi_bvalid(   {axi_rx_bvalid,   axi_tx_bvalid}),
-    .m_axi_bready(   {axi_rx_bready,   axi_tx_bready}),
-    .m_axi_arid(     {axi_rx_arid,     axi_tx_arid}),
-    .m_axi_araddr(   {axi_rx_araddr,   axi_tx_araddr}),
-    .m_axi_arlen(    {axi_rx_arlen,    axi_tx_arlen}),
-    .m_axi_arsize(   {axi_rx_arsize,   axi_tx_arsize}),
-    .m_axi_arburst(  {axi_rx_arburst,  axi_tx_arburst}),
-    .m_axi_arlock(   {axi_rx_arlock,   axi_tx_arlock}),
-    .m_axi_arcache(  {axi_rx_arcache,  axi_tx_arcache}),
-    .m_axi_arprot(   {axi_rx_arprot,   axi_tx_arprot}),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(  {axi_rx_arvalid,  axi_tx_arvalid}),
-    .m_axi_arready(  {axi_rx_arready,  axi_tx_arready}),
-    .m_axi_rid(      {axi_rx_rid,      axi_tx_rid}),
-    .m_axi_rdata(    {axi_rx_rdata,    axi_tx_rdata}),
-    .m_axi_rresp(    {axi_rx_rresp,    axi_tx_rresp}),
-    .m_axi_rlast(    {axi_rx_rlast,    axi_tx_rlast}),
-    .m_axi_ruser(0),
-    .m_axi_rvalid(   {axi_rx_rvalid,   axi_tx_rvalid}),
-    .m_axi_rready(   {axi_rx_rready,   axi_tx_rready})
-);
-
 endmodule
diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v
index 77f636aef..ccfc99f1e 100644
--- a/fpga/common/rtl/rx_engine.v
+++ b/fpga/common/rtl/rx_engine.v
@@ -48,6 +48,10 @@ module rx_engine #
     parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
     // Width of AXI ID signal
     parameter AXI_ID_WIDTH = 8,
+    // Width of AXI stream interface in bits
+    parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
+    // AXI stream tkeep signal width (words per cycle)
+    parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
     // PCIe address width
     parameter PCIE_ADDR_WIDTH = 64,
     // PCIe DMA length field width
@@ -56,6 +60,8 @@ module rx_engine #
     parameter AXI_DMA_LEN_WIDTH = 20,
     // Receive request tag field width
     parameter REQ_TAG_WIDTH = 8,
+    // Descriptor request tag field width
+    parameter DESC_REQ_TAG_WIDTH = 8,
     // PCIe DMA tag field width
     parameter PCIE_DMA_TAG_WIDTH = 8,
     // AXI DMA tag field width
@@ -76,8 +82,10 @@ module rx_engine #
     parameter PKT_TABLE_SIZE = 8,
     // Max receive packet size
     parameter MAX_RX_SIZE = 2048,
-    // AXI base address of this module (as seen by PCIe DMA)
-    parameter AXI_BASE_ADDR = 16'h0000,
+    // Descriptor size (in bytes)
+    parameter DESC_SIZE = 16,
+    // Descriptor size (in bytes)
+    parameter CPL_SIZE = 32,
     // AXI address of packet scratchpad RAM (as seen by PCIe DMA and port AXI DMA)
     parameter SCRATCH_PKT_AXI_ADDR = 16'h1000,
     // Packet scratchpad RAM log segment size
@@ -107,75 +115,51 @@ module rx_engine #
     output wire                             m_axis_rx_req_status_valid,
 
     /*
-     * Descriptor dequeue request output
+     * Descriptor request output
      */
-    output wire [QUEUE_INDEX_WIDTH-1:0]     m_axis_desc_dequeue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]   m_axis_desc_dequeue_req_tag,
-    output wire                             m_axis_desc_dequeue_req_valid,
-    input  wire                             m_axis_desc_dequeue_req_ready,
+    output wire [QUEUE_INDEX_WIDTH-1:0]     m_axis_desc_req_queue,
+    output wire [DESC_REQ_TAG_WIDTH-1:0]    m_axis_desc_req_tag,
+    output wire                             m_axis_desc_req_valid,
+    input  wire                             m_axis_desc_req_ready,
 
     /*
-     * Descriptor dequeue response input
+     * Descriptor request status input
      */
-    input  wire [QUEUE_INDEX_WIDTH-1:0]     s_axis_desc_dequeue_resp_queue,
-    input  wire [QUEUE_PTR_WIDTH-1:0]       s_axis_desc_dequeue_resp_ptr,
-    input  wire [PCIE_ADDR_WIDTH-1:0]       s_axis_desc_dequeue_resp_addr,
-    input  wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_dequeue_resp_cpl,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]   s_axis_desc_dequeue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]    s_axis_desc_dequeue_resp_op_tag,
-    input  wire                             s_axis_desc_dequeue_resp_empty,
-    input  wire                             s_axis_desc_dequeue_resp_error,
-    input  wire                             s_axis_desc_dequeue_resp_valid,
-    output wire                             s_axis_desc_dequeue_resp_ready,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]     s_axis_desc_req_status_queue,
+    input  wire [QUEUE_PTR_WIDTH-1:0]       s_axis_desc_req_status_ptr,
+    input  wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]    s_axis_desc_req_status_tag,
+    input  wire                             s_axis_desc_req_status_empty,
+    input  wire                             s_axis_desc_req_status_error,
+    input  wire                             s_axis_desc_req_status_valid,
 
     /*
-     * Descriptor dequeue commit output
+     * Descriptor data input
      */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]    m_axis_desc_dequeue_commit_op_tag,
-    output wire                             m_axis_desc_dequeue_commit_valid,
-    input  wire                             m_axis_desc_dequeue_commit_ready,
+    input  wire [AXIS_DATA_WIDTH-1:0]       s_axis_desc_tdata,
+    input  wire [AXIS_KEEP_WIDTH-1:0]       s_axis_desc_tkeep,
+    input  wire                             s_axis_desc_tvalid,
+    output wire                             s_axis_desc_tready,
+    input  wire                             s_axis_desc_tlast,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]    s_axis_desc_tid,
+    input  wire                             s_axis_desc_tuser,
 
     /*
-     * Completion enqueue request output
+     * Completion request output
      */
-    output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]   m_axis_cpl_enqueue_req_tag,
-    output wire                             m_axis_cpl_enqueue_req_valid,
-    input  wire                             m_axis_cpl_enqueue_req_ready,
+    output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
+    output wire [DESC_REQ_TAG_WIDTH-1:0]    m_axis_cpl_req_tag,
+    output wire [CPL_SIZE*8-1:0]            m_axis_cpl_req_data,
+    output wire                             m_axis_cpl_req_valid,
+    input  wire                             m_axis_cpl_req_ready,
 
     /*
-     * Completion enqueue response input
+     * Completion request status input
      */
-    input  wire [PCIE_ADDR_WIDTH-1:0]       s_axis_cpl_enqueue_resp_addr,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]   s_axis_cpl_enqueue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]    s_axis_cpl_enqueue_resp_op_tag,
-    input  wire                             s_axis_cpl_enqueue_resp_full,
-    input  wire                             s_axis_cpl_enqueue_resp_error,
-    input  wire                             s_axis_cpl_enqueue_resp_valid,
-    output wire                             s_axis_cpl_enqueue_resp_ready,
-
-    /*
-     * Completion enqueue commit output
-     */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]    m_axis_cpl_enqueue_commit_op_tag,
-    output wire                             m_axis_cpl_enqueue_commit_valid,
-    input  wire                             m_axis_cpl_enqueue_commit_ready,
-
-    /*
-     * PCIe AXI DMA read descriptor output
-     */
-    output wire [PCIE_ADDR_WIDTH-1:0]       m_axis_pcie_axi_dma_read_desc_pcie_addr,
-    output wire [AXI_ADDR_WIDTH-1:0]        m_axis_pcie_axi_dma_read_desc_axi_addr,
-    output wire [PCIE_DMA_LEN_WIDTH-1:0]    m_axis_pcie_axi_dma_read_desc_len,
-    output wire [PCIE_DMA_TAG_WIDTH-1:0]    m_axis_pcie_axi_dma_read_desc_tag,
-    output wire                             m_axis_pcie_axi_dma_read_desc_valid,
-    input  wire                             m_axis_pcie_axi_dma_read_desc_ready,
-
-    /*
-     * PCIe AXI DMA read descriptor status input
-     */
-    input  wire [PCIE_DMA_TAG_WIDTH-1:0]    s_axis_pcie_axi_dma_read_desc_status_tag,
-    input  wire                             s_axis_pcie_axi_dma_read_desc_status_valid,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]    s_axis_cpl_req_status_tag,
+    input  wire                             s_axis_cpl_req_status_full,
+    input  wire                             s_axis_cpl_req_status_error,
+    input  wire                             s_axis_cpl_req_status_valid,
 
     /*
      * PCIe AXI DMA write descriptor output
@@ -224,52 +208,12 @@ module rx_engine #
     input wire                              s_axis_rx_csum_valid,
     output wire                             s_axis_rx_csum_ready,
 
-    /*
-     * AXI slave interface
-     */
-    input  wire [AXI_ID_WIDTH-1:0]          s_axi_awid,
-    input  wire [AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,
-    input  wire [7:0]                       s_axi_awlen,
-    input  wire [2:0]                       s_axi_awsize,
-    input  wire [1:0]                       s_axi_awburst,
-    input  wire                             s_axi_awlock,
-    input  wire [3:0]                       s_axi_awcache,
-    input  wire [2:0]                       s_axi_awprot,
-    input  wire                             s_axi_awvalid,
-    output wire                             s_axi_awready,
-    input  wire [AXI_DATA_WIDTH-1:0]        s_axi_wdata,
-    input  wire [AXI_STRB_WIDTH-1:0]        s_axi_wstrb,
-    input  wire                             s_axi_wlast,
-    input  wire                             s_axi_wvalid,
-    output wire                             s_axi_wready,
-    output wire [AXI_ID_WIDTH-1:0]          s_axi_bid,
-    output wire [1:0]                       s_axi_bresp,
-    output wire                             s_axi_bvalid,
-    input  wire                             s_axi_bready,
-    input  wire [AXI_ID_WIDTH-1:0]          s_axi_arid,
-    input  wire [AXI_ADDR_WIDTH-1:0]        s_axi_araddr,
-    input  wire [7:0]                       s_axi_arlen,
-    input  wire [2:0]                       s_axi_arsize,
-    input  wire [1:0]                       s_axi_arburst,
-    input  wire                             s_axi_arlock,
-    input  wire [3:0]                       s_axi_arcache,
-    input  wire [2:0]                       s_axi_arprot,
-    input  wire                             s_axi_arvalid,
-    output wire                             s_axi_arready,
-    output wire [AXI_ID_WIDTH-1:0]          s_axi_rid,
-    output wire [AXI_DATA_WIDTH-1:0]        s_axi_rdata,
-    output wire [1:0]                       s_axi_rresp,
-    output wire                             s_axi_rlast,
-    output wire                             s_axi_rvalid,
-    input  wire                             s_axi_rready,
-
     /*
      * Configuration
      */
     input  wire                             enable
 );
 
-
 parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
 parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
 parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
@@ -279,16 +223,9 @@ parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
 parameter CL_PKT_TABLE_SIZE = $clog2(PKT_TABLE_SIZE);
 parameter PKT_TAG_MASK = {CL_PKT_TABLE_SIZE{1'b1}};
 
-parameter DATA_FLAG = 1 << CL_DESC_TABLE_SIZE;
-
-parameter DESC_SIZE = 16;
-parameter CPL_SIZE = 32;
-
-parameter BLOCK_SIZE = DESC_SIZE > CPL_SIZE ? DESC_SIZE : CPL_SIZE;
-
 // bus width assertions
 initial begin
-    if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
+    if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
         $error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
         $finish;
     end
@@ -303,16 +240,6 @@ initial begin
         $finish;
     end
 
-    if (AXI_STRB_WIDTH < BLOCK_SIZE) begin
-        $error("Error: AXI interface width must be at least as large as one descriptor (instance %m)");
-        $finish;
-    end
-
-    if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
-        $error("Error: AXI base address must be aligned to interface width (instance %m)");
-        $finish;
-    end
-
     if (SCRATCH_PKT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
         $error("Error: AXI base address must be aligned to interface width (instance %m)");
         $finish;
@@ -332,38 +259,29 @@ initial begin
         $error("Error: QUEUE_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)");
         $finish;
     end
+
+    if (DESC_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
+        $error("Error: DESC_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)");
+        $finish;
+    end
 end
 
-reg [REQ_TAG_WIDTH-1:0] s_axis_rx_req_tag_reg = {REQ_TAG_WIDTH{1'b0}}, s_axis_rx_req_tag_next;
 reg s_axis_rx_req_ready_reg = 1'b0, s_axis_rx_req_ready_next;
 
 reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_rx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_rx_req_status_len_next;
 reg [REQ_TAG_WIDTH-1:0] m_axis_rx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_rx_req_status_tag_next;
 reg m_axis_rx_req_status_valid_reg = 1'b0, m_axis_rx_req_status_valid_next;
 
-reg [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_dequeue_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_desc_dequeue_req_queue_next;
-reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_desc_dequeue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_req_tag_next;
-reg m_axis_desc_dequeue_req_valid_reg = 1'b0, m_axis_desc_dequeue_req_valid_next;
+reg [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_desc_req_queue_next;
+reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_desc_req_tag_next;
+reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next;
 
-reg s_axis_desc_dequeue_resp_ready_reg = 1'b0, s_axis_desc_dequeue_resp_ready_next;
+reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next;
 
-reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_desc_dequeue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_commit_op_tag_next;
-reg m_axis_desc_dequeue_commit_valid_reg = 1'b0, m_axis_desc_dequeue_commit_valid_next;
-
-reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_queue_next;
-reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_cpl_enqueue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_tag_next;
-reg m_axis_cpl_enqueue_req_valid_reg = 1'b0, m_axis_cpl_enqueue_req_valid_next;
-
-reg s_axis_cpl_enqueue_resp_ready_reg = 1'b0, s_axis_cpl_enqueue_resp_ready_next;
-
-reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_cpl_enqueue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_commit_op_tag_next;
-reg m_axis_cpl_enqueue_commit_valid_reg = 1'b0, m_axis_cpl_enqueue_commit_valid_next;
-
-reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
-reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_axi_addr_next;
-reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_len_next;
-reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_tag_next;
-reg m_axis_pcie_axi_dma_read_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_read_desc_valid_next;
+reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next;
+reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next;
+reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next;
+reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;
 
 reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
 reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_axi_addr_next;
@@ -380,18 +298,6 @@ reg s_axis_rx_ptp_ts_ready_reg = 1'b0, s_axis_rx_ptp_ts_ready_next;
 
 reg s_axis_rx_csum_ready_reg = 1'b0, s_axis_rx_csum_ready_next;
 
-reg [PCIE_ADDR_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_pcie_addr_next;
-reg [AXI_ADDR_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_axi_addr_next;
-reg [PCIE_DMA_LEN_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_len_next;
-reg [PCIE_DMA_TAG_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_tag_next;
-reg pkt_write_pcie_axi_dma_write_desc_valid_reg = 1'b0, pkt_write_pcie_axi_dma_write_desc_valid_next;
-
-reg [PCIE_ADDR_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_pcie_addr_next;
-reg [AXI_ADDR_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_axi_addr_next;
-reg [PCIE_DMA_LEN_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_len_next;
-reg [PCIE_DMA_TAG_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_tag_next;
-reg cpl_write_pcie_axi_dma_write_desc_valid_reg = 1'b0, cpl_write_pcie_axi_dma_write_desc_valid_next;
-
 reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
 reg [DESC_TABLE_SIZE-1:0] desc_table_rx_done = 0;
 reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0;
@@ -402,8 +308,6 @@ reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
 reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0];
 reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0];
 reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0];
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_cpl_queue_op_tag[DESC_TABLE_SIZE-1:0];
 reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0];
 reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0];
 reg [PCIE_ADDR_WIDTH-1:0] desc_table_pcie_addr[DESC_TABLE_SIZE-1:0];
@@ -424,10 +328,11 @@ reg desc_table_dequeue_start_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr;
 reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr;
 reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue;
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_dequeue_queue_op_tag;
 reg desc_table_dequeue_invalid;
 reg desc_table_dequeue_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_fetched_ptr;
+reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
+reg [PCIE_ADDR_WIDTH-1:0] desc_table_desc_fetched_pcie_addr;
 reg desc_table_desc_fetched_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_data_write_start_ptr_reg = 0;
 reg desc_table_data_write_start_en;
@@ -441,10 +346,6 @@ reg [15:0] desc_table_store_csum;
 reg desc_table_store_csum_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_cpl_enqueue_start_ptr_reg = 0;
 reg desc_table_cpl_enqueue_start_en;
-reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_ptr;
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_cpl_write_queue_op_tag;
-reg desc_table_cpl_write_invalid;
-reg desc_table_cpl_write_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done_ptr;
 reg desc_table_cpl_write_done_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_finish_ptr_reg = 0;
@@ -462,29 +363,16 @@ assign m_axis_rx_req_status_len = m_axis_rx_req_status_len_reg;
 assign m_axis_rx_req_status_tag = m_axis_rx_req_status_tag_reg;
 assign m_axis_rx_req_status_valid = m_axis_rx_req_status_valid_reg;
 
-assign m_axis_desc_dequeue_req_queue = m_axis_desc_dequeue_req_queue_reg;
-assign m_axis_desc_dequeue_req_tag = m_axis_desc_dequeue_req_tag_reg;
-assign m_axis_desc_dequeue_req_valid = m_axis_desc_dequeue_req_valid_reg;
+assign m_axis_desc_req_queue = m_axis_desc_req_queue_reg;
+assign m_axis_desc_req_tag = m_axis_desc_req_tag_reg;
+assign m_axis_desc_req_valid = m_axis_desc_req_valid_reg;
 
-assign s_axis_desc_dequeue_resp_ready = s_axis_desc_dequeue_resp_ready_reg;
+assign s_axis_desc_tready = s_axis_desc_tready_reg;
 
-assign m_axis_desc_dequeue_commit_op_tag = m_axis_desc_dequeue_commit_op_tag_reg;
-assign m_axis_desc_dequeue_commit_valid = m_axis_desc_dequeue_commit_valid_reg;
-
-assign m_axis_cpl_enqueue_req_queue = m_axis_cpl_enqueue_req_queue_reg;
-assign m_axis_cpl_enqueue_req_tag = m_axis_cpl_enqueue_req_tag_reg;
-assign m_axis_cpl_enqueue_req_valid = m_axis_cpl_enqueue_req_valid_reg;
-
-assign s_axis_cpl_enqueue_resp_ready = s_axis_cpl_enqueue_resp_ready_reg;
-
-assign m_axis_cpl_enqueue_commit_op_tag = m_axis_cpl_enqueue_commit_op_tag_reg;
-assign m_axis_cpl_enqueue_commit_valid = m_axis_cpl_enqueue_commit_valid_reg;
-
-assign m_axis_pcie_axi_dma_read_desc_pcie_addr = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
-assign m_axis_pcie_axi_dma_read_desc_axi_addr = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
-assign m_axis_pcie_axi_dma_read_desc_len = m_axis_pcie_axi_dma_read_desc_len_reg;
-assign m_axis_pcie_axi_dma_read_desc_tag = m_axis_pcie_axi_dma_read_desc_tag_reg;
-assign m_axis_pcie_axi_dma_read_desc_valid = m_axis_pcie_axi_dma_read_desc_valid_reg;
+assign m_axis_cpl_req_queue = m_axis_cpl_req_queue_reg;
+assign m_axis_cpl_req_tag = m_axis_cpl_req_tag_reg;
+assign m_axis_cpl_req_data = m_axis_cpl_req_data_reg;
+assign m_axis_cpl_req_valid = m_axis_cpl_req_valid_reg;
 
 assign m_axis_pcie_axi_dma_write_desc_pcie_addr = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
 assign m_axis_pcie_axi_dma_write_desc_axi_addr = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
@@ -515,171 +403,6 @@ pkt_table_free_enc_inst (
     .output_unencoded()
 );
 
-wire [AXI_ID_WIDTH-1:0]   ram_wr_cmd_id;
-wire [AXI_ADDR_WIDTH-1:0] ram_wr_cmd_addr;
-wire [AXI_DATA_WIDTH-1:0] ram_wr_cmd_data;
-wire [AXI_STRB_WIDTH-1:0] ram_wr_cmd_strb;
-wire                      ram_wr_cmd_en;
-
-wire [AXI_ID_WIDTH-1:0]   ram_rd_cmd_id;
-wire [AXI_ADDR_WIDTH-1:0] ram_rd_cmd_addr;
-wire                      ram_rd_cmd_en;
-wire                      ram_rd_cmd_last;
-reg                       ram_rd_cmd_ready_reg = 1'b0;
-reg  [AXI_ID_WIDTH-1:0]   ram_rd_resp_id_reg = {AXI_ID_WIDTH{1'b0}};
-reg  [AXI_DATA_WIDTH-1:0] ram_rd_resp_data_reg = {AXI_DATA_WIDTH{1'b0}};
-reg                       ram_rd_resp_last_reg = 1'b0;
-reg                       ram_rd_resp_valid_reg = 1'b0;
-wire                      ram_rd_resp_ready;
-
-axi_ram_wr_if #(
-    .DATA_WIDTH(AXI_DATA_WIDTH),
-    .ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .STRB_WIDTH(AXI_STRB_WIDTH),
-    .ID_WIDTH(AXI_ID_WIDTH),
-    .AWUSER_ENABLE(0),
-    .WUSER_ENABLE(0),
-    .BUSER_ENABLE(0)
-)
-axi_ram_wr_if_inst (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awqos(0),
-    .s_axi_awregion(0),
-    .s_axi_awuser(0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .ram_wr_cmd_id(ram_wr_cmd_id),
-    .ram_wr_cmd_addr(ram_wr_cmd_addr),
-    .ram_wr_cmd_lock(),
-    .ram_wr_cmd_cache(),
-    .ram_wr_cmd_prot(),
-    .ram_wr_cmd_qos(),
-    .ram_wr_cmd_region(),
-    .ram_wr_cmd_auser(),
-    .ram_wr_cmd_data(ram_wr_cmd_data),
-    .ram_wr_cmd_strb(ram_wr_cmd_strb),
-    .ram_wr_cmd_user(),
-    .ram_wr_cmd_en(ram_wr_cmd_en),
-    .ram_wr_cmd_last(),
-    .ram_wr_cmd_ready(1'b1)
-);
-
-axi_ram_rd_if #(
-    .DATA_WIDTH(AXI_DATA_WIDTH),
-    .ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .STRB_WIDTH(AXI_STRB_WIDTH),
-    .ID_WIDTH(AXI_ID_WIDTH),
-    .ARUSER_ENABLE(0),
-    .RUSER_ENABLE(0),
-    .PIPELINE_OUTPUT(0)
-)
-axi_ram_rd_if_inst (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arqos(0),
-    .s_axi_arregion(0),
-    .s_axi_aruser(0),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .ram_rd_cmd_id(ram_rd_cmd_id),
-    .ram_rd_cmd_addr(ram_rd_cmd_addr),
-    .ram_rd_cmd_lock(),
-    .ram_rd_cmd_cache(),
-    .ram_rd_cmd_prot(),
-    .ram_rd_cmd_qos(),
-    .ram_rd_cmd_region(),
-    .ram_rd_cmd_auser(),
-    .ram_rd_cmd_en(ram_rd_cmd_en),
-    .ram_rd_cmd_last(ram_rd_cmd_last),
-    .ram_rd_cmd_ready(ram_rd_cmd_ready_reg),
-    .ram_rd_resp_id(ram_rd_resp_id_reg),
-    .ram_rd_resp_data(ram_rd_resp_data_reg),
-    .ram_rd_resp_last(ram_rd_resp_last_reg),
-    .ram_rd_resp_user(0),
-    .ram_rd_resp_valid(ram_rd_resp_valid_reg),
-    .ram_rd_resp_ready(ram_rd_resp_ready)
-);
-
-always @(posedge clk) begin
-    if (ram_wr_cmd_en) begin
-        // AXI write
-        if (ram_wr_cmd_addr[CL_DESC_TABLE_SIZE+5] == 0) begin
-            // descriptors
-            // TODO byte enables
-            desc_table_desc_len[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[64:32];
-            desc_table_pcie_addr[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[127:64];
-        end
-    end
-
-    ram_rd_resp_valid_reg <= ram_rd_resp_valid_reg && !ram_rd_resp_ready;
-    ram_rd_cmd_ready_reg <= !ram_rd_resp_valid_reg || ram_rd_resp_ready;
-
-    if (ram_rd_cmd_en && ram_rd_cmd_ready_reg) begin
-        // AXI read
-        ram_rd_resp_id_reg <= ram_rd_cmd_id;
-        ram_rd_resp_data_reg <= 0;
-        ram_rd_resp_last_reg <= ram_rd_cmd_last;
-        ram_rd_resp_valid_reg <= 1'b1;
-        ram_rd_cmd_ready_reg <= ram_rd_resp_ready;
-
-        if (ram_rd_cmd_addr[CL_DESC_TABLE_SIZE+5] == 0) begin
-            // descriptors
-            ram_rd_resp_data_reg[64:32] <= desc_table_desc_len[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            ram_rd_resp_data_reg[127:64] <= desc_table_pcie_addr[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-        end else begin
-            // completions
-            ram_rd_resp_data_reg[15:0]  <= desc_table_queue[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            ram_rd_resp_data_reg[31:16] <= desc_table_queue_ptr[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            ram_rd_resp_data_reg[47:32] <= desc_table_dma_len[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            if (PTP_TS_ENABLE) begin
-                //ram_rd_resp_data_reg[127:64] <= desc_table_ptp_ts[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] >> 16;
-                ram_rd_resp_data_reg[111:64] <= desc_table_ptp_ts[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] >> 16;
-            end
-            ram_rd_resp_data_reg[127:112] <= desc_table_csum[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-        end
-    end
-
-    if (rst) begin
-        ram_rd_cmd_ready_reg <= 1'b1;
-        ram_rd_resp_valid_reg <= 1'b0;
-    end
-end
-
 // reg [15:0] stall_cnt = 0;
 // wire stalled = stall_cnt[12];
 
@@ -716,36 +439,22 @@ end
 // );
 
 always @* begin
-    s_axis_rx_req_tag_next = s_axis_rx_req_tag_reg;
     s_axis_rx_req_ready_next = 1'b0;
 
     m_axis_rx_req_status_len_next = m_axis_rx_req_status_len_reg;
     m_axis_rx_req_status_tag_next = m_axis_rx_req_status_tag_reg;
     m_axis_rx_req_status_valid_next = 1'b0;
 
-    m_axis_desc_dequeue_req_queue_next = m_axis_desc_dequeue_req_queue_reg;
-    m_axis_desc_dequeue_req_tag_next = m_axis_desc_dequeue_req_tag_reg;
-    m_axis_desc_dequeue_req_valid_next = m_axis_desc_dequeue_req_valid_reg && !m_axis_desc_dequeue_req_ready;
+    m_axis_desc_req_queue_next = m_axis_desc_req_queue_reg;
+    m_axis_desc_req_tag_next = m_axis_desc_req_tag_reg;
+    m_axis_desc_req_valid_next = m_axis_desc_req_valid_reg && !m_axis_desc_req_ready;
 
-    s_axis_desc_dequeue_resp_ready_next = 1'b0;
+    s_axis_desc_tready_next = 1'b0;
 
-    m_axis_desc_dequeue_commit_op_tag_next = m_axis_desc_dequeue_commit_op_tag_reg;
-    m_axis_desc_dequeue_commit_valid_next = m_axis_desc_dequeue_commit_valid_reg && !m_axis_desc_dequeue_commit_ready;
-
-    m_axis_cpl_enqueue_req_queue_next = m_axis_cpl_enqueue_req_queue_reg;
-    m_axis_cpl_enqueue_req_tag_next = m_axis_cpl_enqueue_req_tag_reg;
-    m_axis_cpl_enqueue_req_valid_next = m_axis_cpl_enqueue_req_valid_reg && !m_axis_cpl_enqueue_req_ready;
-
-    s_axis_cpl_enqueue_resp_ready_next = 1'b0;
-
-    m_axis_cpl_enqueue_commit_op_tag_next = m_axis_cpl_enqueue_commit_op_tag_reg;
-    m_axis_cpl_enqueue_commit_valid_next = m_axis_cpl_enqueue_commit_valid_reg && !m_axis_cpl_enqueue_commit_ready;
-
-    m_axis_pcie_axi_dma_read_desc_pcie_addr_next = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
-    m_axis_pcie_axi_dma_read_desc_axi_addr_next = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
-    m_axis_pcie_axi_dma_read_desc_len_next = m_axis_pcie_axi_dma_read_desc_len_reg;
-    m_axis_pcie_axi_dma_read_desc_tag_next = m_axis_pcie_axi_dma_read_desc_tag_reg;
-    m_axis_pcie_axi_dma_read_desc_valid_next = m_axis_pcie_axi_dma_read_desc_valid_reg && !m_axis_pcie_axi_dma_read_desc_ready;
+    m_axis_cpl_req_queue_next = m_axis_cpl_req_queue_reg;
+    m_axis_cpl_req_tag_next = m_axis_cpl_req_tag_reg;
+    m_axis_cpl_req_data_next = m_axis_cpl_req_data_reg;
+    m_axis_cpl_req_valid_next = m_axis_cpl_req_valid_reg && !m_axis_cpl_req_ready;
 
     m_axis_pcie_axi_dma_write_desc_pcie_addr_next = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
     m_axis_pcie_axi_dma_write_desc_axi_addr_next = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
@@ -762,18 +471,6 @@ always @* begin
 
     s_axis_rx_csum_ready_next = 1'b0;
 
-    pkt_write_pcie_axi_dma_write_desc_pcie_addr_next = pkt_write_pcie_axi_dma_write_desc_pcie_addr_reg;
-    pkt_write_pcie_axi_dma_write_desc_axi_addr_next = pkt_write_pcie_axi_dma_write_desc_axi_addr_reg;
-    pkt_write_pcie_axi_dma_write_desc_len_next = pkt_write_pcie_axi_dma_write_desc_len_reg;
-    pkt_write_pcie_axi_dma_write_desc_tag_next = pkt_write_pcie_axi_dma_write_desc_tag_reg;
-    pkt_write_pcie_axi_dma_write_desc_valid_next = pkt_write_pcie_axi_dma_write_desc_valid_reg;
-
-    cpl_write_pcie_axi_dma_write_desc_pcie_addr_next = cpl_write_pcie_axi_dma_write_desc_pcie_addr_reg;
-    cpl_write_pcie_axi_dma_write_desc_axi_addr_next = cpl_write_pcie_axi_dma_write_desc_axi_addr_reg;
-    cpl_write_pcie_axi_dma_write_desc_len_next = cpl_write_pcie_axi_dma_write_desc_len_reg;
-    cpl_write_pcie_axi_dma_write_desc_tag_next = cpl_write_pcie_axi_dma_write_desc_tag_reg;
-    cpl_write_pcie_axi_dma_write_desc_valid_next = cpl_write_pcie_axi_dma_write_desc_valid_reg;
-
     desc_table_start_tag = s_axis_rx_req_tag;
     desc_table_start_queue = s_axis_rx_req_queue;
     desc_table_start_pkt = pkt_table_free_ptr;
@@ -782,13 +479,14 @@ always @* begin
     desc_table_rx_finish_len = s_axis_rx_desc_status_len;
     desc_table_rx_finish_en = 1'b0;
     desc_table_dequeue_start_en = 1'b0;
-    desc_table_dequeue_ptr = s_axis_desc_dequeue_resp_tag;
-    desc_table_dequeue_queue_ptr = s_axis_desc_dequeue_resp_ptr;
-    desc_table_dequeue_cpl_queue = s_axis_desc_dequeue_resp_cpl;
-    desc_table_dequeue_queue_op_tag = s_axis_desc_dequeue_resp_op_tag;
+    desc_table_dequeue_ptr = s_axis_desc_req_status_tag;
+    desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
+    desc_table_dequeue_cpl_queue = s_axis_desc_req_status_cpl;
     desc_table_dequeue_invalid = 1'b0;
     desc_table_dequeue_en = 1'b0;
-    desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
+    desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
+    desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
+    desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
     desc_table_desc_fetched_en = 1'b0;
     desc_table_data_write_start_en = 1'b0;
     desc_table_data_written_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
@@ -798,11 +496,7 @@ always @* begin
     desc_table_store_csum = s_axis_rx_csum;
     desc_table_store_csum_en = 1'b0;
     desc_table_cpl_enqueue_start_en = 1'b0;
-    desc_table_cpl_write_ptr = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
-    desc_table_cpl_write_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag;
-    desc_table_cpl_write_invalid = 1'b0;
-    desc_table_cpl_write_en = 1'b0;
-    desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
+    desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
     desc_table_cpl_write_done_en = 1'b0;
     desc_table_finish_en = 1'b0;
 
@@ -811,7 +505,7 @@ always @* begin
     pkt_table_finish_ptr = desc_table_pkt[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
     pkt_table_finish_en = 1'b0;
 
-    // queue query
+    // receive packet
     // wait for receive request
     s_axis_rx_req_ready_next = enable && pkt_table_free_ptr_valid && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE) && (!m_axis_rx_desc_valid_reg || m_axis_rx_desc_ready);
     if (s_axis_rx_req_ready && s_axis_rx_req_valid) begin
@@ -843,34 +537,32 @@ always @* begin
         desc_table_rx_finish_en = 1'b1;
     end
 
-    // queue query
+    // descriptor fetch
     if (desc_table_active[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && desc_table_dequeue_start_ptr_reg != desc_table_start_ptr_reg) begin
-        if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_req_valid) begin
+        //if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_req_valid) begin
+        if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_req_valid) begin
             // update entry in descriptor table
             desc_table_dequeue_start_en = 1'b1;
 
-            // initiate queue query
-            m_axis_desc_dequeue_req_queue_next = desc_table_queue[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK];
-            m_axis_desc_dequeue_req_tag_next = desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK;
-            m_axis_desc_dequeue_req_valid_next = 1'b1;
+            // initiate descriptor fetch
+            m_axis_desc_req_queue_next = desc_table_queue[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_desc_req_tag_next = desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK;
+            m_axis_desc_req_valid_next = 1'b1;
         end
     end
 
     // descriptor fetch
     // wait for queue query response
-    s_axis_desc_dequeue_resp_ready_next = !m_axis_pcie_axi_dma_read_desc_valid_reg;
-    if (s_axis_desc_dequeue_resp_ready && s_axis_desc_dequeue_resp_valid) begin
-        s_axis_desc_dequeue_resp_ready_next = 1'b0;
+    if (s_axis_desc_req_status_valid) begin
 
         // update entry in descriptor table
-        desc_table_dequeue_ptr = s_axis_desc_dequeue_resp_tag;
-        desc_table_dequeue_queue_ptr = s_axis_desc_dequeue_resp_ptr;
-        desc_table_dequeue_cpl_queue = s_axis_desc_dequeue_resp_cpl;
-        desc_table_dequeue_queue_op_tag = s_axis_desc_dequeue_resp_op_tag;
+        desc_table_dequeue_ptr = s_axis_desc_req_status_tag & DESC_PTR_MASK;
+        desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
+        desc_table_dequeue_cpl_queue = s_axis_desc_req_status_cpl;
         desc_table_dequeue_invalid = 1'b0;
         desc_table_dequeue_en = 1'b1;
 
-        if (s_axis_desc_dequeue_resp_error || s_axis_desc_dequeue_resp_empty) begin
+        if (s_axis_desc_req_status_error || s_axis_desc_req_status_empty) begin
             // queue empty or not active
             // TODO retry if empty?
 
@@ -879,20 +571,17 @@ always @* begin
         end else begin
             // descriptor available to dequeue
 
-            // initiate descriptor fetch to onboard RAM
-            m_axis_pcie_axi_dma_read_desc_pcie_addr_next = s_axis_desc_dequeue_resp_addr;
-            m_axis_pcie_axi_dma_read_desc_axi_addr_next = AXI_BASE_ADDR + (s_axis_desc_dequeue_resp_tag << 5);
-            m_axis_pcie_axi_dma_read_desc_len_next = DESC_SIZE;
-            m_axis_pcie_axi_dma_read_desc_tag_next = s_axis_desc_dequeue_resp_tag;
-            m_axis_pcie_axi_dma_read_desc_valid_next = 1'b1;
+            // wait for descriptor
         end
     end
 
-    // descriptor fetch completion
-    // wait for descriptor fetch completion
-    if (s_axis_pcie_axi_dma_read_desc_status_valid) begin
+    // descriptor data write
+    s_axis_desc_tready_next = 1'b1;
+    if (s_axis_desc_tready && s_axis_desc_tvalid) begin
         // update entry in descriptor table
-        desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
+        desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
+        desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
+        desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
         desc_table_desc_fetched_en = 1'b1;
     end
 
@@ -903,28 +592,28 @@ always @* begin
         if (desc_table_invalid[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK]) begin
             // invalid entry; skip
             desc_table_data_write_start_en = 1'b1;
-        end else if (desc_table_desc_fetched[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && !pkt_write_pcie_axi_dma_write_desc_valid_reg) begin
+        end else if (desc_table_desc_fetched[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && !m_axis_pcie_axi_dma_write_desc_valid_reg) begin
             // update entry in descriptor table
             desc_table_data_write_start_en = 1'b1;
 
             // initiate data write
-            pkt_write_pcie_axi_dma_write_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
-            pkt_write_pcie_axi_dma_write_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + ((desc_table_pkt[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] & DESC_PTR_MASK) << SCRATCH_PKT_AXI_ADDR_SHIFT);
+            m_axis_pcie_axi_dma_write_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_pcie_axi_dma_write_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + ((desc_table_pkt[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] & DESC_PTR_MASK) << SCRATCH_PKT_AXI_ADDR_SHIFT);
             if (desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] < desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK]) begin
                 // limit write to length provided in descriptor
-                pkt_write_pcie_axi_dma_write_desc_len_next = desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
+                m_axis_pcie_axi_dma_write_desc_len_next = desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
             end else begin
                 // write actual packet length
-                pkt_write_pcie_axi_dma_write_desc_len_next = desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
+                m_axis_pcie_axi_dma_write_desc_len_next = desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
             end
-            pkt_write_pcie_axi_dma_write_desc_tag_next = (desc_table_data_write_start_ptr_reg & DESC_PTR_MASK) | DATA_FLAG;
-            pkt_write_pcie_axi_dma_write_desc_valid_next = 1'b1;
+            m_axis_pcie_axi_dma_write_desc_tag_next = desc_table_data_write_start_ptr_reg & DESC_PTR_MASK;
+            m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
         end
     end
 
     // data write completion
     // wait for data write completion
-    if (s_axis_pcie_axi_dma_write_desc_status_valid && (s_axis_pcie_axi_dma_write_desc_status_tag & DATA_FLAG)) begin
+    if (s_axis_pcie_axi_dma_write_desc_status_valid) begin
         // update entry in descriptor table
         desc_table_data_written_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
         desc_table_data_written_en = 1'b1;
@@ -974,7 +663,7 @@ always @* begin
             pkt_table_finish_ptr = desc_table_pkt[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
             pkt_table_finish_en = 1'b1;
 
-        end else if (desc_table_data_written[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_commit_valid && !m_axis_cpl_enqueue_req_valid_next && !cpl_write_pcie_axi_dma_write_desc_valid_reg) begin
+        end else if (desc_table_data_written[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_req_valid_next) begin
             // update entry in descriptor table
             desc_table_cpl_enqueue_start_en = 1'b1;
 
@@ -982,51 +671,27 @@ always @* begin
             pkt_table_finish_ptr = desc_table_pkt[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
             pkt_table_finish_en = 1'b1;
 
-            // initiate queue query
-            m_axis_cpl_enqueue_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
-            m_axis_cpl_enqueue_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
-            m_axis_cpl_enqueue_req_valid_next = 1'b1;
-
-            // commit dequeue operation
-            m_axis_desc_dequeue_commit_op_tag_next = desc_table_queue_op_tag[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
-            m_axis_desc_dequeue_commit_valid_next = 1'b1;
+            // initiate completion write
+            m_axis_cpl_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_cpl_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
+            m_axis_cpl_req_data_next = 0;
+            m_axis_cpl_req_data_next[15:0]  <= desc_table_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_cpl_req_data_next[31:16] <= desc_table_queue_ptr[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_cpl_req_data_next[47:32] <= desc_table_dma_len[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            if (PTP_TS_ENABLE) begin
+                //m_axis_cpl_req_data_next[127:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
+                m_axis_cpl_req_data_next[111:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
+            end
+            m_axis_cpl_req_data_next[127:112] <= desc_table_csum[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_cpl_req_valid_next = 1'b1;
         end
     end
 
     // start completion write
     // wait for queue query response
-    s_axis_cpl_enqueue_resp_ready_next = !cpl_write_pcie_axi_dma_write_desc_valid_reg;
-    if (s_axis_cpl_enqueue_resp_ready && s_axis_cpl_enqueue_resp_valid) begin
-        s_axis_cpl_enqueue_resp_ready_next = 1'b0;
-
+    if (s_axis_cpl_req_status_valid) begin
         // update entry in descriptor table
-        desc_table_cpl_write_ptr = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
-        desc_table_cpl_write_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag;
-        desc_table_cpl_write_invalid = 1'b0;
-        desc_table_cpl_write_en = 1'b1;
-
-        if (s_axis_cpl_enqueue_resp_error || s_axis_cpl_enqueue_resp_full) begin
-            // queue full or not active
-            // TODO retry if queue full?
-
-            // invalidate entry
-            desc_table_cpl_write_invalid = 1'b1;
-        end else begin
-            // space for completion available in queue
-
-            // initiate completion write from onboard RAM
-            cpl_write_pcie_axi_dma_write_desc_pcie_addr_next = s_axis_cpl_enqueue_resp_addr;
-            cpl_write_pcie_axi_dma_write_desc_axi_addr_next = AXI_BASE_ADDR + ((s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK) + 2**CL_DESC_TABLE_SIZE << 5);
-            cpl_write_pcie_axi_dma_write_desc_len_next = CPL_SIZE;
-            cpl_write_pcie_axi_dma_write_desc_tag_next = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
-            cpl_write_pcie_axi_dma_write_desc_valid_next = 1'b1;
-        end
-    end
-
-    // finish completion write
-    if (s_axis_pcie_axi_dma_write_desc_status_valid && !(s_axis_pcie_axi_dma_write_desc_status_tag & DATA_FLAG)) begin
-        // update entry in descriptor table
-        desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
+        desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
         desc_table_cpl_write_done_en = 1'b1;
     end
 
@@ -1040,58 +705,30 @@ always @* begin
             m_axis_rx_req_status_len_next = 0;
             m_axis_rx_req_status_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
             m_axis_rx_req_status_valid_next = 1'b1;
-        end else if (desc_table_cpl_write_done[desc_table_finish_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_enqueue_commit_valid) begin
+        end else if (desc_table_cpl_write_done[desc_table_finish_ptr_reg & DESC_PTR_MASK]) begin
             // invalidate entry in descriptor table
             desc_table_finish_en = 1'b1;
 
-            // commit enqueue operation
-            m_axis_cpl_enqueue_commit_op_tag_next = desc_table_cpl_queue_op_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
-            m_axis_cpl_enqueue_commit_valid_next = 1'b1;
-
             // return receive request completion
             m_axis_rx_req_status_len_next = desc_table_dma_len[desc_table_finish_ptr_reg & DESC_PTR_MASK];
             m_axis_rx_req_status_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
             m_axis_rx_req_status_valid_next = 1'b1;
         end
     end
-
-    // PCIe AXI DMA write request arbitration
-    if (pkt_write_pcie_axi_dma_write_desc_valid_next && (!m_axis_pcie_axi_dma_write_desc_valid_reg || m_axis_pcie_axi_dma_write_desc_ready)) begin
-        m_axis_pcie_axi_dma_write_desc_pcie_addr_next = pkt_write_pcie_axi_dma_write_desc_pcie_addr_next;
-        m_axis_pcie_axi_dma_write_desc_axi_addr_next = pkt_write_pcie_axi_dma_write_desc_axi_addr_next;
-        m_axis_pcie_axi_dma_write_desc_len_next = pkt_write_pcie_axi_dma_write_desc_len_next;
-        m_axis_pcie_axi_dma_write_desc_tag_next = pkt_write_pcie_axi_dma_write_desc_tag_next;
-        m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
-        pkt_write_pcie_axi_dma_write_desc_valid_next = 1'b0;
-    end else if (cpl_write_pcie_axi_dma_write_desc_valid_next && (!m_axis_pcie_axi_dma_write_desc_valid_reg || m_axis_pcie_axi_dma_write_desc_ready)) begin
-        m_axis_pcie_axi_dma_write_desc_pcie_addr_next = cpl_write_pcie_axi_dma_write_desc_pcie_addr_next;
-        m_axis_pcie_axi_dma_write_desc_axi_addr_next = cpl_write_pcie_axi_dma_write_desc_axi_addr_next;
-        m_axis_pcie_axi_dma_write_desc_len_next = cpl_write_pcie_axi_dma_write_desc_len_next;
-        m_axis_pcie_axi_dma_write_desc_tag_next = cpl_write_pcie_axi_dma_write_desc_tag_next;
-        m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
-        cpl_write_pcie_axi_dma_write_desc_valid_next = 1'b0;
-    end
 end
 
 always @(posedge clk) begin
     if (rst) begin
         s_axis_rx_req_ready_reg <= 1'b0;
         m_axis_rx_req_status_valid_reg <= 1'b0;
-        m_axis_desc_dequeue_req_valid_reg <= 1'b0;
-        s_axis_desc_dequeue_resp_ready_reg <= 1'b0;
-        m_axis_desc_dequeue_commit_valid_reg <= 1'b0;
-        m_axis_cpl_enqueue_req_valid_reg <= 1'b0;
-        s_axis_cpl_enqueue_resp_ready_reg <= 1'b0;
-        m_axis_cpl_enqueue_commit_valid_reg <= 1'b0;
-        m_axis_pcie_axi_dma_read_desc_valid_reg <= 1'b0;
+        m_axis_desc_req_valid_reg <= 1'b0;
+        s_axis_desc_tready_reg <= 1'b0;
+        m_axis_cpl_req_valid_reg <= 1'b0;
         m_axis_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
         m_axis_rx_desc_valid_reg <= 1'b0;
         s_axis_rx_ptp_ts_ready_reg <= 1'b0;
         s_axis_rx_csum_ready_reg <= 1'b0;
 
-        pkt_write_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
-        cpl_write_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
-
         desc_table_active <= 0;
         desc_table_invalid <= 0;
         desc_table_desc_fetched <= 0;
@@ -1110,20 +747,13 @@ always @(posedge clk) begin
     end else begin
         s_axis_rx_req_ready_reg <= s_axis_rx_req_ready_next;
         m_axis_rx_req_status_valid_reg <= m_axis_rx_req_status_valid_next;
-        m_axis_desc_dequeue_req_valid_reg <= m_axis_desc_dequeue_req_valid_next;
-        s_axis_desc_dequeue_resp_ready_reg <= s_axis_desc_dequeue_resp_ready_next;
-        m_axis_desc_dequeue_commit_valid_reg <= m_axis_desc_dequeue_commit_valid_next;
-        m_axis_cpl_enqueue_req_valid_reg <= m_axis_cpl_enqueue_req_valid_next;
-        s_axis_cpl_enqueue_resp_ready_reg <= s_axis_cpl_enqueue_resp_ready_next;
-        m_axis_cpl_enqueue_commit_valid_reg <= m_axis_cpl_enqueue_commit_valid_next;
-        m_axis_pcie_axi_dma_read_desc_valid_reg <= m_axis_pcie_axi_dma_read_desc_valid_next;
+        m_axis_desc_req_valid_reg <= m_axis_desc_req_valid_next;
+        s_axis_desc_tready_reg <= s_axis_desc_tready_next;
+        m_axis_cpl_req_valid_reg <= m_axis_cpl_req_valid_next;
         m_axis_pcie_axi_dma_write_desc_valid_reg <= m_axis_pcie_axi_dma_write_desc_valid_next;
         m_axis_rx_desc_valid_reg <= m_axis_rx_desc_valid_next;
         s_axis_rx_ptp_ts_ready_reg <= s_axis_rx_ptp_ts_ready_next;
         s_axis_rx_csum_ready_reg <= s_axis_rx_csum_ready_next;
-
-        pkt_write_pcie_axi_dma_write_desc_valid_reg <= pkt_write_pcie_axi_dma_write_desc_valid_next;
-        cpl_write_pcie_axi_dma_write_desc_valid_reg <= cpl_write_pcie_axi_dma_write_desc_valid_next;
         
         if (desc_table_start_en) begin
             desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b1;
@@ -1163,11 +793,6 @@ always @(posedge clk) begin
         if (desc_table_cpl_enqueue_start_en) begin
             desc_table_cpl_enqueue_start_ptr_reg <= desc_table_cpl_enqueue_start_ptr_reg + 1;
         end
-        if (desc_table_cpl_write_en) begin
-            if (desc_table_cpl_write_invalid) begin
-                desc_table_invalid[desc_table_cpl_write_ptr & DESC_PTR_MASK] <= 1'b1;
-            end
-        end
         if (desc_table_cpl_write_done_en) begin
             desc_table_cpl_write_done[desc_table_cpl_write_done_ptr & DESC_PTR_MASK] <= 1'b1;
         end
@@ -1184,22 +809,15 @@ always @(posedge clk) begin
         end
     end
 
-    s_axis_rx_req_tag_reg <= s_axis_rx_req_tag_next;
-
     m_axis_rx_req_status_len_reg <= m_axis_rx_req_status_len_next;
     m_axis_rx_req_status_tag_reg <= m_axis_rx_req_status_tag_next;
 
-    m_axis_desc_dequeue_req_queue_reg <= m_axis_desc_dequeue_req_queue_next;
-    m_axis_desc_dequeue_req_tag_reg <= m_axis_desc_dequeue_req_tag_next;
-    m_axis_desc_dequeue_commit_op_tag_reg <= m_axis_desc_dequeue_commit_op_tag_next;
-    m_axis_cpl_enqueue_req_queue_reg <= m_axis_cpl_enqueue_req_queue_next;
-    m_axis_cpl_enqueue_req_tag_reg <= m_axis_cpl_enqueue_req_tag_next;
-    m_axis_cpl_enqueue_commit_op_tag_reg <= m_axis_cpl_enqueue_commit_op_tag_next;
+    m_axis_desc_req_queue_reg <= m_axis_desc_req_queue_next;
+    m_axis_desc_req_tag_reg <= m_axis_desc_req_tag_next;
 
-    m_axis_pcie_axi_dma_read_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
-    m_axis_pcie_axi_dma_read_desc_axi_addr_reg <= m_axis_pcie_axi_dma_read_desc_axi_addr_next;
-    m_axis_pcie_axi_dma_read_desc_len_reg <= m_axis_pcie_axi_dma_read_desc_len_next;
-    m_axis_pcie_axi_dma_read_desc_tag_reg <= m_axis_pcie_axi_dma_read_desc_tag_next;
+    m_axis_cpl_req_queue_reg <= m_axis_cpl_req_queue_next;
+    m_axis_cpl_req_tag_reg <= m_axis_cpl_req_tag_next;
+    m_axis_cpl_req_data_reg <= m_axis_cpl_req_data_next;
 
     m_axis_pcie_axi_dma_write_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
     m_axis_pcie_axi_dma_write_desc_axi_addr_reg <= m_axis_pcie_axi_dma_write_desc_axi_addr_next;
@@ -1210,16 +828,6 @@ always @(posedge clk) begin
     m_axis_rx_desc_len_reg <= m_axis_rx_desc_len_next;
     m_axis_rx_desc_tag_reg <= m_axis_rx_desc_tag_next;
 
-    pkt_write_pcie_axi_dma_write_desc_pcie_addr_reg <= pkt_write_pcie_axi_dma_write_desc_pcie_addr_next;
-    pkt_write_pcie_axi_dma_write_desc_axi_addr_reg <= pkt_write_pcie_axi_dma_write_desc_axi_addr_next;
-    pkt_write_pcie_axi_dma_write_desc_len_reg <= pkt_write_pcie_axi_dma_write_desc_len_next;
-    pkt_write_pcie_axi_dma_write_desc_tag_reg <= pkt_write_pcie_axi_dma_write_desc_tag_next;
-
-    cpl_write_pcie_axi_dma_write_desc_pcie_addr_reg <= cpl_write_pcie_axi_dma_write_desc_pcie_addr_next;
-    cpl_write_pcie_axi_dma_write_desc_axi_addr_reg <= cpl_write_pcie_axi_dma_write_desc_axi_addr_next;
-    cpl_write_pcie_axi_dma_write_desc_len_reg <= cpl_write_pcie_axi_dma_write_desc_len_next;
-    cpl_write_pcie_axi_dma_write_desc_tag_reg <= cpl_write_pcie_axi_dma_write_desc_tag_next;
-
     if (desc_table_start_en) begin
         desc_table_queue[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue;
         desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
@@ -1231,7 +839,10 @@ always @(posedge clk) begin
     if (desc_table_dequeue_en) begin
         desc_table_queue_ptr[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_queue_ptr;
         desc_table_cpl_queue[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_cpl_queue;
-        desc_table_queue_op_tag[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_queue_op_tag;
+    end
+    if (desc_table_desc_fetched_en) begin
+        desc_table_desc_len[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_len;
+        desc_table_pcie_addr[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_pcie_addr;
     end
     if (desc_table_store_ptp_ts_en) begin
         desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts;
@@ -1239,9 +850,6 @@ always @(posedge clk) begin
     if (desc_table_store_csum_en) begin
         desc_table_csum[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] <= desc_table_store_csum;
     end
-    if (desc_table_cpl_write_en) begin
-        desc_table_cpl_queue_op_tag[desc_table_cpl_write_ptr & DESC_PTR_MASK] <= desc_table_cpl_write_queue_op_tag;
-    end
 end
 
 endmodule
diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v
index 44f2d1a6f..65735cb22 100644
--- a/fpga/common/rtl/tx_engine.v
+++ b/fpga/common/rtl/tx_engine.v
@@ -48,6 +48,10 @@ module tx_engine #
     parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
     // Width of AXI ID signal
     parameter AXI_ID_WIDTH = 8,
+    // Width of AXI stream interface in bits
+    parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
+    // AXI stream tkeep signal width (words per cycle)
+    parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
     // PCIe address width
     parameter PCIE_ADDR_WIDTH = 64,
     // PCIe DMA length field width
@@ -56,6 +60,8 @@ module tx_engine #
     parameter AXI_DMA_LEN_WIDTH = 20,
     // Transmit request tag field width
     parameter REQ_TAG_WIDTH = 8,
+    // Descriptor request tag field width
+    parameter DESC_REQ_TAG_WIDTH = 8,
     // PCIe DMA tag field width
     parameter PCIE_DMA_TAG_WIDTH = 8,
     // AXI DMA tag field width
@@ -74,8 +80,10 @@ module tx_engine #
     parameter DESC_TABLE_SIZE = 8,
     // Packet table size (number of in-progress packets)
     parameter PKT_TABLE_SIZE = 8,
-    // AXI base address of this module (as seen by PCIe DMA)
-    parameter AXI_BASE_ADDR = 16'h0000,
+    // Descriptor size (in bytes)
+    parameter DESC_SIZE = 16,
+    // Descriptor size (in bytes)
+    parameter CPL_SIZE = 32,
     // AXI address of packet scratchpad RAM (as seen by PCIe DMA and port AXI DMA)
     parameter SCRATCH_PKT_AXI_ADDR = 16'h1000,
     // Packet scratchpad RAM log segment size
@@ -105,59 +113,51 @@ module tx_engine #
     output wire                             m_axis_tx_req_status_valid,
 
     /*
-     * Descriptor dequeue request output
+     * Descriptor request output
      */
-    output wire [QUEUE_INDEX_WIDTH-1:0]     m_axis_desc_dequeue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]   m_axis_desc_dequeue_req_tag,
-    output wire                             m_axis_desc_dequeue_req_valid,
-    input  wire                             m_axis_desc_dequeue_req_ready,
+    output wire [QUEUE_INDEX_WIDTH-1:0]     m_axis_desc_req_queue,
+    output wire [DESC_REQ_TAG_WIDTH-1:0]    m_axis_desc_req_tag,
+    output wire                             m_axis_desc_req_valid,
+    input  wire                             m_axis_desc_req_ready,
 
     /*
-     * Descriptor dequeue response input
+     * Descriptor request status input
      */
-    input  wire [QUEUE_INDEX_WIDTH-1:0]     s_axis_desc_dequeue_resp_queue,
-    input  wire [QUEUE_PTR_WIDTH-1:0]       s_axis_desc_dequeue_resp_ptr,
-    input  wire [PCIE_ADDR_WIDTH-1:0]       s_axis_desc_dequeue_resp_addr,
-    input  wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_dequeue_resp_cpl,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]   s_axis_desc_dequeue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]    s_axis_desc_dequeue_resp_op_tag,
-    input  wire                             s_axis_desc_dequeue_resp_empty,
-    input  wire                             s_axis_desc_dequeue_resp_error,
-    input  wire                             s_axis_desc_dequeue_resp_valid,
-    output wire                             s_axis_desc_dequeue_resp_ready,
+    input  wire [QUEUE_INDEX_WIDTH-1:0]     s_axis_desc_req_status_queue,
+    input  wire [QUEUE_PTR_WIDTH-1:0]       s_axis_desc_req_status_ptr,
+    input  wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]    s_axis_desc_req_status_tag,
+    input  wire                             s_axis_desc_req_status_empty,
+    input  wire                             s_axis_desc_req_status_error,
+    input  wire                             s_axis_desc_req_status_valid,
 
     /*
-     * Descriptor dequeue commit output
+     * Descriptor data input
      */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]    m_axis_desc_dequeue_commit_op_tag,
-    output wire                             m_axis_desc_dequeue_commit_valid,
-    input  wire                             m_axis_desc_dequeue_commit_ready,
+    input  wire [AXIS_DATA_WIDTH-1:0]       s_axis_desc_tdata,
+    input  wire [AXIS_KEEP_WIDTH-1:0]       s_axis_desc_tkeep,
+    input  wire                             s_axis_desc_tvalid,
+    output wire                             s_axis_desc_tready,
+    input  wire                             s_axis_desc_tlast,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]    s_axis_desc_tid,
+    input  wire                             s_axis_desc_tuser,
 
     /*
-     * Completion enqueue request output
+     * Completion request output
      */
-    output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue,
-    output wire [QUEUE_REQ_TAG_WIDTH-1:0]   m_axis_cpl_enqueue_req_tag,
-    output wire                             m_axis_cpl_enqueue_req_valid,
-    input  wire                             m_axis_cpl_enqueue_req_ready,
+    output wire [QUEUE_INDEX_WIDTH-1:0]     m_axis_cpl_req_queue,
+    output wire [DESC_REQ_TAG_WIDTH-1:0]    m_axis_cpl_req_tag,
+    output wire [CPL_SIZE*8-1:0]            m_axis_cpl_req_data,
+    output wire                             m_axis_cpl_req_valid,
+    input  wire                             m_axis_cpl_req_ready,
 
     /*
-     * Completion enqueue response input
+     * Completion request status input
      */
-    input  wire [PCIE_ADDR_WIDTH-1:0]       s_axis_cpl_enqueue_resp_addr,
-    input  wire [QUEUE_REQ_TAG_WIDTH-1:0]   s_axis_cpl_enqueue_resp_tag,
-    input  wire [QUEUE_OP_TAG_WIDTH-1:0]    s_axis_cpl_enqueue_resp_op_tag,
-    input  wire                             s_axis_cpl_enqueue_resp_full,
-    input  wire                             s_axis_cpl_enqueue_resp_error,
-    input  wire                             s_axis_cpl_enqueue_resp_valid,
-    output wire                             s_axis_cpl_enqueue_resp_ready,
-
-    /*
-     * Completion enqueue commit output
-     */
-    output wire [QUEUE_OP_TAG_WIDTH-1:0]    m_axis_cpl_enqueue_commit_op_tag,
-    output wire                             m_axis_cpl_enqueue_commit_valid,
-    input  wire                             m_axis_cpl_enqueue_commit_ready,
+    input  wire [DESC_REQ_TAG_WIDTH-1:0]    s_axis_cpl_req_status_tag,
+    input  wire                             s_axis_cpl_req_status_full,
+    input  wire                             s_axis_cpl_req_status_error,
+    input  wire                             s_axis_cpl_req_status_valid,
 
     /*
      * PCIe AXI DMA read descriptor output
@@ -175,22 +175,6 @@ module tx_engine #
     input  wire [PCIE_DMA_TAG_WIDTH-1:0]    s_axis_pcie_axi_dma_read_desc_status_tag,
     input  wire                             s_axis_pcie_axi_dma_read_desc_status_valid,
 
-    /*
-     * PCIe AXI DMA write descriptor output
-     */
-    output wire [PCIE_ADDR_WIDTH-1:0]       m_axis_pcie_axi_dma_write_desc_pcie_addr,
-    output wire [AXI_ADDR_WIDTH-1:0]        m_axis_pcie_axi_dma_write_desc_axi_addr,
-    output wire [PCIE_DMA_LEN_WIDTH-1:0]    m_axis_pcie_axi_dma_write_desc_len,
-    output wire [PCIE_DMA_TAG_WIDTH-1:0]    m_axis_pcie_axi_dma_write_desc_tag,
-    output wire                             m_axis_pcie_axi_dma_write_desc_valid,
-    input  wire                             m_axis_pcie_axi_dma_write_desc_ready,
-
-    /*
-     * PCIe AXI DMA write descriptor status input
-     */
-    input  wire [PCIE_DMA_TAG_WIDTH-1:0]    s_axis_pcie_axi_dma_write_desc_status_tag,
-    input  wire                             s_axis_pcie_axi_dma_write_desc_status_valid,
-
     /*
      * Transmit descriptor output
      */
@@ -223,45 +207,6 @@ module tx_engine #
     input  wire                             s_axis_tx_ptp_ts_valid,
     output wire                             s_axis_tx_ptp_ts_ready,
 
-    /*
-     * AXI slave interface
-     */
-    input  wire [AXI_ID_WIDTH-1:0]          s_axi_awid,
-    input  wire [AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,
-    input  wire [7:0]                       s_axi_awlen,
-    input  wire [2:0]                       s_axi_awsize,
-    input  wire [1:0]                       s_axi_awburst,
-    input  wire                             s_axi_awlock,
-    input  wire [3:0]                       s_axi_awcache,
-    input  wire [2:0]                       s_axi_awprot,
-    input  wire                             s_axi_awvalid,
-    output wire                             s_axi_awready,
-    input  wire [AXI_DATA_WIDTH-1:0]        s_axi_wdata,
-    input  wire [AXI_STRB_WIDTH-1:0]        s_axi_wstrb,
-    input  wire                             s_axi_wlast,
-    input  wire                             s_axi_wvalid,
-    output wire                             s_axi_wready,
-    output wire [AXI_ID_WIDTH-1:0]          s_axi_bid,
-    output wire [1:0]                       s_axi_bresp,
-    output wire                             s_axi_bvalid,
-    input  wire                             s_axi_bready,
-    input  wire [AXI_ID_WIDTH-1:0]          s_axi_arid,
-    input  wire [AXI_ADDR_WIDTH-1:0]        s_axi_araddr,
-    input  wire [7:0]                       s_axi_arlen,
-    input  wire [2:0]                       s_axi_arsize,
-    input  wire [1:0]                       s_axi_arburst,
-    input  wire                             s_axi_arlock,
-    input  wire [3:0]                       s_axi_arcache,
-    input  wire [2:0]                       s_axi_arprot,
-    input  wire                             s_axi_arvalid,
-    output wire                             s_axi_arready,
-    output wire [AXI_ID_WIDTH-1:0]          s_axi_rid,
-    output wire [AXI_DATA_WIDTH-1:0]        s_axi_rdata,
-    output wire [1:0]                       s_axi_rresp,
-    output wire                             s_axi_rlast,
-    output wire                             s_axi_rvalid,
-    input  wire                             s_axi_rready,
-
     /*
      * Configuration
      */
@@ -277,16 +222,9 @@ parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
 parameter CL_PKT_TABLE_SIZE = $clog2(PKT_TABLE_SIZE);
 parameter PKT_TAG_MASK = {CL_PKT_TABLE_SIZE{1'b1}};
 
-parameter DATA_FLAG = 1 << CL_DESC_TABLE_SIZE;
-
-parameter DESC_SIZE = 16;
-parameter CPL_SIZE = 32;
-
-parameter BLOCK_SIZE = DESC_SIZE > CPL_SIZE ? DESC_SIZE : CPL_SIZE;
-
 // bus width assertions
 initial begin
-    if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
+    if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
         $error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
         $finish;
     end
@@ -301,16 +239,6 @@ initial begin
         $finish;
     end
 
-    if (AXI_STRB_WIDTH < BLOCK_SIZE) begin
-        $error("Error: AXI interface width must be at least as large as one descriptor (instance %m)");
-        $finish;
-    end
-
-    if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
-        $error("Error: AXI base address must be aligned to interface width (instance %m)");
-        $finish;
-    end
-
     if (SCRATCH_PKT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
         $error("Error: AXI base address must be aligned to interface width (instance %m)");
         $finish;
@@ -321,36 +249,38 @@ initial begin
         $finish;
     end
 
+    if (QUEUE_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
+        $error("Error: QUEUE_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)");
+        $finish;
+    end
+
+    if (DESC_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
+        $error("Error: DESC_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)");
+        $finish;
+    end
+
     if (QUEUE_REQ_TAG_WIDTH < REQ_TAG_WIDTH) begin
         $error("Error: QUEUE_REQ_TAG_WIDTH must be at least REQ_TAG_WIDTH (instance %m)");
         $finish;
     end
 end
 
-reg [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag_reg = {REQ_TAG_WIDTH{1'b0}}, s_axis_tx_req_tag_next;
 reg s_axis_tx_req_ready_reg = 1'b0, s_axis_tx_req_ready_next;
 
 reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_tx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_tx_req_status_len_next;
 reg [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_tx_req_status_tag_next;
 reg m_axis_tx_req_status_valid_reg = 1'b0, m_axis_tx_req_status_valid_next;
 
-reg [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_dequeue_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_desc_dequeue_req_queue_next;
-reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_desc_dequeue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_req_tag_next;
-reg m_axis_desc_dequeue_req_valid_reg = 1'b0, m_axis_desc_dequeue_req_valid_next;
+reg [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_desc_req_queue_next;
+reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_desc_req_tag_next;
+reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next;
 
-reg s_axis_desc_dequeue_resp_ready_reg = 1'b0, s_axis_desc_dequeue_resp_ready_next;
+reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next;
 
-reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_desc_dequeue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_commit_op_tag_next;
-reg m_axis_desc_dequeue_commit_valid_reg = 1'b0, m_axis_desc_dequeue_commit_valid_next;
-
-reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_queue_next;
-reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_cpl_enqueue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_tag_next;
-reg m_axis_cpl_enqueue_req_valid_reg = 1'b0, m_axis_cpl_enqueue_req_valid_next;
-
-reg s_axis_cpl_enqueue_resp_ready_reg = 1'b0, s_axis_cpl_enqueue_resp_ready_next;
-
-reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_cpl_enqueue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_commit_op_tag_next;
-reg m_axis_cpl_enqueue_commit_valid_reg = 1'b0, m_axis_cpl_enqueue_commit_valid_next;
+reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next;
+reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next;
+reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next;
+reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;
 
 reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
 reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_axi_addr_next;
@@ -358,12 +288,6 @@ reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len_reg = {PCIE_DMA_L
 reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_tag_next;
 reg m_axis_pcie_axi_dma_read_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_read_desc_valid_next;
 
-reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
-reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_axi_addr_next;
-reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_len_next;
-reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_tag_next;
-reg m_axis_pcie_axi_dma_write_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_write_desc_valid_next;
-
 reg [AXI_ADDR_WIDTH-1:0] m_axis_tx_desc_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_tx_desc_addr_next;
 reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_tx_desc_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_tx_desc_len_next;
 reg [AXI_DMA_TAG_WIDTH-1:0] m_axis_tx_desc_tag_reg = {AXI_DMA_TAG_WIDTH{1'b0}}, m_axis_tx_desc_tag_next;
@@ -385,23 +309,6 @@ reg [AXI_DMA_LEN_WIDTH-1:0] finish_tx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'
 reg [REQ_TAG_WIDTH-1:0] finish_tx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, finish_tx_req_status_tag_next;
 reg finish_tx_req_status_valid_reg = 1'b0, finish_tx_req_status_valid_next;
 
-reg [PCIE_ADDR_WIDTH-1:0] desc_fetch_pcie_axi_dma_read_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, desc_fetch_pcie_axi_dma_read_desc_pcie_addr_next;
-reg [AXI_ADDR_WIDTH-1:0] desc_fetch_pcie_axi_dma_read_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, desc_fetch_pcie_axi_dma_read_desc_axi_addr_next;
-reg [PCIE_DMA_LEN_WIDTH-1:0] desc_fetch_pcie_axi_dma_read_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, desc_fetch_pcie_axi_dma_read_desc_len_next;
-reg [PCIE_DMA_TAG_WIDTH-1:0] desc_fetch_pcie_axi_dma_read_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, desc_fetch_pcie_axi_dma_read_desc_tag_next;
-reg desc_fetch_pcie_axi_dma_read_desc_valid_reg = 1'b0, desc_fetch_pcie_axi_dma_read_desc_valid_next;
-
-reg [PCIE_ADDR_WIDTH-1:0] pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_next;
-reg [AXI_ADDR_WIDTH-1:0] pkt_fetch_pcie_axi_dma_read_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, pkt_fetch_pcie_axi_dma_read_desc_axi_addr_next;
-reg [PCIE_DMA_LEN_WIDTH-1:0] pkt_fetch_pcie_axi_dma_read_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, pkt_fetch_pcie_axi_dma_read_desc_len_next;
-reg [PCIE_DMA_TAG_WIDTH-1:0] pkt_fetch_pcie_axi_dma_read_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, pkt_fetch_pcie_axi_dma_read_desc_tag_next;
-reg pkt_fetch_pcie_axi_dma_read_desc_valid_reg = 1'b0, pkt_fetch_pcie_axi_dma_read_desc_valid_next;
-
-reg [CL_DESC_TABLE_SIZE+1-1:0] active_count_reg = 0;
-reg inc_active;
-reg dec_active_1;
-reg dec_active_2;
-
 reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
 reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0;
 reg [DESC_TABLE_SIZE-1:0] desc_table_desc_fetched = 0;
@@ -412,8 +319,6 @@ reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
 reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0];
 reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0];
 reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0];
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_cpl_queue_op_tag[DESC_TABLE_SIZE-1:0];
 reg [6:0] desc_table_csum_start[DESC_TABLE_SIZE-1:0];
 reg [7:0] desc_table_csum_offset[DESC_TABLE_SIZE-1:0];
 reg desc_table_csum_enable[DESC_TABLE_SIZE-1:0];
@@ -425,16 +330,23 @@ reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0;
 reg [QUEUE_INDEX_WIDTH-1:0] desc_table_start_queue;
 reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag;
-reg [QUEUE_PTR_WIDTH-1:0] desc_table_start_queue_ptr;
-reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_start_cpl_queue;
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_start_queue_op_tag;
 reg desc_table_start_en;
+reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr;
+reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr;
+reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue;
+reg desc_table_dequeue_invalid;
+reg desc_table_dequeue_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_fetched_ptr;
 reg desc_table_desc_fetched_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_data_fetch_start_ptr_reg = 0;
 reg [CL_PKT_TABLE_SIZE-1:0] desc_table_data_fetch_start_pkt;
 reg desc_table_data_fetch_start_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_data_fetched_ptr;
+reg [6:0] desc_table_desc_fetched_csum_start;
+reg [7:0] desc_table_desc_fetched_csum_offset;
+reg desc_table_desc_fetched_csum_enable;
+reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
+reg [PCIE_ADDR_WIDTH-1:0] desc_table_desc_fetched_pcie_addr;
 reg desc_table_data_fetched_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_tx_start_ptr_reg = 0;
 reg desc_table_tx_start_en;
@@ -445,10 +357,6 @@ reg [95:0] desc_table_store_ptp_ts;
 reg desc_table_store_ptp_ts_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_cpl_enqueue_start_ptr_reg = 0;
 reg desc_table_cpl_enqueue_start_en;
-reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_ptr;
-reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_cpl_write_queue_op_tag;
-reg desc_table_cpl_write_invalid;
-reg desc_table_cpl_write_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done_ptr;
 reg desc_table_cpl_write_done_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_finish_ptr_reg = 0;
@@ -466,23 +374,16 @@ assign m_axis_tx_req_status_len = m_axis_tx_req_status_len_reg;
 assign m_axis_tx_req_status_tag = m_axis_tx_req_status_tag_reg;
 assign m_axis_tx_req_status_valid = m_axis_tx_req_status_valid_reg;
 
-assign m_axis_desc_dequeue_req_queue = m_axis_desc_dequeue_req_queue_reg;
-assign m_axis_desc_dequeue_req_tag = m_axis_desc_dequeue_req_tag_reg;
-assign m_axis_desc_dequeue_req_valid = m_axis_desc_dequeue_req_valid_reg;
+assign m_axis_desc_req_queue = m_axis_desc_req_queue_reg;
+assign m_axis_desc_req_tag = m_axis_desc_req_tag_reg;
+assign m_axis_desc_req_valid = m_axis_desc_req_valid_reg;
 
-assign s_axis_desc_dequeue_resp_ready = s_axis_desc_dequeue_resp_ready_reg;
+assign s_axis_desc_tready = s_axis_desc_tready_reg;
 
-assign m_axis_desc_dequeue_commit_op_tag = m_axis_desc_dequeue_commit_op_tag_reg;
-assign m_axis_desc_dequeue_commit_valid = m_axis_desc_dequeue_commit_valid_reg;
-
-assign m_axis_cpl_enqueue_req_queue = m_axis_cpl_enqueue_req_queue_reg;
-assign m_axis_cpl_enqueue_req_tag = m_axis_cpl_enqueue_req_tag_reg;
-assign m_axis_cpl_enqueue_req_valid = m_axis_cpl_enqueue_req_valid_reg;
-
-assign s_axis_cpl_enqueue_resp_ready = s_axis_cpl_enqueue_resp_ready_reg;
-
-assign m_axis_cpl_enqueue_commit_op_tag = m_axis_cpl_enqueue_commit_op_tag_reg;
-assign m_axis_cpl_enqueue_commit_valid = m_axis_cpl_enqueue_commit_valid_reg;
+assign m_axis_cpl_req_queue = m_axis_cpl_req_queue_reg;
+assign m_axis_cpl_req_tag = m_axis_cpl_req_tag_reg;
+assign m_axis_cpl_req_data = m_axis_cpl_req_data_reg;
+assign m_axis_cpl_req_valid = m_axis_cpl_req_valid_reg;
 
 assign m_axis_pcie_axi_dma_read_desc_pcie_addr = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
 assign m_axis_pcie_axi_dma_read_desc_axi_addr = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
@@ -490,12 +391,6 @@ assign m_axis_pcie_axi_dma_read_desc_len = m_axis_pcie_axi_dma_read_desc_len_reg
 assign m_axis_pcie_axi_dma_read_desc_tag = m_axis_pcie_axi_dma_read_desc_tag_reg;
 assign m_axis_pcie_axi_dma_read_desc_valid = m_axis_pcie_axi_dma_read_desc_valid_reg;
 
-assign m_axis_pcie_axi_dma_write_desc_pcie_addr = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
-assign m_axis_pcie_axi_dma_write_desc_axi_addr = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
-assign m_axis_pcie_axi_dma_write_desc_len = m_axis_pcie_axi_dma_write_desc_len_reg;
-assign m_axis_pcie_axi_dma_write_desc_tag = m_axis_pcie_axi_dma_write_desc_tag_reg;
-assign m_axis_pcie_axi_dma_write_desc_valid = m_axis_pcie_axi_dma_write_desc_valid_reg;
-
 assign m_axis_tx_desc_addr = m_axis_tx_desc_addr_reg;
 assign m_axis_tx_desc_len = m_axis_tx_desc_len_reg;
 assign m_axis_tx_desc_tag = m_axis_tx_desc_tag_reg;
@@ -523,175 +418,6 @@ pkt_table_free_enc_inst (
     .output_unencoded()
 );
 
-wire [AXI_ID_WIDTH-1:0]   ram_wr_cmd_id;
-wire [AXI_ADDR_WIDTH-1:0] ram_wr_cmd_addr;
-wire [AXI_DATA_WIDTH-1:0] ram_wr_cmd_data;
-wire [AXI_STRB_WIDTH-1:0] ram_wr_cmd_strb;
-wire                      ram_wr_cmd_en;
-
-wire [AXI_ID_WIDTH-1:0]   ram_rd_cmd_id;
-wire [AXI_ADDR_WIDTH-1:0] ram_rd_cmd_addr;
-wire                      ram_rd_cmd_en;
-wire                      ram_rd_cmd_last;
-reg                       ram_rd_cmd_ready_reg = 1'b0;
-reg  [AXI_ID_WIDTH-1:0]   ram_rd_resp_id_reg = {AXI_ID_WIDTH{1'b0}};
-reg  [AXI_DATA_WIDTH-1:0] ram_rd_resp_data_reg = {AXI_DATA_WIDTH{1'b0}};
-reg                       ram_rd_resp_last_reg = 1'b0;
-reg                       ram_rd_resp_valid_reg = 1'b0;
-wire                      ram_rd_resp_ready;
-
-axi_ram_wr_if #(
-    .DATA_WIDTH(AXI_DATA_WIDTH),
-    .ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .STRB_WIDTH(AXI_STRB_WIDTH),
-    .ID_WIDTH(AXI_ID_WIDTH),
-    .AWUSER_ENABLE(0),
-    .WUSER_ENABLE(0),
-    .BUSER_ENABLE(0)
-)
-axi_ram_wr_if_inst (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awqos(0),
-    .s_axi_awregion(0),
-    .s_axi_awuser(0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .ram_wr_cmd_id(ram_wr_cmd_id),
-    .ram_wr_cmd_addr(ram_wr_cmd_addr),
-    .ram_wr_cmd_lock(),
-    .ram_wr_cmd_cache(),
-    .ram_wr_cmd_prot(),
-    .ram_wr_cmd_qos(),
-    .ram_wr_cmd_region(),
-    .ram_wr_cmd_auser(),
-    .ram_wr_cmd_data(ram_wr_cmd_data),
-    .ram_wr_cmd_strb(ram_wr_cmd_strb),
-    .ram_wr_cmd_user(),
-    .ram_wr_cmd_en(ram_wr_cmd_en),
-    .ram_wr_cmd_last(),
-    .ram_wr_cmd_ready(1'b1)
-);
-
-axi_ram_rd_if #(
-    .DATA_WIDTH(AXI_DATA_WIDTH),
-    .ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .STRB_WIDTH(AXI_STRB_WIDTH),
-    .ID_WIDTH(AXI_ID_WIDTH),
-    .ARUSER_ENABLE(0),
-    .RUSER_ENABLE(0),
-    .PIPELINE_OUTPUT(0)
-)
-axi_ram_rd_if_inst (
-    .clk(clk),
-    .rst(rst),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arqos(0),
-    .s_axi_arregion(0),
-    .s_axi_aruser(0),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .ram_rd_cmd_id(ram_rd_cmd_id),
-    .ram_rd_cmd_addr(ram_rd_cmd_addr),
-    .ram_rd_cmd_lock(),
-    .ram_rd_cmd_cache(),
-    .ram_rd_cmd_prot(),
-    .ram_rd_cmd_qos(),
-    .ram_rd_cmd_region(),
-    .ram_rd_cmd_auser(),
-    .ram_rd_cmd_en(ram_rd_cmd_en),
-    .ram_rd_cmd_last(ram_rd_cmd_last),
-    .ram_rd_cmd_ready(ram_rd_cmd_ready_reg),
-    .ram_rd_resp_id(ram_rd_resp_id_reg),
-    .ram_rd_resp_data(ram_rd_resp_data_reg),
-    .ram_rd_resp_last(ram_rd_resp_last_reg),
-    .ram_rd_resp_user(0),
-    .ram_rd_resp_valid(ram_rd_resp_valid_reg),
-    .ram_rd_resp_ready(ram_rd_resp_ready)
-);
-
-always @(posedge clk) begin
-    if (ram_wr_cmd_en) begin
-        // AXI write
-        if (ram_wr_cmd_addr[CL_DESC_TABLE_SIZE+5] == 0) begin
-            // descriptors
-            // TODO byte enables
-            if (TX_CHECKSUM_ENABLE) begin
-                desc_table_csum_start[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[23:16];
-                desc_table_csum_offset[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[30:24];
-                desc_table_csum_enable[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[31];
-            end
-            desc_table_len[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[64:32];
-            desc_table_pcie_addr[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[127:64];
-        end
-    end
-
-    ram_rd_resp_valid_reg <= ram_rd_resp_valid_reg && !ram_rd_resp_ready;
-    ram_rd_cmd_ready_reg <= !ram_rd_resp_valid_reg || ram_rd_resp_ready;
-
-    if (ram_rd_cmd_en && ram_rd_cmd_ready_reg) begin
-        // AXI read
-        ram_rd_resp_id_reg <= ram_rd_cmd_id;
-        ram_rd_resp_data_reg <= 0;
-        ram_rd_resp_last_reg <= ram_rd_cmd_last;
-        ram_rd_resp_valid_reg <= 1'b1;
-        ram_rd_cmd_ready_reg <= ram_rd_resp_ready;
-
-        if (ram_rd_cmd_addr[CL_DESC_TABLE_SIZE+5] == 0) begin
-            // descriptors
-            ram_rd_resp_data_reg[64:32] <= desc_table_len[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            ram_rd_resp_data_reg[127:64] <= desc_table_pcie_addr[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-        end else begin
-            // completions
-            ram_rd_resp_data_reg[15:0]  <= desc_table_queue[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            ram_rd_resp_data_reg[31:16] <= desc_table_queue_ptr[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            ram_rd_resp_data_reg[47:32] <= desc_table_len[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
-            if (PTP_TS_ENABLE) begin
-                //ram_rd_resp_data_reg[127:64] <= desc_table_ptp_ts[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] >> 16;
-                ram_rd_resp_data_reg[111:64] <= desc_table_ptp_ts[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] >> 16;
-            end
-        end
-    end
-
-    if (rst) begin
-        ram_rd_cmd_ready_reg <= 1'b1;
-        ram_rd_resp_valid_reg <= 1'b0;
-    end
-end
-
 // reg [15:0] stall_cnt = 0;
 // wire stalled = stall_cnt[12];
 
@@ -728,30 +454,22 @@ end
 // );
 
 always @* begin
-    s_axis_tx_req_tag_next = s_axis_tx_req_tag_reg;
     s_axis_tx_req_ready_next = 1'b0;
 
     m_axis_tx_req_status_len_next = m_axis_tx_req_status_len_reg;
     m_axis_tx_req_status_tag_next = m_axis_tx_req_status_tag_reg;
     m_axis_tx_req_status_valid_next = 1'b0;
 
-    m_axis_desc_dequeue_req_queue_next = m_axis_desc_dequeue_req_queue_reg;
-    m_axis_desc_dequeue_req_tag_next = m_axis_desc_dequeue_req_tag_reg;
-    m_axis_desc_dequeue_req_valid_next = m_axis_desc_dequeue_req_valid_reg && !m_axis_desc_dequeue_req_ready;
+    m_axis_desc_req_queue_next = m_axis_desc_req_queue_reg;
+    m_axis_desc_req_tag_next = m_axis_desc_req_tag_reg;
+    m_axis_desc_req_valid_next = m_axis_desc_req_valid_reg && !m_axis_desc_req_ready;
 
-    s_axis_desc_dequeue_resp_ready_next = 1'b0;
+    s_axis_desc_tready_next = 1'b0;
 
-    m_axis_desc_dequeue_commit_op_tag_next = m_axis_desc_dequeue_commit_op_tag_reg;
-    m_axis_desc_dequeue_commit_valid_next = m_axis_desc_dequeue_commit_valid_reg && !m_axis_desc_dequeue_commit_ready;
-
-    m_axis_cpl_enqueue_req_queue_next = m_axis_cpl_enqueue_req_queue_reg;
-    m_axis_cpl_enqueue_req_tag_next = m_axis_cpl_enqueue_req_tag_reg;
-    m_axis_cpl_enqueue_req_valid_next = m_axis_cpl_enqueue_req_valid_reg && !m_axis_cpl_enqueue_req_ready;
-
-    s_axis_cpl_enqueue_resp_ready_next = 1'b0;
-
-    m_axis_cpl_enqueue_commit_op_tag_next = m_axis_cpl_enqueue_commit_op_tag_reg;
-    m_axis_cpl_enqueue_commit_valid_next = m_axis_cpl_enqueue_commit_valid_reg && !m_axis_cpl_enqueue_commit_ready;
+    m_axis_cpl_req_queue_next = m_axis_cpl_req_queue_reg;
+    m_axis_cpl_req_tag_next = m_axis_cpl_req_tag_reg;
+    m_axis_cpl_req_data_next = m_axis_cpl_req_data_reg;
+    m_axis_cpl_req_valid_next = m_axis_cpl_req_valid_reg && !m_axis_cpl_req_ready;
 
     m_axis_pcie_axi_dma_read_desc_pcie_addr_next = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
     m_axis_pcie_axi_dma_read_desc_axi_addr_next = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
@@ -759,12 +477,6 @@ always @* begin
     m_axis_pcie_axi_dma_read_desc_tag_next = m_axis_pcie_axi_dma_read_desc_tag_reg;
     m_axis_pcie_axi_dma_read_desc_valid_next = m_axis_pcie_axi_dma_read_desc_valid_reg && !m_axis_pcie_axi_dma_read_desc_ready;
 
-    m_axis_pcie_axi_dma_write_desc_pcie_addr_next = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
-    m_axis_pcie_axi_dma_write_desc_axi_addr_next = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
-    m_axis_pcie_axi_dma_write_desc_len_next = m_axis_pcie_axi_dma_write_desc_len_reg;
-    m_axis_pcie_axi_dma_write_desc_tag_next = m_axis_pcie_axi_dma_write_desc_tag_reg;
-    m_axis_pcie_axi_dma_write_desc_valid_next = m_axis_pcie_axi_dma_write_desc_valid_reg && !m_axis_pcie_axi_dma_write_desc_ready;
-
     m_axis_tx_desc_addr_next = m_axis_tx_desc_addr_reg;
     m_axis_tx_desc_len_next = m_axis_tx_desc_len_reg;
     m_axis_tx_desc_tag_next = m_axis_tx_desc_tag_reg;
@@ -786,29 +498,26 @@ always @* begin
     finish_tx_req_status_tag_next = finish_tx_req_status_tag_reg;
     finish_tx_req_status_valid_next = finish_tx_req_status_valid_reg;
 
-    desc_fetch_pcie_axi_dma_read_desc_pcie_addr_next = desc_fetch_pcie_axi_dma_read_desc_pcie_addr_reg;
-    desc_fetch_pcie_axi_dma_read_desc_axi_addr_next = desc_fetch_pcie_axi_dma_read_desc_axi_addr_reg;
-    desc_fetch_pcie_axi_dma_read_desc_len_next = desc_fetch_pcie_axi_dma_read_desc_len_reg;
-    desc_fetch_pcie_axi_dma_read_desc_tag_next = desc_fetch_pcie_axi_dma_read_desc_tag_reg;
-    desc_fetch_pcie_axi_dma_read_desc_valid_next = desc_fetch_pcie_axi_dma_read_desc_valid_reg;
-
-    pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_next = pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_reg;
-    pkt_fetch_pcie_axi_dma_read_desc_axi_addr_next = pkt_fetch_pcie_axi_dma_read_desc_axi_addr_reg;
-    pkt_fetch_pcie_axi_dma_read_desc_len_next = pkt_fetch_pcie_axi_dma_read_desc_len_reg;
-    pkt_fetch_pcie_axi_dma_read_desc_tag_next = pkt_fetch_pcie_axi_dma_read_desc_tag_reg;
-    pkt_fetch_pcie_axi_dma_read_desc_valid_next = pkt_fetch_pcie_axi_dma_read_desc_valid_reg;
-
-    inc_active = 1'b0;
-    dec_active_1 = 1'b0;
-    dec_active_2 = 1'b0;
-
-    desc_table_start_tag = s_axis_desc_dequeue_resp_tag;
-    desc_table_start_queue = s_axis_desc_dequeue_resp_queue;
-    desc_table_start_queue_ptr = s_axis_desc_dequeue_resp_ptr;
-    desc_table_start_cpl_queue = s_axis_desc_dequeue_resp_cpl;
-    desc_table_start_queue_op_tag = s_axis_desc_dequeue_resp_op_tag;
+    desc_table_start_tag = s_axis_tx_req_tag;
+    desc_table_start_queue = s_axis_tx_req_queue;
     desc_table_start_en = 1'b0;
-    desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
+    desc_table_dequeue_ptr = s_axis_desc_req_status_tag;
+    desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
+    desc_table_dequeue_cpl_queue = s_axis_desc_req_status_cpl;
+    desc_table_dequeue_invalid = 1'b0;
+    desc_table_dequeue_en = 1'b0;
+    desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
+    if (TX_CHECKSUM_ENABLE) begin
+        desc_table_desc_fetched_csum_start = s_axis_desc_tdata[23:16];
+        desc_table_desc_fetched_csum_offset = s_axis_desc_tdata[30:24];
+        desc_table_desc_fetched_csum_enable = s_axis_desc_tdata[31];
+    end else begin
+        desc_table_desc_fetched_csum_start = 0;
+        desc_table_desc_fetched_csum_offset = 0;
+        desc_table_desc_fetched_csum_enable = 0;
+    end
+    desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
+    desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
     desc_table_desc_fetched_en = 1'b0;
     desc_table_data_fetch_start_pkt = 0;
     desc_table_data_fetch_start_en = 1'b0;
@@ -820,11 +529,7 @@ always @* begin
     desc_table_store_ptp_ts = s_axis_tx_ptp_ts_96;
     desc_table_store_ptp_ts_en = 1'b0;
     desc_table_cpl_enqueue_start_en = 1'b0;
-    desc_table_cpl_write_ptr = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
-    desc_table_cpl_write_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag;
-    desc_table_cpl_write_invalid = 1'b0;
-    desc_table_cpl_write_en = 1'b0;
-    desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
+    desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
     desc_table_cpl_write_done_en = 1'b0;
     desc_table_finish_en = 1'b0;
 
@@ -833,62 +538,63 @@ always @* begin
     pkt_table_finish_ptr = desc_table_pkt[s_axis_tx_desc_status_tag & DESC_PTR_MASK];
     pkt_table_finish_en = 1'b0;
 
-    // queue query
+    // descriptor fetch
     // wait for transmit request
-    s_axis_tx_req_ready_next = enable && active_count_reg < DESC_TABLE_SIZE && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE) && (!m_axis_desc_dequeue_req_valid_reg || m_axis_desc_dequeue_req_ready);
+    s_axis_tx_req_ready_next = enable && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE) && (!m_axis_desc_req_valid || m_axis_desc_req_ready);
     if (s_axis_tx_req_ready && s_axis_tx_req_valid) begin
         s_axis_tx_req_ready_next = 1'b0;
+ 
+        // store in descriptor table
+        desc_table_start_tag = s_axis_tx_req_tag;
+        desc_table_start_queue = s_axis_tx_req_queue;
+        desc_table_start_en = 1'b1;
 
-        // initiate queue query
-        m_axis_desc_dequeue_req_queue_next = s_axis_tx_req_queue;
-        m_axis_desc_dequeue_req_tag_next = s_axis_tx_req_tag;
-        m_axis_desc_dequeue_req_valid_next = 1'b1;
-
-        inc_active = 1'b1;
+        // initiate descriptor fetch
+        m_axis_desc_req_queue_next = s_axis_tx_req_queue;
+        m_axis_desc_req_tag_next = desc_table_start_ptr_reg & DESC_PTR_MASK;
+        m_axis_desc_req_valid_next = 1'b1;
     end
 
     // descriptor fetch
     // wait for queue query response
-    s_axis_desc_dequeue_resp_ready_next = !desc_fetch_pcie_axi_dma_read_desc_valid_reg && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE);
-    if (s_axis_desc_dequeue_resp_ready && s_axis_desc_dequeue_resp_valid) begin
-        s_axis_desc_dequeue_resp_ready_next = 1'b0;
+    if (s_axis_desc_req_status_valid) begin
 
-        // store in descriptor table
-        desc_table_start_tag = s_axis_desc_dequeue_resp_tag;
-        desc_table_start_queue = s_axis_desc_dequeue_resp_queue;
-        desc_table_start_queue_ptr = s_axis_desc_dequeue_resp_ptr;
-        desc_table_start_cpl_queue = s_axis_desc_dequeue_resp_cpl;
-        desc_table_start_queue_op_tag = s_axis_desc_dequeue_resp_op_tag;
+        // update entry in descriptor table
+        desc_table_dequeue_ptr = s_axis_desc_req_status_tag & DESC_PTR_MASK;
+        desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
+        desc_table_dequeue_cpl_queue = s_axis_desc_req_status_cpl;
+        desc_table_dequeue_invalid = 1'b0;
+        desc_table_dequeue_en = 1'b1;
 
-        if (s_axis_desc_dequeue_resp_error || s_axis_desc_dequeue_resp_empty) begin
+        if (s_axis_desc_req_status_error || s_axis_desc_req_status_empty) begin
             // queue empty or not active
 
+            // invalidate entry
+            desc_table_dequeue_invalid = 1'b1;
+
             // return transmit request completion
             early_tx_req_status_len_next = 0;
-            early_tx_req_status_tag_next = s_axis_desc_dequeue_resp_tag;
+            early_tx_req_status_tag_next = desc_table_tag[s_axis_desc_req_status_tag & DESC_PTR_MASK];
             early_tx_req_status_valid_next = 1'b1;
-
-            dec_active_1 = 1'b1;
         end else begin
             // descriptor available to dequeue
-            
-            // store in descriptor table
-            desc_table_start_en = 1'b1;
 
-            // initiate descriptor fetch to onboard RAM
-            desc_fetch_pcie_axi_dma_read_desc_pcie_addr_next = s_axis_desc_dequeue_resp_addr;
-            desc_fetch_pcie_axi_dma_read_desc_axi_addr_next = AXI_BASE_ADDR + ((desc_table_start_ptr_reg & DESC_PTR_MASK) << 5);
-            desc_fetch_pcie_axi_dma_read_desc_len_next = DESC_SIZE;
-            desc_fetch_pcie_axi_dma_read_desc_tag_next = (desc_table_start_ptr_reg & DESC_PTR_MASK);
-            desc_fetch_pcie_axi_dma_read_desc_valid_next = 1'b1;
+            // wait for descriptor
         end
     end
 
-    // descriptor fetch completion
-    // wait for descriptor fetch completion
-    if (s_axis_pcie_axi_dma_read_desc_status_valid && !(s_axis_pcie_axi_dma_read_desc_status_tag & DATA_FLAG)) begin
+    // descriptor data write
+    s_axis_desc_tready_next = 1'b1;
+    if (s_axis_desc_tready && s_axis_desc_tvalid) begin
         // update entry in descriptor table
-        desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
+        desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
+        if (TX_CHECKSUM_ENABLE) begin
+            desc_table_desc_fetched_csum_start = s_axis_desc_tdata[23:16];
+            desc_table_desc_fetched_csum_offset = s_axis_desc_tdata[30:24];
+            desc_table_desc_fetched_csum_enable = s_axis_desc_tdata[31];
+        end
+        desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
+        desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
         desc_table_desc_fetched_en = 1'b1;
     end
 
@@ -899,7 +605,7 @@ always @* begin
         if (desc_table_invalid[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK]) begin
             // invalid entry; skip
             desc_table_data_fetch_start_en = 1'b1;
-        end else if (desc_table_desc_fetched[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] && pkt_table_free_ptr_valid && !pkt_fetch_pcie_axi_dma_read_desc_valid_reg) begin
+        end else if (desc_table_desc_fetched[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] && pkt_table_free_ptr_valid && !m_axis_pcie_axi_dma_read_desc_valid_reg) begin
             // update entry in descriptor table
             desc_table_data_fetch_start_pkt = pkt_table_free_ptr;
             desc_table_data_fetch_start_en = 1'b1;
@@ -909,17 +615,17 @@ always @* begin
             pkt_table_start_en = 1'b1;
 
             // initiate data fetch to onboard RAM
-            pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
-            pkt_fetch_pcie_axi_dma_read_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + (pkt_table_free_ptr << SCRATCH_PKT_AXI_ADDR_SHIFT);
-            pkt_fetch_pcie_axi_dma_read_desc_len_next = desc_table_len[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
-            pkt_fetch_pcie_axi_dma_read_desc_tag_next = (desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK) | DATA_FLAG;
-            pkt_fetch_pcie_axi_dma_read_desc_valid_next = 1'b1;
+            m_axis_pcie_axi_dma_read_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_pcie_axi_dma_read_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + (pkt_table_free_ptr << SCRATCH_PKT_AXI_ADDR_SHIFT);
+            m_axis_pcie_axi_dma_read_desc_len_next = desc_table_len[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_pcie_axi_dma_read_desc_tag_next = desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK;
+            m_axis_pcie_axi_dma_read_desc_valid_next = 1'b1;
         end
     end
 
     // data fetch completion
     // wait for data fetch completion
-    if (s_axis_pcie_axi_dma_read_desc_status_valid && (s_axis_pcie_axi_dma_read_desc_status_tag & DATA_FLAG)) begin
+    if (s_axis_pcie_axi_dma_read_desc_status_valid) begin
         // update entry in descriptor table
         desc_table_data_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
         desc_table_data_fetched_en = 1'b1;
@@ -986,55 +692,30 @@ always @* begin
         if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin
             // invalid entry; skip
             desc_table_cpl_enqueue_start_en = 1'b1;
-        end else if (desc_table_tx_done[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_commit_valid && !m_axis_cpl_enqueue_req_valid_next && !m_axis_pcie_axi_dma_write_desc_valid_reg) begin
+        end else if (desc_table_tx_done[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_req_valid_next) begin
             // update entry in descriptor table
             desc_table_cpl_enqueue_start_en = 1'b1;
 
             // initiate queue query
-            m_axis_cpl_enqueue_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
-            m_axis_cpl_enqueue_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
-            m_axis_cpl_enqueue_req_valid_next = 1'b1;
-
-            // commit dequeue operation
-            m_axis_desc_dequeue_commit_op_tag_next = desc_table_queue_op_tag[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
-            m_axis_desc_dequeue_commit_valid_next = 1'b1;
+            m_axis_cpl_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_cpl_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
+            m_axis_cpl_req_data_next = 0;
+            m_axis_cpl_req_data_next[15:0]  <= desc_table_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_cpl_req_data_next[31:16] <= desc_table_queue_ptr[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            m_axis_cpl_req_data_next[47:32] <= desc_table_len[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
+            if (PTP_TS_ENABLE) begin
+                //m_axis_cpl_req_data_next[127:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
+                m_axis_cpl_req_data_next[111:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
+            end
+            m_axis_cpl_req_valid_next = 1'b1;
         end
     end
 
     // start completion write
     // wait for queue query response
-    s_axis_cpl_enqueue_resp_ready_next = !m_axis_pcie_axi_dma_write_desc_valid_reg;
-    if (s_axis_cpl_enqueue_resp_ready && s_axis_cpl_enqueue_resp_valid) begin
-        s_axis_cpl_enqueue_resp_ready_next = 1'b0;
-
+    if (s_axis_cpl_req_status_valid) begin
         // update entry in descriptor table
-        desc_table_cpl_write_ptr = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
-        desc_table_cpl_write_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag;
-        desc_table_cpl_write_invalid = 1'b0;
-        desc_table_cpl_write_en = 1'b1;
-
-        if (s_axis_cpl_enqueue_resp_error || s_axis_cpl_enqueue_resp_full) begin
-            // queue full or not active
-            // TODO retry if queue full?
-
-            // invalidate entry
-            desc_table_cpl_write_invalid = 1'b1;
-        end else begin
-            // space for completion available in queue
-
-            // initiate completion write from onboard RAM
-            m_axis_pcie_axi_dma_write_desc_pcie_addr_next = s_axis_cpl_enqueue_resp_addr;
-            m_axis_pcie_axi_dma_write_desc_axi_addr_next = AXI_BASE_ADDR + ((s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK) + 2**CL_DESC_TABLE_SIZE << 5);
-            m_axis_pcie_axi_dma_write_desc_len_next = CPL_SIZE;
-            m_axis_pcie_axi_dma_write_desc_tag_next = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
-            m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
-        end
-    end
-
-    // finish completion write
-    if (s_axis_pcie_axi_dma_write_desc_status_valid) begin
-        // update entry in descriptor table
-        desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
+        desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
         desc_table_cpl_write_done_en = 1'b1;
     end
 
@@ -1043,47 +724,17 @@ always @* begin
         if (desc_table_invalid[desc_table_finish_ptr_reg & DESC_PTR_MASK]) begin
             // invalidate entry in descriptor table
             desc_table_finish_en = 1'b1;
-
-            // return transmit request completion
-            m_axis_tx_req_status_len_next = 0;
-            m_axis_tx_req_status_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
-            m_axis_tx_req_status_valid_next = 1'b1;
-
-            dec_active_2 = 1'b1;
-        end else if (desc_table_cpl_write_done[desc_table_finish_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_enqueue_commit_valid) begin
+        end else if (desc_table_cpl_write_done[desc_table_finish_ptr_reg & DESC_PTR_MASK]) begin
             // invalidate entry in descriptor table
             desc_table_finish_en = 1'b1;
 
-            // commit enqueue operation
-            m_axis_cpl_enqueue_commit_op_tag_next = desc_table_cpl_queue_op_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
-            m_axis_cpl_enqueue_commit_valid_next = 1'b1;
-
             // return transmit request completion
             finish_tx_req_status_len_next = desc_table_len[desc_table_finish_ptr_reg & DESC_PTR_MASK];
             finish_tx_req_status_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
             finish_tx_req_status_valid_next = 1'b1;
-
-            dec_active_2 = 1'b1;
         end
     end
 
-    // PCIe AXI DMA read request arbitration
-    if (desc_fetch_pcie_axi_dma_read_desc_valid_next && (!m_axis_pcie_axi_dma_read_desc_valid_reg || m_axis_pcie_axi_dma_read_desc_ready)) begin
-        m_axis_pcie_axi_dma_read_desc_pcie_addr_next = desc_fetch_pcie_axi_dma_read_desc_pcie_addr_next;
-        m_axis_pcie_axi_dma_read_desc_axi_addr_next = desc_fetch_pcie_axi_dma_read_desc_axi_addr_next;
-        m_axis_pcie_axi_dma_read_desc_len_next = desc_fetch_pcie_axi_dma_read_desc_len_next;
-        m_axis_pcie_axi_dma_read_desc_tag_next = desc_fetch_pcie_axi_dma_read_desc_tag_next;
-        m_axis_pcie_axi_dma_read_desc_valid_next = 1'b1;
-        desc_fetch_pcie_axi_dma_read_desc_valid_next = 1'b0;
-    end else if (pkt_fetch_pcie_axi_dma_read_desc_valid_next && (!m_axis_pcie_axi_dma_read_desc_valid_reg || m_axis_pcie_axi_dma_read_desc_ready)) begin
-        m_axis_pcie_axi_dma_read_desc_pcie_addr_next = pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_next;
-        m_axis_pcie_axi_dma_read_desc_axi_addr_next = pkt_fetch_pcie_axi_dma_read_desc_axi_addr_next;
-        m_axis_pcie_axi_dma_read_desc_len_next = pkt_fetch_pcie_axi_dma_read_desc_len_next;
-        m_axis_pcie_axi_dma_read_desc_tag_next = pkt_fetch_pcie_axi_dma_read_desc_tag_next;
-        m_axis_pcie_axi_dma_read_desc_valid_next = 1'b1;
-        pkt_fetch_pcie_axi_dma_read_desc_valid_next = 1'b0;
-    end
-
     // transmit request completion arbitration
     if (finish_tx_req_status_valid_next && !m_axis_tx_req_status_valid_reg) begin
         m_axis_tx_req_status_len_next = finish_tx_req_status_len_next;
@@ -1102,24 +753,16 @@ always @(posedge clk) begin
     if (rst) begin
         s_axis_tx_req_ready_reg <= 1'b0;
         m_axis_tx_req_status_valid_reg <= 1'b0;
-        m_axis_desc_dequeue_req_valid_reg <= 1'b0;
-        s_axis_desc_dequeue_resp_ready_reg <= 1'b0;
-        m_axis_desc_dequeue_commit_valid_reg <= 1'b0;
-        m_axis_cpl_enqueue_req_valid_reg <= 1'b0;
-        s_axis_cpl_enqueue_resp_ready_reg <= 1'b0;
-        m_axis_cpl_enqueue_commit_valid_reg <= 1'b0;
+        m_axis_desc_req_valid_reg <= 1'b0;
+        s_axis_desc_tready_reg <= 1'b0;
+        m_axis_cpl_req_valid_reg <= 1'b0;
         m_axis_pcie_axi_dma_read_desc_valid_reg <= 1'b0;
-        m_axis_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
         m_axis_tx_desc_valid_reg <= 1'b0;
         s_axis_tx_ptp_ts_ready_reg <= 1'b0;
         m_axis_tx_csum_cmd_valid_reg <= 1'b0;
 
         early_tx_req_status_valid_reg <= 1'b0;
         finish_tx_req_status_valid_reg <= 1'b0;
-        desc_fetch_pcie_axi_dma_read_desc_valid_reg <= 1'b0;
-        pkt_fetch_pcie_axi_dma_read_desc_valid_reg <= 1'b0;
-
-        active_count_reg <= 0;
 
         desc_table_active <= 0;
         desc_table_invalid <= 0;
@@ -1138,24 +781,16 @@ always @(posedge clk) begin
     end else begin
         s_axis_tx_req_ready_reg <= s_axis_tx_req_ready_next;
         m_axis_tx_req_status_valid_reg <= m_axis_tx_req_status_valid_next;
-        m_axis_desc_dequeue_req_valid_reg <= m_axis_desc_dequeue_req_valid_next;
-        s_axis_desc_dequeue_resp_ready_reg <= s_axis_desc_dequeue_resp_ready_next;
-        m_axis_desc_dequeue_commit_valid_reg <= m_axis_desc_dequeue_commit_valid_next;
-        m_axis_cpl_enqueue_req_valid_reg <= m_axis_cpl_enqueue_req_valid_next;
-        s_axis_cpl_enqueue_resp_ready_reg <= s_axis_cpl_enqueue_resp_ready_next;
-        m_axis_cpl_enqueue_commit_valid_reg <= m_axis_cpl_enqueue_commit_valid_next;
+        m_axis_desc_req_valid_reg <= m_axis_desc_req_valid_next;
+        s_axis_desc_tready_reg <= s_axis_desc_tready_next;
+        m_axis_cpl_req_valid_reg <= m_axis_cpl_req_valid_next;
         m_axis_pcie_axi_dma_read_desc_valid_reg <= m_axis_pcie_axi_dma_read_desc_valid_next;
-        m_axis_pcie_axi_dma_write_desc_valid_reg <= m_axis_pcie_axi_dma_write_desc_valid_next;
         m_axis_tx_desc_valid_reg <= m_axis_tx_desc_valid_next;
         s_axis_tx_ptp_ts_ready_reg <= s_axis_tx_ptp_ts_ready_next;
         m_axis_tx_csum_cmd_valid_reg <= m_axis_tx_csum_cmd_valid_next;
 
         early_tx_req_status_valid_reg <= early_tx_req_status_valid_next;
         finish_tx_req_status_valid_reg <= finish_tx_req_status_valid_next;
-        desc_fetch_pcie_axi_dma_read_desc_valid_reg <= desc_fetch_pcie_axi_dma_read_desc_valid_next;
-        pkt_fetch_pcie_axi_dma_read_desc_valid_reg <= pkt_fetch_pcie_axi_dma_read_desc_valid_next;
-        
-        active_count_reg <= active_count_reg + inc_active - dec_active_1 - dec_active_2;
 
         if (desc_table_start_en) begin
             desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b1;
@@ -1166,6 +801,11 @@ always @(posedge clk) begin
             desc_table_cpl_write_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
             desc_table_start_ptr_reg <= desc_table_start_ptr_reg + 1;
         end
+        if (desc_table_dequeue_en) begin
+            if (desc_table_dequeue_invalid) begin
+                desc_table_invalid[desc_table_dequeue_ptr & DESC_PTR_MASK] <= 1'b1;
+            end
+        end
         if (desc_table_desc_fetched_en) begin
             desc_table_desc_fetched[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= 1'b1;
         end
@@ -1188,11 +828,6 @@ always @(posedge clk) begin
         if (desc_table_cpl_enqueue_start_en) begin
             desc_table_cpl_enqueue_start_ptr_reg <= desc_table_cpl_enqueue_start_ptr_reg + 1;
         end
-        if (desc_table_cpl_write_en) begin
-            if (desc_table_cpl_write_invalid) begin
-                desc_table_invalid[desc_table_cpl_write_ptr & DESC_PTR_MASK] <= 1'b1;
-            end
-        end
         if (desc_table_cpl_write_done_en) begin
             desc_table_cpl_write_done[desc_table_cpl_write_done_ptr & DESC_PTR_MASK] <= 1'b1;
         end
@@ -1209,28 +844,21 @@ always @(posedge clk) begin
         end
     end
 
-    s_axis_tx_req_tag_reg <= s_axis_tx_req_tag_next;
-
     m_axis_tx_req_status_len_reg <= m_axis_tx_req_status_len_next;
     m_axis_tx_req_status_tag_reg <= m_axis_tx_req_status_tag_next;
 
-    m_axis_desc_dequeue_req_queue_reg <= m_axis_desc_dequeue_req_queue_next;
-    m_axis_desc_dequeue_req_tag_reg <= m_axis_desc_dequeue_req_tag_next;
-    m_axis_desc_dequeue_commit_op_tag_reg <= m_axis_desc_dequeue_commit_op_tag_next;
-    m_axis_cpl_enqueue_req_queue_reg <= m_axis_cpl_enqueue_req_queue_next;
-    m_axis_cpl_enqueue_req_tag_reg <= m_axis_cpl_enqueue_req_tag_next;
-    m_axis_cpl_enqueue_commit_op_tag_reg <= m_axis_cpl_enqueue_commit_op_tag_next;
+    m_axis_desc_req_queue_reg <= m_axis_desc_req_queue_next;
+    m_axis_desc_req_tag_reg <= m_axis_desc_req_tag_next;
+
+    m_axis_cpl_req_queue_reg <= m_axis_cpl_req_queue_next;
+    m_axis_cpl_req_tag_reg <= m_axis_cpl_req_tag_next;
+    m_axis_cpl_req_data_reg <= m_axis_cpl_req_data_next;
 
     m_axis_pcie_axi_dma_read_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
     m_axis_pcie_axi_dma_read_desc_axi_addr_reg <= m_axis_pcie_axi_dma_read_desc_axi_addr_next;
     m_axis_pcie_axi_dma_read_desc_len_reg <= m_axis_pcie_axi_dma_read_desc_len_next;
     m_axis_pcie_axi_dma_read_desc_tag_reg <= m_axis_pcie_axi_dma_read_desc_tag_next;
 
-    m_axis_pcie_axi_dma_write_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
-    m_axis_pcie_axi_dma_write_desc_axi_addr_reg <= m_axis_pcie_axi_dma_write_desc_axi_addr_next;
-    m_axis_pcie_axi_dma_write_desc_len_reg <= m_axis_pcie_axi_dma_write_desc_len_next;
-    m_axis_pcie_axi_dma_write_desc_tag_reg <= m_axis_pcie_axi_dma_write_desc_tag_next;
-
     m_axis_tx_desc_addr_reg <= m_axis_tx_desc_addr_next;
     m_axis_tx_desc_len_reg <= m_axis_tx_desc_len_next;
     m_axis_tx_desc_tag_reg <= m_axis_tx_desc_tag_next;
@@ -1246,22 +874,20 @@ always @(posedge clk) begin
     finish_tx_req_status_len_reg <= finish_tx_req_status_len_next;
     finish_tx_req_status_tag_reg <= finish_tx_req_status_tag_next;
 
-    desc_fetch_pcie_axi_dma_read_desc_pcie_addr_reg <= desc_fetch_pcie_axi_dma_read_desc_pcie_addr_next;
-    desc_fetch_pcie_axi_dma_read_desc_axi_addr_reg <= desc_fetch_pcie_axi_dma_read_desc_axi_addr_next;
-    desc_fetch_pcie_axi_dma_read_desc_len_reg <= desc_fetch_pcie_axi_dma_read_desc_len_next;
-    desc_fetch_pcie_axi_dma_read_desc_tag_reg <= desc_fetch_pcie_axi_dma_read_desc_tag_next;
-
-    pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_reg <= pkt_fetch_pcie_axi_dma_read_desc_pcie_addr_next;
-    pkt_fetch_pcie_axi_dma_read_desc_axi_addr_reg <= pkt_fetch_pcie_axi_dma_read_desc_axi_addr_next;
-    pkt_fetch_pcie_axi_dma_read_desc_len_reg <= pkt_fetch_pcie_axi_dma_read_desc_len_next;
-    pkt_fetch_pcie_axi_dma_read_desc_tag_reg <= pkt_fetch_pcie_axi_dma_read_desc_tag_next;
-
     if (desc_table_start_en) begin
         desc_table_queue[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue;
         desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
-        desc_table_queue_ptr[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue_ptr;
-        desc_table_cpl_queue[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_cpl_queue;
-        desc_table_queue_op_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue_op_tag;
+    end
+    if (desc_table_dequeue_en) begin
+        desc_table_queue_ptr[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_queue_ptr;
+        desc_table_cpl_queue[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_cpl_queue;
+     end
+    if (desc_table_desc_fetched_en) begin
+        desc_table_csum_start[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_csum_start;
+        desc_table_csum_offset[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_csum_offset;
+        desc_table_csum_enable[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_csum_enable;
+        desc_table_len[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_len;
+        desc_table_pcie_addr[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_pcie_addr;
     end
     if (desc_table_data_fetch_start_en) begin
         desc_table_pkt[desc_table_data_fetch_start_ptr_reg & DESC_PTR_MASK] <= desc_table_data_fetch_start_pkt;
@@ -1269,9 +895,6 @@ always @(posedge clk) begin
     if (desc_table_store_ptp_ts_en) begin
         desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts;
     end
-    if (desc_table_cpl_write_en) begin
-        desc_table_cpl_queue_op_tag[desc_table_cpl_write_ptr & DESC_PTR_MASK] <= desc_table_cpl_write_queue_op_tag;
-    end
 end
 
 endmodule