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https://github.com/corundum/corundum.git
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Pull out descriptor and completion handling logic
This commit is contained in:
Alex Forencich
parent
6aa48f9127
commit
2325966973
File diff suppressed because it is too large
Load Diff
@ -48,6 +48,8 @@ module port #
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parameter PCIE_DMA_TAG_WIDTH = 8,
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// Request tag field width
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parameter REQ_TAG_WIDTH = 8,
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// Descriptor request tag field width
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parameter DESC_REQ_TAG_WIDTH = 8,
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// Queue request tag field width
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parameter QUEUE_REQ_TAG_WIDTH = 8,
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// Queue operation tag field width
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@ -56,10 +58,14 @@ module port #
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parameter TX_QUEUE_INDEX_WIDTH = 8,
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// Receive queue index width
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parameter RX_QUEUE_INDEX_WIDTH = 8,
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// Max queue index width
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parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH,
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// Transmit completion queue index width
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parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
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// Receive completion queue index width
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parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
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// Max completion queue index width
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parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH,
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// Transmit descriptor table size (number of in-flight operations)
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parameter TX_DESC_TABLE_SIZE = 16,
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// Transmit packet table size (number of in-progress packets)
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@ -109,40 +115,64 @@ module port #
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH
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parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
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// Descriptor size (in bytes)
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parameter DESC_SIZE = 16,
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// Descriptor size (in bytes)
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parameter CPL_SIZE = 32
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TX descriptor dequeue request output
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* Descriptor request output
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*/
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output wire [TX_QUEUE_INDEX_WIDTH-1:0] m_axis_tx_desc_dequeue_req_queue,
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output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_tx_desc_dequeue_req_tag,
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output wire m_axis_tx_desc_dequeue_req_valid,
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input wire m_axis_tx_desc_dequeue_req_ready,
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output wire [0:0] m_axis_desc_req_sel,
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
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output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
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output wire m_axis_desc_req_valid,
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input wire m_axis_desc_req_ready,
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/*
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* TX descriptor dequeue response input
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* Descriptor request status input
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*/
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input wire [TX_QUEUE_INDEX_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_queue,
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input wire [QUEUE_PTR_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_ptr,
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input wire [PCIE_ADDR_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_addr,
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input wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_cpl,
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input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_tag,
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input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_op_tag,
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input wire s_axis_tx_desc_dequeue_resp_empty,
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input wire s_axis_tx_desc_dequeue_resp_error,
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input wire s_axis_tx_desc_dequeue_resp_valid,
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output wire s_axis_tx_desc_dequeue_resp_ready,
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input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
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input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
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input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
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input wire s_axis_desc_req_status_empty,
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input wire s_axis_desc_req_status_error,
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input wire s_axis_desc_req_status_valid,
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/*
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* TX descriptor dequeue commit output
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* Descriptor data input
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*/
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output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_tx_desc_dequeue_commit_op_tag,
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output wire m_axis_tx_desc_dequeue_commit_valid,
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input wire m_axis_tx_desc_dequeue_commit_ready,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_desc_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
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input wire s_axis_desc_tvalid,
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output wire s_axis_desc_tready,
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input wire s_axis_desc_tlast,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
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input wire s_axis_desc_tuser,
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/*
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* Completion request output
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*/
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output wire [0:0] m_axis_cpl_req_sel,
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
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output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
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output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
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output wire m_axis_cpl_req_valid,
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input wire m_axis_cpl_req_ready,
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/*
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* Completion request status input
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*/
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
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input wire s_axis_cpl_req_status_full,
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input wire s_axis_cpl_req_status_error,
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input wire s_axis_cpl_req_status_valid,
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/*
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* TX doorbell input
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@ -150,91 +180,6 @@ module port #
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input wire [TX_QUEUE_INDEX_WIDTH-1:0] s_axis_tx_doorbell_queue,
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input wire s_axis_tx_doorbell_valid,
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/*
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* TX completion enqueue request output
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*/
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output wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_tx_cpl_enqueue_req_queue,
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output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_tx_cpl_enqueue_req_tag,
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output wire m_axis_tx_cpl_enqueue_req_valid,
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input wire m_axis_tx_cpl_enqueue_req_ready,
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/*
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* TX completion enqueue response input
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*/
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//input wire [QUEUE_PTR_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_ptr,
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input wire [PCIE_ADDR_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_addr,
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//input wire [EVENT_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_event,
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input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_tag,
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input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_op_tag,
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input wire s_axis_tx_cpl_enqueue_resp_full,
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input wire s_axis_tx_cpl_enqueue_resp_error,
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input wire s_axis_tx_cpl_enqueue_resp_valid,
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output wire s_axis_tx_cpl_enqueue_resp_ready,
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/*
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* TX completion enqueue commit output
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*/
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output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_tx_cpl_enqueue_commit_op_tag,
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output wire m_axis_tx_cpl_enqueue_commit_valid,
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input wire m_axis_tx_cpl_enqueue_commit_ready,
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/*
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* RX descriptor dequeue request output
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*/
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output wire [RX_QUEUE_INDEX_WIDTH-1:0] m_axis_rx_desc_dequeue_req_queue,
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output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_rx_desc_dequeue_req_tag,
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output wire m_axis_rx_desc_dequeue_req_valid,
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input wire m_axis_rx_desc_dequeue_req_ready,
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/*
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* RX descriptor dequeue response input
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*/
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input wire [RX_QUEUE_INDEX_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_queue,
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input wire [QUEUE_PTR_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_ptr,
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input wire [PCIE_ADDR_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_addr,
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input wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_cpl,
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input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_tag,
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input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_op_tag,
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input wire s_axis_rx_desc_dequeue_resp_empty,
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input wire s_axis_rx_desc_dequeue_resp_error,
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input wire s_axis_rx_desc_dequeue_resp_valid,
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output wire s_axis_rx_desc_dequeue_resp_ready,
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/*
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* RX descriptor dequeue commit output
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*/
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output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_rx_desc_dequeue_commit_op_tag,
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output wire m_axis_rx_desc_dequeue_commit_valid,
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input wire m_axis_rx_desc_dequeue_commit_ready,
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/*
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* RX completion enqueue request output
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*/
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output wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_rx_cpl_enqueue_req_queue,
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output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_rx_cpl_enqueue_req_tag,
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output wire m_axis_rx_cpl_enqueue_req_valid,
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input wire m_axis_rx_cpl_enqueue_req_ready,
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/*
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* RX completion enqueue response input
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*/
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//input wire [QUEUE_PTR_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_ptr,
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input wire [PCIE_ADDR_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_addr,
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//input wire [EVENT_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_event,
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input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_tag,
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input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_op_tag,
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input wire s_axis_rx_cpl_enqueue_resp_full,
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input wire s_axis_rx_cpl_enqueue_resp_error,
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input wire s_axis_rx_cpl_enqueue_resp_valid,
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output wire s_axis_rx_cpl_enqueue_resp_ready,
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/*
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* RX completion enqueue commit output
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*/
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output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_rx_cpl_enqueue_commit_op_tag,
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output wire m_axis_rx_cpl_enqueue_commit_valid,
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input wire m_axis_rx_cpl_enqueue_commit_ready,
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/*
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* PCIe read descriptor output
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*/
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@ -329,45 +274,6 @@ module port #
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input wire m_axi_rvalid,
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output wire m_axi_rready,
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/*
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* AXI slave inteface
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*/
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input wire [AXI_ID_WIDTH-1:0] s_axi_awid,
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [7:0] s_axi_awlen,
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input wire [2:0] s_axi_awsize,
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input wire [1:0] s_axi_awburst,
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input wire s_axi_awlock,
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input wire [3:0] s_axi_awcache,
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input wire [2:0] s_axi_awprot,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
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input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb,
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input wire s_axi_wlast,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [AXI_ID_WIDTH-1:0] s_axi_bid,
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output wire [1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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input wire [AXI_ID_WIDTH-1:0] s_axi_arid,
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [7:0] s_axi_arlen,
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input wire [2:0] s_axi_arsize,
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input wire [1:0] s_axi_arburst,
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input wire s_axi_arlock,
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input wire [3:0] s_axi_arcache,
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input wire [2:0] s_axi_arprot,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [AXI_ID_WIDTH-1:0] s_axi_rid,
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output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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output wire s_axi_rlast,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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/*
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* Transmit data output
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*/
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@ -409,13 +315,10 @@ module port #
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input wire ptp_ts_step
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);
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parameter DESC_SIZE = 16;
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parameter CPL_SIZE = 32;
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parameter AXI_DMA_TAG_WIDTH = 8;
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parameter AXI_DMA_LEN_WIDTH = 16;
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parameter PCIE_DMA_TAG_WIDTH_INT = PCIE_DMA_TAG_WIDTH - $clog2(2);
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parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(2);
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// AXI lite connections
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wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
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@ -458,79 +361,6 @@ wire [1:0] axil_sched_rresp;
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wire axil_sched_rvalid;
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wire axil_sched_rready;
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// AXI connections
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wire [AXI_ID_WIDTH-1:0] axi_tx_awid;
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wire [AXI_ADDR_WIDTH-1:0] axi_tx_awaddr;
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wire [7:0] axi_tx_awlen;
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wire [2:0] axi_tx_awsize;
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wire [1:0] axi_tx_awburst;
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wire axi_tx_awlock;
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wire [3:0] axi_tx_awcache;
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wire [2:0] axi_tx_awprot;
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wire axi_tx_awvalid;
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wire axi_tx_awready;
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wire [AXI_DATA_WIDTH-1:0] axi_tx_wdata;
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wire [AXI_STRB_WIDTH-1:0] axi_tx_wstrb;
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wire axi_tx_wlast;
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wire axi_tx_wvalid;
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wire axi_tx_wready;
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wire [AXI_ID_WIDTH-1:0] axi_tx_bid;
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wire [1:0] axi_tx_bresp;
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wire axi_tx_bvalid;
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wire axi_tx_bready;
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wire [AXI_ID_WIDTH-1:0] axi_tx_arid;
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wire [AXI_ADDR_WIDTH-1:0] axi_tx_araddr;
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wire [7:0] axi_tx_arlen;
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wire [2:0] axi_tx_arsize;
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wire [1:0] axi_tx_arburst;
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wire axi_tx_arlock;
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wire [3:0] axi_tx_arcache;
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wire [2:0] axi_tx_arprot;
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wire axi_tx_arvalid;
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wire axi_tx_arready;
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wire [AXI_ID_WIDTH-1:0] axi_tx_rid;
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wire [AXI_DATA_WIDTH-1:0] axi_tx_rdata;
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wire [1:0] axi_tx_rresp;
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wire axi_tx_rlast;
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wire axi_tx_rvalid;
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wire axi_tx_rready;
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wire [AXI_ID_WIDTH-1:0] axi_rx_awid;
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wire [AXI_ADDR_WIDTH-1:0] axi_rx_awaddr;
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wire [7:0] axi_rx_awlen;
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wire [2:0] axi_rx_awsize;
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wire [1:0] axi_rx_awburst;
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wire axi_rx_awlock;
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wire [3:0] axi_rx_awcache;
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wire [2:0] axi_rx_awprot;
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wire axi_rx_awvalid;
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wire axi_rx_awready;
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wire [AXI_DATA_WIDTH-1:0] axi_rx_wdata;
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wire [AXI_STRB_WIDTH-1:0] axi_rx_wstrb;
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wire axi_rx_wlast;
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wire axi_rx_wvalid;
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wire axi_rx_wready;
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wire [AXI_ID_WIDTH-1:0] axi_rx_bid;
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wire [1:0] axi_rx_bresp;
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wire axi_rx_bvalid;
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wire axi_rx_bready;
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wire [AXI_ID_WIDTH-1:0] axi_rx_arid;
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wire [AXI_ADDR_WIDTH-1:0] axi_rx_araddr;
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wire [7:0] axi_rx_arlen;
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wire [2:0] axi_rx_arsize;
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wire [1:0] axi_rx_arburst;
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wire axi_rx_arlock;
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wire [3:0] axi_rx_arcache;
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wire [2:0] axi_rx_arprot;
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wire axi_rx_arvalid;
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wire axi_rx_arready;
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wire [AXI_ID_WIDTH-1:0] axi_rx_rid;
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wire [AXI_DATA_WIDTH-1:0] axi_rx_rdata;
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wire [1:0] axi_rx_rresp;
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wire axi_rx_rlast;
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wire axi_rx_rvalid;
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wire axi_rx_rready;
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// Checksumming
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wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
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wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
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@ -539,46 +369,74 @@ wire tx_axis_tready_int;
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wire tx_axis_tlast_int;
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wire tx_axis_tuser_int;
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// PCIe DMA
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wire [PCIE_ADDR_WIDTH-1:0] tx_pcie_axi_dma_read_desc_pcie_addr;
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wire [AXI_ADDR_WIDTH-1:0] tx_pcie_axi_dma_read_desc_axi_addr;
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wire [PCIE_DMA_LEN_WIDTH-1:0] tx_pcie_axi_dma_read_desc_len;
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wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_read_desc_tag;
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wire tx_pcie_axi_dma_read_desc_valid;
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wire tx_pcie_axi_dma_read_desc_ready;
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// Descriptor and completion
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wire [0:0] rx_desc_req_sel = 1'b1;
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wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_queue;
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wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_tag;
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wire rx_desc_req_valid;
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wire rx_desc_req_ready;
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wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_read_desc_status_tag;
|
||||
wire tx_pcie_axi_dma_read_desc_status_valid;
|
||||
wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_queue;
|
||||
wire [QUEUE_PTR_WIDTH-1:0] rx_desc_req_status_ptr;
|
||||
wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_cpl;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_status_tag;
|
||||
wire rx_desc_req_status_empty;
|
||||
wire rx_desc_req_status_error;
|
||||
wire rx_desc_req_status_valid;
|
||||
|
||||
wire [PCIE_ADDR_WIDTH-1:0] tx_pcie_axi_dma_write_desc_pcie_addr;
|
||||
wire [AXI_ADDR_WIDTH-1:0] tx_pcie_axi_dma_write_desc_axi_addr;
|
||||
wire [PCIE_DMA_LEN_WIDTH-1:0] tx_pcie_axi_dma_write_desc_len;
|
||||
wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_write_desc_tag;
|
||||
wire tx_pcie_axi_dma_write_desc_valid;
|
||||
wire tx_pcie_axi_dma_write_desc_ready;
|
||||
wire [AXIS_DATA_WIDTH-1:0] rx_desc_tdata;
|
||||
wire [AXIS_KEEP_WIDTH-1:0] rx_desc_tkeep;
|
||||
wire rx_desc_tvalid;
|
||||
wire rx_desc_tready;
|
||||
wire rx_desc_tlast;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_tid;
|
||||
wire rx_desc_tuser;
|
||||
|
||||
wire [PCIE_DMA_TAG_WIDTH_INT-1:0] tx_pcie_axi_dma_write_desc_status_tag;
|
||||
wire tx_pcie_axi_dma_write_desc_status_valid;
|
||||
wire [0:0] tx_desc_req_sel = 1'b0;
|
||||
wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_queue;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_tag;
|
||||
wire tx_desc_req_valid;
|
||||
wire tx_desc_req_ready;
|
||||
|
||||
wire [PCIE_ADDR_WIDTH-1:0] rx_pcie_axi_dma_read_desc_pcie_addr;
|
||||
wire [AXI_ADDR_WIDTH-1:0] rx_pcie_axi_dma_read_desc_axi_addr;
|
||||
wire [PCIE_DMA_LEN_WIDTH-1:0] rx_pcie_axi_dma_read_desc_len;
|
||||
wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_read_desc_tag;
|
||||
wire rx_pcie_axi_dma_read_desc_valid;
|
||||
wire rx_pcie_axi_dma_read_desc_ready;
|
||||
wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_queue;
|
||||
wire [QUEUE_PTR_WIDTH-1:0] tx_desc_req_status_ptr;
|
||||
wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_cpl;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_status_tag;
|
||||
wire tx_desc_req_status_empty;
|
||||
wire tx_desc_req_status_error;
|
||||
wire tx_desc_req_status_valid;
|
||||
|
||||
wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_read_desc_status_tag;
|
||||
wire rx_pcie_axi_dma_read_desc_status_valid;
|
||||
wire [AXIS_DATA_WIDTH-1:0] tx_desc_tdata;
|
||||
wire [AXIS_KEEP_WIDTH-1:0] tx_desc_tkeep;
|
||||
wire tx_desc_tvalid;
|
||||
wire tx_desc_tready;
|
||||
wire tx_desc_tlast;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_tid;
|
||||
wire tx_desc_tuser;
|
||||
|
||||
wire [PCIE_ADDR_WIDTH-1:0] rx_pcie_axi_dma_write_desc_pcie_addr;
|
||||
wire [AXI_ADDR_WIDTH-1:0] rx_pcie_axi_dma_write_desc_axi_addr;
|
||||
wire [PCIE_DMA_LEN_WIDTH-1:0] rx_pcie_axi_dma_write_desc_len;
|
||||
wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_write_desc_tag;
|
||||
wire rx_pcie_axi_dma_write_desc_valid;
|
||||
wire rx_pcie_axi_dma_write_desc_ready;
|
||||
wire [0:0] rx_cpl_req_sel = 1'b1;
|
||||
wire [QUEUE_INDEX_WIDTH-1:0] rx_cpl_req_queue;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_tag;
|
||||
wire [CPL_SIZE*8-1:0] rx_cpl_req_data;
|
||||
wire rx_cpl_req_valid;
|
||||
wire rx_cpl_req_ready;
|
||||
|
||||
wire [PCIE_DMA_TAG_WIDTH_INT-1:0] rx_pcie_axi_dma_write_desc_status_tag;
|
||||
wire rx_pcie_axi_dma_write_desc_status_valid;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_status_tag;
|
||||
wire rx_cpl_req_status_full;
|
||||
wire rx_cpl_req_status_error;
|
||||
wire rx_cpl_req_status_valid;
|
||||
|
||||
wire [0:0] tx_cpl_req_sel = 1'b0;
|
||||
wire [QUEUE_INDEX_WIDTH-1:0] tx_cpl_req_queue;
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_tag;
|
||||
wire [CPL_SIZE*8-1:0] tx_cpl_req_data;
|
||||
wire tx_cpl_req_valid;
|
||||
wire tx_cpl_req_ready;
|
||||
|
||||
wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_status_tag;
|
||||
wire tx_cpl_req_status_full;
|
||||
wire tx_cpl_req_status_error;
|
||||
wire tx_cpl_req_status_valid;
|
||||
|
||||
// TX engine
|
||||
wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_req_queue;
|
||||
@ -1129,7 +987,8 @@ tx_engine #(
|
||||
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
|
||||
.AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
|
||||
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
|
||||
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
|
||||
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
||||
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
|
||||
.AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
|
||||
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
|
||||
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
|
||||
@ -1138,7 +997,6 @@ tx_engine #(
|
||||
.CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
|
||||
.AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h004000),
|
||||
.SCRATCH_PKT_AXI_ADDR(TX_RAM_AXI_BASE_ADDR),
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE)
|
||||
@ -1163,91 +1021,67 @@ tx_engine_inst (
|
||||
.m_axis_tx_req_status_valid(tx_req_status_valid),
|
||||
|
||||
/*
|
||||
* Descriptor dequeue request output
|
||||
* Descriptor request output
|
||||
*/
|
||||
.m_axis_desc_dequeue_req_queue(m_axis_tx_desc_dequeue_req_queue),
|
||||
.m_axis_desc_dequeue_req_tag(m_axis_tx_desc_dequeue_req_tag),
|
||||
.m_axis_desc_dequeue_req_valid(m_axis_tx_desc_dequeue_req_valid),
|
||||
.m_axis_desc_dequeue_req_ready(m_axis_tx_desc_dequeue_req_ready),
|
||||
.m_axis_desc_req_queue(tx_desc_req_queue),
|
||||
.m_axis_desc_req_tag(tx_desc_req_tag),
|
||||
.m_axis_desc_req_valid(tx_desc_req_valid),
|
||||
.m_axis_desc_req_ready(tx_desc_req_ready),
|
||||
|
||||
/*
|
||||
* Descriptor dequeue response input
|
||||
* Descriptor request status input
|
||||
*/
|
||||
.s_axis_desc_dequeue_resp_queue(s_axis_tx_desc_dequeue_resp_queue),
|
||||
.s_axis_desc_dequeue_resp_ptr(s_axis_tx_desc_dequeue_resp_ptr),
|
||||
.s_axis_desc_dequeue_resp_addr(s_axis_tx_desc_dequeue_resp_addr),
|
||||
.s_axis_desc_dequeue_resp_cpl(s_axis_tx_desc_dequeue_resp_cpl),
|
||||
.s_axis_desc_dequeue_resp_tag(s_axis_tx_desc_dequeue_resp_tag),
|
||||
.s_axis_desc_dequeue_resp_op_tag(s_axis_tx_desc_dequeue_resp_op_tag),
|
||||
.s_axis_desc_dequeue_resp_empty(s_axis_tx_desc_dequeue_resp_empty),
|
||||
.s_axis_desc_dequeue_resp_error(s_axis_tx_desc_dequeue_resp_error),
|
||||
.s_axis_desc_dequeue_resp_valid(s_axis_tx_desc_dequeue_resp_valid),
|
||||
.s_axis_desc_dequeue_resp_ready(s_axis_tx_desc_dequeue_resp_ready),
|
||||
.s_axis_desc_req_status_queue(tx_desc_req_status_queue),
|
||||
.s_axis_desc_req_status_ptr(tx_desc_req_status_ptr),
|
||||
.s_axis_desc_req_status_cpl(tx_desc_req_status_cpl),
|
||||
.s_axis_desc_req_status_tag(tx_desc_req_status_tag),
|
||||
.s_axis_desc_req_status_empty(tx_desc_req_status_empty),
|
||||
.s_axis_desc_req_status_error(tx_desc_req_status_error),
|
||||
.s_axis_desc_req_status_valid(tx_desc_req_status_valid),
|
||||
|
||||
/*
|
||||
* Descriptor dequeue commit output
|
||||
* Descriptor data input
|
||||
*/
|
||||
.m_axis_desc_dequeue_commit_op_tag(m_axis_tx_desc_dequeue_commit_op_tag),
|
||||
.m_axis_desc_dequeue_commit_valid(m_axis_tx_desc_dequeue_commit_valid),
|
||||
.m_axis_desc_dequeue_commit_ready(m_axis_tx_desc_dequeue_commit_ready),
|
||||
.s_axis_desc_tdata(tx_desc_tdata),
|
||||
.s_axis_desc_tkeep(tx_desc_tkeep),
|
||||
.s_axis_desc_tvalid(tx_desc_tvalid),
|
||||
.s_axis_desc_tready(tx_desc_tready),
|
||||
.s_axis_desc_tlast(tx_desc_tlast),
|
||||
.s_axis_desc_tid(tx_desc_tid),
|
||||
.s_axis_desc_tuser(tx_desc_tuser),
|
||||
|
||||
/*
|
||||
* Completion enqueue request output
|
||||
* Completion request output
|
||||
*/
|
||||
.m_axis_cpl_enqueue_req_queue(m_axis_tx_cpl_enqueue_req_queue),
|
||||
.m_axis_cpl_enqueue_req_tag(m_axis_tx_cpl_enqueue_req_tag),
|
||||
.m_axis_cpl_enqueue_req_valid(m_axis_tx_cpl_enqueue_req_valid),
|
||||
.m_axis_cpl_enqueue_req_ready(m_axis_tx_cpl_enqueue_req_ready),
|
||||
.m_axis_cpl_req_queue(tx_cpl_req_queue),
|
||||
.m_axis_cpl_req_tag(tx_cpl_req_tag),
|
||||
.m_axis_cpl_req_data(tx_cpl_req_data),
|
||||
.m_axis_cpl_req_valid(tx_cpl_req_valid),
|
||||
.m_axis_cpl_req_ready(tx_cpl_req_ready),
|
||||
|
||||
/*
|
||||
* Completion enqueue response input
|
||||
* Completion request status input
|
||||
*/
|
||||
.s_axis_cpl_enqueue_resp_addr(s_axis_tx_cpl_enqueue_resp_addr),
|
||||
.s_axis_cpl_enqueue_resp_tag(s_axis_tx_cpl_enqueue_resp_tag),
|
||||
.s_axis_cpl_enqueue_resp_op_tag(s_axis_tx_cpl_enqueue_resp_op_tag),
|
||||
.s_axis_cpl_enqueue_resp_full(s_axis_tx_cpl_enqueue_resp_full),
|
||||
.s_axis_cpl_enqueue_resp_error(s_axis_tx_cpl_enqueue_resp_error),
|
||||
.s_axis_cpl_enqueue_resp_valid(s_axis_tx_cpl_enqueue_resp_valid),
|
||||
.s_axis_cpl_enqueue_resp_ready(s_axis_tx_cpl_enqueue_resp_ready),
|
||||
|
||||
/*
|
||||
* Completion enqueue commit output
|
||||
*/
|
||||
.m_axis_cpl_enqueue_commit_op_tag(m_axis_tx_cpl_enqueue_commit_op_tag),
|
||||
.m_axis_cpl_enqueue_commit_valid(m_axis_tx_cpl_enqueue_commit_valid),
|
||||
.m_axis_cpl_enqueue_commit_ready(m_axis_tx_cpl_enqueue_commit_ready),
|
||||
.s_axis_cpl_req_status_tag(tx_cpl_req_status_tag),
|
||||
.s_axis_cpl_req_status_full(tx_cpl_req_status_full),
|
||||
.s_axis_cpl_req_status_error(tx_cpl_req_status_error),
|
||||
.s_axis_cpl_req_status_valid(tx_cpl_req_status_valid),
|
||||
|
||||
/*
|
||||
* PCIe DMA read descriptor output
|
||||
*/
|
||||
.m_axis_pcie_axi_dma_read_desc_pcie_addr(tx_pcie_axi_dma_read_desc_pcie_addr),
|
||||
.m_axis_pcie_axi_dma_read_desc_axi_addr(tx_pcie_axi_dma_read_desc_axi_addr),
|
||||
.m_axis_pcie_axi_dma_read_desc_len(tx_pcie_axi_dma_read_desc_len),
|
||||
.m_axis_pcie_axi_dma_read_desc_tag(tx_pcie_axi_dma_read_desc_tag),
|
||||
.m_axis_pcie_axi_dma_read_desc_valid(tx_pcie_axi_dma_read_desc_valid),
|
||||
.m_axis_pcie_axi_dma_read_desc_ready(tx_pcie_axi_dma_read_desc_ready),
|
||||
.m_axis_pcie_axi_dma_read_desc_pcie_addr(m_axis_pcie_axi_dma_read_desc_pcie_addr),
|
||||
.m_axis_pcie_axi_dma_read_desc_axi_addr(m_axis_pcie_axi_dma_read_desc_axi_addr),
|
||||
.m_axis_pcie_axi_dma_read_desc_len(m_axis_pcie_axi_dma_read_desc_len),
|
||||
.m_axis_pcie_axi_dma_read_desc_tag(m_axis_pcie_axi_dma_read_desc_tag),
|
||||
.m_axis_pcie_axi_dma_read_desc_valid(m_axis_pcie_axi_dma_read_desc_valid),
|
||||
.m_axis_pcie_axi_dma_read_desc_ready(m_axis_pcie_axi_dma_read_desc_ready),
|
||||
|
||||
/*
|
||||
* PCIe DMA read descriptor status input
|
||||
*/
|
||||
.s_axis_pcie_axi_dma_read_desc_status_tag(tx_pcie_axi_dma_read_desc_status_tag),
|
||||
.s_axis_pcie_axi_dma_read_desc_status_valid(tx_pcie_axi_dma_read_desc_status_valid),
|
||||
|
||||
/*
|
||||
* PCIe DMA write descriptor output
|
||||
*/
|
||||
.m_axis_pcie_axi_dma_write_desc_pcie_addr(tx_pcie_axi_dma_write_desc_pcie_addr),
|
||||
.m_axis_pcie_axi_dma_write_desc_axi_addr(tx_pcie_axi_dma_write_desc_axi_addr),
|
||||
.m_axis_pcie_axi_dma_write_desc_len(tx_pcie_axi_dma_write_desc_len),
|
||||
.m_axis_pcie_axi_dma_write_desc_tag(tx_pcie_axi_dma_write_desc_tag),
|
||||
.m_axis_pcie_axi_dma_write_desc_valid(tx_pcie_axi_dma_write_desc_valid),
|
||||
.m_axis_pcie_axi_dma_write_desc_ready(tx_pcie_axi_dma_write_desc_ready),
|
||||
|
||||
/*
|
||||
* PCIe DMA write descriptor status input
|
||||
*/
|
||||
.s_axis_pcie_axi_dma_write_desc_status_tag(tx_pcie_axi_dma_write_desc_status_tag),
|
||||
.s_axis_pcie_axi_dma_write_desc_status_valid(tx_pcie_axi_dma_write_desc_status_valid),
|
||||
.s_axis_pcie_axi_dma_read_desc_status_tag(s_axis_pcie_axi_dma_read_desc_status_tag),
|
||||
.s_axis_pcie_axi_dma_read_desc_status_valid(s_axis_pcie_axi_dma_read_desc_status_valid),
|
||||
|
||||
/*
|
||||
* Transmit descriptor output
|
||||
@ -1281,45 +1115,6 @@ tx_engine_inst (
|
||||
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
|
||||
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
|
||||
|
||||
/*
|
||||
* AXI slave interface
|
||||
*/
|
||||
.s_axi_awid(axi_tx_awid),
|
||||
.s_axi_awaddr(axi_tx_awaddr),
|
||||
.s_axi_awlen(axi_tx_awlen),
|
||||
.s_axi_awsize(axi_tx_awsize),
|
||||
.s_axi_awburst(axi_tx_awburst),
|
||||
.s_axi_awlock(axi_tx_awlock),
|
||||
.s_axi_awcache(axi_tx_awcache),
|
||||
.s_axi_awprot(axi_tx_awprot),
|
||||
.s_axi_awvalid(axi_tx_awvalid),
|
||||
.s_axi_awready(axi_tx_awready),
|
||||
.s_axi_wdata(axi_tx_wdata),
|
||||
.s_axi_wstrb(axi_tx_wstrb),
|
||||
.s_axi_wlast(axi_tx_wlast),
|
||||
.s_axi_wvalid(axi_tx_wvalid),
|
||||
.s_axi_wready(axi_tx_wready),
|
||||
.s_axi_bid(axi_tx_bid),
|
||||
.s_axi_bresp(axi_tx_bresp),
|
||||
.s_axi_bvalid(axi_tx_bvalid),
|
||||
.s_axi_bready(axi_tx_bready),
|
||||
.s_axi_arid(axi_tx_arid),
|
||||
.s_axi_araddr(axi_tx_araddr),
|
||||
.s_axi_arlen(axi_tx_arlen),
|
||||
.s_axi_arsize(axi_tx_arsize),
|
||||
.s_axi_arburst(axi_tx_arburst),
|
||||
.s_axi_arlock(axi_tx_arlock),
|
||||
.s_axi_arcache(axi_tx_arcache),
|
||||
.s_axi_arprot(axi_tx_arprot),
|
||||
.s_axi_arvalid(axi_tx_arvalid),
|
||||
.s_axi_arready(axi_tx_arready),
|
||||
.s_axi_rid(axi_tx_rid),
|
||||
.s_axi_rdata(axi_tx_rdata),
|
||||
.s_axi_rresp(axi_tx_rresp),
|
||||
.s_axi_rlast(axi_tx_rlast),
|
||||
.s_axi_rvalid(axi_tx_rvalid),
|
||||
.s_axi_rready(axi_tx_rready),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
@ -1334,7 +1129,8 @@ rx_engine #(
|
||||
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
|
||||
.AXI_DMA_LEN_WIDTH(AXI_DMA_LEN_WIDTH),
|
||||
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
|
||||
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
|
||||
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
||||
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH),
|
||||
.AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
|
||||
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
|
||||
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
|
||||
@ -1343,7 +1139,6 @@ rx_engine #(
|
||||
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
|
||||
.AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h006000),
|
||||
.SCRATCH_PKT_AXI_ADDR(RX_RAM_AXI_BASE_ADDR),
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE)
|
||||
@ -1367,91 +1162,67 @@ rx_engine_inst (
|
||||
.m_axis_rx_req_status_valid(rx_req_status_valid),
|
||||
|
||||
/*
|
||||
* Descriptor dequeue request output
|
||||
* Descriptor request output
|
||||
*/
|
||||
.m_axis_desc_dequeue_req_queue(m_axis_rx_desc_dequeue_req_queue),
|
||||
.m_axis_desc_dequeue_req_tag(m_axis_rx_desc_dequeue_req_tag),
|
||||
.m_axis_desc_dequeue_req_valid(m_axis_rx_desc_dequeue_req_valid),
|
||||
.m_axis_desc_dequeue_req_ready(m_axis_rx_desc_dequeue_req_ready),
|
||||
.m_axis_desc_req_queue(rx_desc_req_queue),
|
||||
.m_axis_desc_req_tag(rx_desc_req_tag),
|
||||
.m_axis_desc_req_valid(rx_desc_req_valid),
|
||||
.m_axis_desc_req_ready(rx_desc_req_ready),
|
||||
|
||||
/*
|
||||
* Descriptor dequeue response input
|
||||
* Descriptor request status input
|
||||
*/
|
||||
.s_axis_desc_dequeue_resp_queue(s_axis_rx_desc_dequeue_resp_queue),
|
||||
.s_axis_desc_dequeue_resp_ptr(s_axis_rx_desc_dequeue_resp_ptr),
|
||||
.s_axis_desc_dequeue_resp_addr(s_axis_rx_desc_dequeue_resp_addr),
|
||||
.s_axis_desc_dequeue_resp_cpl(s_axis_rx_desc_dequeue_resp_cpl),
|
||||
.s_axis_desc_dequeue_resp_tag(s_axis_rx_desc_dequeue_resp_tag),
|
||||
.s_axis_desc_dequeue_resp_op_tag(s_axis_rx_desc_dequeue_resp_op_tag),
|
||||
.s_axis_desc_dequeue_resp_empty(s_axis_rx_desc_dequeue_resp_empty),
|
||||
.s_axis_desc_dequeue_resp_error(s_axis_rx_desc_dequeue_resp_error),
|
||||
.s_axis_desc_dequeue_resp_valid(s_axis_rx_desc_dequeue_resp_valid),
|
||||
.s_axis_desc_dequeue_resp_ready(s_axis_rx_desc_dequeue_resp_ready),
|
||||
.s_axis_desc_req_status_queue(rx_desc_req_status_queue),
|
||||
.s_axis_desc_req_status_ptr(rx_desc_req_status_ptr),
|
||||
.s_axis_desc_req_status_cpl(rx_desc_req_status_cpl),
|
||||
.s_axis_desc_req_status_tag(rx_desc_req_status_tag),
|
||||
.s_axis_desc_req_status_empty(rx_desc_req_status_empty),
|
||||
.s_axis_desc_req_status_error(rx_desc_req_status_error),
|
||||
.s_axis_desc_req_status_valid(rx_desc_req_status_valid),
|
||||
|
||||
/*
|
||||
* Descriptor dequeue commit output
|
||||
* Descriptor data input
|
||||
*/
|
||||
.m_axis_desc_dequeue_commit_op_tag(m_axis_rx_desc_dequeue_commit_op_tag),
|
||||
.m_axis_desc_dequeue_commit_valid(m_axis_rx_desc_dequeue_commit_valid),
|
||||
.m_axis_desc_dequeue_commit_ready(m_axis_rx_desc_dequeue_commit_ready),
|
||||
.s_axis_desc_tdata(rx_desc_tdata),
|
||||
.s_axis_desc_tkeep(rx_desc_tkeep),
|
||||
.s_axis_desc_tvalid(rx_desc_tvalid),
|
||||
.s_axis_desc_tready(rx_desc_tready),
|
||||
.s_axis_desc_tlast(rx_desc_tlast),
|
||||
.s_axis_desc_tid(rx_desc_tid),
|
||||
.s_axis_desc_tuser(rx_desc_tuser),
|
||||
|
||||
/*
|
||||
* Completion enqueue request output
|
||||
* Completion request output
|
||||
*/
|
||||
.m_axis_cpl_enqueue_req_queue(m_axis_rx_cpl_enqueue_req_queue),
|
||||
.m_axis_cpl_enqueue_req_tag(m_axis_rx_cpl_enqueue_req_tag),
|
||||
.m_axis_cpl_enqueue_req_valid(m_axis_rx_cpl_enqueue_req_valid),
|
||||
.m_axis_cpl_enqueue_req_ready(m_axis_rx_cpl_enqueue_req_ready),
|
||||
.m_axis_cpl_req_queue(rx_cpl_req_queue),
|
||||
.m_axis_cpl_req_tag(rx_cpl_req_tag),
|
||||
.m_axis_cpl_req_data(rx_cpl_req_data),
|
||||
.m_axis_cpl_req_valid(rx_cpl_req_valid),
|
||||
.m_axis_cpl_req_ready(rx_cpl_req_ready),
|
||||
|
||||
/*
|
||||
* Completion enqueue response input
|
||||
* Completion request status input
|
||||
*/
|
||||
.s_axis_cpl_enqueue_resp_addr(s_axis_rx_cpl_enqueue_resp_addr),
|
||||
.s_axis_cpl_enqueue_resp_tag(s_axis_rx_cpl_enqueue_resp_tag),
|
||||
.s_axis_cpl_enqueue_resp_op_tag(s_axis_rx_cpl_enqueue_resp_op_tag),
|
||||
.s_axis_cpl_enqueue_resp_full(s_axis_rx_cpl_enqueue_resp_full),
|
||||
.s_axis_cpl_enqueue_resp_error(s_axis_rx_cpl_enqueue_resp_error),
|
||||
.s_axis_cpl_enqueue_resp_valid(s_axis_rx_cpl_enqueue_resp_valid),
|
||||
.s_axis_cpl_enqueue_resp_ready(s_axis_rx_cpl_enqueue_resp_ready),
|
||||
|
||||
/*
|
||||
* Completion enqueue commit output
|
||||
*/
|
||||
.m_axis_cpl_enqueue_commit_op_tag(m_axis_rx_cpl_enqueue_commit_op_tag),
|
||||
.m_axis_cpl_enqueue_commit_valid(m_axis_rx_cpl_enqueue_commit_valid),
|
||||
.m_axis_cpl_enqueue_commit_ready(m_axis_rx_cpl_enqueue_commit_ready),
|
||||
|
||||
/*
|
||||
* PCIe DMA read descriptor output
|
||||
*/
|
||||
.m_axis_pcie_axi_dma_read_desc_pcie_addr(rx_pcie_axi_dma_read_desc_pcie_addr),
|
||||
.m_axis_pcie_axi_dma_read_desc_axi_addr(rx_pcie_axi_dma_read_desc_axi_addr),
|
||||
.m_axis_pcie_axi_dma_read_desc_len(rx_pcie_axi_dma_read_desc_len),
|
||||
.m_axis_pcie_axi_dma_read_desc_tag(rx_pcie_axi_dma_read_desc_tag),
|
||||
.m_axis_pcie_axi_dma_read_desc_valid(rx_pcie_axi_dma_read_desc_valid),
|
||||
.m_axis_pcie_axi_dma_read_desc_ready(rx_pcie_axi_dma_read_desc_ready),
|
||||
|
||||
/*
|
||||
* PCIe DMA read descriptor status input
|
||||
*/
|
||||
.s_axis_pcie_axi_dma_read_desc_status_tag(rx_pcie_axi_dma_read_desc_status_tag),
|
||||
.s_axis_pcie_axi_dma_read_desc_status_valid(rx_pcie_axi_dma_read_desc_status_valid),
|
||||
.s_axis_cpl_req_status_tag(rx_cpl_req_status_tag),
|
||||
.s_axis_cpl_req_status_full(rx_cpl_req_status_full),
|
||||
.s_axis_cpl_req_status_error(rx_cpl_req_status_error),
|
||||
.s_axis_cpl_req_status_valid(rx_cpl_req_status_valid),
|
||||
|
||||
/*
|
||||
* PCIe DMA write descriptor output
|
||||
*/
|
||||
.m_axis_pcie_axi_dma_write_desc_pcie_addr(rx_pcie_axi_dma_write_desc_pcie_addr),
|
||||
.m_axis_pcie_axi_dma_write_desc_axi_addr(rx_pcie_axi_dma_write_desc_axi_addr),
|
||||
.m_axis_pcie_axi_dma_write_desc_len(rx_pcie_axi_dma_write_desc_len),
|
||||
.m_axis_pcie_axi_dma_write_desc_tag(rx_pcie_axi_dma_write_desc_tag),
|
||||
.m_axis_pcie_axi_dma_write_desc_valid(rx_pcie_axi_dma_write_desc_valid),
|
||||
.m_axis_pcie_axi_dma_write_desc_ready(rx_pcie_axi_dma_write_desc_ready),
|
||||
.m_axis_pcie_axi_dma_write_desc_pcie_addr(m_axis_pcie_axi_dma_write_desc_pcie_addr),
|
||||
.m_axis_pcie_axi_dma_write_desc_axi_addr(m_axis_pcie_axi_dma_write_desc_axi_addr),
|
||||
.m_axis_pcie_axi_dma_write_desc_len(m_axis_pcie_axi_dma_write_desc_len),
|
||||
.m_axis_pcie_axi_dma_write_desc_tag(m_axis_pcie_axi_dma_write_desc_tag),
|
||||
.m_axis_pcie_axi_dma_write_desc_valid(m_axis_pcie_axi_dma_write_desc_valid),
|
||||
.m_axis_pcie_axi_dma_write_desc_ready(m_axis_pcie_axi_dma_write_desc_ready),
|
||||
|
||||
/*
|
||||
* PCIe DMA write descriptor status input
|
||||
*/
|
||||
.s_axis_pcie_axi_dma_write_desc_status_tag(rx_pcie_axi_dma_write_desc_status_tag),
|
||||
.s_axis_pcie_axi_dma_write_desc_status_valid(rx_pcie_axi_dma_write_desc_status_valid),
|
||||
.s_axis_pcie_axi_dma_write_desc_status_tag(s_axis_pcie_axi_dma_write_desc_status_tag),
|
||||
.s_axis_pcie_axi_dma_write_desc_status_valid(s_axis_pcie_axi_dma_write_desc_status_valid),
|
||||
|
||||
/*
|
||||
* Receive descriptor output
|
||||
@ -1484,45 +1255,6 @@ rx_engine_inst (
|
||||
.s_axis_rx_csum_valid(rx_fifo_csum_valid),
|
||||
.s_axis_rx_csum_ready(rx_fifo_csum_ready),
|
||||
|
||||
/*
|
||||
* AXI slave interface
|
||||
*/
|
||||
.s_axi_awid(axi_rx_awid),
|
||||
.s_axi_awaddr(axi_rx_awaddr),
|
||||
.s_axi_awlen(axi_rx_awlen),
|
||||
.s_axi_awsize(axi_rx_awsize),
|
||||
.s_axi_awburst(axi_rx_awburst),
|
||||
.s_axi_awlock(axi_rx_awlock),
|
||||
.s_axi_awcache(axi_rx_awcache),
|
||||
.s_axi_awprot(axi_rx_awprot),
|
||||
.s_axi_awvalid(axi_rx_awvalid),
|
||||
.s_axi_awready(axi_rx_awready),
|
||||
.s_axi_wdata(axi_rx_wdata),
|
||||
.s_axi_wstrb(axi_rx_wstrb),
|
||||
.s_axi_wlast(axi_rx_wlast),
|
||||
.s_axi_wvalid(axi_rx_wvalid),
|
||||
.s_axi_wready(axi_rx_wready),
|
||||
.s_axi_bid(axi_rx_bid),
|
||||
.s_axi_bresp(axi_rx_bresp),
|
||||
.s_axi_bvalid(axi_rx_bvalid),
|
||||
.s_axi_bready(axi_rx_bready),
|
||||
.s_axi_arid(axi_rx_arid),
|
||||
.s_axi_araddr(axi_rx_araddr),
|
||||
.s_axi_arlen(axi_rx_arlen),
|
||||
.s_axi_arsize(axi_rx_arsize),
|
||||
.s_axi_arburst(axi_rx_arburst),
|
||||
.s_axi_arlock(axi_rx_arlock),
|
||||
.s_axi_arcache(axi_rx_arcache),
|
||||
.s_axi_arprot(axi_rx_arprot),
|
||||
.s_axi_arvalid(axi_rx_arvalid),
|
||||
.s_axi_arready(axi_rx_arready),
|
||||
.s_axi_rid(axi_rx_rid),
|
||||
.s_axi_rdata(axi_rx_rdata),
|
||||
.s_axi_rresp(axi_rx_rresp),
|
||||
.s_axi_rlast(axi_rx_rlast),
|
||||
.s_axi_rvalid(axi_rx_rvalid),
|
||||
.s_axi_rready(axi_rx_rready),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
@ -1807,134 +1539,4 @@ axi_dma_inst (
|
||||
.write_abort(1'b0)
|
||||
);
|
||||
|
||||
parameter RAM_COUNT = 3;
|
||||
parameter RAM_SIZE = 2**16;
|
||||
parameter RAM_ADDR_WIDTH = $clog2(RAM_SIZE);
|
||||
parameter RAM_BASE_ADDR_WIDTH = RAM_COUNT*AXI_ADDR_WIDTH;
|
||||
parameter RAM_BASE_ADDR = calcRAMBaseAddrs(RAM_ADDR_WIDTH);
|
||||
|
||||
function [RAM_BASE_ADDR_WIDTH-1:0] calcRAMBaseAddrs(input [31:0] ram_width);
|
||||
integer i;
|
||||
begin
|
||||
calcRAMBaseAddrs = {RAM_BASE_ADDR_WIDTH{1'b0}};
|
||||
for (i = 0; i < RAM_COUNT; i = i + 1) begin
|
||||
calcRAMBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**ram_width);
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
parameter AXI_S_COUNT = 2;
|
||||
parameter AXI_M_COUNT = RAM_COUNT+1;
|
||||
|
||||
parameter RAM_ID_WIDTH = AXI_ID_WIDTH+$clog2(AXI_S_COUNT);
|
||||
|
||||
axi_interconnect #(
|
||||
.S_COUNT(1),
|
||||
.M_COUNT(2),
|
||||
.DATA_WIDTH(AXI_DATA_WIDTH),
|
||||
.ADDR_WIDTH(AXI_ADDR_WIDTH),
|
||||
.STRB_WIDTH(AXI_STRB_WIDTH),
|
||||
.ID_WIDTH(RAM_ID_WIDTH),
|
||||
.AWUSER_ENABLE(0),
|
||||
.WUSER_ENABLE(0),
|
||||
.BUSER_ENABLE(0),
|
||||
.ARUSER_ENABLE(0),
|
||||
.RUSER_ENABLE(0),
|
||||
.FORWARD_ID(0),
|
||||
.M_REGIONS(1),
|
||||
.M_BASE_ADDR({23'h006000, 23'h004000}),
|
||||
.M_ADDR_WIDTH({2{32'd13}}),
|
||||
.M_CONNECT_READ({2{{1{1'b1}}}}),
|
||||
.M_CONNECT_WRITE({2{{1{1'b1}}}})
|
||||
)
|
||||
axi_interconnect_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(0),
|
||||
.s_axi_awuser(0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(0),
|
||||
.s_axi_aruser(0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
|
||||
.m_axi_awid( {axi_rx_awid, axi_tx_awid}),
|
||||
.m_axi_awaddr( {axi_rx_awaddr, axi_tx_awaddr}),
|
||||
.m_axi_awlen( {axi_rx_awlen, axi_tx_awlen}),
|
||||
.m_axi_awsize( {axi_rx_awsize, axi_tx_awsize}),
|
||||
.m_axi_awburst( {axi_rx_awburst, axi_tx_awburst}),
|
||||
.m_axi_awlock( {axi_rx_awlock, axi_tx_awlock}),
|
||||
.m_axi_awcache( {axi_rx_awcache, axi_tx_awcache}),
|
||||
.m_axi_awprot( {axi_rx_awprot, axi_tx_awprot}),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid( {axi_rx_awvalid, axi_tx_awvalid}),
|
||||
.m_axi_awready( {axi_rx_awready, axi_tx_awready}),
|
||||
.m_axi_wdata( {axi_rx_wdata, axi_tx_wdata}),
|
||||
.m_axi_wstrb( {axi_rx_wstrb, axi_tx_wstrb}),
|
||||
.m_axi_wlast( {axi_rx_wlast, axi_tx_wlast}),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid( {axi_rx_wvalid, axi_tx_wvalid}),
|
||||
.m_axi_wready( {axi_rx_wready, axi_tx_wready}),
|
||||
.m_axi_bid( {axi_rx_bid, axi_tx_bid}),
|
||||
.m_axi_bresp( {axi_rx_bresp, axi_tx_bresp}),
|
||||
.m_axi_buser(0),
|
||||
.m_axi_bvalid( {axi_rx_bvalid, axi_tx_bvalid}),
|
||||
.m_axi_bready( {axi_rx_bready, axi_tx_bready}),
|
||||
.m_axi_arid( {axi_rx_arid, axi_tx_arid}),
|
||||
.m_axi_araddr( {axi_rx_araddr, axi_tx_araddr}),
|
||||
.m_axi_arlen( {axi_rx_arlen, axi_tx_arlen}),
|
||||
.m_axi_arsize( {axi_rx_arsize, axi_tx_arsize}),
|
||||
.m_axi_arburst( {axi_rx_arburst, axi_tx_arburst}),
|
||||
.m_axi_arlock( {axi_rx_arlock, axi_tx_arlock}),
|
||||
.m_axi_arcache( {axi_rx_arcache, axi_tx_arcache}),
|
||||
.m_axi_arprot( {axi_rx_arprot, axi_tx_arprot}),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid( {axi_rx_arvalid, axi_tx_arvalid}),
|
||||
.m_axi_arready( {axi_rx_arready, axi_tx_arready}),
|
||||
.m_axi_rid( {axi_rx_rid, axi_tx_rid}),
|
||||
.m_axi_rdata( {axi_rx_rdata, axi_tx_rdata}),
|
||||
.m_axi_rresp( {axi_rx_rresp, axi_tx_rresp}),
|
||||
.m_axi_rlast( {axi_rx_rlast, axi_tx_rlast}),
|
||||
.m_axi_ruser(0),
|
||||
.m_axi_rvalid( {axi_rx_rvalid, axi_tx_rvalid}),
|
||||
.m_axi_rready( {axi_rx_rready, axi_tx_rready})
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -48,6 +48,10 @@ module rx_engine #
|
||||
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
|
||||
// Width of AXI ID signal
|
||||
parameter AXI_ID_WIDTH = 8,
|
||||
// Width of AXI stream interface in bits
|
||||
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
|
||||
// AXI stream tkeep signal width (words per cycle)
|
||||
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH,
|
||||
// PCIe address width
|
||||
parameter PCIE_ADDR_WIDTH = 64,
|
||||
// PCIe DMA length field width
|
||||
@ -56,6 +60,8 @@ module rx_engine #
|
||||
parameter AXI_DMA_LEN_WIDTH = 20,
|
||||
// Receive request tag field width
|
||||
parameter REQ_TAG_WIDTH = 8,
|
||||
// Descriptor request tag field width
|
||||
parameter DESC_REQ_TAG_WIDTH = 8,
|
||||
// PCIe DMA tag field width
|
||||
parameter PCIE_DMA_TAG_WIDTH = 8,
|
||||
// AXI DMA tag field width
|
||||
@ -76,8 +82,10 @@ module rx_engine #
|
||||
parameter PKT_TABLE_SIZE = 8,
|
||||
// Max receive packet size
|
||||
parameter MAX_RX_SIZE = 2048,
|
||||
// AXI base address of this module (as seen by PCIe DMA)
|
||||
parameter AXI_BASE_ADDR = 16'h0000,
|
||||
// Descriptor size (in bytes)
|
||||
parameter DESC_SIZE = 16,
|
||||
// Descriptor size (in bytes)
|
||||
parameter CPL_SIZE = 32,
|
||||
// AXI address of packet scratchpad RAM (as seen by PCIe DMA and port AXI DMA)
|
||||
parameter SCRATCH_PKT_AXI_ADDR = 16'h1000,
|
||||
// Packet scratchpad RAM log segment size
|
||||
@ -107,75 +115,51 @@ module rx_engine #
|
||||
output wire m_axis_rx_req_status_valid,
|
||||
|
||||
/*
|
||||
* Descriptor dequeue request output
|
||||
* Descriptor request output
|
||||
*/
|
||||
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_dequeue_req_queue,
|
||||
output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_desc_dequeue_req_tag,
|
||||
output wire m_axis_desc_dequeue_req_valid,
|
||||
input wire m_axis_desc_dequeue_req_ready,
|
||||
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
|
||||
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
|
||||
output wire m_axis_desc_req_valid,
|
||||
input wire m_axis_desc_req_ready,
|
||||
|
||||
/*
|
||||
* Descriptor dequeue response input
|
||||
* Descriptor request status input
|
||||
*/
|
||||
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_dequeue_resp_queue,
|
||||
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_dequeue_resp_ptr,
|
||||
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_desc_dequeue_resp_addr,
|
||||
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_dequeue_resp_cpl,
|
||||
input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_desc_dequeue_resp_tag,
|
||||
input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_desc_dequeue_resp_op_tag,
|
||||
input wire s_axis_desc_dequeue_resp_empty,
|
||||
input wire s_axis_desc_dequeue_resp_error,
|
||||
input wire s_axis_desc_dequeue_resp_valid,
|
||||
output wire s_axis_desc_dequeue_resp_ready,
|
||||
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
|
||||
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
|
||||
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
|
||||
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
|
||||
input wire s_axis_desc_req_status_empty,
|
||||
input wire s_axis_desc_req_status_error,
|
||||
input wire s_axis_desc_req_status_valid,
|
||||
|
||||
/*
|
||||
* Descriptor dequeue commit output
|
||||
* Descriptor data input
|
||||
*/
|
||||
output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_desc_dequeue_commit_op_tag,
|
||||
output wire m_axis_desc_dequeue_commit_valid,
|
||||
input wire m_axis_desc_dequeue_commit_ready,
|
||||
input wire [AXIS_DATA_WIDTH-1:0] s_axis_desc_tdata,
|
||||
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
|
||||
input wire s_axis_desc_tvalid,
|
||||
output wire s_axis_desc_tready,
|
||||
input wire s_axis_desc_tlast,
|
||||
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
|
||||
input wire s_axis_desc_tuser,
|
||||
|
||||
/*
|
||||
* Completion enqueue request output
|
||||
* Completion request output
|
||||
*/
|
||||
output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue,
|
||||
output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_cpl_enqueue_req_tag,
|
||||
output wire m_axis_cpl_enqueue_req_valid,
|
||||
input wire m_axis_cpl_enqueue_req_ready,
|
||||
output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
|
||||
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
|
||||
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
|
||||
output wire m_axis_cpl_req_valid,
|
||||
input wire m_axis_cpl_req_ready,
|
||||
|
||||
/*
|
||||
* Completion enqueue response input
|
||||
* Completion request status input
|
||||
*/
|
||||
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_cpl_enqueue_resp_addr,
|
||||
input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_cpl_enqueue_resp_tag,
|
||||
input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_cpl_enqueue_resp_op_tag,
|
||||
input wire s_axis_cpl_enqueue_resp_full,
|
||||
input wire s_axis_cpl_enqueue_resp_error,
|
||||
input wire s_axis_cpl_enqueue_resp_valid,
|
||||
output wire s_axis_cpl_enqueue_resp_ready,
|
||||
|
||||
/*
|
||||
* Completion enqueue commit output
|
||||
*/
|
||||
output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_cpl_enqueue_commit_op_tag,
|
||||
output wire m_axis_cpl_enqueue_commit_valid,
|
||||
input wire m_axis_cpl_enqueue_commit_ready,
|
||||
|
||||
/*
|
||||
* PCIe AXI DMA read descriptor output
|
||||
*/
|
||||
output wire [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr,
|
||||
output wire [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr,
|
||||
output wire [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len,
|
||||
output wire [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag,
|
||||
output wire m_axis_pcie_axi_dma_read_desc_valid,
|
||||
input wire m_axis_pcie_axi_dma_read_desc_ready,
|
||||
|
||||
/*
|
||||
* PCIe AXI DMA read descriptor status input
|
||||
*/
|
||||
input wire [PCIE_DMA_TAG_WIDTH-1:0] s_axis_pcie_axi_dma_read_desc_status_tag,
|
||||
input wire s_axis_pcie_axi_dma_read_desc_status_valid,
|
||||
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
|
||||
input wire s_axis_cpl_req_status_full,
|
||||
input wire s_axis_cpl_req_status_error,
|
||||
input wire s_axis_cpl_req_status_valid,
|
||||
|
||||
/*
|
||||
* PCIe AXI DMA write descriptor output
|
||||
@ -224,52 +208,12 @@ module rx_engine #
|
||||
input wire s_axis_rx_csum_valid,
|
||||
output wire s_axis_rx_csum_ready,
|
||||
|
||||
/*
|
||||
* AXI slave interface
|
||||
*/
|
||||
input wire [AXI_ID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [7:0] s_axi_awlen,
|
||||
input wire [2:0] s_axi_awsize,
|
||||
input wire [1:0] s_axi_awburst,
|
||||
input wire s_axi_awlock,
|
||||
input wire [3:0] s_axi_awcache,
|
||||
input wire [2:0] s_axi_awprot,
|
||||
input wire s_axi_awvalid,
|
||||
output wire s_axi_awready,
|
||||
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire s_axi_wvalid,
|
||||
output wire s_axi_wready,
|
||||
output wire [AXI_ID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [1:0] s_axi_bresp,
|
||||
output wire s_axi_bvalid,
|
||||
input wire s_axi_bready,
|
||||
input wire [AXI_ID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [7:0] s_axi_arlen,
|
||||
input wire [2:0] s_axi_arsize,
|
||||
input wire [1:0] s_axi_arburst,
|
||||
input wire s_axi_arlock,
|
||||
input wire [3:0] s_axi_arcache,
|
||||
input wire [2:0] s_axi_arprot,
|
||||
input wire s_axi_arvalid,
|
||||
output wire s_axi_arready,
|
||||
output wire [AXI_ID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire s_axi_rvalid,
|
||||
input wire s_axi_rready,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire enable
|
||||
);
|
||||
|
||||
|
||||
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
|
||||
parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
|
||||
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
|
||||
@ -279,16 +223,9 @@ parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
|
||||
parameter CL_PKT_TABLE_SIZE = $clog2(PKT_TABLE_SIZE);
|
||||
parameter PKT_TAG_MASK = {CL_PKT_TABLE_SIZE{1'b1}};
|
||||
|
||||
parameter DATA_FLAG = 1 << CL_DESC_TABLE_SIZE;
|
||||
|
||||
parameter DESC_SIZE = 16;
|
||||
parameter CPL_SIZE = 32;
|
||||
|
||||
parameter BLOCK_SIZE = DESC_SIZE > CPL_SIZE ? DESC_SIZE : CPL_SIZE;
|
||||
|
||||
// bus width assertions
|
||||
initial begin
|
||||
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
|
||||
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
|
||||
$error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
@ -303,16 +240,6 @@ initial begin
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (AXI_STRB_WIDTH < BLOCK_SIZE) begin
|
||||
$error("Error: AXI interface width must be at least as large as one descriptor (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
|
||||
$error("Error: AXI base address must be aligned to interface width (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (SCRATCH_PKT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
|
||||
$error("Error: AXI base address must be aligned to interface width (instance %m)");
|
||||
$finish;
|
||||
@ -332,38 +259,29 @@ initial begin
|
||||
$error("Error: QUEUE_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (DESC_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
|
||||
$error("Error: DESC_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
reg [REQ_TAG_WIDTH-1:0] s_axis_rx_req_tag_reg = {REQ_TAG_WIDTH{1'b0}}, s_axis_rx_req_tag_next;
|
||||
reg s_axis_rx_req_ready_reg = 1'b0, s_axis_rx_req_ready_next;
|
||||
|
||||
reg [AXI_DMA_LEN_WIDTH-1:0] m_axis_rx_req_status_len_reg = {AXI_DMA_LEN_WIDTH{1'b0}}, m_axis_rx_req_status_len_next;
|
||||
reg [REQ_TAG_WIDTH-1:0] m_axis_rx_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_rx_req_status_tag_next;
|
||||
reg m_axis_rx_req_status_valid_reg = 1'b0, m_axis_rx_req_status_valid_next;
|
||||
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_dequeue_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_desc_dequeue_req_queue_next;
|
||||
reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_desc_dequeue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_req_tag_next;
|
||||
reg m_axis_desc_dequeue_req_valid_reg = 1'b0, m_axis_desc_dequeue_req_valid_next;
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_desc_req_queue_next;
|
||||
reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_desc_req_tag_next;
|
||||
reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next;
|
||||
|
||||
reg s_axis_desc_dequeue_resp_ready_reg = 1'b0, s_axis_desc_dequeue_resp_ready_next;
|
||||
reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next;
|
||||
|
||||
reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_desc_dequeue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_desc_dequeue_commit_op_tag_next;
|
||||
reg m_axis_desc_dequeue_commit_valid_reg = 1'b0, m_axis_desc_dequeue_commit_valid_next;
|
||||
|
||||
reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_queue_next;
|
||||
reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_cpl_enqueue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_tag_next;
|
||||
reg m_axis_cpl_enqueue_req_valid_reg = 1'b0, m_axis_cpl_enqueue_req_valid_next;
|
||||
|
||||
reg s_axis_cpl_enqueue_resp_ready_reg = 1'b0, s_axis_cpl_enqueue_resp_ready_next;
|
||||
|
||||
reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_cpl_enqueue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_commit_op_tag_next;
|
||||
reg m_axis_cpl_enqueue_commit_valid_reg = 1'b0, m_axis_cpl_enqueue_commit_valid_next;
|
||||
|
||||
reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
|
||||
reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_axi_addr_next;
|
||||
reg [PCIE_DMA_LEN_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_len_next;
|
||||
reg [PCIE_DMA_TAG_WIDTH-1:0] m_axis_pcie_axi_dma_read_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, m_axis_pcie_axi_dma_read_desc_tag_next;
|
||||
reg m_axis_pcie_axi_dma_read_desc_valid_reg = 1'b0, m_axis_pcie_axi_dma_read_desc_valid_next;
|
||||
reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next;
|
||||
reg [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {DESC_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next;
|
||||
reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next;
|
||||
reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;
|
||||
|
||||
reg [PCIE_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
reg [AXI_ADDR_WIDTH-1:0] m_axis_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axis_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
@ -380,18 +298,6 @@ reg s_axis_rx_ptp_ts_ready_reg = 1'b0, s_axis_rx_ptp_ts_ready_next;
|
||||
|
||||
reg s_axis_rx_csum_ready_reg = 1'b0, s_axis_rx_csum_ready_next;
|
||||
|
||||
reg [PCIE_ADDR_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
reg [AXI_ADDR_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
reg [PCIE_DMA_LEN_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_len_next;
|
||||
reg [PCIE_DMA_TAG_WIDTH-1:0] pkt_write_pcie_axi_dma_write_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, pkt_write_pcie_axi_dma_write_desc_tag_next;
|
||||
reg pkt_write_pcie_axi_dma_write_desc_valid_reg = 1'b0, pkt_write_pcie_axi_dma_write_desc_valid_next;
|
||||
|
||||
reg [PCIE_ADDR_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
reg [AXI_ADDR_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
reg [PCIE_DMA_LEN_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_len_reg = {PCIE_DMA_LEN_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_len_next;
|
||||
reg [PCIE_DMA_TAG_WIDTH-1:0] cpl_write_pcie_axi_dma_write_desc_tag_reg = {PCIE_DMA_TAG_WIDTH{1'b0}}, cpl_write_pcie_axi_dma_write_desc_tag_next;
|
||||
reg cpl_write_pcie_axi_dma_write_desc_valid_reg = 1'b0, cpl_write_pcie_axi_dma_write_desc_valid_next;
|
||||
|
||||
reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
|
||||
reg [DESC_TABLE_SIZE-1:0] desc_table_rx_done = 0;
|
||||
reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0;
|
||||
@ -402,8 +308,6 @@ reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0];
|
||||
reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0];
|
||||
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
|
||||
reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0];
|
||||
reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_cpl_queue_op_tag[DESC_TABLE_SIZE-1:0];
|
||||
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0];
|
||||
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0];
|
||||
reg [PCIE_ADDR_WIDTH-1:0] desc_table_pcie_addr[DESC_TABLE_SIZE-1:0];
|
||||
@ -424,10 +328,11 @@ reg desc_table_dequeue_start_en;
|
||||
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr;
|
||||
reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr;
|
||||
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue;
|
||||
reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_dequeue_queue_op_tag;
|
||||
reg desc_table_dequeue_invalid;
|
||||
reg desc_table_dequeue_en;
|
||||
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_fetched_ptr;
|
||||
reg [AXI_DMA_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
|
||||
reg [PCIE_ADDR_WIDTH-1:0] desc_table_desc_fetched_pcie_addr;
|
||||
reg desc_table_desc_fetched_en;
|
||||
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_data_write_start_ptr_reg = 0;
|
||||
reg desc_table_data_write_start_en;
|
||||
@ -441,10 +346,6 @@ reg [15:0] desc_table_store_csum;
|
||||
reg desc_table_store_csum_en;
|
||||
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_cpl_enqueue_start_ptr_reg = 0;
|
||||
reg desc_table_cpl_enqueue_start_en;
|
||||
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_ptr;
|
||||
reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_cpl_write_queue_op_tag;
|
||||
reg desc_table_cpl_write_invalid;
|
||||
reg desc_table_cpl_write_en;
|
||||
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done_ptr;
|
||||
reg desc_table_cpl_write_done_en;
|
||||
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_finish_ptr_reg = 0;
|
||||
@ -462,29 +363,16 @@ assign m_axis_rx_req_status_len = m_axis_rx_req_status_len_reg;
|
||||
assign m_axis_rx_req_status_tag = m_axis_rx_req_status_tag_reg;
|
||||
assign m_axis_rx_req_status_valid = m_axis_rx_req_status_valid_reg;
|
||||
|
||||
assign m_axis_desc_dequeue_req_queue = m_axis_desc_dequeue_req_queue_reg;
|
||||
assign m_axis_desc_dequeue_req_tag = m_axis_desc_dequeue_req_tag_reg;
|
||||
assign m_axis_desc_dequeue_req_valid = m_axis_desc_dequeue_req_valid_reg;
|
||||
assign m_axis_desc_req_queue = m_axis_desc_req_queue_reg;
|
||||
assign m_axis_desc_req_tag = m_axis_desc_req_tag_reg;
|
||||
assign m_axis_desc_req_valid = m_axis_desc_req_valid_reg;
|
||||
|
||||
assign s_axis_desc_dequeue_resp_ready = s_axis_desc_dequeue_resp_ready_reg;
|
||||
assign s_axis_desc_tready = s_axis_desc_tready_reg;
|
||||
|
||||
assign m_axis_desc_dequeue_commit_op_tag = m_axis_desc_dequeue_commit_op_tag_reg;
|
||||
assign m_axis_desc_dequeue_commit_valid = m_axis_desc_dequeue_commit_valid_reg;
|
||||
|
||||
assign m_axis_cpl_enqueue_req_queue = m_axis_cpl_enqueue_req_queue_reg;
|
||||
assign m_axis_cpl_enqueue_req_tag = m_axis_cpl_enqueue_req_tag_reg;
|
||||
assign m_axis_cpl_enqueue_req_valid = m_axis_cpl_enqueue_req_valid_reg;
|
||||
|
||||
assign s_axis_cpl_enqueue_resp_ready = s_axis_cpl_enqueue_resp_ready_reg;
|
||||
|
||||
assign m_axis_cpl_enqueue_commit_op_tag = m_axis_cpl_enqueue_commit_op_tag_reg;
|
||||
assign m_axis_cpl_enqueue_commit_valid = m_axis_cpl_enqueue_commit_valid_reg;
|
||||
|
||||
assign m_axis_pcie_axi_dma_read_desc_pcie_addr = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
|
||||
assign m_axis_pcie_axi_dma_read_desc_axi_addr = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
|
||||
assign m_axis_pcie_axi_dma_read_desc_len = m_axis_pcie_axi_dma_read_desc_len_reg;
|
||||
assign m_axis_pcie_axi_dma_read_desc_tag = m_axis_pcie_axi_dma_read_desc_tag_reg;
|
||||
assign m_axis_pcie_axi_dma_read_desc_valid = m_axis_pcie_axi_dma_read_desc_valid_reg;
|
||||
assign m_axis_cpl_req_queue = m_axis_cpl_req_queue_reg;
|
||||
assign m_axis_cpl_req_tag = m_axis_cpl_req_tag_reg;
|
||||
assign m_axis_cpl_req_data = m_axis_cpl_req_data_reg;
|
||||
assign m_axis_cpl_req_valid = m_axis_cpl_req_valid_reg;
|
||||
|
||||
assign m_axis_pcie_axi_dma_write_desc_pcie_addr = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
|
||||
assign m_axis_pcie_axi_dma_write_desc_axi_addr = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
|
||||
@ -515,171 +403,6 @@ pkt_table_free_enc_inst (
|
||||
.output_unencoded()
|
||||
);
|
||||
|
||||
wire [AXI_ID_WIDTH-1:0] ram_wr_cmd_id;
|
||||
wire [AXI_ADDR_WIDTH-1:0] ram_wr_cmd_addr;
|
||||
wire [AXI_DATA_WIDTH-1:0] ram_wr_cmd_data;
|
||||
wire [AXI_STRB_WIDTH-1:0] ram_wr_cmd_strb;
|
||||
wire ram_wr_cmd_en;
|
||||
|
||||
wire [AXI_ID_WIDTH-1:0] ram_rd_cmd_id;
|
||||
wire [AXI_ADDR_WIDTH-1:0] ram_rd_cmd_addr;
|
||||
wire ram_rd_cmd_en;
|
||||
wire ram_rd_cmd_last;
|
||||
reg ram_rd_cmd_ready_reg = 1'b0;
|
||||
reg [AXI_ID_WIDTH-1:0] ram_rd_resp_id_reg = {AXI_ID_WIDTH{1'b0}};
|
||||
reg [AXI_DATA_WIDTH-1:0] ram_rd_resp_data_reg = {AXI_DATA_WIDTH{1'b0}};
|
||||
reg ram_rd_resp_last_reg = 1'b0;
|
||||
reg ram_rd_resp_valid_reg = 1'b0;
|
||||
wire ram_rd_resp_ready;
|
||||
|
||||
axi_ram_wr_if #(
|
||||
.DATA_WIDTH(AXI_DATA_WIDTH),
|
||||
.ADDR_WIDTH(AXI_ADDR_WIDTH),
|
||||
.STRB_WIDTH(AXI_STRB_WIDTH),
|
||||
.ID_WIDTH(AXI_ID_WIDTH),
|
||||
.AWUSER_ENABLE(0),
|
||||
.WUSER_ENABLE(0),
|
||||
.BUSER_ENABLE(0)
|
||||
)
|
||||
axi_ram_wr_if_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(0),
|
||||
.s_axi_awregion(0),
|
||||
.s_axi_awuser(0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.ram_wr_cmd_id(ram_wr_cmd_id),
|
||||
.ram_wr_cmd_addr(ram_wr_cmd_addr),
|
||||
.ram_wr_cmd_lock(),
|
||||
.ram_wr_cmd_cache(),
|
||||
.ram_wr_cmd_prot(),
|
||||
.ram_wr_cmd_qos(),
|
||||
.ram_wr_cmd_region(),
|
||||
.ram_wr_cmd_auser(),
|
||||
.ram_wr_cmd_data(ram_wr_cmd_data),
|
||||
.ram_wr_cmd_strb(ram_wr_cmd_strb),
|
||||
.ram_wr_cmd_user(),
|
||||
.ram_wr_cmd_en(ram_wr_cmd_en),
|
||||
.ram_wr_cmd_last(),
|
||||
.ram_wr_cmd_ready(1'b1)
|
||||
);
|
||||
|
||||
axi_ram_rd_if #(
|
||||
.DATA_WIDTH(AXI_DATA_WIDTH),
|
||||
.ADDR_WIDTH(AXI_ADDR_WIDTH),
|
||||
.STRB_WIDTH(AXI_STRB_WIDTH),
|
||||
.ID_WIDTH(AXI_ID_WIDTH),
|
||||
.ARUSER_ENABLE(0),
|
||||
.RUSER_ENABLE(0),
|
||||
.PIPELINE_OUTPUT(0)
|
||||
)
|
||||
axi_ram_rd_if_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(0),
|
||||
.s_axi_arregion(0),
|
||||
.s_axi_aruser(0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.ram_rd_cmd_id(ram_rd_cmd_id),
|
||||
.ram_rd_cmd_addr(ram_rd_cmd_addr),
|
||||
.ram_rd_cmd_lock(),
|
||||
.ram_rd_cmd_cache(),
|
||||
.ram_rd_cmd_prot(),
|
||||
.ram_rd_cmd_qos(),
|
||||
.ram_rd_cmd_region(),
|
||||
.ram_rd_cmd_auser(),
|
||||
.ram_rd_cmd_en(ram_rd_cmd_en),
|
||||
.ram_rd_cmd_last(ram_rd_cmd_last),
|
||||
.ram_rd_cmd_ready(ram_rd_cmd_ready_reg),
|
||||
.ram_rd_resp_id(ram_rd_resp_id_reg),
|
||||
.ram_rd_resp_data(ram_rd_resp_data_reg),
|
||||
.ram_rd_resp_last(ram_rd_resp_last_reg),
|
||||
.ram_rd_resp_user(0),
|
||||
.ram_rd_resp_valid(ram_rd_resp_valid_reg),
|
||||
.ram_rd_resp_ready(ram_rd_resp_ready)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ram_wr_cmd_en) begin
|
||||
// AXI write
|
||||
if (ram_wr_cmd_addr[CL_DESC_TABLE_SIZE+5] == 0) begin
|
||||
// descriptors
|
||||
// TODO byte enables
|
||||
desc_table_desc_len[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[64:32];
|
||||
desc_table_pcie_addr[ram_wr_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] <= ram_wr_cmd_data[127:64];
|
||||
end
|
||||
end
|
||||
|
||||
ram_rd_resp_valid_reg <= ram_rd_resp_valid_reg && !ram_rd_resp_ready;
|
||||
ram_rd_cmd_ready_reg <= !ram_rd_resp_valid_reg || ram_rd_resp_ready;
|
||||
|
||||
if (ram_rd_cmd_en && ram_rd_cmd_ready_reg) begin
|
||||
// AXI read
|
||||
ram_rd_resp_id_reg <= ram_rd_cmd_id;
|
||||
ram_rd_resp_data_reg <= 0;
|
||||
ram_rd_resp_last_reg <= ram_rd_cmd_last;
|
||||
ram_rd_resp_valid_reg <= 1'b1;
|
||||
ram_rd_cmd_ready_reg <= ram_rd_resp_ready;
|
||||
|
||||
if (ram_rd_cmd_addr[CL_DESC_TABLE_SIZE+5] == 0) begin
|
||||
// descriptors
|
||||
ram_rd_resp_data_reg[64:32] <= desc_table_desc_len[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
|
||||
ram_rd_resp_data_reg[127:64] <= desc_table_pcie_addr[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
|
||||
end else begin
|
||||
// completions
|
||||
ram_rd_resp_data_reg[15:0] <= desc_table_queue[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
|
||||
ram_rd_resp_data_reg[31:16] <= desc_table_queue_ptr[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
|
||||
ram_rd_resp_data_reg[47:32] <= desc_table_dma_len[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
|
||||
if (PTP_TS_ENABLE) begin
|
||||
//ram_rd_resp_data_reg[127:64] <= desc_table_ptp_ts[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] >> 16;
|
||||
ram_rd_resp_data_reg[111:64] <= desc_table_ptp_ts[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]] >> 16;
|
||||
end
|
||||
ram_rd_resp_data_reg[127:112] <= desc_table_csum[ram_rd_cmd_addr[(CL_DESC_TABLE_SIZE+5)-1:5]];
|
||||
end
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
ram_rd_cmd_ready_reg <= 1'b1;
|
||||
ram_rd_resp_valid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// reg [15:0] stall_cnt = 0;
|
||||
// wire stalled = stall_cnt[12];
|
||||
|
||||
@ -716,36 +439,22 @@ end
|
||||
// );
|
||||
|
||||
always @* begin
|
||||
s_axis_rx_req_tag_next = s_axis_rx_req_tag_reg;
|
||||
s_axis_rx_req_ready_next = 1'b0;
|
||||
|
||||
m_axis_rx_req_status_len_next = m_axis_rx_req_status_len_reg;
|
||||
m_axis_rx_req_status_tag_next = m_axis_rx_req_status_tag_reg;
|
||||
m_axis_rx_req_status_valid_next = 1'b0;
|
||||
|
||||
m_axis_desc_dequeue_req_queue_next = m_axis_desc_dequeue_req_queue_reg;
|
||||
m_axis_desc_dequeue_req_tag_next = m_axis_desc_dequeue_req_tag_reg;
|
||||
m_axis_desc_dequeue_req_valid_next = m_axis_desc_dequeue_req_valid_reg && !m_axis_desc_dequeue_req_ready;
|
||||
m_axis_desc_req_queue_next = m_axis_desc_req_queue_reg;
|
||||
m_axis_desc_req_tag_next = m_axis_desc_req_tag_reg;
|
||||
m_axis_desc_req_valid_next = m_axis_desc_req_valid_reg && !m_axis_desc_req_ready;
|
||||
|
||||
s_axis_desc_dequeue_resp_ready_next = 1'b0;
|
||||
s_axis_desc_tready_next = 1'b0;
|
||||
|
||||
m_axis_desc_dequeue_commit_op_tag_next = m_axis_desc_dequeue_commit_op_tag_reg;
|
||||
m_axis_desc_dequeue_commit_valid_next = m_axis_desc_dequeue_commit_valid_reg && !m_axis_desc_dequeue_commit_ready;
|
||||
|
||||
m_axis_cpl_enqueue_req_queue_next = m_axis_cpl_enqueue_req_queue_reg;
|
||||
m_axis_cpl_enqueue_req_tag_next = m_axis_cpl_enqueue_req_tag_reg;
|
||||
m_axis_cpl_enqueue_req_valid_next = m_axis_cpl_enqueue_req_valid_reg && !m_axis_cpl_enqueue_req_ready;
|
||||
|
||||
s_axis_cpl_enqueue_resp_ready_next = 1'b0;
|
||||
|
||||
m_axis_cpl_enqueue_commit_op_tag_next = m_axis_cpl_enqueue_commit_op_tag_reg;
|
||||
m_axis_cpl_enqueue_commit_valid_next = m_axis_cpl_enqueue_commit_valid_reg && !m_axis_cpl_enqueue_commit_ready;
|
||||
|
||||
m_axis_pcie_axi_dma_read_desc_pcie_addr_next = m_axis_pcie_axi_dma_read_desc_pcie_addr_reg;
|
||||
m_axis_pcie_axi_dma_read_desc_axi_addr_next = m_axis_pcie_axi_dma_read_desc_axi_addr_reg;
|
||||
m_axis_pcie_axi_dma_read_desc_len_next = m_axis_pcie_axi_dma_read_desc_len_reg;
|
||||
m_axis_pcie_axi_dma_read_desc_tag_next = m_axis_pcie_axi_dma_read_desc_tag_reg;
|
||||
m_axis_pcie_axi_dma_read_desc_valid_next = m_axis_pcie_axi_dma_read_desc_valid_reg && !m_axis_pcie_axi_dma_read_desc_ready;
|
||||
m_axis_cpl_req_queue_next = m_axis_cpl_req_queue_reg;
|
||||
m_axis_cpl_req_tag_next = m_axis_cpl_req_tag_reg;
|
||||
m_axis_cpl_req_data_next = m_axis_cpl_req_data_reg;
|
||||
m_axis_cpl_req_valid_next = m_axis_cpl_req_valid_reg && !m_axis_cpl_req_ready;
|
||||
|
||||
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = m_axis_pcie_axi_dma_write_desc_pcie_addr_reg;
|
||||
m_axis_pcie_axi_dma_write_desc_axi_addr_next = m_axis_pcie_axi_dma_write_desc_axi_addr_reg;
|
||||
@ -762,18 +471,6 @@ always @* begin
|
||||
|
||||
s_axis_rx_csum_ready_next = 1'b0;
|
||||
|
||||
pkt_write_pcie_axi_dma_write_desc_pcie_addr_next = pkt_write_pcie_axi_dma_write_desc_pcie_addr_reg;
|
||||
pkt_write_pcie_axi_dma_write_desc_axi_addr_next = pkt_write_pcie_axi_dma_write_desc_axi_addr_reg;
|
||||
pkt_write_pcie_axi_dma_write_desc_len_next = pkt_write_pcie_axi_dma_write_desc_len_reg;
|
||||
pkt_write_pcie_axi_dma_write_desc_tag_next = pkt_write_pcie_axi_dma_write_desc_tag_reg;
|
||||
pkt_write_pcie_axi_dma_write_desc_valid_next = pkt_write_pcie_axi_dma_write_desc_valid_reg;
|
||||
|
||||
cpl_write_pcie_axi_dma_write_desc_pcie_addr_next = cpl_write_pcie_axi_dma_write_desc_pcie_addr_reg;
|
||||
cpl_write_pcie_axi_dma_write_desc_axi_addr_next = cpl_write_pcie_axi_dma_write_desc_axi_addr_reg;
|
||||
cpl_write_pcie_axi_dma_write_desc_len_next = cpl_write_pcie_axi_dma_write_desc_len_reg;
|
||||
cpl_write_pcie_axi_dma_write_desc_tag_next = cpl_write_pcie_axi_dma_write_desc_tag_reg;
|
||||
cpl_write_pcie_axi_dma_write_desc_valid_next = cpl_write_pcie_axi_dma_write_desc_valid_reg;
|
||||
|
||||
desc_table_start_tag = s_axis_rx_req_tag;
|
||||
desc_table_start_queue = s_axis_rx_req_queue;
|
||||
desc_table_start_pkt = pkt_table_free_ptr;
|
||||
@ -782,13 +479,14 @@ always @* begin
|
||||
desc_table_rx_finish_len = s_axis_rx_desc_status_len;
|
||||
desc_table_rx_finish_en = 1'b0;
|
||||
desc_table_dequeue_start_en = 1'b0;
|
||||
desc_table_dequeue_ptr = s_axis_desc_dequeue_resp_tag;
|
||||
desc_table_dequeue_queue_ptr = s_axis_desc_dequeue_resp_ptr;
|
||||
desc_table_dequeue_cpl_queue = s_axis_desc_dequeue_resp_cpl;
|
||||
desc_table_dequeue_queue_op_tag = s_axis_desc_dequeue_resp_op_tag;
|
||||
desc_table_dequeue_ptr = s_axis_desc_req_status_tag;
|
||||
desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
|
||||
desc_table_dequeue_cpl_queue = s_axis_desc_req_status_cpl;
|
||||
desc_table_dequeue_invalid = 1'b0;
|
||||
desc_table_dequeue_en = 1'b0;
|
||||
desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
|
||||
desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
|
||||
desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
|
||||
desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
|
||||
desc_table_desc_fetched_en = 1'b0;
|
||||
desc_table_data_write_start_en = 1'b0;
|
||||
desc_table_data_written_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
|
||||
@ -798,11 +496,7 @@ always @* begin
|
||||
desc_table_store_csum = s_axis_rx_csum;
|
||||
desc_table_store_csum_en = 1'b0;
|
||||
desc_table_cpl_enqueue_start_en = 1'b0;
|
||||
desc_table_cpl_write_ptr = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
|
||||
desc_table_cpl_write_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag;
|
||||
desc_table_cpl_write_invalid = 1'b0;
|
||||
desc_table_cpl_write_en = 1'b0;
|
||||
desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
|
||||
desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
|
||||
desc_table_cpl_write_done_en = 1'b0;
|
||||
desc_table_finish_en = 1'b0;
|
||||
|
||||
@ -811,7 +505,7 @@ always @* begin
|
||||
pkt_table_finish_ptr = desc_table_pkt[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
pkt_table_finish_en = 1'b0;
|
||||
|
||||
// queue query
|
||||
// receive packet
|
||||
// wait for receive request
|
||||
s_axis_rx_req_ready_next = enable && pkt_table_free_ptr_valid && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE) && (!m_axis_rx_desc_valid_reg || m_axis_rx_desc_ready);
|
||||
if (s_axis_rx_req_ready && s_axis_rx_req_valid) begin
|
||||
@ -843,34 +537,32 @@ always @* begin
|
||||
desc_table_rx_finish_en = 1'b1;
|
||||
end
|
||||
|
||||
// queue query
|
||||
// descriptor fetch
|
||||
if (desc_table_active[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && desc_table_dequeue_start_ptr_reg != desc_table_start_ptr_reg) begin
|
||||
if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_req_valid) begin
|
||||
//if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_req_valid) begin
|
||||
if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_req_valid) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_dequeue_start_en = 1'b1;
|
||||
|
||||
// initiate queue query
|
||||
m_axis_desc_dequeue_req_queue_next = desc_table_queue[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_desc_dequeue_req_tag_next = desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK;
|
||||
m_axis_desc_dequeue_req_valid_next = 1'b1;
|
||||
// initiate descriptor fetch
|
||||
m_axis_desc_req_queue_next = desc_table_queue[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_desc_req_tag_next = desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK;
|
||||
m_axis_desc_req_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// descriptor fetch
|
||||
// wait for queue query response
|
||||
s_axis_desc_dequeue_resp_ready_next = !m_axis_pcie_axi_dma_read_desc_valid_reg;
|
||||
if (s_axis_desc_dequeue_resp_ready && s_axis_desc_dequeue_resp_valid) begin
|
||||
s_axis_desc_dequeue_resp_ready_next = 1'b0;
|
||||
if (s_axis_desc_req_status_valid) begin
|
||||
|
||||
// update entry in descriptor table
|
||||
desc_table_dequeue_ptr = s_axis_desc_dequeue_resp_tag;
|
||||
desc_table_dequeue_queue_ptr = s_axis_desc_dequeue_resp_ptr;
|
||||
desc_table_dequeue_cpl_queue = s_axis_desc_dequeue_resp_cpl;
|
||||
desc_table_dequeue_queue_op_tag = s_axis_desc_dequeue_resp_op_tag;
|
||||
desc_table_dequeue_ptr = s_axis_desc_req_status_tag & DESC_PTR_MASK;
|
||||
desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
|
||||
desc_table_dequeue_cpl_queue = s_axis_desc_req_status_cpl;
|
||||
desc_table_dequeue_invalid = 1'b0;
|
||||
desc_table_dequeue_en = 1'b1;
|
||||
|
||||
if (s_axis_desc_dequeue_resp_error || s_axis_desc_dequeue_resp_empty) begin
|
||||
if (s_axis_desc_req_status_error || s_axis_desc_req_status_empty) begin
|
||||
// queue empty or not active
|
||||
// TODO retry if empty?
|
||||
|
||||
@ -879,20 +571,17 @@ always @* begin
|
||||
end else begin
|
||||
// descriptor available to dequeue
|
||||
|
||||
// initiate descriptor fetch to onboard RAM
|
||||
m_axis_pcie_axi_dma_read_desc_pcie_addr_next = s_axis_desc_dequeue_resp_addr;
|
||||
m_axis_pcie_axi_dma_read_desc_axi_addr_next = AXI_BASE_ADDR + (s_axis_desc_dequeue_resp_tag << 5);
|
||||
m_axis_pcie_axi_dma_read_desc_len_next = DESC_SIZE;
|
||||
m_axis_pcie_axi_dma_read_desc_tag_next = s_axis_desc_dequeue_resp_tag;
|
||||
m_axis_pcie_axi_dma_read_desc_valid_next = 1'b1;
|
||||
// wait for descriptor
|
||||
end
|
||||
end
|
||||
|
||||
// descriptor fetch completion
|
||||
// wait for descriptor fetch completion
|
||||
if (s_axis_pcie_axi_dma_read_desc_status_valid) begin
|
||||
// descriptor data write
|
||||
s_axis_desc_tready_next = 1'b1;
|
||||
if (s_axis_desc_tready && s_axis_desc_tvalid) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_desc_fetched_ptr = s_axis_pcie_axi_dma_read_desc_status_tag & DESC_PTR_MASK;
|
||||
desc_table_desc_fetched_ptr = s_axis_desc_tid & DESC_PTR_MASK;
|
||||
desc_table_desc_fetched_len = s_axis_desc_tdata[64:32];
|
||||
desc_table_desc_fetched_pcie_addr = s_axis_desc_tdata[127:64];
|
||||
desc_table_desc_fetched_en = 1'b1;
|
||||
end
|
||||
|
||||
@ -903,28 +592,28 @@ always @* begin
|
||||
if (desc_table_invalid[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK]) begin
|
||||
// invalid entry; skip
|
||||
desc_table_data_write_start_en = 1'b1;
|
||||
end else if (desc_table_desc_fetched[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && !pkt_write_pcie_axi_dma_write_desc_valid_reg) begin
|
||||
end else if (desc_table_desc_fetched[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] && !m_axis_pcie_axi_dma_write_desc_valid_reg) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_data_write_start_en = 1'b1;
|
||||
|
||||
// initiate data write
|
||||
pkt_write_pcie_axi_dma_write_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
|
||||
pkt_write_pcie_axi_dma_write_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + ((desc_table_pkt[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] & DESC_PTR_MASK) << SCRATCH_PKT_AXI_ADDR_SHIFT);
|
||||
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = desc_table_pcie_addr[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_pcie_axi_dma_write_desc_axi_addr_next = SCRATCH_PKT_AXI_ADDR + ((desc_table_pkt[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] & DESC_PTR_MASK) << SCRATCH_PKT_AXI_ADDR_SHIFT);
|
||||
if (desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK] < desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK]) begin
|
||||
// limit write to length provided in descriptor
|
||||
pkt_write_pcie_axi_dma_write_desc_len_next = desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_pcie_axi_dma_write_desc_len_next = desc_table_desc_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
|
||||
end else begin
|
||||
// write actual packet length
|
||||
pkt_write_pcie_axi_dma_write_desc_len_next = desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_pcie_axi_dma_write_desc_len_next = desc_table_dma_len[desc_table_data_write_start_ptr_reg & DESC_PTR_MASK];
|
||||
end
|
||||
pkt_write_pcie_axi_dma_write_desc_tag_next = (desc_table_data_write_start_ptr_reg & DESC_PTR_MASK) | DATA_FLAG;
|
||||
pkt_write_pcie_axi_dma_write_desc_valid_next = 1'b1;
|
||||
m_axis_pcie_axi_dma_write_desc_tag_next = desc_table_data_write_start_ptr_reg & DESC_PTR_MASK;
|
||||
m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// data write completion
|
||||
// wait for data write completion
|
||||
if (s_axis_pcie_axi_dma_write_desc_status_valid && (s_axis_pcie_axi_dma_write_desc_status_tag & DATA_FLAG)) begin
|
||||
if (s_axis_pcie_axi_dma_write_desc_status_valid) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_data_written_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
|
||||
desc_table_data_written_en = 1'b1;
|
||||
@ -974,7 +663,7 @@ always @* begin
|
||||
pkt_table_finish_ptr = desc_table_pkt[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
pkt_table_finish_en = 1'b1;
|
||||
|
||||
end else if (desc_table_data_written[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_dequeue_commit_valid && !m_axis_cpl_enqueue_req_valid_next && !cpl_write_pcie_axi_dma_write_desc_valid_reg) begin
|
||||
end else if (desc_table_data_written[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_req_valid_next) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_cpl_enqueue_start_en = 1'b1;
|
||||
|
||||
@ -982,51 +671,27 @@ always @* begin
|
||||
pkt_table_finish_ptr = desc_table_pkt[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
pkt_table_finish_en = 1'b1;
|
||||
|
||||
// initiate queue query
|
||||
m_axis_cpl_enqueue_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_cpl_enqueue_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
|
||||
m_axis_cpl_enqueue_req_valid_next = 1'b1;
|
||||
|
||||
// commit dequeue operation
|
||||
m_axis_desc_dequeue_commit_op_tag_next = desc_table_queue_op_tag[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_desc_dequeue_commit_valid_next = 1'b1;
|
||||
// initiate completion write
|
||||
m_axis_cpl_req_queue_next = desc_table_cpl_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_cpl_req_tag_next = desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK;
|
||||
m_axis_cpl_req_data_next = 0;
|
||||
m_axis_cpl_req_data_next[15:0] <= desc_table_queue[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_cpl_req_data_next[31:16] <= desc_table_queue_ptr[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_cpl_req_data_next[47:32] <= desc_table_dma_len[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
if (PTP_TS_ENABLE) begin
|
||||
//m_axis_cpl_req_data_next[127:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
|
||||
m_axis_cpl_req_data_next[111:64] <= desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
|
||||
end
|
||||
m_axis_cpl_req_data_next[127:112] <= desc_table_csum[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_cpl_req_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// start completion write
|
||||
// wait for queue query response
|
||||
s_axis_cpl_enqueue_resp_ready_next = !cpl_write_pcie_axi_dma_write_desc_valid_reg;
|
||||
if (s_axis_cpl_enqueue_resp_ready && s_axis_cpl_enqueue_resp_valid) begin
|
||||
s_axis_cpl_enqueue_resp_ready_next = 1'b0;
|
||||
|
||||
if (s_axis_cpl_req_status_valid) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_cpl_write_ptr = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
|
||||
desc_table_cpl_write_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag;
|
||||
desc_table_cpl_write_invalid = 1'b0;
|
||||
desc_table_cpl_write_en = 1'b1;
|
||||
|
||||
if (s_axis_cpl_enqueue_resp_error || s_axis_cpl_enqueue_resp_full) begin
|
||||
// queue full or not active
|
||||
// TODO retry if queue full?
|
||||
|
||||
// invalidate entry
|
||||
desc_table_cpl_write_invalid = 1'b1;
|
||||
end else begin
|
||||
// space for completion available in queue
|
||||
|
||||
// initiate completion write from onboard RAM
|
||||
cpl_write_pcie_axi_dma_write_desc_pcie_addr_next = s_axis_cpl_enqueue_resp_addr;
|
||||
cpl_write_pcie_axi_dma_write_desc_axi_addr_next = AXI_BASE_ADDR + ((s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK) + 2**CL_DESC_TABLE_SIZE << 5);
|
||||
cpl_write_pcie_axi_dma_write_desc_len_next = CPL_SIZE;
|
||||
cpl_write_pcie_axi_dma_write_desc_tag_next = s_axis_cpl_enqueue_resp_tag & DESC_PTR_MASK;
|
||||
cpl_write_pcie_axi_dma_write_desc_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// finish completion write
|
||||
if (s_axis_pcie_axi_dma_write_desc_status_valid && !(s_axis_pcie_axi_dma_write_desc_status_tag & DATA_FLAG)) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_cpl_write_done_ptr = s_axis_pcie_axi_dma_write_desc_status_tag & DESC_PTR_MASK;
|
||||
desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
|
||||
desc_table_cpl_write_done_en = 1'b1;
|
||||
end
|
||||
|
||||
@ -1040,58 +705,30 @@ always @* begin
|
||||
m_axis_rx_req_status_len_next = 0;
|
||||
m_axis_rx_req_status_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_rx_req_status_valid_next = 1'b1;
|
||||
end else if (desc_table_cpl_write_done[desc_table_finish_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_enqueue_commit_valid) begin
|
||||
end else if (desc_table_cpl_write_done[desc_table_finish_ptr_reg & DESC_PTR_MASK]) begin
|
||||
// invalidate entry in descriptor table
|
||||
desc_table_finish_en = 1'b1;
|
||||
|
||||
// commit enqueue operation
|
||||
m_axis_cpl_enqueue_commit_op_tag_next = desc_table_cpl_queue_op_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_cpl_enqueue_commit_valid_next = 1'b1;
|
||||
|
||||
// return receive request completion
|
||||
m_axis_rx_req_status_len_next = desc_table_dma_len[desc_table_finish_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_rx_req_status_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_rx_req_status_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// PCIe AXI DMA write request arbitration
|
||||
if (pkt_write_pcie_axi_dma_write_desc_valid_next && (!m_axis_pcie_axi_dma_write_desc_valid_reg || m_axis_pcie_axi_dma_write_desc_ready)) begin
|
||||
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = pkt_write_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
m_axis_pcie_axi_dma_write_desc_axi_addr_next = pkt_write_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
m_axis_pcie_axi_dma_write_desc_len_next = pkt_write_pcie_axi_dma_write_desc_len_next;
|
||||
m_axis_pcie_axi_dma_write_desc_tag_next = pkt_write_pcie_axi_dma_write_desc_tag_next;
|
||||
m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
|
||||
pkt_write_pcie_axi_dma_write_desc_valid_next = 1'b0;
|
||||
end else if (cpl_write_pcie_axi_dma_write_desc_valid_next && (!m_axis_pcie_axi_dma_write_desc_valid_reg || m_axis_pcie_axi_dma_write_desc_ready)) begin
|
||||
m_axis_pcie_axi_dma_write_desc_pcie_addr_next = cpl_write_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
m_axis_pcie_axi_dma_write_desc_axi_addr_next = cpl_write_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
m_axis_pcie_axi_dma_write_desc_len_next = cpl_write_pcie_axi_dma_write_desc_len_next;
|
||||
m_axis_pcie_axi_dma_write_desc_tag_next = cpl_write_pcie_axi_dma_write_desc_tag_next;
|
||||
m_axis_pcie_axi_dma_write_desc_valid_next = 1'b1;
|
||||
cpl_write_pcie_axi_dma_write_desc_valid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
s_axis_rx_req_ready_reg <= 1'b0;
|
||||
m_axis_rx_req_status_valid_reg <= 1'b0;
|
||||
m_axis_desc_dequeue_req_valid_reg <= 1'b0;
|
||||
s_axis_desc_dequeue_resp_ready_reg <= 1'b0;
|
||||
m_axis_desc_dequeue_commit_valid_reg <= 1'b0;
|
||||
m_axis_cpl_enqueue_req_valid_reg <= 1'b0;
|
||||
s_axis_cpl_enqueue_resp_ready_reg <= 1'b0;
|
||||
m_axis_cpl_enqueue_commit_valid_reg <= 1'b0;
|
||||
m_axis_pcie_axi_dma_read_desc_valid_reg <= 1'b0;
|
||||
m_axis_desc_req_valid_reg <= 1'b0;
|
||||
s_axis_desc_tready_reg <= 1'b0;
|
||||
m_axis_cpl_req_valid_reg <= 1'b0;
|
||||
m_axis_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
|
||||
m_axis_rx_desc_valid_reg <= 1'b0;
|
||||
s_axis_rx_ptp_ts_ready_reg <= 1'b0;
|
||||
s_axis_rx_csum_ready_reg <= 1'b0;
|
||||
|
||||
pkt_write_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
|
||||
cpl_write_pcie_axi_dma_write_desc_valid_reg <= 1'b0;
|
||||
|
||||
desc_table_active <= 0;
|
||||
desc_table_invalid <= 0;
|
||||
desc_table_desc_fetched <= 0;
|
||||
@ -1110,21 +747,14 @@ always @(posedge clk) begin
|
||||
end else begin
|
||||
s_axis_rx_req_ready_reg <= s_axis_rx_req_ready_next;
|
||||
m_axis_rx_req_status_valid_reg <= m_axis_rx_req_status_valid_next;
|
||||
m_axis_desc_dequeue_req_valid_reg <= m_axis_desc_dequeue_req_valid_next;
|
||||
s_axis_desc_dequeue_resp_ready_reg <= s_axis_desc_dequeue_resp_ready_next;
|
||||
m_axis_desc_dequeue_commit_valid_reg <= m_axis_desc_dequeue_commit_valid_next;
|
||||
m_axis_cpl_enqueue_req_valid_reg <= m_axis_cpl_enqueue_req_valid_next;
|
||||
s_axis_cpl_enqueue_resp_ready_reg <= s_axis_cpl_enqueue_resp_ready_next;
|
||||
m_axis_cpl_enqueue_commit_valid_reg <= m_axis_cpl_enqueue_commit_valid_next;
|
||||
m_axis_pcie_axi_dma_read_desc_valid_reg <= m_axis_pcie_axi_dma_read_desc_valid_next;
|
||||
m_axis_desc_req_valid_reg <= m_axis_desc_req_valid_next;
|
||||
s_axis_desc_tready_reg <= s_axis_desc_tready_next;
|
||||
m_axis_cpl_req_valid_reg <= m_axis_cpl_req_valid_next;
|
||||
m_axis_pcie_axi_dma_write_desc_valid_reg <= m_axis_pcie_axi_dma_write_desc_valid_next;
|
||||
m_axis_rx_desc_valid_reg <= m_axis_rx_desc_valid_next;
|
||||
s_axis_rx_ptp_ts_ready_reg <= s_axis_rx_ptp_ts_ready_next;
|
||||
s_axis_rx_csum_ready_reg <= s_axis_rx_csum_ready_next;
|
||||
|
||||
pkt_write_pcie_axi_dma_write_desc_valid_reg <= pkt_write_pcie_axi_dma_write_desc_valid_next;
|
||||
cpl_write_pcie_axi_dma_write_desc_valid_reg <= cpl_write_pcie_axi_dma_write_desc_valid_next;
|
||||
|
||||
if (desc_table_start_en) begin
|
||||
desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b1;
|
||||
desc_table_invalid[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
|
||||
@ -1163,11 +793,6 @@ always @(posedge clk) begin
|
||||
if (desc_table_cpl_enqueue_start_en) begin
|
||||
desc_table_cpl_enqueue_start_ptr_reg <= desc_table_cpl_enqueue_start_ptr_reg + 1;
|
||||
end
|
||||
if (desc_table_cpl_write_en) begin
|
||||
if (desc_table_cpl_write_invalid) begin
|
||||
desc_table_invalid[desc_table_cpl_write_ptr & DESC_PTR_MASK] <= 1'b1;
|
||||
end
|
||||
end
|
||||
if (desc_table_cpl_write_done_en) begin
|
||||
desc_table_cpl_write_done[desc_table_cpl_write_done_ptr & DESC_PTR_MASK] <= 1'b1;
|
||||
end
|
||||
@ -1184,22 +809,15 @@ always @(posedge clk) begin
|
||||
end
|
||||
end
|
||||
|
||||
s_axis_rx_req_tag_reg <= s_axis_rx_req_tag_next;
|
||||
|
||||
m_axis_rx_req_status_len_reg <= m_axis_rx_req_status_len_next;
|
||||
m_axis_rx_req_status_tag_reg <= m_axis_rx_req_status_tag_next;
|
||||
|
||||
m_axis_desc_dequeue_req_queue_reg <= m_axis_desc_dequeue_req_queue_next;
|
||||
m_axis_desc_dequeue_req_tag_reg <= m_axis_desc_dequeue_req_tag_next;
|
||||
m_axis_desc_dequeue_commit_op_tag_reg <= m_axis_desc_dequeue_commit_op_tag_next;
|
||||
m_axis_cpl_enqueue_req_queue_reg <= m_axis_cpl_enqueue_req_queue_next;
|
||||
m_axis_cpl_enqueue_req_tag_reg <= m_axis_cpl_enqueue_req_tag_next;
|
||||
m_axis_cpl_enqueue_commit_op_tag_reg <= m_axis_cpl_enqueue_commit_op_tag_next;
|
||||
m_axis_desc_req_queue_reg <= m_axis_desc_req_queue_next;
|
||||
m_axis_desc_req_tag_reg <= m_axis_desc_req_tag_next;
|
||||
|
||||
m_axis_pcie_axi_dma_read_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_read_desc_pcie_addr_next;
|
||||
m_axis_pcie_axi_dma_read_desc_axi_addr_reg <= m_axis_pcie_axi_dma_read_desc_axi_addr_next;
|
||||
m_axis_pcie_axi_dma_read_desc_len_reg <= m_axis_pcie_axi_dma_read_desc_len_next;
|
||||
m_axis_pcie_axi_dma_read_desc_tag_reg <= m_axis_pcie_axi_dma_read_desc_tag_next;
|
||||
m_axis_cpl_req_queue_reg <= m_axis_cpl_req_queue_next;
|
||||
m_axis_cpl_req_tag_reg <= m_axis_cpl_req_tag_next;
|
||||
m_axis_cpl_req_data_reg <= m_axis_cpl_req_data_next;
|
||||
|
||||
m_axis_pcie_axi_dma_write_desc_pcie_addr_reg <= m_axis_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
m_axis_pcie_axi_dma_write_desc_axi_addr_reg <= m_axis_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
@ -1210,16 +828,6 @@ always @(posedge clk) begin
|
||||
m_axis_rx_desc_len_reg <= m_axis_rx_desc_len_next;
|
||||
m_axis_rx_desc_tag_reg <= m_axis_rx_desc_tag_next;
|
||||
|
||||
pkt_write_pcie_axi_dma_write_desc_pcie_addr_reg <= pkt_write_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
pkt_write_pcie_axi_dma_write_desc_axi_addr_reg <= pkt_write_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
pkt_write_pcie_axi_dma_write_desc_len_reg <= pkt_write_pcie_axi_dma_write_desc_len_next;
|
||||
pkt_write_pcie_axi_dma_write_desc_tag_reg <= pkt_write_pcie_axi_dma_write_desc_tag_next;
|
||||
|
||||
cpl_write_pcie_axi_dma_write_desc_pcie_addr_reg <= cpl_write_pcie_axi_dma_write_desc_pcie_addr_next;
|
||||
cpl_write_pcie_axi_dma_write_desc_axi_addr_reg <= cpl_write_pcie_axi_dma_write_desc_axi_addr_next;
|
||||
cpl_write_pcie_axi_dma_write_desc_len_reg <= cpl_write_pcie_axi_dma_write_desc_len_next;
|
||||
cpl_write_pcie_axi_dma_write_desc_tag_reg <= cpl_write_pcie_axi_dma_write_desc_tag_next;
|
||||
|
||||
if (desc_table_start_en) begin
|
||||
desc_table_queue[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue;
|
||||
desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
|
||||
@ -1231,7 +839,10 @@ always @(posedge clk) begin
|
||||
if (desc_table_dequeue_en) begin
|
||||
desc_table_queue_ptr[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_queue_ptr;
|
||||
desc_table_cpl_queue[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_cpl_queue;
|
||||
desc_table_queue_op_tag[desc_table_dequeue_ptr & DESC_PTR_MASK] <= desc_table_dequeue_queue_op_tag;
|
||||
end
|
||||
if (desc_table_desc_fetched_en) begin
|
||||
desc_table_desc_len[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_len;
|
||||
desc_table_pcie_addr[desc_table_desc_fetched_ptr & DESC_PTR_MASK] <= desc_table_desc_fetched_pcie_addr;
|
||||
end
|
||||
if (desc_table_store_ptp_ts_en) begin
|
||||
desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts;
|
||||
@ -1239,9 +850,6 @@ always @(posedge clk) begin
|
||||
if (desc_table_store_csum_en) begin
|
||||
desc_table_csum[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] <= desc_table_store_csum;
|
||||
end
|
||||
if (desc_table_cpl_write_en) begin
|
||||
desc_table_cpl_queue_op_tag[desc_table_cpl_write_ptr & DESC_PTR_MASK] <= desc_table_cpl_write_queue_op_tag;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
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Reference in New Issue
Block a user