FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Fix TLP mux pause

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-06-21 02:30:38 -07:00
parent 1b2140a849
commit 23595150dd
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rtl/pcie_tlp_fifo_mux.v
View File

@ -347,7 +347,7 @@ always @* begin
// compute mux settings
for (port = 0; port < PORTS; port = port + 1) begin
port_seg_valid[port] = pause[port] ? 0 : {2{fifo_ctrl_tlp_valid[port]}} >> fifo_ctrl_seg_offset[port];
port_seg_valid[port] = {2{fifo_ctrl_tlp_valid[port]}} >> fifo_ctrl_seg_offset[port];
port_seg_eop[port] = {2{fifo_ctrl_tlp_eop[port]}} >> fifo_ctrl_seg_offset[port];
end
@ -383,7 +383,7 @@ always @* begin
port_cyc = cur_port;
seg_offset_cyc = port_seg_offset_cyc[cur_port];
seg_count_cyc = port_seg_count_cyc[cur_port];
if (port_seg_valid[cur_port][0]) begin
if (!pause[cur_port] && port_seg_valid[cur_port][0]) begin
// set frame
frame_cyc = 1;
sel_tlp_seq_valid_cyc[OUT_TLP_SEG_COUNT*cur_port+seg] = 1'b1;