diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v index 5f8eb2ddc..a9f5c1055 100644 --- a/rtl/axis_arb_mux.v +++ b/rtl/axis_arb_mux.v @@ -43,8 +43,10 @@ module axis_arb_mux # parameter KEEP_WIDTH = (DATA_WIDTH/8), // Propagate tid signal parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, + // input tid signal width + parameter S_ID_WIDTH = 8, + // output tid signal width + parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), // Propagate tdest signal parameter DEST_ENABLE = 0, // tdest signal width @@ -67,26 +69,26 @@ module axis_arb_mux # /* * AXI Stream inputs */ - input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata, - input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep, - input wire [S_COUNT-1:0] s_axis_tvalid, - output wire [S_COUNT-1:0] s_axis_tready, - input wire [S_COUNT-1:0] s_axis_tlast, - input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid, - input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest, - input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, + input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata, + input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep, + input wire [S_COUNT-1:0] s_axis_tvalid, + output wire [S_COUNT-1:0] s_axis_tready, + input wire [S_COUNT-1:0] s_axis_tlast, + input wire [S_COUNT*S_ID_WIDTH-1:0] s_axis_tid, + input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest, + input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, /* * AXI Stream output */ - output wire [DATA_WIDTH-1:0] m_axis_tdata, - output wire [KEEP_WIDTH-1:0] m_axis_tkeep, - output wire m_axis_tvalid, - input wire m_axis_tready, - output wire m_axis_tlast, - output wire [ID_WIDTH-1:0] m_axis_tid, - output wire [DEST_WIDTH-1:0] m_axis_tdest, - output wire [USER_WIDTH-1:0] m_axis_tuser + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [M_ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser ); parameter CL_S_COUNT = $clog2(S_COUNT); @@ -103,7 +105,7 @@ reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; reg m_axis_tvalid_int; reg m_axis_tready_int_reg = 1'b0; reg m_axis_tlast_int; -reg [ID_WIDTH-1:0] m_axis_tid_int; +reg [M_ID_WIDTH-1:0] m_axis_tid_int; reg [DEST_WIDTH-1:0] m_axis_tdest_int; reg [USER_WIDTH-1:0] m_axis_tuser_int; wire m_axis_tready_int_early; @@ -116,7 +118,7 @@ wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH + wire current_s_tvalid = s_axis_tvalid[grant_encoded]; wire current_s_tready = s_axis_tready[grant_encoded]; wire current_s_tlast = s_axis_tlast[grant_encoded]; -wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH]; +wire [S_ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH]; wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; @@ -157,7 +159,7 @@ reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; reg m_axis_tlast_reg = 1'b0; -reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [M_ID_WIDTH-1:0] m_axis_tid_reg = {M_ID_WIDTH{1'b0}}; reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; @@ -165,7 +167,7 @@ reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; reg temp_m_axis_tlast_reg = 1'b0; -reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [M_ID_WIDTH-1:0] temp_m_axis_tid_reg = {M_ID_WIDTH{1'b0}}; reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; @@ -178,7 +180,7 @@ assign m_axis_tdata = m_axis_tdata_reg; assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; assign m_axis_tvalid = m_axis_tvalid_reg; assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; -assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; +assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {M_ID_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; diff --git a/rtl/axis_arb_mux_wrap.py b/rtl/axis_arb_mux_wrap.py index 4cfe2b8fc..7e02d207f 100755 --- a/rtl/axis_arb_mux_wrap.py +++ b/rtl/axis_arb_mux_wrap.py @@ -78,8 +78,10 @@ module {{name}} # parameter KEEP_WIDTH = (DATA_WIDTH/8), // Propagate tid signal parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, + // input tid signal width + parameter S_ID_WIDTH = 8, + // output tid signal width + parameter M_ID_WIDTH = S_ID_WIDTH+{{cn}}, // Propagate tdest signal parameter DEST_ENABLE = 0, // tdest signal width @@ -96,33 +98,33 @@ module {{name}} # parameter ARB_LSB_HIGH_PRIORITY = 1 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI Stream inputs */ {%- for p in range(n) %} - input wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata, - input wire [KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep, - input wire s{{'%02d'%p}}_axis_tvalid, - output wire s{{'%02d'%p}}_axis_tready, - input wire s{{'%02d'%p}}_axis_tlast, - input wire [ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid, - input wire [DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest, - input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser, + input wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata, + input wire [KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep, + input wire s{{'%02d'%p}}_axis_tvalid, + output wire s{{'%02d'%p}}_axis_tready, + input wire s{{'%02d'%p}}_axis_tlast, + input wire [S_ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid, + input wire [DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest, + input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser, {% endfor %} /* * AXI Stream output */ - output wire [DATA_WIDTH-1:0] m_axis_tdata, - output wire [KEEP_WIDTH-1:0] m_axis_tkeep, - output wire m_axis_tvalid, - input wire m_axis_tready, - output wire m_axis_tlast, - output wire [ID_WIDTH-1:0] m_axis_tid, - output wire [DEST_WIDTH-1:0] m_axis_tdest, - output wire [USER_WIDTH-1:0] m_axis_tuser + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [M_ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser ); axis_arb_mux #( @@ -131,7 +133,8 @@ axis_arb_mux #( .KEEP_ENABLE(KEEP_ENABLE), .KEEP_WIDTH(KEEP_WIDTH), .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), + .S_ID_WIDTH(S_ID_WIDTH), + .M_ID_WIDTH(M_ID_WIDTH), .DEST_ENABLE(DEST_ENABLE), .DEST_WIDTH(DEST_WIDTH), .USER_ENABLE(USER_ENABLE), diff --git a/rtl/axis_demux.v b/rtl/axis_demux.v index fbfc748d2..c49fe425b 100644 --- a/rtl/axis_demux.v +++ b/rtl/axis_demux.v @@ -47,47 +47,49 @@ module axis_demux # parameter ID_WIDTH = 8, // Propagate tdest signal parameter DEST_ENABLE = 0, - // tdest signal width - parameter DEST_WIDTH = 8, + // output tdest signal width + parameter M_DEST_WIDTH = 8, + // input tdest signal width + parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(M_COUNT), // Propagate tuser signal parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI input */ - input wire [DATA_WIDTH-1:0] s_axis_tdata, - input wire [KEEP_WIDTH-1:0] s_axis_tkeep, - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire s_axis_tlast, - input wire [ID_WIDTH-1:0] s_axis_tid, - input wire [DEST_WIDTH-1:0] s_axis_tdest, - input wire [USER_WIDTH-1:0] s_axis_tuser, + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [S_DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, /* * AXI outputs */ - output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata, - output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep, - output wire [M_COUNT-1:0] m_axis_tvalid, - input wire [M_COUNT-1:0] m_axis_tready, - output wire [M_COUNT-1:0] m_axis_tlast, - output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid, - output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest, - output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser, + output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata, + output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep, + output wire [M_COUNT-1:0] m_axis_tvalid, + input wire [M_COUNT-1:0] m_axis_tready, + output wire [M_COUNT-1:0] m_axis_tlast, + output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid, + output wire [M_COUNT*M_DEST_WIDTH-1:0] m_axis_tdest, + output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser, /* * Control */ - input wire enable, - input wire drop, - input wire [$clog2(M_COUNT)-1:0] select + input wire enable, + input wire drop, + input wire [$clog2(M_COUNT)-1:0] select ); parameter CL_M_COUNT = $clog2(M_COUNT); @@ -99,15 +101,15 @@ reg frame_reg = 1'b0, frame_ctl, frame_next; reg s_axis_tready_reg = 1'b0, s_axis_tready_next; // internal datapath -reg [DATA_WIDTH-1:0] m_axis_tdata_int; -reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; -reg [M_COUNT-1:0] m_axis_tvalid_int; -reg m_axis_tready_int_reg = 1'b0; -reg m_axis_tlast_int; -reg [ID_WIDTH-1:0] m_axis_tid_int; -reg [DEST_WIDTH-1:0] m_axis_tdest_int; -reg [USER_WIDTH-1:0] m_axis_tuser_int; -wire m_axis_tready_int_early; +reg [DATA_WIDTH-1:0] m_axis_tdata_int; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; +reg [M_COUNT-1:0] m_axis_tvalid_int; +reg m_axis_tready_int_reg = 1'b0; +reg m_axis_tlast_int; +reg [ID_WIDTH-1:0] m_axis_tid_int; +reg [M_DEST_WIDTH-1:0] m_axis_tdest_int; +reg [USER_WIDTH-1:0] m_axis_tuser_int; +wire m_axis_tready_int_early; assign s_axis_tready = s_axis_tready_reg && enable; @@ -167,21 +169,21 @@ always @(posedge clk) begin end // output datapath logic -reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; -reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; -reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next; -reg m_axis_tlast_reg = 1'b0; -reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; -reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; -reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; +reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next; +reg m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [M_DEST_WIDTH-1:0] m_axis_tdest_reg = {M_DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; -reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; -reg [M_COUNT-1:0] temp_m_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_tvalid_next; -reg temp_m_axis_tlast_reg = 1'b0; -reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; -reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; -reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; +reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg [M_COUNT-1:0] temp_m_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_tvalid_next; +reg temp_m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [M_DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {M_DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; // datapath control reg store_axis_int_to_output; @@ -193,7 +195,7 @@ assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP assign m_axis_tvalid = m_axis_tvalid_reg; assign m_axis_tlast = {M_COUNT{m_axis_tlast_reg}}; assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}}; -assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}}; // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) diff --git a/rtl/axis_demux_wrap.py b/rtl/axis_demux_wrap.py index 8f69561db..682e31b0e 100755 --- a/rtl/axis_demux_wrap.py +++ b/rtl/axis_demux_wrap.py @@ -82,49 +82,50 @@ module {{name}} # parameter ID_WIDTH = 8, // Propagate tdest signal parameter DEST_ENABLE = 0, - // tdest signal width - parameter DEST_WIDTH = 8, + // output tdest signal width + parameter M_DEST_WIDTH = 1, + // input tdest signal width + parameter S_DEST_WIDTH = M_DEST_WIDTH+{{cn}}, // Propagate tuser signal parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI Stream input */ - input wire [DATA_WIDTH-1:0] s_axis_tdata, - input wire [KEEP_WIDTH-1:0] s_axis_tkeep, - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire s_axis_tlast, - input wire [ID_WIDTH-1:0] s_axis_tid, - input wire [DEST_WIDTH-1:0] s_axis_tdest, - input wire [USER_WIDTH-1:0] s_axis_tuser, + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [S_DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, /* * AXI Stream outputs */ {%- for p in range(n) %} - output wire [DATA_WIDTH-1:0] m{{'%02d'%p}}_axis_tdata, - output wire [KEEP_WIDTH-1:0] m{{'%02d'%p}}_axis_tkeep, - output wire m{{'%02d'%p}}_axis_tvalid, - input wire m{{'%02d'%p}}_axis_tready, - output wire m{{'%02d'%p}}_axis_tlast, - output wire [ID_WIDTH-1:0] m{{'%02d'%p}}_axis_tid, - output wire [DEST_WIDTH-1:0] m{{'%02d'%p}}_axis_tdest, - output wire [USER_WIDTH-1:0] m{{'%02d'%p}}_axis_tuser, -{% endfor -%} - + output wire [DATA_WIDTH-1:0] m{{'%02d'%p}}_axis_tdata, + output wire [KEEP_WIDTH-1:0] m{{'%02d'%p}}_axis_tkeep, + output wire m{{'%02d'%p}}_axis_tvalid, + input wire m{{'%02d'%p}}_axis_tready, + output wire m{{'%02d'%p}}_axis_tlast, + output wire [ID_WIDTH-1:0] m{{'%02d'%p}}_axis_tid, + output wire [M_DEST_WIDTH-1:0] m{{'%02d'%p}}_axis_tdest, + output wire [USER_WIDTH-1:0] m{{'%02d'%p}}_axis_tuser, +{% endfor %} /* * Control */ - input wire enable, - input wire drop, - input wire [{{cn-1}}:0] select + input wire enable, + input wire drop, + input wire [{{cn-1}}:0] select ); axis_demux #( @@ -135,7 +136,8 @@ axis_demux #( .ID_ENABLE(ID_ENABLE), .ID_WIDTH(ID_WIDTH), .DEST_ENABLE(DEST_ENABLE), - .DEST_WIDTH(DEST_WIDTH), + .S_DEST_WIDTH(S_DEST_WIDTH), + .M_DEST_WIDTH(M_DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH) ) diff --git a/rtl/axis_ram_switch.v b/rtl/axis_ram_switch.v index c936232c5..a88184161 100644 --- a/rtl/axis_ram_switch.v +++ b/rtl/axis_ram_switch.v @@ -61,11 +61,15 @@ module axis_ram_switch # parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), // Propagate tid signal parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, - // tdest signal width + // input tid signal width + parameter S_ID_WIDTH = 8, + // output tid signal width + parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), + // output tdest signal width + parameter M_DEST_WIDTH = 1, + // input tdest signal width // must be wide enough to uniquely address outputs - parameter DEST_WIDTH = $clog2(M_COUNT), + parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(M_COUNT), // Propagate tuser signal parameter USER_ENABLE = 1, // tuser signal width @@ -80,12 +84,12 @@ module axis_ram_switch # // When set, s_axis_tready is always asserted parameter DROP_WHEN_FULL = 0, // Output interface routing base tdest selection - // Concatenate M_COUNT DEST_WIDTH sized constants + // Concatenate M_COUNT S_DEST_WIDTH sized constants // Port selected if M_BASE <= tdest <= M_TOP // set to zero for default routing with tdest MSBs as port index parameter M_BASE = 0, // Output interface routing top tdest selection - // Concatenate M_COUNT DEST_WIDTH sized constants + // Concatenate M_COUNT S_DEST_WIDTH sized constants // Port selected if M_BASE <= tdest <= M_TOP // set to zero to inherit from M_BASE parameter M_TOP = 0, @@ -100,39 +104,39 @@ module axis_ram_switch # parameter RAM_PIPELINE = 2 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI Stream inputs */ - input wire [S_COUNT*S_DATA_WIDTH-1:0] s_axis_tdata, - input wire [S_COUNT*S_KEEP_WIDTH-1:0] s_axis_tkeep, - input wire [S_COUNT-1:0] s_axis_tvalid, - output wire [S_COUNT-1:0] s_axis_tready, - input wire [S_COUNT-1:0] s_axis_tlast, - input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid, - input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest, - input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, + input wire [S_COUNT*S_DATA_WIDTH-1:0] s_axis_tdata, + input wire [S_COUNT*S_KEEP_WIDTH-1:0] s_axis_tkeep, + input wire [S_COUNT-1:0] s_axis_tvalid, + output wire [S_COUNT-1:0] s_axis_tready, + input wire [S_COUNT-1:0] s_axis_tlast, + input wire [S_COUNT*S_ID_WIDTH-1:0] s_axis_tid, + input wire [S_COUNT*S_DEST_WIDTH-1:0] s_axis_tdest, + input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, /* * AXI Stream outputs */ - output wire [M_COUNT*M_DATA_WIDTH-1:0] m_axis_tdata, - output wire [M_COUNT*M_KEEP_WIDTH-1:0] m_axis_tkeep, - output wire [M_COUNT-1:0] m_axis_tvalid, - input wire [M_COUNT-1:0] m_axis_tready, - output wire [M_COUNT-1:0] m_axis_tlast, - output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid, - output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest, - output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser, + output wire [M_COUNT*M_DATA_WIDTH-1:0] m_axis_tdata, + output wire [M_COUNT*M_KEEP_WIDTH-1:0] m_axis_tkeep, + output wire [M_COUNT-1:0] m_axis_tvalid, + input wire [M_COUNT-1:0] m_axis_tready, + output wire [M_COUNT-1:0] m_axis_tlast, + output wire [M_COUNT*M_ID_WIDTH-1:0] m_axis_tid, + output wire [M_COUNT*M_DEST_WIDTH-1:0] m_axis_tdest, + output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser, /* * Status */ - output wire [S_COUNT-1:0] status_overflow, - output wire [S_COUNT-1:0] status_bad_frame, - output wire [S_COUNT-1:0] status_good_frame + output wire [S_COUNT-1:0] status_overflow, + output wire [S_COUNT-1:0] status_bad_frame, + output wire [S_COUNT-1:0] status_good_frame ); parameter CL_S_COUNT = $clog2(S_COUNT); @@ -179,8 +183,8 @@ initial begin $finish; end - if (DEST_WIDTH < CL_M_COUNT) begin - $error("Error: DEST_WIDTH too small for port count (instance %m)"); + if (S_DEST_WIDTH < CL_M_COUNT) begin + $error("Error: S_DEST_WIDTH too small for port count (instance %m)"); $finish; end @@ -188,21 +192,21 @@ initial begin // M_BASE is zero, route with tdest as port index $display("Addressing configuration for axis_switch instance %m"); for (i = 0; i < M_COUNT; i = i + 1) begin - $display("%d: %08x-%08x (connect mask %b)", i, i << (DEST_WIDTH-CL_M_COUNT), ((i+1) << (DEST_WIDTH-CL_M_COUNT))-1, M_CONNECT[i*S_COUNT +: S_COUNT]); + $display("%d: %08x-%08x (connect mask %b)", i, i << (S_DEST_WIDTH-CL_M_COUNT), ((i+1) << (S_DEST_WIDTH-CL_M_COUNT))-1, M_CONNECT[i*S_COUNT +: S_COUNT]); end end else if (M_TOP == 0) begin // M_TOP is zero, assume equal to M_BASE $display("Addressing configuration for axis_switch instance %m"); for (i = 0; i < M_COUNT; i = i + 1) begin - $display("%d: %08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); + $display("%d: %08x (connect mask %b)", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); end for (i = 0; i < M_COUNT; i = i + 1) begin for (j = i+1; j < M_COUNT; j = j + 1) begin - if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] == M_BASE[j*DEST_WIDTH +: DEST_WIDTH]) begin - $display("%d: %08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH]); - $display("%d: %08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH]); + if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] == M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH]) begin + $display("%d: %08x", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH]); + $display("%d: %08x", j, M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH]); $error("Error: ranges overlap (instance %m)"); $finish; end @@ -211,11 +215,11 @@ initial begin end else begin $display("Addressing configuration for axis_switch instance %m"); for (i = 0; i < M_COUNT; i = i + 1) begin - $display("%d: %08x-%08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); + $display("%d: %08x-%08x (connect mask %b)", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); end for (i = 0; i < M_COUNT; i = i + 1) begin - if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] > M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin + if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] > M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]) begin $error("Error: invalid range (instance %m)"); $finish; end @@ -223,9 +227,9 @@ initial begin for (i = 0; i < M_COUNT; i = i + 1) begin for (j = i+1; j < M_COUNT; j = j + 1) begin - if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[j*DEST_WIDTH +: DEST_WIDTH] && M_BASE[j*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin - $display("%d: %08x-%08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH]); - $display("%d: %08x-%08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH], M_TOP[j*DEST_WIDTH +: DEST_WIDTH]); + if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] <= M_TOP[j*S_DEST_WIDTH +: S_DEST_WIDTH] && M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH] <= M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]) begin + $display("%d: %08x-%08x", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]); + $display("%d: %08x-%08x", j, M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[j*S_DEST_WIDTH +: S_DEST_WIDTH]); $error("Error: ranges overlap (instance %m)"); $finish; end @@ -349,21 +353,21 @@ always @(posedge clk) begin end // Interconnect -wire [S_COUNT*RAM_ADDR_WIDTH-1:0] int_cmd_addr; -wire [S_COUNT*ADDR_WIDTH-1:0] int_cmd_len; -wire [S_COUNT*CMD_ADDR_WIDTH-1:0] int_cmd_id; -wire [S_COUNT*KEEP_WIDTH-1:0] int_cmd_tkeep; -wire [S_COUNT*ID_WIDTH-1:0] int_cmd_tid; -wire [S_COUNT*DEST_WIDTH-1:0] int_cmd_tdest; -wire [S_COUNT*USER_WIDTH-1:0] int_cmd_tuser; +wire [S_COUNT*RAM_ADDR_WIDTH-1:0] int_cmd_addr; +wire [S_COUNT*ADDR_WIDTH-1:0] int_cmd_len; +wire [S_COUNT*CMD_ADDR_WIDTH-1:0] int_cmd_id; +wire [S_COUNT*KEEP_WIDTH-1:0] int_cmd_tkeep; +wire [S_COUNT*S_ID_WIDTH-1:0] int_cmd_tid; +wire [S_COUNT*S_DEST_WIDTH-1:0] int_cmd_tdest; +wire [S_COUNT*USER_WIDTH-1:0] int_cmd_tuser; -wire [S_COUNT*M_COUNT-1:0] int_cmd_valid; -wire [M_COUNT*S_COUNT-1:0] int_cmd_ready; +wire [S_COUNT*M_COUNT-1:0] int_cmd_valid; +wire [M_COUNT*S_COUNT-1:0] int_cmd_ready; -wire [M_COUNT*CMD_ADDR_WIDTH-1:0] int_cmd_status_id; +wire [M_COUNT*CMD_ADDR_WIDTH-1:0] int_cmd_status_id; -wire [M_COUNT*S_COUNT-1:0] int_cmd_status_valid; -wire [S_COUNT*M_COUNT-1:0] int_cmd_status_ready; +wire [M_COUNT*S_COUNT-1:0] int_cmd_status_valid; +wire [S_COUNT*M_COUNT-1:0] int_cmd_status_ready; generate @@ -371,14 +375,14 @@ generate for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces - wire [DATA_WIDTH-1:0] port_axis_tdata; - wire [KEEP_WIDTH-1:0] port_axis_tkeep; - wire port_axis_tvalid; - wire port_axis_tready; - wire port_axis_tlast; - wire [ID_WIDTH-1:0] port_axis_tid; - wire [DEST_WIDTH-1:0] port_axis_tdest; - wire [USER_WIDTH-1:0] port_axis_tuser; + wire [DATA_WIDTH-1:0] port_axis_tdata; + wire [KEEP_WIDTH-1:0] port_axis_tkeep; + wire port_axis_tvalid; + wire port_axis_tready; + wire port_axis_tlast; + wire [S_ID_WIDTH-1:0] port_axis_tid; + wire [S_DEST_WIDTH-1:0] port_axis_tdest; + wire [USER_WIDTH-1:0] port_axis_tuser; axis_adapter #( .S_DATA_WIDTH(S_DATA_WIDTH), @@ -388,9 +392,9 @@ generate .M_KEEP_ENABLE(1), .M_KEEP_WIDTH(KEEP_WIDTH), .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), + .ID_WIDTH(S_ID_WIDTH), .DEST_ENABLE(1), - .DEST_WIDTH(DEST_WIDTH), + .DEST_WIDTH(S_DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH) ) @@ -403,8 +407,8 @@ generate .s_axis_tvalid(s_axis_tvalid[m]), .s_axis_tready(s_axis_tready[m]), .s_axis_tlast(s_axis_tlast[m]), - .s_axis_tid(s_axis_tid[ID_WIDTH*m +: ID_WIDTH]), - .s_axis_tdest(s_axis_tdest[DEST_WIDTH*m +: DEST_WIDTH]), + .s_axis_tid(s_axis_tid[S_ID_WIDTH*m +: S_ID_WIDTH]), + .s_axis_tdest(s_axis_tdest[S_DEST_WIDTH*m +: S_DEST_WIDTH]), .s_axis_tuser(s_axis_tuser[USER_WIDTH*m +: USER_WIDTH]), // AXI output .m_axis_tdata(port_axis_tdata), @@ -442,7 +446,7 @@ generate drop_next = 1'b0; end else begin // M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index - if (port_axis_tdest[DEST_WIDTH-CL_M_COUNT +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin + if (port_axis_tdest[S_DEST_WIDTH-CL_M_COUNT +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin select_next = k; select_valid_next = 1'b1; drop_next = 1'b0; @@ -450,13 +454,13 @@ generate end end else if (M_TOP == 0) begin // M_TOP is zero, assume equal to M_BASE - if (port_axis_tdest == M_BASE[k*DEST_WIDTH +: DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin + if (port_axis_tdest == M_BASE[k*S_DEST_WIDTH +: S_DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin select_next = k; select_valid_next = 1'b1; drop_next = 1'b0; end end else begin - if (port_axis_tdest >= M_BASE[k*DEST_WIDTH +: DEST_WIDTH] && port_axis_tdest <= M_TOP[k*DEST_WIDTH +: DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin + if (port_axis_tdest >= M_BASE[k*S_DEST_WIDTH +: S_DEST_WIDTH] && port_axis_tdest <= M_TOP[k*S_DEST_WIDTH +: S_DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin select_next = k; select_valid_next = 1'b1; drop_next = 1'b0; @@ -542,8 +546,8 @@ generate reg [ADDR_WIDTH-1:0] cmd_table_len[2**CMD_ADDR_WIDTH-1:0]; reg [CL_M_COUNT-1:0] cmd_table_select[2**CMD_ADDR_WIDTH-1:0]; reg [KEEP_WIDTH-1:0] cmd_table_tkeep[2**CMD_ADDR_WIDTH-1:0]; - reg [ID_WIDTH-1:0] cmd_table_tid[2**CMD_ADDR_WIDTH-1:0]; - reg [DEST_WIDTH-1:0] cmd_table_tdest[2**CMD_ADDR_WIDTH-1:0]; + reg [S_ID_WIDTH-1:0] cmd_table_tid[2**CMD_ADDR_WIDTH-1:0]; + reg [S_DEST_WIDTH-1:0] cmd_table_tdest[2**CMD_ADDR_WIDTH-1:0]; reg [USER_WIDTH-1:0] cmd_table_tuser[2**CMD_ADDR_WIDTH-1:0]; reg [CMD_ADDR_WIDTH+1-1:0] cmd_table_start_ptr_reg = 0; @@ -552,8 +556,8 @@ generate reg [ADDR_WIDTH-1:0] cmd_table_start_len; reg [CL_M_COUNT-1:0] cmd_table_start_select; reg [KEEP_WIDTH-1:0] cmd_table_start_tkeep; - reg [ID_WIDTH-1:0] cmd_table_start_tid; - reg [DEST_WIDTH-1:0] cmd_table_start_tdest; + reg [S_ID_WIDTH-1:0] cmd_table_start_tid; + reg [S_DEST_WIDTH-1:0] cmd_table_start_tdest; reg [USER_WIDTH-1:0] cmd_table_start_tuser; reg cmd_table_start_en; reg [CMD_ADDR_WIDTH+1-1:0] cmd_table_read_ptr_reg = 0; @@ -563,14 +567,14 @@ generate reg [CMD_ADDR_WIDTH+1-1:0] cmd_table_finish_ptr_reg = 0; reg cmd_table_finish_en; - reg [RAM_ADDR_WIDTH-1:0] cmd_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, cmd_addr_next; - reg [ADDR_WIDTH-1:0] cmd_len_reg = {ADDR_WIDTH{1'b0}}, cmd_len_next; - reg [CMD_ADDR_WIDTH-1:0] cmd_id_reg = {CMD_ADDR_WIDTH{1'b0}}, cmd_id_next; - reg [KEEP_WIDTH-1:0] cmd_tkeep_reg = {KEEP_WIDTH{1'b0}}, cmd_tkeep_next; - reg [ID_WIDTH-1:0] cmd_tid_reg = {ID_WIDTH{1'b0}}, cmd_tid_next; - reg [DEST_WIDTH-1:0] cmd_tdest_reg = {DEST_WIDTH{1'b0}}, cmd_tdest_next; - reg [USER_WIDTH-1:0] cmd_tuser_reg = {USER_WIDTH{1'b0}}, cmd_tuser_next; - reg [M_COUNT-1:0] cmd_valid_reg = 0, cmd_valid_next; + reg [RAM_ADDR_WIDTH-1:0] cmd_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, cmd_addr_next; + reg [ADDR_WIDTH-1:0] cmd_len_reg = {ADDR_WIDTH{1'b0}}, cmd_len_next; + reg [CMD_ADDR_WIDTH-1:0] cmd_id_reg = {CMD_ADDR_WIDTH{1'b0}}, cmd_id_next; + reg [KEEP_WIDTH-1:0] cmd_tkeep_reg = {KEEP_WIDTH{1'b0}}, cmd_tkeep_next; + reg [S_ID_WIDTH-1:0] cmd_tid_reg = {S_ID_WIDTH{1'b0}}, cmd_tid_next; + reg [S_DEST_WIDTH-1:0] cmd_tdest_reg = {S_DEST_WIDTH{1'b0}}, cmd_tdest_next; + reg [USER_WIDTH-1:0] cmd_tuser_reg = {USER_WIDTH{1'b0}}, cmd_tuser_next; + reg [M_COUNT-1:0] cmd_valid_reg = 0, cmd_valid_next; reg cmd_status_ready_reg = 1'b0, cmd_status_ready_next; @@ -590,8 +594,8 @@ generate assign int_cmd_len[m*ADDR_WIDTH +: ADDR_WIDTH] = cmd_len_reg; assign int_cmd_id[m*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH] = cmd_id_reg; assign int_cmd_tkeep[m*KEEP_WIDTH +: KEEP_WIDTH] = cmd_tkeep_reg; - assign int_cmd_tid[m*ID_WIDTH +: ID_WIDTH] = cmd_tid_reg; - assign int_cmd_tdest[m*DEST_WIDTH +: DEST_WIDTH] = cmd_tdest_reg; + assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH] = cmd_tid_reg; + assign int_cmd_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] = cmd_tdest_reg; assign int_cmd_tuser[m*USER_WIDTH +: USER_WIDTH] = cmd_tuser_reg; assign int_cmd_valid[m*M_COUNT +: M_COUNT] = cmd_valid_reg; @@ -825,8 +829,8 @@ generate wire [ADDR_WIDTH-1:0] cmd_len_mux = int_cmd_len[grant_encoded*ADDR_WIDTH +: ADDR_WIDTH]; wire [CMD_ADDR_WIDTH-1:0] cmd_id_mux = int_cmd_id[grant_encoded*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH]; wire [KEEP_WIDTH-1:0] cmd_tkeep_mux = int_cmd_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH]; - wire [ID_WIDTH-1:0] cmd_tid_mux = int_cmd_tid[grant_encoded*ID_WIDTH +: ID_WIDTH]; - wire [DEST_WIDTH-1:0] cmd_tdest_mux = int_cmd_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; + wire [M_ID_WIDTH-1:0] cmd_tid_mux = int_cmd_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH]; + wire [M_DEST_WIDTH-1:0] cmd_tdest_mux = int_cmd_tdest[grant_encoded*S_DEST_WIDTH +: S_DEST_WIDTH]; wire [USER_WIDTH-1:0] cmd_tuser_mux = int_cmd_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; wire cmd_valid_mux = int_cmd_valid[grant_encoded*M_COUNT+n] && grant_valid; wire cmd_ready_mux; @@ -846,18 +850,18 @@ generate reg [CMD_ADDR_WIDTH-1:0] id_reg = 0, id_next; reg [KEEP_WIDTH-1:0] last_cycle_tkeep_reg = {KEEP_WIDTH{1'b0}}, last_cycle_tkeep_next; - reg [ID_WIDTH-1:0] tid_reg = {ID_WIDTH{1'b0}}, tid_next; - reg [DEST_WIDTH-1:0] tdest_reg = {DEST_WIDTH{1'b0}}, tdest_next; + reg [M_ID_WIDTH-1:0] tid_reg = {M_ID_WIDTH{1'b0}}, tid_next; + reg [M_DEST_WIDTH-1:0] tdest_reg = {M_DEST_WIDTH{1'b0}}, tdest_next; reg [USER_WIDTH-1:0] tuser_reg = {USER_WIDTH{1'b0}}, tuser_next; - reg [DATA_WIDTH-1:0] out_axis_tdata_reg = {DATA_WIDTH{1'b0}}, out_axis_tdata_next; - reg [KEEP_WIDTH-1:0] out_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, out_axis_tkeep_next; - reg out_axis_tvalid_reg = 1'b0, out_axis_tvalid_next; - wire out_axis_tready; - reg out_axis_tlast_reg = 1'b0, out_axis_tlast_next; - reg [ID_WIDTH-1:0] out_axis_tid_reg = {ID_WIDTH{1'b0}}, out_axis_tid_next; - reg [DEST_WIDTH-1:0] out_axis_tdest_reg = {DEST_WIDTH{1'b0}}, out_axis_tdest_next; - reg [USER_WIDTH-1:0] out_axis_tuser_reg = {USER_WIDTH{1'b0}}, out_axis_tuser_next; + reg [DATA_WIDTH-1:0] out_axis_tdata_reg = {DATA_WIDTH{1'b0}}, out_axis_tdata_next; + reg [KEEP_WIDTH-1:0] out_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, out_axis_tkeep_next; + reg out_axis_tvalid_reg = 1'b0, out_axis_tvalid_next; + wire out_axis_tready; + reg out_axis_tlast_reg = 1'b0, out_axis_tlast_next; + reg [M_ID_WIDTH-1:0] out_axis_tid_reg = {M_ID_WIDTH{1'b0}}, out_axis_tid_next; + reg [M_DEST_WIDTH-1:0] out_axis_tdest_reg = {M_DEST_WIDTH{1'b0}}, out_axis_tdest_next; + reg [USER_WIDTH-1:0] out_axis_tuser_reg = {USER_WIDTH{1'b0}}, out_axis_tuser_next; reg [RAM_ADDR_WIDTH-1:0] ram_rd_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, ram_rd_addr_next; reg ram_rd_en_reg = 1'b0, ram_rd_en_next; @@ -878,8 +882,8 @@ generate reg [DATA_WIDTH-1:0] out_fifo_tdata[31:0]; reg [KEEP_WIDTH-1:0] out_fifo_tkeep[31:0]; reg out_fifo_tlast[31:0]; - reg [ID_WIDTH-1:0] out_fifo_tid[31:0]; - reg [DEST_WIDTH-1:0] out_fifo_tdest[31:0]; + reg [M_ID_WIDTH-1:0] out_fifo_tid[31:0]; + reg [M_DEST_WIDTH-1:0] out_fifo_tdest[31:0]; reg [USER_WIDTH-1:0] out_fifo_tuser[31:0]; reg [5:0] out_fifo_data_wr_ptr_reg = 0; @@ -888,8 +892,8 @@ generate reg [5:0] out_fifo_ctrl_wr_ptr_reg = 0; reg [KEEP_WIDTH-1:0] out_fifo_ctrl_wr_tkeep; reg out_fifo_ctrl_wr_tlast; - reg [ID_WIDTH-1:0] out_fifo_ctrl_wr_tid; - reg [DEST_WIDTH-1:0] out_fifo_ctrl_wr_tdest; + reg [M_ID_WIDTH-1:0] out_fifo_ctrl_wr_tid; + reg [M_DEST_WIDTH-1:0] out_fifo_ctrl_wr_tdest; reg [USER_WIDTH-1:0] out_fifo_ctrl_wr_tuser; reg out_fifo_ctrl_wr_en; reg [5:0] out_fifo_rd_ptr_reg = 0; @@ -1071,9 +1075,9 @@ generate .M_KEEP_ENABLE(M_KEEP_ENABLE), .M_KEEP_WIDTH(M_KEEP_WIDTH), .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), + .ID_WIDTH(M_ID_WIDTH), .DEST_ENABLE(1), - .DEST_WIDTH(DEST_WIDTH), + .DEST_WIDTH(M_DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH) ) @@ -1095,8 +1099,8 @@ generate .m_axis_tvalid(m_axis_tvalid[n]), .m_axis_tready(m_axis_tready[n]), .m_axis_tlast(m_axis_tlast[n]), - .m_axis_tid(m_axis_tid[ID_WIDTH*n +: ID_WIDTH]), - .m_axis_tdest(m_axis_tdest[DEST_WIDTH*n +: DEST_WIDTH]), + .m_axis_tid(m_axis_tid[M_ID_WIDTH*n +: M_ID_WIDTH]), + .m_axis_tdest(m_axis_tdest[M_DEST_WIDTH*n +: M_DEST_WIDTH]), .m_axis_tuser(m_axis_tuser[USER_WIDTH*n +: USER_WIDTH]) ); end // m_ifaces diff --git a/rtl/axis_ram_switch_wrap.py b/rtl/axis_ram_switch_wrap.py index 6e07113f4..4d8e25b29 100755 --- a/rtl/axis_ram_switch_wrap.py +++ b/rtl/axis_ram_switch_wrap.py @@ -100,11 +100,15 @@ module {{name}} # parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), // Propagate tid signal parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, - // tdest signal width + // input tid signal width + parameter S_ID_WIDTH = 8, + // output tid signal width + parameter M_ID_WIDTH = S_ID_WIDTH+{{cm}}, + // output tdest signal width + parameter M_DEST_WIDTH = 1, + // input tdest signal width // must be wide enough to uniquely address outputs - parameter DEST_WIDTH = {{cn}}, + parameter S_DEST_WIDTH = M_DEST_WIDTH+{{cn}}, // Propagate tuser signal parameter USER_ENABLE = 1, // tuser signal width @@ -143,27 +147,27 @@ module {{name}} # * AXI Stream inputs */ {%- for p in range(m) %} - input wire [S_DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata, - input wire [S_KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep, - input wire s{{'%02d'%p}}_axis_tvalid, - output wire s{{'%02d'%p}}_axis_tready, - input wire s{{'%02d'%p}}_axis_tlast, - input wire [ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid, - input wire [DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest, - input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser, + input wire [S_DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata, + input wire [S_KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep, + input wire s{{'%02d'%p}}_axis_tvalid, + output wire s{{'%02d'%p}}_axis_tready, + input wire s{{'%02d'%p}}_axis_tlast, + input wire [S_ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid, + input wire [S_DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest, + input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser, {% endfor %} /* * AXI Stream outputs */ {%- for p in range(n) %} - output wire [M_DATA_WIDTH-1:0] m{{'%02d'%p}}_axis_tdata, - output wire [M_KEEP_WIDTH-1:0] m{{'%02d'%p}}_axis_tkeep, - output wire m{{'%02d'%p}}_axis_tvalid, - input wire m{{'%02d'%p}}_axis_tready, - output wire m{{'%02d'%p}}_axis_tlast, - output wire [ID_WIDTH-1:0] m{{'%02d'%p}}_axis_tid, - output wire [DEST_WIDTH-1:0] m{{'%02d'%p}}_axis_tdest, - output wire [USER_WIDTH-1:0] m{{'%02d'%p}}_axis_tuser, + output wire [M_DATA_WIDTH-1:0] m{{'%02d'%p}}_axis_tdata, + output wire [M_KEEP_WIDTH-1:0] m{{'%02d'%p}}_axis_tkeep, + output wire m{{'%02d'%p}}_axis_tvalid, + input wire m{{'%02d'%p}}_axis_tready, + output wire m{{'%02d'%p}}_axis_tlast, + output wire [M_ID_WIDTH-1:0] m{{'%02d'%p}}_axis_tid, + output wire [M_DEST_WIDTH-1:0] m{{'%02d'%p}}_axis_tdest, + output wire [USER_WIDTH-1:0] m{{'%02d'%p}}_axis_tuser, {% endfor %} /* * Status @@ -174,7 +178,7 @@ module {{name}} # ); // parameter sizing helpers -function [DEST_WIDTH-1:0] w_dw(input [DEST_WIDTH-1:0] val); +function [S_DEST_WIDTH-1:0] w_dw(input [S_DEST_WIDTH-1:0] val); w_dw = val; endfunction @@ -195,8 +199,10 @@ axis_ram_switch #( .M_KEEP_ENABLE(M_KEEP_ENABLE), .M_KEEP_WIDTH(M_KEEP_WIDTH), .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), - .DEST_WIDTH(DEST_WIDTH), + .S_ID_WIDTH(S_ID_WIDTH), + .M_ID_WIDTH(M_ID_WIDTH), + .S_DEST_WIDTH(S_DEST_WIDTH), + .M_DEST_WIDTH(M_DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH), .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), diff --git a/rtl/axis_switch.v b/rtl/axis_switch.v index 4688d639f..f65368f72 100644 --- a/rtl/axis_switch.v +++ b/rtl/axis_switch.v @@ -45,22 +45,26 @@ module axis_switch # parameter KEEP_WIDTH = (DATA_WIDTH/8), // Propagate tid signal parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, - // tdest signal width + // input tid signal width + parameter S_ID_WIDTH = 8, + // output tid signal width + parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), + // output tdest signal width + parameter M_DEST_WIDTH = 1, + // input tdest signal width // must be wide enough to uniquely address outputs - parameter DEST_WIDTH = $clog2(M_COUNT), + parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(M_COUNT), // Propagate tuser signal parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1, // Output interface routing base tdest selection - // Concatenate M_COUNT DEST_WIDTH sized constants + // Concatenate M_COUNT S_DEST_WIDTH sized constants // Port selected if M_BASE <= tdest <= M_TOP // set to zero for default routing with tdest MSBs as port index parameter M_BASE = 0, // Output interface routing top tdest selection - // Concatenate M_COUNT DEST_WIDTH sized constants + // Concatenate M_COUNT S_DEST_WIDTH sized constants // Port selected if M_BASE <= tdest <= M_TOP // set to zero to inherit from M_BASE parameter M_TOP = 0, @@ -79,32 +83,32 @@ module axis_switch # parameter ARB_LSB_HIGH_PRIORITY = 1 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * AXI Stream inputs */ - input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata, - input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep, - input wire [S_COUNT-1:0] s_axis_tvalid, - output wire [S_COUNT-1:0] s_axis_tready, - input wire [S_COUNT-1:0] s_axis_tlast, - input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid, - input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest, - input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, + input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata, + input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep, + input wire [S_COUNT-1:0] s_axis_tvalid, + output wire [S_COUNT-1:0] s_axis_tready, + input wire [S_COUNT-1:0] s_axis_tlast, + input wire [S_COUNT*S_ID_WIDTH-1:0] s_axis_tid, + input wire [S_COUNT*S_DEST_WIDTH-1:0] s_axis_tdest, + input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, /* * AXI Stream outputs */ - output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata, - output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep, - output wire [M_COUNT-1:0] m_axis_tvalid, - input wire [M_COUNT-1:0] m_axis_tready, - output wire [M_COUNT-1:0] m_axis_tlast, - output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid, - output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest, - output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser + output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata, + output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep, + output wire [M_COUNT-1:0] m_axis_tvalid, + input wire [M_COUNT-1:0] m_axis_tready, + output wire [M_COUNT-1:0] m_axis_tlast, + output wire [M_COUNT*M_ID_WIDTH-1:0] m_axis_tid, + output wire [M_COUNT*M_DEST_WIDTH-1:0] m_axis_tdest, + output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser ); parameter CL_S_COUNT = $clog2(S_COUNT); @@ -114,8 +118,8 @@ integer i, j; // check configuration initial begin - if (DEST_WIDTH < CL_M_COUNT) begin - $error("Error: DEST_WIDTH too small for port count (instance %m)"); + if (S_DEST_WIDTH < CL_M_COUNT) begin + $error("Error: S_DEST_WIDTH too small for port count (instance %m)"); $finish; end @@ -123,21 +127,21 @@ initial begin // M_BASE is zero, route with tdest as port index $display("Addressing configuration for axis_switch instance %m"); for (i = 0; i < M_COUNT; i = i + 1) begin - $display("%d: %08x-%08x (connect mask %b)", i, i << (DEST_WIDTH-CL_M_COUNT), ((i+1) << (DEST_WIDTH-CL_M_COUNT))-1, M_CONNECT[i*S_COUNT +: S_COUNT]); + $display("%d: %08x-%08x (connect mask %b)", i, i << (S_DEST_WIDTH-CL_M_COUNT), ((i+1) << (S_DEST_WIDTH-CL_M_COUNT))-1, M_CONNECT[i*S_COUNT +: S_COUNT]); end end else if (M_TOP == 0) begin // M_TOP is zero, assume equal to M_BASE $display("Addressing configuration for axis_switch instance %m"); for (i = 0; i < M_COUNT; i = i + 1) begin - $display("%d: %08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); + $display("%d: %08x (connect mask %b)", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); end for (i = 0; i < M_COUNT; i = i + 1) begin for (j = i+1; j < M_COUNT; j = j + 1) begin - if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] == M_BASE[j*DEST_WIDTH +: DEST_WIDTH]) begin - $display("%d: %08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH]); - $display("%d: %08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH]); + if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] == M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH]) begin + $display("%d: %08x", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH]); + $display("%d: %08x", j, M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH]); $error("Error: ranges overlap (instance %m)"); $finish; end @@ -146,11 +150,11 @@ initial begin end else begin $display("Addressing configuration for axis_switch instance %m"); for (i = 0; i < M_COUNT; i = i + 1) begin - $display("%d: %08x-%08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); + $display("%d: %08x-%08x (connect mask %b)", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]); end for (i = 0; i < M_COUNT; i = i + 1) begin - if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] > M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin + if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] > M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]) begin $error("Error: invalid range (instance %m)"); $finish; end @@ -158,9 +162,9 @@ initial begin for (i = 0; i < M_COUNT; i = i + 1) begin for (j = i+1; j < M_COUNT; j = j + 1) begin - if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[j*DEST_WIDTH +: DEST_WIDTH] && M_BASE[j*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin - $display("%d: %08x-%08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH]); - $display("%d: %08x-%08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH], M_TOP[j*DEST_WIDTH +: DEST_WIDTH]); + if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] <= M_TOP[j*S_DEST_WIDTH +: S_DEST_WIDTH] && M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH] <= M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]) begin + $display("%d: %08x-%08x", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]); + $display("%d: %08x-%08x", j, M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[j*S_DEST_WIDTH +: S_DEST_WIDTH]); $error("Error: ranges overlap (instance %m)"); $finish; end @@ -169,17 +173,17 @@ initial begin end end -wire [S_COUNT*DATA_WIDTH-1:0] int_s_axis_tdata; -wire [S_COUNT*KEEP_WIDTH-1:0] int_s_axis_tkeep; -wire [S_COUNT-1:0] int_s_axis_tvalid; -wire [S_COUNT-1:0] int_s_axis_tready; -wire [S_COUNT-1:0] int_s_axis_tlast; -wire [S_COUNT*ID_WIDTH-1:0] int_s_axis_tid; -wire [S_COUNT*DEST_WIDTH-1:0] int_s_axis_tdest; -wire [S_COUNT*USER_WIDTH-1:0] int_s_axis_tuser; +wire [S_COUNT*DATA_WIDTH-1:0] int_s_axis_tdata; +wire [S_COUNT*KEEP_WIDTH-1:0] int_s_axis_tkeep; +wire [S_COUNT-1:0] int_s_axis_tvalid; +wire [S_COUNT-1:0] int_s_axis_tready; +wire [S_COUNT-1:0] int_s_axis_tlast; +wire [S_COUNT*S_ID_WIDTH-1:0] int_s_axis_tid; +wire [S_COUNT*S_DEST_WIDTH-1:0] int_s_axis_tdest; +wire [S_COUNT*USER_WIDTH-1:0] int_s_axis_tuser; -wire [S_COUNT*M_COUNT-1:0] int_axis_tvalid; -wire [M_COUNT*S_COUNT-1:0] int_axis_tready; +wire [S_COUNT*M_COUNT-1:0] int_axis_tvalid; +wire [M_COUNT*S_COUNT-1:0] int_axis_tready; generate @@ -212,7 +216,7 @@ generate drop_next = 1'b0; end else begin // M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index - if (int_s_axis_tdest[m*DEST_WIDTH+(DEST_WIDTH-CL_M_COUNT) +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin + if (int_s_axis_tdest[m*S_DEST_WIDTH+(S_DEST_WIDTH-CL_M_COUNT) +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin select_next = k; select_valid_next = 1'b1; drop_next = 1'b0; @@ -220,13 +224,13 @@ generate end end else if (M_TOP == 0) begin // M_TOP is zero, assume equal to M_BASE - if (int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] == M_BASE[k*DEST_WIDTH +: DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin + if (int_s_axis_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] == M_BASE[k*S_DEST_WIDTH +: S_DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin select_next = k; select_valid_next = 1'b1; drop_next = 1'b0; end end else begin - if (int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] >= M_BASE[k*DEST_WIDTH +: DEST_WIDTH] && int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[k*DEST_WIDTH +: DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin + if (int_s_axis_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] >= M_BASE[k*S_DEST_WIDTH +: S_DEST_WIDTH] && int_s_axis_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] <= M_TOP[k*S_DEST_WIDTH +: S_DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin select_next = k; select_valid_next = 1'b1; drop_next = 1'b0; @@ -258,9 +262,9 @@ generate .KEEP_WIDTH(KEEP_WIDTH), .LAST_ENABLE(1), .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), + .ID_WIDTH(S_ID_WIDTH), .DEST_ENABLE(1), - .DEST_WIDTH(DEST_WIDTH), + .DEST_WIDTH(S_DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH), .REG_TYPE(S_REG_TYPE) @@ -274,8 +278,8 @@ generate .s_axis_tvalid(s_axis_tvalid[m]), .s_axis_tready(s_axis_tready[m]), .s_axis_tlast(s_axis_tlast[m]), - .s_axis_tid(s_axis_tid[m*ID_WIDTH +: ID_WIDTH]), - .s_axis_tdest(s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH]), + .s_axis_tid(s_axis_tid[m*S_ID_WIDTH +: S_ID_WIDTH]), + .s_axis_tdest(s_axis_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH]), .s_axis_tuser(s_axis_tuser[m*USER_WIDTH +: USER_WIDTH]), // AXI output .m_axis_tdata(int_s_axis_tdata[m*DATA_WIDTH +: DATA_WIDTH]), @@ -283,8 +287,8 @@ generate .m_axis_tvalid(int_s_axis_tvalid[m]), .m_axis_tready(int_s_axis_tready[m]), .m_axis_tlast(int_s_axis_tlast[m]), - .m_axis_tid(int_s_axis_tid[m*ID_WIDTH +: ID_WIDTH]), - .m_axis_tdest(int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH]), + .m_axis_tid(int_s_axis_tid[m*S_ID_WIDTH +: S_ID_WIDTH]), + .m_axis_tdest(int_s_axis_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH]), .m_axis_tuser(int_s_axis_tuser[m*USER_WIDTH +: USER_WIDTH]) ); end // s_ifaces @@ -316,20 +320,20 @@ generate ); // mux - wire [DATA_WIDTH-1:0] s_axis_tdata_mux = int_s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH]; - wire [KEEP_WIDTH-1:0] s_axis_tkeep_mux = int_s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH]; - wire s_axis_tvalid_mux = int_axis_tvalid[grant_encoded*M_COUNT+n] && grant_valid; - wire s_axis_tready_mux; - wire s_axis_tlast_mux = int_s_axis_tlast[grant_encoded]; - wire [ID_WIDTH-1:0] s_axis_tid_mux = int_s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH]; - wire [DEST_WIDTH-1:0] s_axis_tdest_mux = int_s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; - wire [USER_WIDTH-1:0] s_axis_tuser_mux = int_s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; + wire [DATA_WIDTH-1:0] m_axis_tdata_mux = int_s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH]; + wire [KEEP_WIDTH-1:0] m_axis_tkeep_mux = int_s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH]; + wire m_axis_tvalid_mux = int_axis_tvalid[grant_encoded*M_COUNT+n] && grant_valid; + wire m_axis_tready_mux; + wire m_axis_tlast_mux = int_s_axis_tlast[grant_encoded]; + wire [M_ID_WIDTH-1:0] m_axis_tid_mux = int_s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH]; + wire [M_DEST_WIDTH-1:0] m_axis_tdest_mux = int_s_axis_tdest[grant_encoded*S_DEST_WIDTH +: S_DEST_WIDTH]; + wire [USER_WIDTH-1:0] m_axis_tuser_mux = int_s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; - assign int_axis_tready[n*S_COUNT +: S_COUNT] = (grant_valid && s_axis_tready_mux) << grant_encoded; + assign int_axis_tready[n*S_COUNT +: S_COUNT] = (grant_valid && m_axis_tready_mux) << grant_encoded; for (m = 0; m < S_COUNT; m = m + 1) begin assign request[m] = int_axis_tvalid[m*M_COUNT+n] && !grant[m]; - assign acknowledge[m] = grant[m] && int_axis_tvalid[m*M_COUNT+n] && s_axis_tlast_mux && s_axis_tready_mux; + assign acknowledge[m] = grant[m] && int_axis_tvalid[m*M_COUNT+n] && m_axis_tlast_mux && m_axis_tready_mux; end // M side register @@ -339,9 +343,9 @@ generate .KEEP_WIDTH(KEEP_WIDTH), .LAST_ENABLE(1), .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), + .ID_WIDTH(M_ID_WIDTH), .DEST_ENABLE(1), - .DEST_WIDTH(DEST_WIDTH), + .DEST_WIDTH(M_DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH), .REG_TYPE(M_REG_TYPE) @@ -350,22 +354,22 @@ generate .clk(clk), .rst(rst), // AXI input - .s_axis_tdata(s_axis_tdata_mux), - .s_axis_tkeep(s_axis_tkeep_mux), - .s_axis_tvalid(s_axis_tvalid_mux), - .s_axis_tready(s_axis_tready_mux), - .s_axis_tlast(s_axis_tlast_mux), - .s_axis_tid(s_axis_tid_mux), - .s_axis_tdest(s_axis_tdest_mux), - .s_axis_tuser(s_axis_tuser_mux), + .s_axis_tdata(m_axis_tdata_mux), + .s_axis_tkeep(m_axis_tkeep_mux), + .s_axis_tvalid(m_axis_tvalid_mux), + .s_axis_tready(m_axis_tready_mux), + .s_axis_tlast(m_axis_tlast_mux), + .s_axis_tid(m_axis_tid_mux), + .s_axis_tdest(m_axis_tdest_mux), + .s_axis_tuser(m_axis_tuser_mux), // AXI output .m_axis_tdata(m_axis_tdata[n*DATA_WIDTH +: DATA_WIDTH]), .m_axis_tkeep(m_axis_tkeep[n*KEEP_WIDTH +: KEEP_WIDTH]), .m_axis_tvalid(m_axis_tvalid[n]), .m_axis_tready(m_axis_tready[n]), .m_axis_tlast(m_axis_tlast[n]), - .m_axis_tid(m_axis_tid[n*ID_WIDTH +: ID_WIDTH]), - .m_axis_tdest(m_axis_tdest[n*DEST_WIDTH +: DEST_WIDTH]), + .m_axis_tid(m_axis_tid[n*M_ID_WIDTH +: M_ID_WIDTH]), + .m_axis_tdest(m_axis_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]), .m_axis_tuser(m_axis_tuser[n*USER_WIDTH +: USER_WIDTH]) ); end // m_ifaces diff --git a/rtl/axis_switch_wrap.py b/rtl/axis_switch_wrap.py index d7d3bbfc6..87efd5494 100755 --- a/rtl/axis_switch_wrap.py +++ b/rtl/axis_switch_wrap.py @@ -84,11 +84,15 @@ module {{name}} # parameter KEEP_WIDTH = (DATA_WIDTH/8), // Propagate tid signal parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, - // tdest signal width + // input tid signal width + parameter S_ID_WIDTH = 8, + // output tid signal width + parameter M_ID_WIDTH = S_ID_WIDTH+{{cm}}, + // output tdest signal width + parameter M_DEST_WIDTH = 1, + // input tdest signal width // must be wide enough to uniquely address outputs - parameter DEST_WIDTH = {{cn}}, + parameter S_DEST_WIDTH = M_DEST_WIDTH+{{cn}}, // Propagate tuser signal parameter USER_ENABLE = 1, // tuser signal width @@ -122,32 +126,32 @@ module {{name}} # * AXI Stream inputs */ {%- for p in range(m) %} - input wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata, - input wire [KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep, - input wire s{{'%02d'%p}}_axis_tvalid, - output wire s{{'%02d'%p}}_axis_tready, - input wire s{{'%02d'%p}}_axis_tlast, - input wire [ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid, - input wire [DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest, - input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser, + input wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata, + input wire [KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep, + input wire s{{'%02d'%p}}_axis_tvalid, + output wire s{{'%02d'%p}}_axis_tready, + input wire s{{'%02d'%p}}_axis_tlast, + input wire [S_ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid, + input wire [S_DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest, + input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser, {% endfor %} /* * AXI Stream outputs */ {%- for p in range(n) %} - output wire [DATA_WIDTH-1:0] m{{'%02d'%p}}_axis_tdata, - output wire [KEEP_WIDTH-1:0] m{{'%02d'%p}}_axis_tkeep, - output wire m{{'%02d'%p}}_axis_tvalid, - input wire m{{'%02d'%p}}_axis_tready, - output wire m{{'%02d'%p}}_axis_tlast, - output wire [ID_WIDTH-1:0] m{{'%02d'%p}}_axis_tid, - output wire [DEST_WIDTH-1:0] m{{'%02d'%p}}_axis_tdest, - output wire [USER_WIDTH-1:0] m{{'%02d'%p}}_axis_tuser{% if not loop.last %},{% endif %} + output wire [DATA_WIDTH-1:0] m{{'%02d'%p}}_axis_tdata, + output wire [KEEP_WIDTH-1:0] m{{'%02d'%p}}_axis_tkeep, + output wire m{{'%02d'%p}}_axis_tvalid, + input wire m{{'%02d'%p}}_axis_tready, + output wire m{{'%02d'%p}}_axis_tlast, + output wire [M_ID_WIDTH-1:0] m{{'%02d'%p}}_axis_tid, + output wire [M_DEST_WIDTH-1:0] m{{'%02d'%p}}_axis_tdest, + output wire [USER_WIDTH-1:0] m{{'%02d'%p}}_axis_tuser{% if not loop.last %},{% endif %} {% endfor -%} ); // parameter sizing helpers -function [DEST_WIDTH-1:0] w_dw(input [DEST_WIDTH-1:0] val); +function [S_DEST_WIDTH-1:0] w_dw(input [S_DEST_WIDTH-1:0] val); w_dw = val; endfunction @@ -162,8 +166,10 @@ axis_switch #( .KEEP_ENABLE(KEEP_ENABLE), .KEEP_WIDTH(KEEP_WIDTH), .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), - .DEST_WIDTH(DEST_WIDTH), + .S_ID_WIDTH(S_ID_WIDTH), + .M_ID_WIDTH(M_ID_WIDTH), + .S_DEST_WIDTH(S_DEST_WIDTH), + .M_DEST_WIDTH(M_DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH), .M_BASE({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_BASE){% if not loop.last %}, {% endif %}{% endfor %} }), diff --git a/tb/axis_arb_mux/Makefile b/tb/axis_arb_mux/Makefile index 3e3dc20a6..7d91e5897 100644 --- a/tb/axis_arb_mux/Makefile +++ b/tb/axis_arb_mux/Makefile @@ -42,7 +42,8 @@ export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 8 +export PARAM_S_ID_WIDTH ?= 8 +export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PARAM_PORTS)-1).bit_length())") export PARAM_DEST_ENABLE ?= 1 export PARAM_DEST_WIDTH ?= 8 export PARAM_USER_ENABLE ?= 1 @@ -58,7 +59,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).M_ID_WIDTH=$(PARAM_M_ID_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).S_ID_WIDTH=$(PARAM_S_ID_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) @@ -78,7 +80,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) + COMPILE_ARGS += -GM_ID_WIDTH=$(PARAM_M_ID_WIDTH) + COMPILE_ARGS += -GS_ID_WIDTH=$(PARAM_S_ID_WIDTH) COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) diff --git a/tb/axis_arb_mux/test_axis_arb_mux.py b/tb/axis_arb_mux/test_axis_arb_mux.py index b67a410f7..d69b0b156 100644 --- a/tb/axis_arb_mux/test_axis_arb_mux.py +++ b/tb/axis_arb_mux/test_axis_arb_mux.py @@ -316,7 +316,8 @@ def test_axis_arb_mux(request, ports, data_width, round_robin): parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 parameters['ID_ENABLE'] = 1 - parameters['ID_WIDTH'] = 8 + parameters['S_ID_WIDTH'] = 8 + parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (ports-1).bit_length() parameters['DEST_ENABLE'] = 1 parameters['DEST_WIDTH'] = 8 parameters['USER_ENABLE'] = 1 diff --git a/tb/axis_demux/Makefile b/tb/axis_demux/Makefile index 8f529ef77..a7e2a1dd3 100644 --- a/tb/axis_demux/Makefile +++ b/tb/axis_demux/Makefile @@ -42,7 +42,8 @@ export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 export PARAM_DEST_ENABLE ?= 1 -export PARAM_DEST_WIDTH ?= 8 +export PARAM_M_DEST_WIDTH ?= 8 +export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PARAM_PORTS)-1).bit_length())") export PARAM_USER_ENABLE ?= 1 export PARAM_USER_WIDTH ?= 1 @@ -55,7 +56,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).DEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).S_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).M_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) @@ -72,7 +74,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) COMPILE_ARGS += -GDEST_ENABLE=$(PARAM_DEST_ENABLE) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) + COMPILE_ARGS += -GS_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) + COMPILE_ARGS += -GM_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) diff --git a/tb/axis_demux/test_axis_demux.py b/tb/axis_demux/test_axis_demux.py index dbd9e6098..1231bf4e7 100644 --- a/tb/axis_demux/test_axis_demux.py +++ b/tb/axis_demux/test_axis_demux.py @@ -183,7 +183,8 @@ def test_axis_demux(request, ports, data_width): parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 - parameters['DEST_WIDTH'] = 8 + parameters['M_DEST_WIDTH'] = 8 + parameters['S_DEST_WIDTH'] = parameters['M_DEST_WIDTH'] + (ports-1).bit_length() parameters['USER_ENABLE'] = 1 parameters['USER_WIDTH'] = 1 diff --git a/tb/axis_ram_switch/Makefile b/tb/axis_ram_switch/Makefile index c5e6aa307..49866a772 100644 --- a/tb/axis_ram_switch/Makefile +++ b/tb/axis_ram_switch/Makefile @@ -50,8 +50,10 @@ export PARAM_M_DATA_WIDTH ?= 8 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 ) export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 16 -export PARAM_DEST_WIDTH ?= 8 +export PARAM_S_ID_WIDTH ?= 16 +export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PARAM_S_COUNT)-1).bit_length())") +export PARAM_M_DEST_WIDTH ?= 8 +export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PARAM_M_COUNT)-1).bit_length())") export PARAM_USER_ENABLE ?= 1 export PARAM_USER_WIDTH ?= 1 export PARAM_USER_BAD_FRAME_VALUE ?= 1 @@ -75,8 +77,10 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).S_ID_WIDTH=$(PARAM_S_ID_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).M_ID_WIDTH=$(PARAM_M_ID_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).S_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).M_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) @@ -104,8 +108,10 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GM_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE) COMPILE_ARGS += -GM_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH) COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) + COMPILE_ARGS += -GS_ID_WIDTH=$(PARAM_S_ID_WIDTH) + COMPILE_ARGS += -GM_ID_WIDTH=$(PARAM_M_ID_WIDTH) + COMPILE_ARGS += -GS_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) + COMPILE_ARGS += -GM_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE) diff --git a/tb/axis_ram_switch/test_axis_ram_switch.py b/tb/axis_ram_switch/test_axis_ram_switch.py index 244a8af1c..16380a391 100644 --- a/tb/axis_ram_switch/test_axis_ram_switch.py +++ b/tb/axis_ram_switch/test_axis_ram_switch.py @@ -335,8 +335,10 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width): parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8) parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8 parameters['ID_ENABLE'] = 1 - parameters['ID_WIDTH'] = 16 - parameters['DEST_WIDTH'] = 8 + parameters['S_ID_WIDTH'] = 16 + parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length() + parameters['M_DEST_WIDTH'] = 8 + parameters['S_DEST_WIDTH'] = parameters['M_DEST_WIDTH'] + (m_count-1).bit_length() parameters['USER_ENABLE'] = 1 parameters['USER_WIDTH'] = 1 parameters['USER_BAD_FRAME_VALUE'] = 1 diff --git a/tb/axis_switch/Makefile b/tb/axis_switch/Makefile index d066c5393..115ea3255 100644 --- a/tb/axis_switch/Makefile +++ b/tb/axis_switch/Makefile @@ -44,8 +44,10 @@ export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) export PARAM_ID_ENABLE ?= 1 -export PARAM_ID_WIDTH ?= 16 -export PARAM_DEST_WIDTH ?= 8 +export PARAM_S_ID_WIDTH ?= 16 +export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PARAM_S_COUNT)-1).bit_length())") +export PARAM_M_DEST_WIDTH ?= 8 +export PARAM_S_DEST_WIDTH ?= $(shell python -c "print($(PARAM_M_DEST_WIDTH) + ($(PARAM_M_COUNT)-1).bit_length())") export PARAM_USER_ENABLE ?= 1 export PARAM_USER_WIDTH ?= 1 export PARAM_S_REG_TYPE ?= 0 @@ -60,8 +62,10 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).S_ID_WIDTH=$(PARAM_S_ID_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).M_ID_WIDTH=$(PARAM_M_ID_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).S_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).M_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH) COMPILE_ARGS += -P $(TOPLEVEL).S_REG_TYPE=$(PARAM_S_REG_TYPE) @@ -80,8 +84,10 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE) COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH) COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE) - COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH) - COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH) + COMPILE_ARGS += -GS_ID_WIDTH=$(PARAM_S_ID_WIDTH) + COMPILE_ARGS += -GM_ID_WIDTH=$(PARAM_M_ID_WIDTH) + COMPILE_ARGS += -GS_DEST_WIDTH=$(PARAM_S_DEST_WIDTH) + COMPILE_ARGS += -GM_DEST_WIDTH=$(PARAM_M_DEST_WIDTH) COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE) COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH) COMPILE_ARGS += -GS_REG_TYPE=$(PARAM_S_REG_TYPE) diff --git a/tb/axis_switch/test_axis_switch.py b/tb/axis_switch/test_axis_switch.py index ef8486426..3097836f3 100644 --- a/tb/axis_switch/test_axis_switch.py +++ b/tb/axis_switch/test_axis_switch.py @@ -328,8 +328,10 @@ def test_axis_switch(request, s_count, m_count, data_width): parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 parameters['ID_ENABLE'] = 1 - parameters['ID_WIDTH'] = 16 - parameters['DEST_WIDTH'] = 8 + parameters['S_ID_WIDTH'] = 16 + parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length() + parameters['M_DEST_WIDTH'] = 8 + parameters['S_DEST_WIDTH'] = parameters['M_DEST_WIDTH'] + (m_count-1).bit_length() parameters['USER_ENABLE'] = 1 parameters['USER_WIDTH'] = 1 parameters['S_REG_TYPE'] = 0