From bc2757dde93a4ee3e6b845bd73675df762d4b2e0 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 31 Jan 2023 16:22:05 -0800 Subject: [PATCH 1/3] Cache clock edge events Signed-off-by: Alex Forencich --- tb/dma_psdp_ram.py | 16 ++++++++++++---- tb/pcie_if.py | 28 +++++++++++++++++++++------- 2 files changed, 33 insertions(+), 11 deletions(-) diff --git a/tb/dma_psdp_ram.py b/tb/dma_psdp_ram.py index de33e0f28..c0199cf95 100644 --- a/tb/dma_psdp_ram.py +++ b/tb/dma_psdp_ram.py @@ -141,8 +141,10 @@ class PsdpRamWrite(Memory): async def _run(self): cmd_ready = 0 + clock_edge_event = RisingEdge(self.clock) + while True: - await RisingEdge(self.clock) + await clock_edge_event wr_done = 0 @@ -191,9 +193,11 @@ class PsdpRamWrite(Memory): self.bus.wr_done.value = wr_done async def _run_pause(self): + clock_edge_event = RisingEdge(self.clock) + for val in self._pause_generator: self.pause = val - await RisingEdge(self.clock) + await clock_edge_event class PsdpRamRead(Memory): @@ -257,8 +261,10 @@ class PsdpRamRead(Memory): resp_valid = 0 resp_data = 0 + clock_edge_event = RisingEdge(self.clock) + while True: - await RisingEdge(self.clock) + await clock_edge_event cmd_valid_sample = self.bus.rd_cmd_valid.value @@ -319,9 +325,11 @@ class PsdpRamRead(Memory): self.bus.rd_resp_valid.value = resp_valid async def _run_pause(self): + clock_edge_event = RisingEdge(self.clock) + for val in self._pause_generator: self.pause = val - await RisingEdge(self.clock) + await clock_edge_event class PsdpRam(Memory): diff --git a/tb/pcie_if.py b/tb/pcie_if.py index 00e8fc4cc..7a6010a54 100644 --- a/tb/pcie_if.py +++ b/tb/pcie_if.py @@ -354,9 +354,11 @@ class PcieIfBase: self.set_pause_generator(None) async def _run_pause(self): + clock_edge_event = RisingEdge(self.clock) + for val in self._pause_generator: self.pause = val - await RisingEdge(self.clock) + await clock_edge_event class PcieIfSource(PcieIfBase): @@ -459,8 +461,10 @@ class PcieIfSource(PcieIfBase): async def _run_source(self): self.active = False + clock_edge_event = RisingEdge(self.clock) + while True: - await RisingEdge(self.clock) + await clock_edge_event # read handshake signals ready_sample = self.bus.ready.value @@ -613,8 +617,10 @@ class PcieIfSink(PcieIfBase): await self.active_event.wait() async def _run_sink(self): + clock_edge_event = RisingEdge(self.clock) + while True: - await RisingEdge(self.clock) + await clock_edge_event # read handshake signals ready_sample = self.bus.ready.value @@ -1189,11 +1195,13 @@ class PcieIfDevice(Device): self.rd_req_tx_seq_num_queue.put_nowait(frame.seq) async def _run_rd_req_tx_seq_num_logic(self): + clock_edge_event = RisingEdge(self.clk) + if self.rd_req_tx_seq_num is not None: width = len(self.rd_req_tx_seq_num) // len(self.rd_req_tx_seq_num_valid) while True: - await RisingEdge(self.clk) + await clock_edge_event if self.rd_req_tx_seq_num is not None: data = 0 @@ -1215,11 +1223,13 @@ class PcieIfDevice(Device): self.wr_req_tx_seq_num_queue.put_nowait(frame.seq) async def _run_wr_req_tx_seq_num_logic(self): + clock_edge_event = RisingEdge(self.clk) + if self.wr_req_tx_seq_num is not None: width = len(self.wr_req_tx_seq_num) // len(self.wr_req_tx_seq_num_valid) while True: - await RisingEdge(self.clk) + await clock_edge_event if self.wr_req_tx_seq_num is not None: data = 0 @@ -1240,8 +1250,10 @@ class PcieIfDevice(Device): await self.send(tlp) async def _run_cfg_status_logic(self): + clock_edge_event = RisingEdge(self.clk) + while True: - await RisingEdge(self.clk) + await clock_edge_event if self.cfg_max_payload is not None: self.cfg_max_payload.value = self.functions[0].pcie_cap.max_payload_size @@ -1251,8 +1263,10 @@ class PcieIfDevice(Device): self.cfg_ext_tag_enable.value = self.functions[0].pcie_cap.extended_tag_field_enable async def _run_fc_logic(self): + clock_edge_event = RisingEdge(self.clk) + while True: - await RisingEdge(self.clk) + await clock_edge_event if self.tx_fc_ph_av is not None: self.tx_fc_ph_av.value = self.upstream_port.fc_state[0].ph.tx_credits_available & 0xff From c6c83a7c68713fe587f2d1e637823fa47c11855e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 17 Feb 2023 15:58:34 -0800 Subject: [PATCH 2/3] Remove recursively-expanded macros for module parameters in makefiles Signed-off-by: Alex Forencich --- example/520N_MX/fpga/tb/fpga_core/Makefile | 16 +++--- .../ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile | 32 ++++++------ .../fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/AU200/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/AU200/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/AU250/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/AU250/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/AU280/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/AU280/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/AU50/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/AU50/fpga_axi/tb/fpga_core/Makefile | 14 ++--- .../DE10_Agilex/fpga/tb/fpga_core/Makefile | 20 +++---- example/ExaNIC_X10/fpga/tb/fpga_core/Makefile | 32 ++++++------ .../ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/ExaNIC_X25/fpga/tb/fpga_core/Makefile | 32 ++++++------ .../ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/S10DX_DK/fpga/tb/fpga_core/Makefile | 20 +++---- example/S10MX_DK/fpga/tb/fpga_core/Makefile | 16 +++--- example/VCU108/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/VCU108/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/VCU118/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/VCU118/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/VCU1525/fpga/tb/fpga_core/Makefile | 32 ++++++------ .../VCU1525/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/ZCU106/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/ZCU106/fpga_axi/tb/fpga_core/Makefile | 14 ++--- example/common/tb/example_core_pcie/Makefile | 38 +++++++------- .../tb/example_core_pcie_ptile/Makefile | 34 ++++++------ .../common/tb/example_core_pcie_s10/Makefile | 32 ++++++------ .../common/tb/example_core_pcie_us/Makefile | 44 ++++++++-------- example/fb2CG/fpga/tb/fpga_core/Makefile | 32 ++++++------ example/fb2CG/fpga_axi/tb/fpga_core/Makefile | 14 ++--- tb/dma_client_axis_sink/Makefile | 36 ++++++------- tb/dma_client_axis_source/Makefile | 36 ++++++------- tb/dma_if_axi/Makefile | 36 ++++++------- tb/dma_if_axi_rd/Makefile | 28 +++++----- tb/dma_if_axi_wr/Makefile | 32 ++++++------ tb/dma_if_pcie_rd/Makefile | 40 +++++++------- tb/dma_if_pcie_us/Makefile | 44 ++++++++-------- tb/dma_if_pcie_us_rd/Makefile | 38 +++++++------- tb/dma_if_pcie_us_wr/Makefile | 34 ++++++------ tb/dma_if_pcie_wr/Makefile | 42 +++++++-------- tb/irq_rate_limit/Makefile | 2 +- tb/pcie_axi_master/Makefile | 20 +++---- tb/pcie_axi_master_rd/Makefile | 20 +++---- tb/pcie_axi_master_wr/Makefile | 18 +++---- tb/pcie_axil_master/Makefile | 16 +++--- tb/pcie_axil_master_minimal/Makefile | 16 +++--- tb/pcie_msix/Makefile | 18 +++---- tb/pcie_ptile_if/Makefile | 28 +++++----- tb/pcie_ptile_if_rx/Makefile | 20 +++---- tb/pcie_ptile_if_tx/Makefile | 18 +++---- tb/pcie_s10_if/Makefile | 30 +++++------ tb/pcie_s10_if_rx/Makefile | 16 +++--- tb/pcie_s10_if_tx/Makefile | 14 ++--- tb/pcie_tlp_demux/Makefile | 18 +++---- tb/pcie_tlp_demux_bar/Makefile | 24 ++++----- tb/pcie_tlp_fifo/Makefile | 12 ++--- tb/pcie_tlp_fifo_mux/Makefile | 20 +++---- tb/pcie_tlp_mux/Makefile | 14 ++--- tb/pcie_us_axi_dma/Makefile | 42 +++++++-------- tb/pcie_us_axi_dma_rd/Makefile | 36 ++++++------- tb/pcie_us_axi_dma_wr/Makefile | 32 ++++++------ tb/pcie_us_axi_master/Makefile | 18 +++---- tb/pcie_us_axi_master_rd/Makefile | 18 +++---- tb/pcie_us_axi_master_wr/Makefile | 16 +++--- tb/pcie_us_axil_master/Makefile | 16 +++--- tb/pcie_us_if/Makefile | 52 +++++++++---------- tb/pcie_us_if_cc/Makefile | 16 +++--- tb/pcie_us_if_cq/Makefile | 16 +++--- tb/pcie_us_if_rc/Makefile | 16 +++--- tb/pcie_us_if_rq/Makefile | 22 ++++---- 72 files changed, 881 insertions(+), 881 deletions(-) diff --git a/example/520N_MX/fpga/tb/fpga_core/Makefile b/example/520N_MX/fpga/tb/fpga_core/Makefile index 2bc1b9daa..b016e53b2 100644 --- a/example/520N_MX/fpga/tb/fpga_core/Makefile +++ b/example/520N_MX/fpga/tb/fpga_core/Makefile @@ -58,14 +58,14 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile +++ b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile +++ b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU200/fpga/tb/fpga_core/Makefile b/example/AU200/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/AU200/fpga/tb/fpga_core/Makefile +++ b/example/AU200/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU200/fpga_axi/tb/fpga_core/Makefile b/example/AU200/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/AU200/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU200/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU250/fpga/tb/fpga_core/Makefile b/example/AU250/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/AU250/fpga/tb/fpga_core/Makefile +++ b/example/AU250/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU250/fpga_axi/tb/fpga_core/Makefile b/example/AU250/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/AU250/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU250/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU280/fpga/tb/fpga_core/Makefile b/example/AU280/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/AU280/fpga/tb/fpga_core/Makefile +++ b/example/AU280/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU280/fpga_axi/tb/fpga_core/Makefile b/example/AU280/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/AU280/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU280/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU50/fpga/tb/fpga_core/Makefile b/example/AU50/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/AU50/fpga/tb/fpga_core/Makefile +++ b/example/AU50/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU50/fpga_axi/tb/fpga_core/Makefile b/example/AU50/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/AU50/fpga_axi/tb/fpga_core/Makefile +++ b/example/AU50/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/DE10_Agilex/fpga/tb/fpga_core/Makefile b/example/DE10_Agilex/fpga/tb/fpga_core/Makefile index 20d9dc13a..851a0d132 100644 --- a/example/DE10_Agilex/fpga/tb/fpga_core/Makefile +++ b/example/DE10_Agilex/fpga/tb/fpga_core/Makefile @@ -59,16 +59,16 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_SEG_HDR_WIDTH ?= 128 -export PARAM_SEG_PRFX_WIDTH ?= 32 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_SEG_HDR_WIDTH := 128 +export PARAM_SEG_PRFX_WIDTH := 32 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile b/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile index 2a79fa692..7dbce3f62 100644 --- a/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile +++ b/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 256 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60 +export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75 +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85 +export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33 +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 4 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile index 34789c492..83abb0568 100644 --- a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile +++ b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 -export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 +export PARAM_AXIS_PCIE_DATA_WIDTH := 256 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60 +export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75 +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85 +export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33 +export PARAM_RQ_SEQ_NUM_WIDTH := 4 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X25/fpga/tb/fpga_core/Makefile b/example/ExaNIC_X25/fpga/tb/fpga_core/Makefile index 8997ffca8..12e50309d 100644 --- a/example/ExaNIC_X25/fpga/tb/fpga_core/Makefile +++ b/example/ExaNIC_X25/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 256 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile index c34cf28f9..8df1050af 100644 --- a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile +++ b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 256 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/S10DX_DK/fpga/tb/fpga_core/Makefile b/example/S10DX_DK/fpga/tb/fpga_core/Makefile index 20d9dc13a..851a0d132 100644 --- a/example/S10DX_DK/fpga/tb/fpga_core/Makefile +++ b/example/S10DX_DK/fpga/tb/fpga_core/Makefile @@ -59,16 +59,16 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_SEG_HDR_WIDTH ?= 128 -export PARAM_SEG_PRFX_WIDTH ?= 32 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_SEG_HDR_WIDTH := 128 +export PARAM_SEG_PRFX_WIDTH := 32 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/S10MX_DK/fpga/tb/fpga_core/Makefile b/example/S10MX_DK/fpga/tb/fpga_core/Makefile index 2bc1b9daa..b016e53b2 100644 --- a/example/S10MX_DK/fpga/tb/fpga_core/Makefile +++ b/example/S10MX_DK/fpga/tb/fpga_core/Makefile @@ -58,14 +58,14 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU108/fpga/tb/fpga_core/Makefile b/example/VCU108/fpga/tb/fpga_core/Makefile index 2a79fa692..7dbce3f62 100644 --- a/example/VCU108/fpga/tb/fpga_core/Makefile +++ b/example/VCU108/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 256 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60 +export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75 +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85 +export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33 +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 4 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU108/fpga_axi/tb/fpga_core/Makefile b/example/VCU108/fpga_axi/tb/fpga_core/Makefile index 34789c492..83abb0568 100644 --- a/example/VCU108/fpga_axi/tb/fpga_core/Makefile +++ b/example/VCU108/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 -export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 +export PARAM_AXIS_PCIE_DATA_WIDTH := 256 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60 +export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75 +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85 +export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33 +export PARAM_RQ_SEQ_NUM_WIDTH := 4 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU118/fpga/tb/fpga_core/Makefile b/example/VCU118/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/VCU118/fpga/tb/fpga_core/Makefile +++ b/example/VCU118/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU118/fpga_axi/tb/fpga_core/Makefile b/example/VCU118/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/VCU118/fpga_axi/tb/fpga_core/Makefile +++ b/example/VCU118/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU1525/fpga/tb/fpga_core/Makefile b/example/VCU1525/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/VCU1525/fpga/tb/fpga_core/Makefile +++ b/example/VCU1525/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU1525/fpga_axi/tb/fpga_core/Makefile b/example/VCU1525/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/VCU1525/fpga_axi/tb/fpga_core/Makefile +++ b/example/VCU1525/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ZCU106/fpga/tb/fpga_core/Makefile b/example/ZCU106/fpga/tb/fpga_core/Makefile index 3261dc678..14def6a10 100644 --- a/example/ZCU106/fpga/tb/fpga_core/Makefile +++ b/example/ZCU106/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 128 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 128 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ZCU106/fpga_axi/tb/fpga_core/Makefile b/example/ZCU106/fpga_axi/tb/fpga_core/Makefile index 255624fd4..6d78bf572 100644 --- a/example/ZCU106/fpga_axi/tb/fpga_core/Makefile +++ b/example/ZCU106/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 128 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 128 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/common/tb/example_core_pcie/Makefile b/example/common/tb/example_core_pcie/Makefile index aff109460..2c6986bac 100644 --- a/example/common/tb/example_core_pcie/Makefile +++ b/example/common/tb/example_core_pcie/Makefile @@ -48,25 +48,25 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 512 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_TX_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 256 -export PARAM_IMM_ENABLE ?= 1 -export PARAM_IMM_WIDTH ?= 32 -export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 -export PARAM_CHECK_BUS_NUMBER ?= 1 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_TLP_DATA_WIDTH := 512 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_COUNT := 1 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_TX_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 256 +export PARAM_IMM_ENABLE := 1 +export PARAM_IMM_WIDTH := 32 +export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 +export PARAM_CHECK_BUS_NUMBER := 1 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/common/tb/example_core_pcie_ptile/Makefile b/example/common/tb/example_core_pcie_ptile/Makefile index 514e9d63f..21d5fe0c3 100644 --- a/example/common/tb/example_core_pcie_ptile/Makefile +++ b/example/common/tb/example_core_pcie_ptile/Makefile @@ -58,23 +58,23 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_SEG_HDR_WIDTH ?= 128 -export PARAM_SEG_PRFX_WIDTH ?= 32 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_TX_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 256 -export PARAM_IMM_ENABLE ?= 1 -export PARAM_IMM_WIDTH ?= 32 -export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_SEG_HDR_WIDTH := 128 +export PARAM_SEG_PRFX_WIDTH := 32 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_TX_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 256 +export PARAM_IMM_ENABLE := 1 +export PARAM_IMM_WIDTH := 32 +export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/common/tb/example_core_pcie_s10/Makefile b/example/common/tb/example_core_pcie_s10/Makefile index 367cc8338..82abc6534 100644 --- a/example/common/tb/example_core_pcie_s10/Makefile +++ b/example/common/tb/example_core_pcie_s10/Makefile @@ -57,22 +57,22 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v # module parameters -export PARAM_SEG_COUNT ?= 1 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_TX_SEQ_NUM_ENABLE ?= 1 -export PARAM_L_TILE ?= 0 -export PARAM_PCIE_TAG_COUNT ?= 256 -export PARAM_IMM_ENABLE ?= 1 -export PARAM_IMM_WIDTH ?= 32 -export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_SEG_COUNT := 1 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_TX_SEQ_NUM_ENABLE := 1 +export PARAM_L_TILE := 0 +export PARAM_PCIE_TAG_COUNT := 256 +export PARAM_IMM_ENABLE := 1 +export PARAM_IMM_WIDTH := 32 +export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/common/tb/example_core_pcie_us/Makefile b/example/common/tb/example_core_pcie_us/Makefile index b1e686cbb..fe26130c3 100644 --- a/example/common/tb/example_core_pcie_us/Makefile +++ b/example/common/tb/example_core_pcie_us/Makefile @@ -57,28 +57,28 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 256 -export PARAM_IMM_ENABLE ?= 1 -export PARAM_IMM_WIDTH ?= 32 -export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 256 +export PARAM_IMM_ENABLE := 1 +export PARAM_IMM_WIDTH := 32 +export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/fb2CG/fpga/tb/fpga_core/Makefile b/example/fb2CG/fpga/tb/fpga_core/Makefile index b825a9cbe..f8390a004 100644 --- a/example/fb2CG/fpga/tb/fpga_core/Makefile +++ b/example/fb2CG/fpga/tb/fpga_core/Makefile @@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_PCIE_TAG_COUNT ?= 64 -export PARAM_BAR0_APERTURE ?= 24 -export PARAM_BAR2_APERTURE ?= 24 -export PARAM_BAR4_APERTURE ?= 16 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_PCIE_TAG_COUNT := 64 +export PARAM_BAR0_APERTURE := 24 +export PARAM_BAR2_APERTURE := 24 +export PARAM_BAR4_APERTURE := 16 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/fb2CG/fpga_axi/tb/fpga_core/Makefile b/example/fb2CG/fpga_axi/tb/fpga_core/Makefile index d099c30a3..e730af529 100644 --- a/example/fb2CG/fpga_axi/tb/fpga_core/Makefile +++ b/example/fb2CG/fpga_axi/tb/fpga_core/Makefile @@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RQ_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_client_axis_sink/Makefile b/tb/dma_client_axis_sink/Makefile index 6594cff8b..08d029751 100644 --- a/tb/dma_client_axis_sink/Makefile +++ b/tb/dma_client_axis_sink/Makefile @@ -32,24 +32,24 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_RAM_DATA_WIDTH ?= 128 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") -export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_AXIS_DATA_WIDTH ?= 64 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_AXIS_LAST_ENABLE ?= 1 -export PARAM_AXIS_ID_ENABLE ?= 1 -export PARAM_AXIS_ID_WIDTH ?= 8 -export PARAM_AXIS_DEST_ENABLE ?= 1 -export PARAM_AXIS_DEST_WIDTH ?= 8 -export PARAM_AXIS_USER_ENABLE ?= 1 -export PARAM_AXIS_USER_WIDTH ?= 1 -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 +export PARAM_RAM_DATA_WIDTH := 128 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") +export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) +export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_AXIS_DATA_WIDTH := 64 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_AXIS_LAST_ENABLE := 1 +export PARAM_AXIS_ID_ENABLE := 1 +export PARAM_AXIS_ID_WIDTH := 8 +export PARAM_AXIS_DEST_ENABLE := 1 +export PARAM_AXIS_DEST_WIDTH := 8 +export PARAM_AXIS_USER_ENABLE := 1 +export PARAM_AXIS_USER_WIDTH := 1 +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_client_axis_source/Makefile b/tb/dma_client_axis_source/Makefile index 459ae62e6..de1240192 100644 --- a/tb/dma_client_axis_source/Makefile +++ b/tb/dma_client_axis_source/Makefile @@ -32,24 +32,24 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_RAM_DATA_WIDTH ?= 128 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") -export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_AXIS_DATA_WIDTH ?= 64 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_AXIS_LAST_ENABLE ?= 1 -export PARAM_AXIS_ID_ENABLE ?= 1 -export PARAM_AXIS_ID_WIDTH ?= 8 -export PARAM_AXIS_DEST_ENABLE ?= 1 -export PARAM_AXIS_DEST_WIDTH ?= 8 -export PARAM_AXIS_USER_ENABLE ?= 1 -export PARAM_AXIS_USER_WIDTH ?= 1 -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 +export PARAM_RAM_DATA_WIDTH := 128 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") +export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) +export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_AXIS_DATA_WIDTH := 64 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_AXIS_LAST_ENABLE := 1 +export PARAM_AXIS_ID_ENABLE := 1 +export PARAM_AXIS_ID_WIDTH := 8 +export PARAM_AXIS_DEST_ENABLE := 1 +export PARAM_AXIS_DEST_WIDTH := 8 +export PARAM_AXIS_USER_ENABLE := 1 +export PARAM_AXIS_USER_WIDTH := 1 +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_axi/Makefile b/tb/dma_if_axi/Makefile index e239c58f7..b4816223d 100644 --- a/tb/dma_if_axi/Makefile +++ b/tb/dma_if_axi/Makefile @@ -34,24 +34,24 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v # module parameters -export PARAM_AXI_DATA_WIDTH ?= 64 -export PARAM_AXI_ADDR_WIDTH ?= 16 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_RAM_SEG_COUNT ?= 2 -export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_IMM_ENABLE ?= 1 -export PARAM_IMM_WIDTH ?= $(PARAM_AXI_DATA_WIDTH) -export PARAM_LEN_WIDTH ?= 16 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_READ_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") -export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") -export PARAM_READ_USE_AXI_ID ?= 0 -export PARAM_WRITE_USE_AXI_ID ?= 1 +export PARAM_AXI_DATA_WIDTH := 64 +export PARAM_AXI_ADDR_WIDTH := 16 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_RAM_SEG_COUNT := 2 +export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) +export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_IMM_ENABLE := 1 +export PARAM_IMM_WIDTH := $(PARAM_AXI_DATA_WIDTH) +export PARAM_LEN_WIDTH := 16 +export PARAM_TAG_WIDTH := 8 +export PARAM_READ_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") +export PARAM_WRITE_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") +export PARAM_READ_USE_AXI_ID := 0 +export PARAM_WRITE_USE_AXI_ID := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_axi_rd/Makefile b/tb/dma_if_axi_rd/Makefile index eb6757c33..acb4905fa 100644 --- a/tb/dma_if_axi_rd/Makefile +++ b/tb/dma_if_axi_rd/Makefile @@ -32,20 +32,20 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXI_DATA_WIDTH ?= 64 -export PARAM_AXI_ADDR_WIDTH ?= 16 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_RAM_SEG_COUNT ?= 2 -export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_LEN_WIDTH ?= 16 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") -export PARAM_USE_AXI_ID ?= 0 +export PARAM_AXI_DATA_WIDTH := 64 +export PARAM_AXI_ADDR_WIDTH := 16 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_RAM_SEG_COUNT := 2 +export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) +export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_LEN_WIDTH := 16 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") +export PARAM_USE_AXI_ID := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_axi_wr/Makefile b/tb/dma_if_axi_wr/Makefile index 0eddba394..18792f69a 100644 --- a/tb/dma_if_axi_wr/Makefile +++ b/tb/dma_if_axi_wr/Makefile @@ -32,22 +32,22 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXI_DATA_WIDTH ?= 64 -export PARAM_AXI_ADDR_WIDTH ?= 16 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_RAM_SEG_COUNT ?= 2 -export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_IMM_ENABLE ?= 1 -export PARAM_IMM_WIDTH ?= $(PARAM_AXI_DATA_WIDTH) -export PARAM_LEN_WIDTH ?= 16 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") -export PARAM_USE_AXI_ID ?= 1 +export PARAM_AXI_DATA_WIDTH := 64 +export PARAM_AXI_ADDR_WIDTH := 16 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_RAM_SEG_COUNT := 2 +export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) +export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_IMM_ENABLE := 1 +export PARAM_IMM_WIDTH := $(PARAM_AXI_DATA_WIDTH) +export PARAM_LEN_WIDTH := 16 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") +export PARAM_USE_AXI_ID := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_pcie_rd/Makefile b/tb/dma_if_pcie_rd/Makefile index 506e506fa..aaad83d4a 100644 --- a/tb/dma_if_pcie_rd/Makefile +++ b/tb/dma_if_pcie_rd/Makefile @@ -32,26 +32,26 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_TX_SEQ_NUM_ENABLE ?= 1 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) -export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_PCIE_TAG_COUNT ?= 256 -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 -export PARAM_CHECK_BUS_NUMBER ?= 1 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_COUNT := 1 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_TX_SEQ_NUM_ENABLE := 1 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_RAM_SEG_COUNT := $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) +export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) +export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_PCIE_TAG_COUNT := 256 +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 +export PARAM_CHECK_BUS_NUMBER := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_pcie_us/Makefile b/tb/dma_if_pcie_us/Makefile index 6031b63b7..3579dfd79 100644 --- a/tb/dma_if_pcie_us/Makefile +++ b/tb/dma_if_pcie_us/Makefile @@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") -export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_READ_TX_FC_ENABLE ?= 1 -export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_WRITE_TX_FC_ENABLE ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") +export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) +export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_READ_TX_FC_ENABLE := 1 +export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_WRITE_TX_FC_ENABLE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_pcie_us_rd/Makefile b/tb/dma_if_pcie_us_rd/Makefile index 6d3ddd8b7..19448a498 100644 --- a/tb/dma_if_pcie_us_rd/Makefile +++ b/tb/dma_if_pcie_us_rd/Makefile @@ -32,25 +32,25 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") -export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TX_FC_ENABLE ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") +export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) +export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TX_FC_ENABLE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_pcie_us_wr/Makefile b/tb/dma_if_pcie_us_wr/Makefile index ec0988213..b1dd9253a 100644 --- a/tb/dma_if_pcie_us_wr/Makefile +++ b/tb/dma_if_pcie_us_wr/Makefile @@ -32,23 +32,23 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") -export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) -export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TX_FC_ENABLE ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") +export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) +export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TX_FC_ENABLE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/dma_if_pcie_wr/Makefile b/tb/dma_if_pcie_wr/Makefile index 15c04e40f..86d575a6c 100644 --- a/tb/dma_if_pcie_wr/Makefile +++ b/tb/dma_if_pcie_wr/Makefile @@ -32,27 +32,27 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_TX_SEQ_NUM_ENABLE ?= 1 -export PARAM_RAM_SEL_WIDTH ?= 2 -export PARAM_RAM_ADDR_WIDTH ?= 16 -export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) -export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) -export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) -export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_IMM_ENABLE ?= 1 -export PARAM_IMM_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) ) -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_COUNT := 1 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_TX_SEQ_NUM_ENABLE := 1 +export PARAM_RAM_SEL_WIDTH := 2 +export PARAM_RAM_ADDR_WIDTH := 16 +export PARAM_RAM_SEG_COUNT := $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) +export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) +export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) +export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_IMM_ENABLE := 1 +export PARAM_IMM_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) ) +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/irq_rate_limit/Makefile b/tb/irq_rate_limit/Makefile index 02c2a97c5..69efa53be 100644 --- a/tb/irq_rate_limit/Makefile +++ b/tb/irq_rate_limit/Makefile @@ -32,7 +32,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES = ../../rtl/$(DUT).v # module parameters -export PARAM_IRQ_INDEX_WIDTH ?= 11 +export PARAM_IRQ_INDEX_WIDTH := 11 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_axi_master/Makefile b/tb/pcie_axi_master/Makefile index 93af99288..4263ae7d5 100644 --- a/tb/pcie_axi_master/Makefile +++ b/tb/pcie_axi_master/Makefile @@ -37,16 +37,16 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_demux.v VERILOG_SOURCES += ../../rtl/pulse_merge.v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 64 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_AXI_DATA_WIDTH := $(PARAM_TLP_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 64 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_axi_master_rd/Makefile b/tb/pcie_axi_master_rd/Makefile index b8540619d..9838d53b5 100644 --- a/tb/pcie_axi_master_rd/Makefile +++ b/tb/pcie_axi_master_rd/Makefile @@ -33,16 +33,16 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 64 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_AXI_DATA_WIDTH := $(PARAM_TLP_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 64 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_axi_master_wr/Makefile b/tb/pcie_axi_master_wr/Makefile index ae6df3c31..564c22790 100644 --- a/tb/pcie_axi_master_wr/Makefile +++ b/tb/pcie_axi_master_wr/Makefile @@ -33,15 +33,15 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 64 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_AXI_DATA_WIDTH := $(PARAM_TLP_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 64 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_axil_master/Makefile b/tb/pcie_axil_master/Makefile index 466cef93f..9bdbe6ff2 100644 --- a/tb/pcie_axil_master/Makefile +++ b/tb/pcie_axil_master/Makefile @@ -33,14 +33,14 @@ MODULE = test_$(DUT) VERILOG_SOURCES = ../../rtl/$(DUT).v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_AXIL_DATA_WIDTH ?= 32 -export PARAM_AXIL_ADDR_WIDTH ?= 64 -export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_AXIL_DATA_WIDTH := 32 +export PARAM_AXIL_ADDR_WIDTH := 64 +export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_axil_master_minimal/Makefile b/tb/pcie_axil_master_minimal/Makefile index 72fb1a671..95bd32429 100644 --- a/tb/pcie_axil_master_minimal/Makefile +++ b/tb/pcie_axil_master_minimal/Makefile @@ -33,14 +33,14 @@ MODULE = test_$(DUT) VERILOG_SOURCES = ../../rtl/$(DUT).v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_AXIL_DATA_WIDTH ?= 32 -export PARAM_AXIL_ADDR_WIDTH ?= 64 -export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_AXIL_DATA_WIDTH := 32 +export PARAM_AXIL_ADDR_WIDTH := 64 +export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_msix/Makefile b/tb/pcie_msix/Makefile index 4c8186547..d94fab9c5 100644 --- a/tb/pcie_msix/Makefile +++ b/tb/pcie_msix/Makefile @@ -32,15 +32,15 @@ MODULE = test_$(DUT) VERILOG_SOURCES = ../../rtl/$(DUT).v # module parameters -export PARAM_IRQ_INDEX_WIDTH ?= 11 -export PARAM_AXIL_DATA_WIDTH ?= 32 -export PARAM_AXIL_ADDR_WIDTH ?= $(shell expr $(PARAM_IRQ_INDEX_WIDTH) + 5 ) -export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 +export PARAM_IRQ_INDEX_WIDTH := 11 +export PARAM_AXIL_DATA_WIDTH := 32 +export PARAM_AXIL_ADDR_WIDTH := $(shell expr $(PARAM_IRQ_INDEX_WIDTH) + 5 ) +export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TLP_FORCE_64_BIT_ADDR := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_ptile_if/Makefile b/tb/pcie_ptile_if/Makefile index a6f377f8a..dc935982f 100644 --- a/tb/pcie_ptile_if/Makefile +++ b/tb/pcie_ptile_if/Makefile @@ -41,20 +41,20 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_SEG_HDR_WIDTH ?= 128 -export PARAM_SEG_PRFX_WIDTH ?= 32 -export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_PF_COUNT ?= 1 -export PARAM_VF_COUNT ?= 0 -export PARAM_F_COUNT ?= $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) -export PARAM_IO_BAR_INDEX ?= 3 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_SEG_HDR_WIDTH := 128 +export PARAM_SEG_PRFX_WIDTH := 32 +export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_PF_COUNT := 1 +export PARAM_VF_COUNT := 0 +export PARAM_F_COUNT := $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) +export PARAM_IO_BAR_INDEX := 3 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_ptile_if_rx/Makefile b/tb/pcie_ptile_if_rx/Makefile index 66f38bd1b..5149916b5 100644 --- a/tb/pcie_ptile_if_rx/Makefile +++ b/tb/pcie_ptile_if_rx/Makefile @@ -35,16 +35,16 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_SEG_HDR_WIDTH ?= 128 -export PARAM_SEG_PRFX_WIDTH ?= 32 -export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_IO_BAR_INDEX ?= 3 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_SEG_HDR_WIDTH := 128 +export PARAM_SEG_PRFX_WIDTH := 32 +export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_IO_BAR_INDEX := 3 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_ptile_if_tx/Makefile b/tb/pcie_ptile_if_tx/Makefile index 9c1d22817..701d9b41a 100644 --- a/tb/pcie_ptile_if_tx/Makefile +++ b/tb/pcie_ptile_if_tx/Makefile @@ -36,15 +36,15 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_HDR_WIDTH ?= 128 -export PARAM_SEG_PRFX_WIDTH ?= 32 -export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_HDR_WIDTH := 128 +export PARAM_SEG_PRFX_WIDTH := 32 +export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_s10_if/Makefile b/tb/pcie_s10_if/Makefile index 65990edb8..d7d1fe444 100644 --- a/tb/pcie_s10_if/Makefile +++ b/tb/pcie_s10_if/Makefile @@ -43,21 +43,21 @@ VERILOG_SOURCES += ../../rtl/arbiter.v VERILOG_SOURCES += ../../rtl/priority_encoder.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 -export PARAM_L_TILE ?= 0 -export PARAM_PF_COUNT ?= 1 -export PARAM_VF_COUNT ?= 0 -export PARAM_F_COUNT ?= $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) -export PARAM_IO_BAR_INDEX ?= 3 -export PARAM_MSI_ENABLE ?= 1 -export PARAM_MSI_COUNT ?= 32 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_WIDTH := 6 +export PARAM_L_TILE := 0 +export PARAM_PF_COUNT := 1 +export PARAM_VF_COUNT := 0 +export PARAM_F_COUNT := $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) +export PARAM_IO_BAR_INDEX := 3 +export PARAM_MSI_ENABLE := 1 +export PARAM_MSI_COUNT := 32 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_s10_if_rx/Makefile b/tb/pcie_s10_if_rx/Makefile index c482190cf..f7f905399 100644 --- a/tb/pcie_s10_if_rx/Makefile +++ b/tb/pcie_s10_if_rx/Makefile @@ -35,14 +35,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) -export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_IO_BAR_INDEX ?= 3 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) +export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_IO_BAR_INDEX := 3 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_s10_if_tx/Makefile b/tb/pcie_s10_if_tx/Makefile index 508e7cf50..5b1ac3e41 100644 --- a/tb/pcie_s10_if_tx/Makefile +++ b/tb/pcie_s10_if_tx/Makefile @@ -35,13 +35,13 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v # module parameters -export PARAM_SEG_COUNT ?= 2 -export PARAM_SEG_DATA_WIDTH ?= 256 -export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_WIDTH ?= 6 +export PARAM_SEG_COUNT := 2 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_WIDTH := 6 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_tlp_demux/Makefile b/tb/pcie_tlp_demux/Makefile index 22f9fdb1b..2fac725ce 100644 --- a/tb/pcie_tlp_demux/Makefile +++ b/tb/pcie_tlp_demux/Makefile @@ -38,15 +38,15 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_SEQ_NUM_WIDTH ?= 6 -export PARAM_IN_TLP_SEG_COUNT ?= 1 -export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) -export PARAM_FIFO_ENABLE ?= 1 -export PARAM_FIFO_DEPTH ?= 4096 -export PARAM_FIFO_WATERMARK ?= $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_SEQ_NUM_WIDTH := 6 +export PARAM_IN_TLP_SEG_COUNT := 1 +export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT) +export PARAM_FIFO_ENABLE := 1 +export PARAM_FIFO_DEPTH := 4096 +export PARAM_FIFO_WATERMARK := $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_tlp_demux_bar/Makefile b/tb/pcie_tlp_demux_bar/Makefile index e1f23ef17..6c5bd8943 100644 --- a/tb/pcie_tlp_demux_bar/Makefile +++ b/tb/pcie_tlp_demux_bar/Makefile @@ -39,18 +39,18 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_SEQ_NUM_WIDTH ?= 6 -export PARAM_IN_TLP_SEG_COUNT ?= 1 -export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) -export PARAM_FIFO_ENABLE ?= 1 -export PARAM_FIFO_DEPTH ?= 4096 -export PARAM_FIFO_WATERMARK ?= $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) -export PARAM_BAR_BASE ?= 0 -export PARAM_BAR_STRIDE ?= 1 -export PARAM_BAR_IDS ?= 0 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_SEQ_NUM_WIDTH := 6 +export PARAM_IN_TLP_SEG_COUNT := 1 +export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT) +export PARAM_FIFO_ENABLE := 1 +export PARAM_FIFO_DEPTH := 4096 +export PARAM_FIFO_WATERMARK := $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) +export PARAM_BAR_BASE := 0 +export PARAM_BAR_STRIDE := 1 +export PARAM_BAR_IDS := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_tlp_fifo/Makefile b/tb/pcie_tlp_fifo/Makefile index 848a4be87..ade14e424 100644 --- a/tb/pcie_tlp_fifo/Makefile +++ b/tb/pcie_tlp_fifo/Makefile @@ -33,12 +33,12 @@ VERILOG_SOURCES = ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_DEPTH ?= 4096 -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_IN_TLP_SEG_COUNT ?= 1 -export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) +export PARAM_DEPTH := 4096 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_IN_TLP_SEG_COUNT := 1 +export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_tlp_fifo_mux/Makefile b/tb/pcie_tlp_fifo_mux/Makefile index a3491acb4..79a437196 100644 --- a/tb/pcie_tlp_fifo_mux/Makefile +++ b/tb/pcie_tlp_fifo_mux/Makefile @@ -38,16 +38,16 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fc_count.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_SEQ_NUM_WIDTH ?= 6 -export PARAM_IN_TLP_SEG_COUNT ?= 1 -export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) -export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0 -export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 -export PARAM_FIFO_DEPTH ?= 4096 -export PARAM_FIFO_WATERMARK ?= $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_SEQ_NUM_WIDTH := 6 +export PARAM_IN_TLP_SEG_COUNT := 1 +export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT) +export PARAM_ARB_TYPE_ROUND_ROBIN := 0 +export PARAM_ARB_LSB_HIGH_PRIORITY := 1 +export PARAM_FIFO_DEPTH := 4096 +export PARAM_FIFO_WATERMARK := $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_tlp_mux/Makefile b/tb/pcie_tlp_mux/Makefile index 0485b5b49..5980ab94d 100644 --- a/tb/pcie_tlp_mux/Makefile +++ b/tb/pcie_tlp_mux/Makefile @@ -36,13 +36,13 @@ VERILOG_SOURCES += $(WRAPPER).v VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_TLP_DATA_WIDTH ?= 64 -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_SEQ_NUM_WIDTH ?= 6 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0 -export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 +export PARAM_TLP_DATA_WIDTH := 64 +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_SEQ_NUM_WIDTH := 6 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_ARB_TYPE_ROUND_ROBIN := 0 +export PARAM_ARB_LSB_HIGH_PRIORITY := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_axi_dma/Makefile b/tb/pcie_us_axi_dma/Makefile index ebc9beda9..7cce24d09 100644 --- a/tb/pcie_us_axi_dma/Makefile +++ b/tb/pcie_us_axi_dma/Makefile @@ -34,27 +34,27 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 24 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_READ_TX_FC_ENABLE ?= 1 -export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_WRITE_TX_FC_ENABLE ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 24 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_READ_TX_FC_ENABLE := 1 +export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_WRITE_TX_FC_ENABLE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_axi_dma_rd/Makefile b/tb/pcie_us_axi_dma_rd/Makefile index cf49a5079..a5b4e5527 100644 --- a/tb/pcie_us_axi_dma_rd/Makefile +++ b/tb/pcie_us_axi_dma_rd/Makefile @@ -32,24 +32,24 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 24 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) -export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TX_FC_ENABLE ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 24 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT) +export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TX_FC_ENABLE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_axi_dma_wr/Makefile b/tb/pcie_us_axi_dma_wr/Makefile index 27f0f00e5..b4a34b509 100644 --- a/tb/pcie_us_axi_dma_wr/Makefile +++ b/tb/pcie_us_axi_dma_wr/Makefile @@ -32,22 +32,22 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 24 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 -export PARAM_PCIE_ADDR_WIDTH ?= 64 -export PARAM_LEN_WIDTH ?= 20 -export PARAM_TAG_WIDTH ?= 8 -export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) -export PARAM_TX_FC_ENABLE ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_RQ_SEQ_NUM_ENABLE := 1 +export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 24 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 +export PARAM_PCIE_ADDR_WIDTH := 64 +export PARAM_LEN_WIDTH := 20 +export PARAM_TAG_WIDTH := 8 +export PARAM_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) +export PARAM_TX_FC_ENABLE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_axi_master/Makefile b/tb/pcie_us_axi_master/Makefile index 33e47f09c..2d3c3eacb 100644 --- a/tb/pcie_us_axi_master/Makefile +++ b/tb/pcie_us_axi_master/Makefile @@ -37,15 +37,15 @@ VERILOG_SOURCES += ../../rtl/pcie_us_axis_cq_demux.v VERILOG_SOURCES += ../../rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 64 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 64 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_axi_master_rd/Makefile b/tb/pcie_us_axi_master_rd/Makefile index e1e26b18a..74fa2c2c2 100644 --- a/tb/pcie_us_axi_master_rd/Makefile +++ b/tb/pcie_us_axi_master_rd/Makefile @@ -33,15 +33,15 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 64 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 64 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_axi_master_wr/Makefile b/tb/pcie_us_axi_master_wr/Makefile index 8a3199bc0..14ec363c9 100644 --- a/tb/pcie_us_axi_master_wr/Makefile +++ b/tb/pcie_us_axi_master_wr/Makefile @@ -33,14 +33,14 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_AXI_ADDR_WIDTH ?= 64 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_AXI_ID_WIDTH ?= 8 -export PARAM_AXI_MAX_BURST_LEN ?= 256 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_AXI_ADDR_WIDTH := 64 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_AXI_ID_WIDTH := 8 +export PARAM_AXI_MAX_BURST_LEN := 256 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_axil_master/Makefile b/tb/pcie_us_axil_master/Makefile index 466339c4e..8f71f1763 100644 --- a/tb/pcie_us_axil_master/Makefile +++ b/tb/pcie_us_axil_master/Makefile @@ -33,14 +33,14 @@ MODULE = test_$(DUT) VERILOG_SOURCES = ../../rtl/$(DUT).v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_AXI_DATA_WIDTH ?= 32 -export PARAM_AXI_ADDR_WIDTH ?= 64 -export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PARITY ?= 0 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_AXI_DATA_WIDTH := 32 +export PARAM_AXI_ADDR_WIDTH := 64 +export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PARITY := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_if/Makefile b/tb/pcie_us_if/Makefile index 3dceac9c6..31521f7c7 100644 --- a/tb/pcie_us_if/Makefile +++ b/tb/pcie_us_if/Makefile @@ -42,32 +42,32 @@ VERILOG_SOURCES += ../../rtl/arbiter.v VERILOG_SOURCES += ../../rtl/priority_encoder.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_COUNT ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2) -export PARAM_TX_SEQ_NUM_WIDTH ?= $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 ) -export PARAM_PF_COUNT ?= 1 -export PARAM_VF_COUNT ?= 0 -export PARAM_F_COUNT ?= $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) -export PARAM_READ_EXT_TAG_ENABLE ?= 1 -export PARAM_READ_MAX_READ_REQ_SIZE ?= 1 -export PARAM_READ_MAX_PAYLOAD_SIZE ?= 1 -export PARAM_MSIX_ENABLE ?= 1 -export PARAM_MSI_ENABLE ?= 1 -export PARAM_MSI_COUNT ?= 32 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_COUNT := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2) +export PARAM_TX_SEQ_NUM_WIDTH := $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 ) +export PARAM_PF_COUNT := 1 +export PARAM_VF_COUNT := 0 +export PARAM_F_COUNT := $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) +export PARAM_READ_EXT_TAG_ENABLE := 1 +export PARAM_READ_MAX_READ_REQ_SIZE := 1 +export PARAM_READ_MAX_PAYLOAD_SIZE := 1 +export PARAM_MSIX_ENABLE := 1 +export PARAM_MSI_ENABLE := 1 +export PARAM_MSI_COUNT := 32 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_if_cc/Makefile b/tb/pcie_us_if_cc/Makefile index 19219cac5..c19b00af4 100644 --- a/tb/pcie_us_if_cc/Makefile +++ b/tb/pcie_us_if_cc/Makefile @@ -34,14 +34,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) -export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) -export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) +export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) +export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_if_cq/Makefile b/tb/pcie_us_if_cq/Makefile index 77a987056..2cedd2765 100644 --- a/tb/pcie_us_if_cq/Makefile +++ b/tb/pcie_us_if_cq/Makefile @@ -34,14 +34,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) -export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) -export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) +export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) +export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_if_rc/Makefile b/tb/pcie_us_if_rc/Makefile index 61ecf35f7..e8e93790d 100644 --- a/tb/pcie_us_if_rc/Makefile +++ b/tb/pcie_us_if_rc/Makefile @@ -34,14 +34,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) -export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1) -export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) +export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1) +export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/pcie_us_if_rq/Makefile b/tb/pcie_us_if_rq/Makefile index 80f0780d6..2f7a2d915 100644 --- a/tb/pcie_us_if_rq/Makefile +++ b/tb/pcie_us_if_rq/Makefile @@ -34,17 +34,17 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 -export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) -export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) -export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) -export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) -export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) -export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) -export PARAM_TLP_HDR_WIDTH ?= 128 -export PARAM_TLP_SEG_COUNT ?= 1 -export PARAM_TX_SEQ_NUM_COUNT ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2) -export PARAM_TX_SEQ_NUM_WIDTH ?= $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 ) +export PARAM_AXIS_PCIE_DATA_WIDTH := 64 +export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) +export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) +export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) +export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) +export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH) +export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) +export PARAM_TLP_HDR_WIDTH := 128 +export PARAM_TLP_SEG_COUNT := 1 +export PARAM_TX_SEQ_NUM_COUNT := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2) +export PARAM_TX_SEQ_NUM_WIDTH := $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 ) ifeq ($(SIM), icarus) PLUSARGS += -fst From 1ad973f7a72bdf54ce0a505036367398e6450c40 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 17 Feb 2023 16:05:56 -0800 Subject: [PATCH 3/3] Update ubuntu version in CI Signed-off-by: Alex Forencich --- .github/workflows/regression-tests.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/regression-tests.yml b/.github/workflows/regression-tests.yml index dc6a60e32..6392e31dd 100644 --- a/.github/workflows/regression-tests.yml +++ b/.github/workflows/regression-tests.yml @@ -5,7 +5,7 @@ on: [push, pull_request] jobs: build: name: Python ${{ matrix.python-version }} (${{ matrix.group }}/20) - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 strategy: matrix: