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merged changes in pcie

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This commit is contained in:
Alex Forencich 2023-02-17 16:20:00 -08:00
commit 24c74b3003
75 changed files with 915 additions and 893 deletions
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2
fpga/lib/pcie/.github/workflows/regression-tests.yml vendored
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@ -5,7 +5,7 @@ on: [push, pull_request]
jobs: jobs:
build: build:
name: Python ${{ matrix.python-version }} (${{ matrix.group }}/20) name: Python ${{ matrix.python-version }} (${{ matrix.group }}/20)
runs-on: ubuntu-20.04 runs-on: ubuntu-22.04
strategy: strategy:
matrix: matrix:

16
fpga/lib/pcie/example/520N_MX/fpga/tb/fpga_core/Makefile
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@ -58,14 +58,14 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/AU200/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/AU200/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/AU250/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/AU250/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/AU280/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/AU280/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/AU50/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/AU50/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

20
fpga/lib/pcie/example/DE10_Agilex/fpga/tb/fpga_core/Makefile
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@ -59,16 +59,16 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_SEG_HDR_WIDTH ?= 128 export PARAM_SEG_HDR_WIDTH := 128
export PARAM_SEG_PRFX_WIDTH ?= 32 export PARAM_SEG_PRFX_WIDTH := 32
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 export PARAM_AXIS_PCIE_DATA_WIDTH := 256
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 export PARAM_RQ_SEQ_NUM_WIDTH := 4
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 export PARAM_AXIS_PCIE_DATA_WIDTH := 256
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33
export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 export PARAM_RQ_SEQ_NUM_WIDTH := 4
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/ExaNIC_X25/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 export PARAM_AXIS_PCIE_DATA_WIDTH := 256
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 export PARAM_AXIS_PCIE_DATA_WIDTH := 256
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

20
fpga/lib/pcie/example/S10DX_DK/fpga/tb/fpga_core/Makefile
View File

@ -59,16 +59,16 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_SEG_HDR_WIDTH ?= 128 export PARAM_SEG_HDR_WIDTH := 128
export PARAM_SEG_PRFX_WIDTH ?= 32 export PARAM_SEG_PRFX_WIDTH := 32
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/example/S10MX_DK/fpga/tb/fpga_core/Makefile
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@ -58,14 +58,14 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/VCU108/fpga/tb/fpga_core/Makefile
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@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 export PARAM_AXIS_PCIE_DATA_WIDTH := 256
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 export PARAM_RQ_SEQ_NUM_WIDTH := 4
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/VCU108/fpga_axi/tb/fpga_core/Makefile
View File

@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 export PARAM_AXIS_PCIE_DATA_WIDTH := 256
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= 60 export PARAM_AXIS_PCIE_RQ_USER_WIDTH := 60
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= 75 export PARAM_AXIS_PCIE_RC_USER_WIDTH := 75
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= 85 export PARAM_AXIS_PCIE_CQ_USER_WIDTH := 85
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= 33 export PARAM_AXIS_PCIE_CC_USER_WIDTH := 33
export PARAM_RQ_SEQ_NUM_WIDTH ?= 4 export PARAM_RQ_SEQ_NUM_WIDTH := 4
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/VCU118/fpga/tb/fpga_core/Makefile
View File

@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/VCU118/fpga_axi/tb/fpga_core/Makefile
View File

@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/VCU1525/fpga/tb/fpga_core/Makefile
View File

@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/VCU1525/fpga_axi/tb/fpga_core/Makefile
View File

@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/ZCU106/fpga/tb/fpga_core/Makefile
View File

@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 128 export PARAM_AXIS_PCIE_DATA_WIDTH := 128
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/ZCU106/fpga_axi/tb/fpga_core/Makefile
View File

@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 128 export PARAM_AXIS_PCIE_DATA_WIDTH := 128
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

38
fpga/lib/pcie/example/common/tb/example_core_pcie/Makefile
View File

@ -48,25 +48,25 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 512 export PARAM_TLP_DATA_WIDTH := 512
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_COUNT ?= 1 export PARAM_TX_SEQ_NUM_COUNT := 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1 export PARAM_TX_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 256 export PARAM_PCIE_TAG_COUNT := 256
export PARAM_IMM_ENABLE ?= 1 export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH ?= 32 export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
export PARAM_CHECK_BUS_NUMBER ?= 1 export PARAM_CHECK_BUS_NUMBER := 1
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

34
fpga/lib/pcie/example/common/tb/example_core_pcie_ptile/Makefile
View File

@ -58,23 +58,23 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_SEG_HDR_WIDTH ?= 128 export PARAM_SEG_HDR_WIDTH := 128
export PARAM_SEG_PRFX_WIDTH ?= 32 export PARAM_SEG_PRFX_WIDTH := 32
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1 export PARAM_TX_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 256 export PARAM_PCIE_TAG_COUNT := 256
export PARAM_IMM_ENABLE ?= 1 export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH ?= 32 export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/common/tb/example_core_pcie_s10/Makefile
View File

@ -57,22 +57,22 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 1 export PARAM_SEG_COUNT := 1
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1 export PARAM_TX_SEQ_NUM_ENABLE := 1
export PARAM_L_TILE ?= 0 export PARAM_L_TILE := 0
export PARAM_PCIE_TAG_COUNT ?= 256 export PARAM_PCIE_TAG_COUNT := 256
export PARAM_IMM_ENABLE ?= 1 export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH ?= 32 export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

44
fpga/lib/pcie/example/common/tb/example_core_pcie_us/Makefile
View File

@ -57,28 +57,28 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 256 export PARAM_PCIE_TAG_COUNT := 256
export PARAM_IMM_ENABLE ?= 1 export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH ?= 32 export PARAM_IMM_WIDTH := 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/example/fb2CG/fpga/tb/fpga_core/Makefile
View File

@ -58,22 +58,22 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_PCIE_TAG_COUNT ?= 64 export PARAM_PCIE_TAG_COUNT := 64
export PARAM_BAR0_APERTURE ?= 24 export PARAM_BAR0_APERTURE := 24
export PARAM_BAR2_APERTURE ?= 24 export PARAM_BAR2_APERTURE := 24
export PARAM_BAR4_APERTURE ?= 16 export PARAM_BAR4_APERTURE := 16
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/example/fb2CG/fpga_axi/tb/fpga_core/Makefile
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@ -48,13 +48,13 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_DATA_WIDTH := 512
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= 6 export PARAM_RQ_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

36
fpga/lib/pcie/tb/dma_client_axis_sink/Makefile
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@ -32,24 +32,24 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_RAM_DATA_WIDTH ?= 128 export PARAM_RAM_DATA_WIDTH := 128
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))")
export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) )
export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 )
export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_AXIS_DATA_WIDTH ?= 64 export PARAM_AXIS_DATA_WIDTH := 64
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE ?= 1 export PARAM_AXIS_LAST_ENABLE := 1
export PARAM_AXIS_ID_ENABLE ?= 1 export PARAM_AXIS_ID_ENABLE := 1
export PARAM_AXIS_ID_WIDTH ?= 8 export PARAM_AXIS_ID_WIDTH := 8
export PARAM_AXIS_DEST_ENABLE ?= 1 export PARAM_AXIS_DEST_ENABLE := 1
export PARAM_AXIS_DEST_WIDTH ?= 8 export PARAM_AXIS_DEST_WIDTH := 8
export PARAM_AXIS_USER_ENABLE ?= 1 export PARAM_AXIS_USER_ENABLE := 1
export PARAM_AXIS_USER_WIDTH ?= 1 export PARAM_AXIS_USER_WIDTH := 1
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

36
fpga/lib/pcie/tb/dma_client_axis_source/Makefile
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@ -32,24 +32,24 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_RAM_DATA_WIDTH ?= 128 export PARAM_RAM_DATA_WIDTH := 128
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))") export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_RAM_DATA_WIDTH) // 128))")
export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) ) export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_RAM_DATA_WIDTH) / $(PARAM_SEG_COUNT) )
export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 )
export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_AXIS_DATA_WIDTH ?= 64 export PARAM_AXIS_DATA_WIDTH := 64
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
export PARAM_AXIS_LAST_ENABLE ?= 1 export PARAM_AXIS_LAST_ENABLE := 1
export PARAM_AXIS_ID_ENABLE ?= 1 export PARAM_AXIS_ID_ENABLE := 1
export PARAM_AXIS_ID_WIDTH ?= 8 export PARAM_AXIS_ID_WIDTH := 8
export PARAM_AXIS_DEST_ENABLE ?= 1 export PARAM_AXIS_DEST_ENABLE := 1
export PARAM_AXIS_DEST_WIDTH ?= 8 export PARAM_AXIS_DEST_WIDTH := 8
export PARAM_AXIS_USER_ENABLE ?= 1 export PARAM_AXIS_USER_ENABLE := 1
export PARAM_AXIS_USER_WIDTH ?= 1 export PARAM_AXIS_USER_WIDTH := 1
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

36
fpga/lib/pcie/tb/dma_if_axi/Makefile
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@ -34,24 +34,24 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
# module parameters # module parameters
export PARAM_AXI_DATA_WIDTH ?= 64 export PARAM_AXI_DATA_WIDTH := 64
export PARAM_AXI_ADDR_WIDTH ?= 16 export PARAM_AXI_ADDR_WIDTH := 16
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_RAM_SEG_COUNT ?= 2 export PARAM_RAM_SEG_COUNT := 2
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_IMM_ENABLE ?= 1 export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH ?= $(PARAM_AXI_DATA_WIDTH) export PARAM_IMM_WIDTH := $(PARAM_AXI_DATA_WIDTH)
export PARAM_LEN_WIDTH ?= 16 export PARAM_LEN_WIDTH := 16
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_READ_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") export PARAM_READ_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") export PARAM_WRITE_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_READ_USE_AXI_ID ?= 0 export PARAM_READ_USE_AXI_ID := 0
export PARAM_WRITE_USE_AXI_ID ?= 1 export PARAM_WRITE_USE_AXI_ID := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

28
fpga/lib/pcie/tb/dma_if_axi_rd/Makefile
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@ -32,20 +32,20 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXI_DATA_WIDTH ?= 64 export PARAM_AXI_DATA_WIDTH := 64
export PARAM_AXI_ADDR_WIDTH ?= 16 export PARAM_AXI_ADDR_WIDTH := 16
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_RAM_SEG_COUNT ?= 2 export PARAM_RAM_SEG_COUNT := 2
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_LEN_WIDTH ?= 16 export PARAM_LEN_WIDTH := 16
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") export PARAM_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 0 export PARAM_USE_AXI_ID := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/tb/dma_if_axi_wr/Makefile
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@ -32,22 +32,22 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXI_DATA_WIDTH ?= 64 export PARAM_AXI_DATA_WIDTH := 64
export PARAM_AXI_ADDR_WIDTH ?= 16 export PARAM_AXI_ADDR_WIDTH := 16
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_RAM_SEG_COUNT ?= 2 export PARAM_RAM_SEG_COUNT := 2
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_IMM_ENABLE ?= 1 export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH ?= $(PARAM_AXI_DATA_WIDTH) export PARAM_IMM_WIDTH := $(PARAM_AXI_DATA_WIDTH)
export PARAM_LEN_WIDTH ?= 16 export PARAM_LEN_WIDTH := 16
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))") export PARAM_OP_TABLE_SIZE := $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 1 export PARAM_USE_AXI_ID := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

40
fpga/lib/pcie/tb/dma_if_pcie_rd/Makefile
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@ -32,26 +32,26 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_COUNT ?= 1 export PARAM_TX_SEQ_NUM_COUNT := 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1 export PARAM_TX_SEQ_NUM_ENABLE := 1
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) export PARAM_RAM_SEG_COUNT := $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 )
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_PCIE_TAG_COUNT ?= 256 export PARAM_PCIE_TAG_COUNT := 256
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
export PARAM_CHECK_BUS_NUMBER ?= 1 export PARAM_CHECK_BUS_NUMBER := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

44
fpga/lib/pcie/tb/dma_if_pcie_us/Makefile
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@ -34,28 +34,28 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))")
export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) )
export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 )
export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64)
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_READ_TX_FC_ENABLE ?= 1 export PARAM_READ_TX_FC_ENABLE := 1
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_FC_ENABLE ?= 1 export PARAM_WRITE_TX_FC_ENABLE := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

38
fpga/lib/pcie/tb/dma_if_pcie_us_rd/Makefile
View File

@ -32,25 +32,25 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))")
export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) )
export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 )
export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64)
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_FC_ENABLE ?= 1 export PARAM_TX_FC_ENABLE := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

34
fpga/lib/pcie/tb/dma_if_pcie_us_wr/Makefile
View File

@ -32,23 +32,23 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_SEG_COUNT ?= $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))") export PARAM_SEG_COUNT := $(shell python -c "print(max(2, $(PARAM_AXIS_PCIE_DATA_WIDTH) * 2 // 128))")
export PARAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) ) export PARAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) \* 2 / $(PARAM_SEG_COUNT) )
export PARAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 ) export PARAM_SEG_BE_WIDTH := $(shell expr $(PARAM_SEG_DATA_WIDTH) / 8 )
export PARAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_SEG_COUNT)*$(PARAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_FC_ENABLE ?= 1 export PARAM_TX_FC_ENABLE := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

42
fpga/lib/pcie/tb/dma_if_pcie_wr/Makefile
View File

@ -32,27 +32,27 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_COUNT ?= 1 export PARAM_TX_SEQ_NUM_COUNT := 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1 export PARAM_TX_SEQ_NUM_ENABLE := 1
export PARAM_RAM_SEL_WIDTH ?= 2 export PARAM_RAM_SEL_WIDTH := 2
export PARAM_RAM_ADDR_WIDTH ?= 16 export PARAM_RAM_ADDR_WIDTH := 16
export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 ) export PARAM_RAM_SEG_COUNT := $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 )
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) ) export PARAM_RAM_SEG_DATA_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 ) export PARAM_RAM_SEG_BE_WIDTH := $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())") export PARAM_RAM_SEG_ADDR_WIDTH := $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_IMM_ENABLE ?= 1 export PARAM_IMM_ENABLE := 1
export PARAM_IMM_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) ) export PARAM_IMM_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) )
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/dma_psdp_ram.py
View File

@ -141,8 +141,10 @@ class PsdpRamWrite(Memory):
async def _run(self): async def _run(self):
cmd_ready = 0 cmd_ready = 0
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
wr_done = 0 wr_done = 0
@ -191,9 +193,11 @@ class PsdpRamWrite(Memory):
self.bus.wr_done.value = wr_done self.bus.wr_done.value = wr_done
async def _run_pause(self): async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator: for val in self._pause_generator:
self.pause = val self.pause = val
await RisingEdge(self.clock) await clock_edge_event
class PsdpRamRead(Memory): class PsdpRamRead(Memory):
@ -257,8 +261,10 @@ class PsdpRamRead(Memory):
resp_valid = 0 resp_valid = 0
resp_data = 0 resp_data = 0
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
cmd_valid_sample = self.bus.rd_cmd_valid.value cmd_valid_sample = self.bus.rd_cmd_valid.value
@ -319,9 +325,11 @@ class PsdpRamRead(Memory):
self.bus.rd_resp_valid.value = resp_valid self.bus.rd_resp_valid.value = resp_valid
async def _run_pause(self): async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator: for val in self._pause_generator:
self.pause = val self.pause = val
await RisingEdge(self.clock) await clock_edge_event
class PsdpRam(Memory): class PsdpRam(Memory):

2
fpga/lib/pcie/tb/irq_rate_limit/Makefile
View File

@ -32,7 +32,7 @@ MODULE = test_$(DUT)
VERILOG_SOURCES = ../../rtl/$(DUT).v VERILOG_SOURCES = ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_IRQ_INDEX_WIDTH ?= 11 export PARAM_IRQ_INDEX_WIDTH := 11
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

20
fpga/lib/pcie/tb/pcie_axi_master/Makefile
View File

@ -37,16 +37,16 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../rtl/pulse_merge.v VERILOG_SOURCES += ../../rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_TLP_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH := 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

20
fpga/lib/pcie/tb/pcie_axi_master_rd/Makefile
View File

@ -33,16 +33,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_TLP_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH := 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

18
fpga/lib/pcie/tb/pcie_axi_master_wr/Makefile
View File

@ -33,15 +33,15 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_TLP_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH := 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_axil_master/Makefile
View File

@ -33,14 +33,14 @@ MODULE = test_$(DUT)
VERILOG_SOURCES = ../../rtl/$(DUT).v VERILOG_SOURCES = ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_AXIL_DATA_WIDTH ?= 32 export PARAM_AXIL_DATA_WIDTH := 32
export PARAM_AXIL_ADDR_WIDTH ?= 64 export PARAM_AXIL_ADDR_WIDTH := 64
export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_axil_master_minimal/Makefile
View File

@ -33,14 +33,14 @@ MODULE = test_$(DUT)
VERILOG_SOURCES = ../../rtl/$(DUT).v VERILOG_SOURCES = ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_AXIL_DATA_WIDTH ?= 32 export PARAM_AXIL_DATA_WIDTH := 32
export PARAM_AXIL_ADDR_WIDTH ?= 64 export PARAM_AXIL_ADDR_WIDTH := 64
export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

28
fpga/lib/pcie/tb/pcie_if.py
View File

@ -354,9 +354,11 @@ class PcieIfBase:
self.set_pause_generator(None) self.set_pause_generator(None)
async def _run_pause(self): async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator: for val in self._pause_generator:
self.pause = val self.pause = val
await RisingEdge(self.clock) await clock_edge_event
class PcieIfSource(PcieIfBase): class PcieIfSource(PcieIfBase):
@ -459,8 +461,10 @@ class PcieIfSource(PcieIfBase):
async def _run_source(self): async def _run_source(self):
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
# read handshake signals # read handshake signals
ready_sample = self.bus.ready.value ready_sample = self.bus.ready.value
@ -613,8 +617,10 @@ class PcieIfSink(PcieIfBase):
await self.active_event.wait() await self.active_event.wait()
async def _run_sink(self): async def _run_sink(self):
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
# read handshake signals # read handshake signals
ready_sample = self.bus.ready.value ready_sample = self.bus.ready.value
@ -1189,11 +1195,13 @@ class PcieIfDevice(Device):
self.rd_req_tx_seq_num_queue.put_nowait(frame.seq) self.rd_req_tx_seq_num_queue.put_nowait(frame.seq)
async def _run_rd_req_tx_seq_num_logic(self): async def _run_rd_req_tx_seq_num_logic(self):
clock_edge_event = RisingEdge(self.clk)
if self.rd_req_tx_seq_num is not None: if self.rd_req_tx_seq_num is not None:
width = len(self.rd_req_tx_seq_num) // len(self.rd_req_tx_seq_num_valid) width = len(self.rd_req_tx_seq_num) // len(self.rd_req_tx_seq_num_valid)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.rd_req_tx_seq_num is not None: if self.rd_req_tx_seq_num is not None:
data = 0 data = 0
@ -1215,11 +1223,13 @@ class PcieIfDevice(Device):
self.wr_req_tx_seq_num_queue.put_nowait(frame.seq) self.wr_req_tx_seq_num_queue.put_nowait(frame.seq)
async def _run_wr_req_tx_seq_num_logic(self): async def _run_wr_req_tx_seq_num_logic(self):
clock_edge_event = RisingEdge(self.clk)
if self.wr_req_tx_seq_num is not None: if self.wr_req_tx_seq_num is not None:
width = len(self.wr_req_tx_seq_num) // len(self.wr_req_tx_seq_num_valid) width = len(self.wr_req_tx_seq_num) // len(self.wr_req_tx_seq_num_valid)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.wr_req_tx_seq_num is not None: if self.wr_req_tx_seq_num is not None:
data = 0 data = 0
@ -1240,8 +1250,10 @@ class PcieIfDevice(Device):
await self.send(tlp) await self.send(tlp)
async def _run_cfg_status_logic(self): async def _run_cfg_status_logic(self):
clock_edge_event = RisingEdge(self.clk)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.cfg_max_payload is not None: if self.cfg_max_payload is not None:
self.cfg_max_payload.value = self.functions[0].pcie_cap.max_payload_size self.cfg_max_payload.value = self.functions[0].pcie_cap.max_payload_size
@ -1251,8 +1263,10 @@ class PcieIfDevice(Device):
self.cfg_ext_tag_enable.value = self.functions[0].pcie_cap.extended_tag_field_enable self.cfg_ext_tag_enable.value = self.functions[0].pcie_cap.extended_tag_field_enable
async def _run_fc_logic(self): async def _run_fc_logic(self):
clock_edge_event = RisingEdge(self.clk)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.tx_fc_ph_av is not None: if self.tx_fc_ph_av is not None:
self.tx_fc_ph_av.value = self.upstream_port.fc_state[0].ph.tx_credits_available & 0xff self.tx_fc_ph_av.value = self.upstream_port.fc_state[0].ph.tx_credits_available & 0xff

18
fpga/lib/pcie/tb/pcie_msix/Makefile
View File

@ -32,15 +32,15 @@ MODULE = test_$(DUT)
VERILOG_SOURCES = ../../rtl/$(DUT).v VERILOG_SOURCES = ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_IRQ_INDEX_WIDTH ?= 11 export PARAM_IRQ_INDEX_WIDTH := 11
export PARAM_AXIL_DATA_WIDTH ?= 32 export PARAM_AXIL_DATA_WIDTH := 32
export PARAM_AXIL_ADDR_WIDTH ?= $(shell expr $(PARAM_IRQ_INDEX_WIDTH) + 5 ) export PARAM_AXIL_ADDR_WIDTH := $(shell expr $(PARAM_IRQ_INDEX_WIDTH) + 5 )
export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

28
fpga/lib/pcie/tb/pcie_ptile_if/Makefile
View File

@ -41,20 +41,20 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_SEG_HDR_WIDTH ?= 128 export PARAM_SEG_HDR_WIDTH := 128
export PARAM_SEG_PRFX_WIDTH ?= 32 export PARAM_SEG_PRFX_WIDTH := 32
export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) )
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_PF_COUNT ?= 1 export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT ?= 0 export PARAM_VF_COUNT := 0
export PARAM_F_COUNT ?= $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) export PARAM_F_COUNT := $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) )
export PARAM_IO_BAR_INDEX ?= 3 export PARAM_IO_BAR_INDEX := 3
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

20
fpga/lib/pcie/tb/pcie_ptile_if_rx/Makefile
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@ -35,16 +35,16 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_SEG_HDR_WIDTH ?= 128 export PARAM_SEG_HDR_WIDTH := 128
export PARAM_SEG_PRFX_WIDTH ?= 32 export PARAM_SEG_PRFX_WIDTH := 32
export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) )
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_IO_BAR_INDEX ?= 3 export PARAM_IO_BAR_INDEX := 3
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

18
fpga/lib/pcie/tb/pcie_ptile_if_tx/Makefile
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@ -36,15 +36,15 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_HDR_WIDTH ?= 128 export PARAM_SEG_HDR_WIDTH := 128
export PARAM_SEG_PRFX_WIDTH ?= 32 export PARAM_SEG_PRFX_WIDTH := 32
export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) )
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

30
fpga/lib/pcie/tb/pcie_s10_if/Makefile
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@ -43,21 +43,21 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) )
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
export PARAM_L_TILE ?= 0 export PARAM_L_TILE := 0
export PARAM_PF_COUNT ?= 1 export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT ?= 0 export PARAM_VF_COUNT := 0
export PARAM_F_COUNT ?= $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) export PARAM_F_COUNT := $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) )
export PARAM_IO_BAR_INDEX ?= 3 export PARAM_IO_BAR_INDEX := 3
export PARAM_MSI_ENABLE ?= 1 export PARAM_MSI_ENABLE := 1
export PARAM_MSI_COUNT ?= 32 export PARAM_MSI_COUNT := 32
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_s10_if_rx/Makefile
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@ -35,14 +35,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" ) export PARAM_SEG_EMPTY_WIDTH := $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) )
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_IO_BAR_INDEX ?= 3 export PARAM_IO_BAR_INDEX := 3
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/tb/pcie_s10_if_tx/Makefile
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@ -35,13 +35,13 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_mux.v
# module parameters # module parameters
export PARAM_SEG_COUNT ?= 2 export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH ?= 256 export PARAM_SEG_DATA_WIDTH := 256
export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) ) export PARAM_TLP_DATA_WIDTH := $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) )
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6 export PARAM_TX_SEQ_NUM_WIDTH := 6
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

18
fpga/lib/pcie/tb/pcie_tlp_demux/Makefile
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@ -38,15 +38,15 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_SEQ_NUM_WIDTH ?= 6 export PARAM_SEQ_NUM_WIDTH := 6
export PARAM_IN_TLP_SEG_COUNT ?= 1 export PARAM_IN_TLP_SEG_COUNT := 1
export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT)
export PARAM_FIFO_ENABLE ?= 1 export PARAM_FIFO_ENABLE := 1
export PARAM_FIFO_DEPTH ?= 4096 export PARAM_FIFO_DEPTH := 4096
export PARAM_FIFO_WATERMARK ?= $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) export PARAM_FIFO_WATERMARK := $(shell expr $(PARAM_FIFO_DEPTH) / 2 )
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

24
fpga/lib/pcie/tb/pcie_tlp_demux_bar/Makefile
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@ -39,18 +39,18 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_SEQ_NUM_WIDTH ?= 6 export PARAM_SEQ_NUM_WIDTH := 6
export PARAM_IN_TLP_SEG_COUNT ?= 1 export PARAM_IN_TLP_SEG_COUNT := 1
export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT)
export PARAM_FIFO_ENABLE ?= 1 export PARAM_FIFO_ENABLE := 1
export PARAM_FIFO_DEPTH ?= 4096 export PARAM_FIFO_DEPTH := 4096
export PARAM_FIFO_WATERMARK ?= $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) export PARAM_FIFO_WATERMARK := $(shell expr $(PARAM_FIFO_DEPTH) / 2 )
export PARAM_BAR_BASE ?= 0 export PARAM_BAR_BASE := 0
export PARAM_BAR_STRIDE ?= 1 export PARAM_BAR_STRIDE := 1
export PARAM_BAR_IDS ?= 0 export PARAM_BAR_IDS := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

12
fpga/lib/pcie/tb/pcie_tlp_fifo/Makefile
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@ -33,12 +33,12 @@ VERILOG_SOURCES = ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_DEPTH ?= 4096 export PARAM_DEPTH := 4096
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_IN_TLP_SEG_COUNT ?= 1 export PARAM_IN_TLP_SEG_COUNT := 1
export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT)
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

20
fpga/lib/pcie/tb/pcie_tlp_fifo_mux/Makefile
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@ -38,16 +38,16 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fc_count.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_SEQ_NUM_WIDTH ?= 6 export PARAM_SEQ_NUM_WIDTH := 6
export PARAM_IN_TLP_SEG_COUNT ?= 1 export PARAM_IN_TLP_SEG_COUNT := 1
export PARAM_OUT_TLP_SEG_COUNT ?= $(PARAM_IN_TLP_SEG_COUNT) export PARAM_OUT_TLP_SEG_COUNT := $(PARAM_IN_TLP_SEG_COUNT)
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0 export PARAM_ARB_TYPE_ROUND_ROBIN := 0
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 export PARAM_ARB_LSB_HIGH_PRIORITY := 1
export PARAM_FIFO_DEPTH ?= 4096 export PARAM_FIFO_DEPTH := 4096
export PARAM_FIFO_WATERMARK ?= $(shell expr $(PARAM_FIFO_DEPTH) / 2 ) export PARAM_FIFO_WATERMARK := $(shell expr $(PARAM_FIFO_DEPTH) / 2 )
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

14
fpga/lib/pcie/tb/pcie_tlp_mux/Makefile
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@ -36,13 +36,13 @@ VERILOG_SOURCES += $(WRAPPER).v
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_TLP_DATA_WIDTH ?= 64 export PARAM_TLP_DATA_WIDTH := 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_SEQ_NUM_WIDTH ?= 6 export PARAM_SEQ_NUM_WIDTH := 6
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0 export PARAM_ARB_TYPE_ROUND_ROBIN := 0
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1 export PARAM_ARB_LSB_HIGH_PRIORITY := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

42
fpga/lib/pcie/tb/pcie_us_axi_dma/Makefile
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@ -34,27 +34,27 @@ VERILOG_SOURCES += ../../rtl/$(DUT)_rd.v
VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v VERILOG_SOURCES += ../../rtl/$(DUT)_wr.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 24 export PARAM_AXI_ADDR_WIDTH := 24
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64)
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_READ_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_READ_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_READ_TX_FC_ENABLE ?= 1 export PARAM_READ_TX_FC_ENABLE := 1
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_FC_ENABLE ?= 1 export PARAM_WRITE_TX_FC_ENABLE := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

36
fpga/lib/pcie/tb/pcie_us_axi_dma_rd/Makefile
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@ -32,24 +32,24 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 24 export PARAM_AXI_ADDR_WIDTH := 24
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_PCIE_TAG_COUNT ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64) export PARAM_PCIE_TAG_COUNT := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),256,64)
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT) export PARAM_OP_TABLE_SIZE := $(PARAM_PCIE_TAG_COUNT)
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_FC_ENABLE ?= 1 export PARAM_TX_FC_ENABLE := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

32
fpga/lib/pcie/tb/pcie_us_axi_dma_wr/Makefile
View File

@ -32,22 +32,22 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_RQ_SEQ_NUM_ENABLE ?= 1 export PARAM_RQ_SEQ_NUM_ENABLE := 1
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 24 export PARAM_AXI_ADDR_WIDTH := 24
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
export PARAM_PCIE_ADDR_WIDTH ?= 64 export PARAM_PCIE_ADDR_WIDTH := 64
export PARAM_LEN_WIDTH ?= 20 export PARAM_LEN_WIDTH := 20
export PARAM_TAG_WIDTH ?= 8 export PARAM_TAG_WIDTH := 8
export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_OP_TABLE_SIZE := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" ) export PARAM_TX_LIMIT := $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_FC_ENABLE ?= 1 export PARAM_TX_FC_ENABLE := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

18
fpga/lib/pcie/tb/pcie_us_axi_master/Makefile
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@ -37,15 +37,15 @@ VERILOG_SOURCES += ../../rtl/pcie_us_axis_cq_demux.v
VERILOG_SOURCES += ../../rtl/pulse_merge.v VERILOG_SOURCES += ../../rtl/pulse_merge.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH := 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

18
fpga/lib/pcie/tb/pcie_us_axi_master_rd/Makefile
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@ -33,15 +33,15 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH := 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_us_axi_master_wr/Makefile
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@ -33,14 +33,14 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_AXI_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH := 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8 export PARAM_AXI_ID_WIDTH := 8
export PARAM_AXI_MAX_BURST_LEN ?= 256 export PARAM_AXI_MAX_BURST_LEN := 256
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_us_axil_master/Makefile
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@ -33,14 +33,14 @@ MODULE = test_$(DUT)
VERILOG_SOURCES = ../../rtl/$(DUT).v VERILOG_SOURCES = ../../rtl/$(DUT).v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_AXI_DATA_WIDTH ?= 32 export PARAM_AXI_DATA_WIDTH := 32
export PARAM_AXI_ADDR_WIDTH ?= 64 export PARAM_AXI_ADDR_WIDTH := 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 ) export PARAM_AXI_STRB_WIDTH := $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_ENABLE_PARITY ?= 0 export PARAM_ENABLE_PARITY := 0
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

52
fpga/lib/pcie/tb/pcie_us_if/Makefile
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@ -42,32 +42,32 @@ VERILOG_SOURCES += ../../rtl/arbiter.v
VERILOG_SOURCES += ../../rtl/priority_encoder.v VERILOG_SOURCES += ../../rtl/priority_encoder.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_COUNT ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2) export PARAM_TX_SEQ_NUM_COUNT := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2)
export PARAM_TX_SEQ_NUM_WIDTH ?= $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 ) export PARAM_TX_SEQ_NUM_WIDTH := $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 )
export PARAM_PF_COUNT ?= 1 export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT ?= 0 export PARAM_VF_COUNT := 0
export PARAM_F_COUNT ?= $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) ) export PARAM_F_COUNT := $(shell expr $(PARAM_PF_COUNT) + $(PARAM_VF_COUNT) )
export PARAM_READ_EXT_TAG_ENABLE ?= 1 export PARAM_READ_EXT_TAG_ENABLE := 1
export PARAM_READ_MAX_READ_REQ_SIZE ?= 1 export PARAM_READ_MAX_READ_REQ_SIZE := 1
export PARAM_READ_MAX_PAYLOAD_SIZE ?= 1 export PARAM_READ_MAX_PAYLOAD_SIZE := 1
export PARAM_MSIX_ENABLE ?= 1 export PARAM_MSIX_ENABLE := 1
export PARAM_MSI_ENABLE ?= 1 export PARAM_MSI_ENABLE := 1
export PARAM_MSI_COUNT ?= 32 export PARAM_MSI_COUNT := 32
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_us_if_cc/Makefile
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@ -34,14 +34,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81) export PARAM_AXIS_PCIE_CC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_CC_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) export PARAM_CC_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1)
export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_us_if_cq/Makefile
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@ -34,14 +34,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183) export PARAM_AXIS_PCIE_CQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_CQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1) export PARAM_CQ_STRADDLE := $(if $(filter-out 512,$(PARAM_DATA_WIDTH)),0,1)
export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

16
fpga/lib/pcie/tb/pcie_us_if_rc/Makefile
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@ -34,14 +34,14 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) export PARAM_AXIS_PCIE_RC_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
export PARAM_RC_STRADDLE ?= $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1) export PARAM_RC_STRADDLE := $(if $(filter-out 256 512,$(PARAM_DATA_WIDTH)),0,1)
export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst

22
fpga/lib/pcie/tb/pcie_us_if_rq/Makefile
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@ -34,17 +34,17 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v VERILOG_SOURCES += ../../rtl/pcie_tlp_fifo_raw.v
# module parameters # module parameters
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 64 export PARAM_AXIS_PCIE_DATA_WIDTH := 64
export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RQ_USER_WIDTH := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
export PARAM_RQ_STRADDLE ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1) export PARAM_RQ_STRADDLE := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),0,1)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4) export PARAM_RQ_SEQ_NUM_WIDTH := $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH) export PARAM_TLP_DATA_WIDTH := $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 ) export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128 export PARAM_TLP_HDR_WIDTH := 128
export PARAM_TLP_SEG_COUNT ?= 1 export PARAM_TLP_SEG_COUNT := 1
export PARAM_TX_SEQ_NUM_COUNT ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2) export PARAM_TX_SEQ_NUM_COUNT := $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2)
export PARAM_TX_SEQ_NUM_WIDTH ?= $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 ) export PARAM_TX_SEQ_NUM_WIDTH := $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 )
ifeq ($(SIM), icarus) ifeq ($(SIM), icarus)
PLUSARGS += -fst PLUSARGS += -fst