From 24c758dbdee58b89160d942d0667a39d2d6390ca Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 22 Aug 2023 12:53:43 -0700 Subject: [PATCH] fpga/mqnic/XUPP3R: Update XUP-P3R pins Signed-off-by: Alex Forencich --- fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc | 24 ++++++++++++------- fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v | 4 ++++ fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v | 2 ++ .../fpga_100g/tb/fpga_core/test_fpga_core.py | 3 +++ fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc | 24 ++++++++++++------- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v | 4 ++++ fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v | 2 ++ .../fpga_25g/tb/fpga_core/test_fpga_core.py | 3 +++ 8 files changed, 50 insertions(+), 16 deletions(-) diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc b/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc index d4a699a77..8da575a20 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc @@ -1,11 +1,10 @@ -# XDC constraints for the Xilinx VCU1525 board +# XDC constraints for the BittWare XUP-P3R board # part: xcvu9p-flgb2104-2-e # General configuration set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] @@ -58,15 +57,24 @@ set_property -dict {LOC AV22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports { set_false_path -to [get_ports {led[*]}] set_output_delay 0 [get_ports {led[*]}] -# Reset -#set_property -dict {LOC IOSTANDARD LVCMOS12} [get_ports reset] +# Timing +set_property -dict {LOC AU22 IOSTANDARD LVCMOS18} [get_ports ext_pps_in] ;# from J1 +set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports ext_clk_in] ;# from J2 -#set_false_path -from [get_ports {reset}] -#set_input_delay 0 [get_ports {reset}] +create_clock -period 100.000 -name ext_clk_in [get_ports ext_clk_in] + +set_false_path -from [get_ports {ext_pps_in ext_clk_in}] +set_input_delay 0 [get_ports {ext_pps_in ext_clk_in}] + +# Reset +#set_property -dict {LOC AT23 IOSTANDARD LVCMOS18} [get_ports sys_rst_l] + +#set_false_path -from [get_ports {sys_rst_l}] +#set_input_delay 0 [get_ports {sys_rst_l}] # UART -#set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] -#set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] +#set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] +#set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] #set_false_path -to [get_ports {uart_txd}] #set_output_delay 0 [get_ports {uart_txd}] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index c8cb2b05c..13cb9e4e9 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -153,6 +153,8 @@ module fpga # * GPIO */ output wire [3:0] led, + input wire ext_pps_in, + input wire ext_clk_in, /* * I2C and related signals @@ -2377,6 +2379,8 @@ core_inst ( * GPIO */ .led(led_int), + .ext_pps_in(ext_pps_in), + .ext_clk_in(ext_clk_in), /* * I2C diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 0b81be5b4..b2e786d5b 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -177,6 +177,8 @@ module fpga_core # * GPIO */ output wire [3:0] led, + input wire ext_pps_in, + input wire ext_clk_in, /* * I2C diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index 87d0d9352..bb5f49167 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -315,6 +315,9 @@ class TB(object): dut.eeprom_i2c_scl_i.setimmediatevalue(1) dut.eeprom_i2c_sda_i.setimmediatevalue(1) + dut.ext_pps_in.setimmediatevalue(0) + dut.ext_clk_in.setimmediatevalue(0) + dut.qspi_dq_i.setimmediatevalue(0) self.loopback_enable = False diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc b/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc index d4a699a77..8da575a20 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc @@ -1,11 +1,10 @@ -# XDC constraints for the Xilinx VCU1525 board +# XDC constraints for the BittWare XUP-P3R board # part: xcvu9p-flgb2104-2-e # General configuration set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] @@ -58,15 +57,24 @@ set_property -dict {LOC AV22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports { set_false_path -to [get_ports {led[*]}] set_output_delay 0 [get_ports {led[*]}] -# Reset -#set_property -dict {LOC IOSTANDARD LVCMOS12} [get_ports reset] +# Timing +set_property -dict {LOC AU22 IOSTANDARD LVCMOS18} [get_ports ext_pps_in] ;# from J1 +set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports ext_clk_in] ;# from J2 -#set_false_path -from [get_ports {reset}] -#set_input_delay 0 [get_ports {reset}] +create_clock -period 100.000 -name ext_clk_in [get_ports ext_clk_in] + +set_false_path -from [get_ports {ext_pps_in ext_clk_in}] +set_input_delay 0 [get_ports {ext_pps_in ext_clk_in}] + +# Reset +#set_property -dict {LOC AT23 IOSTANDARD LVCMOS18} [get_ports sys_rst_l] + +#set_false_path -from [get_ports {sys_rst_l}] +#set_input_delay 0 [get_ports {sys_rst_l}] # UART -#set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] -#set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] +#set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] +#set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] #set_false_path -to [get_ports {uart_txd}] #set_output_delay 0 [get_ports {uart_txd}] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index afb8d7a3e..d5f27604b 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -157,6 +157,8 @@ module fpga # * GPIO */ output wire [3:0] led, + input wire ext_pps_in, + input wire ext_clk_in, /* * I2C and related signals @@ -2637,6 +2639,8 @@ core_inst ( * GPIO */ .led(led), + .ext_pps_in(ext_pps_in), + .ext_clk_in(ext_clk_in), /* * I2C diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index f579d7237..ef793abd4 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -186,6 +186,8 @@ module fpga_core # * GPIO */ output wire [3:0] led, + input wire ext_pps_in, + input wire ext_clk_in, /* * I2C diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index 941f3aae9..e4707143f 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -307,6 +307,9 @@ class TB(object): dut.eeprom_i2c_scl_i.setimmediatevalue(1) dut.eeprom_i2c_sda_i.setimmediatevalue(1) + dut.ext_pps_in.setimmediatevalue(0) + dut.ext_clk_in.setimmediatevalue(0) + dut.qspi_dq_i.setimmediatevalue(0) self.loopback_enable = False