FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

fpga/mqnic/XUPP3R: Update XUP-P3R pins

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-08-22 12:53:43 -07:00
parent 99645f894e
commit 24c758dbde
8 changed files with 50 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc
View File

@ -1,11 +1,10 @@
# XDC constraints for the Xilinx VCU1525 board # XDC constraints for the BittWare XUP-P3R board
# part: xcvu9p-flgb2104-2-e # part: xcvu9p-flgb2104-2-e
# General configuration # General configuration
set_property CFGBVS GND [current_design] set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design] set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
@ -58,15 +57,24 @@ set_property -dict {LOC AV22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
set_false_path -to [get_ports {led[*]}] set_false_path -to [get_ports {led[*]}]
set_output_delay 0 [get_ports {led[*]}] set_output_delay 0 [get_ports {led[*]}]
# Reset # Timing
#set_property -dict {LOC IOSTANDARD LVCMOS12} [get_ports reset] set_property -dict {LOC AU22 IOSTANDARD LVCMOS18} [get_ports ext_pps_in] ;# from J1
set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports ext_clk_in] ;# from J2
#set_false_path -from [get_ports {reset}] create_clock -period 100.000 -name ext_clk_in [get_ports ext_clk_in]
#set_input_delay 0 [get_ports {reset}]
set_false_path -from [get_ports {ext_pps_in ext_clk_in}]
set_input_delay 0 [get_ports {ext_pps_in ext_clk_in}]
# Reset
#set_property -dict {LOC AT23 IOSTANDARD LVCMOS18} [get_ports sys_rst_l]
#set_false_path -from [get_ports {sys_rst_l}]
#set_input_delay 0 [get_ports {sys_rst_l}]
# UART # UART
#set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] #set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
#set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] #set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
#set_false_path -to [get_ports {uart_txd}] #set_false_path -to [get_ports {uart_txd}]
#set_output_delay 0 [get_ports {uart_txd}] #set_output_delay 0 [get_ports {uart_txd}]

4
fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
View File

@ -153,6 +153,8 @@ module fpga #
* GPIO * GPIO
*/ */
output wire [3:0] led, output wire [3:0] led,
input wire ext_pps_in,
input wire ext_clk_in,
/* /*
* I2C and related signals * I2C and related signals
@ -2377,6 +2379,8 @@ core_inst (
* GPIO * GPIO
*/ */
.led(led_int), .led(led_int),
.ext_pps_in(ext_pps_in),
.ext_clk_in(ext_clk_in),
/* /*
* I2C * I2C

2
fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
View File

@ -177,6 +177,8 @@ module fpga_core #
* GPIO * GPIO
*/ */
output wire [3:0] led, output wire [3:0] led,
input wire ext_pps_in,
input wire ext_clk_in,
/* /*
* I2C * I2C

3
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -315,6 +315,9 @@ class TB(object):
dut.eeprom_i2c_scl_i.setimmediatevalue(1) dut.eeprom_i2c_scl_i.setimmediatevalue(1)
dut.eeprom_i2c_sda_i.setimmediatevalue(1) dut.eeprom_i2c_sda_i.setimmediatevalue(1)
dut.ext_pps_in.setimmediatevalue(0)
dut.ext_clk_in.setimmediatevalue(0)
dut.qspi_dq_i.setimmediatevalue(0) dut.qspi_dq_i.setimmediatevalue(0)
self.loopback_enable = False self.loopback_enable = False

24
fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc
View File

@ -1,11 +1,10 @@
# XDC constraints for the Xilinx VCU1525 board # XDC constraints for the BittWare XUP-P3R board
# part: xcvu9p-flgb2104-2-e # part: xcvu9p-flgb2104-2-e
# General configuration # General configuration
set_property CFGBVS GND [current_design] set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design] set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
@ -58,15 +57,24 @@ set_property -dict {LOC AV22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
set_false_path -to [get_ports {led[*]}] set_false_path -to [get_ports {led[*]}]
set_output_delay 0 [get_ports {led[*]}] set_output_delay 0 [get_ports {led[*]}]
# Reset # Timing
#set_property -dict {LOC IOSTANDARD LVCMOS12} [get_ports reset] set_property -dict {LOC AU22 IOSTANDARD LVCMOS18} [get_ports ext_pps_in] ;# from J1
set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports ext_clk_in] ;# from J2
#set_false_path -from [get_ports {reset}] create_clock -period 100.000 -name ext_clk_in [get_ports ext_clk_in]
#set_input_delay 0 [get_ports {reset}]
set_false_path -from [get_ports {ext_pps_in ext_clk_in}]
set_input_delay 0 [get_ports {ext_pps_in ext_clk_in}]
# Reset
#set_property -dict {LOC AT23 IOSTANDARD LVCMOS18} [get_ports sys_rst_l]
#set_false_path -from [get_ports {sys_rst_l}]
#set_input_delay 0 [get_ports {sys_rst_l}]
# UART # UART
#set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] #set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
#set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] #set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
#set_false_path -to [get_ports {uart_txd}] #set_false_path -to [get_ports {uart_txd}]
#set_output_delay 0 [get_ports {uart_txd}] #set_output_delay 0 [get_ports {uart_txd}]

4
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
View File

@ -157,6 +157,8 @@ module fpga #
* GPIO * GPIO
*/ */
output wire [3:0] led, output wire [3:0] led,
input wire ext_pps_in,
input wire ext_clk_in,
/* /*
* I2C and related signals * I2C and related signals
@ -2637,6 +2639,8 @@ core_inst (
* GPIO * GPIO
*/ */
.led(led), .led(led),
.ext_pps_in(ext_pps_in),
.ext_clk_in(ext_clk_in),
/* /*
* I2C * I2C

2
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
View File

@ -186,6 +186,8 @@ module fpga_core #
* GPIO * GPIO
*/ */
output wire [3:0] led, output wire [3:0] led,
input wire ext_pps_in,
input wire ext_clk_in,
/* /*
* I2C * I2C

3
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -307,6 +307,9 @@ class TB(object):
dut.eeprom_i2c_scl_i.setimmediatevalue(1) dut.eeprom_i2c_scl_i.setimmediatevalue(1)
dut.eeprom_i2c_sda_i.setimmediatevalue(1) dut.eeprom_i2c_sda_i.setimmediatevalue(1)
dut.ext_pps_in.setimmediatevalue(0)
dut.ext_clk_in.setimmediatevalue(0)
dut.qspi_dq_i.setimmediatevalue(0) dut.qspi_dq_i.setimmediatevalue(0)
self.loopback_enable = False self.loopback_enable = False