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Parameter updates and documentation

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This commit is contained in:
Alex Forencich 2019-07-27 23:47:46 -07:00
parent 772e01c95c
commit 26f6774182
22 changed files with 479 additions and 257 deletions
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28
fpga/common/rtl/cpl_queue_manager.v
View File

@ -40,19 +40,33 @@ either expressed or implied, of The Regents of the University of California.
*/
module cpl_queue_manager #
(
// Base address width
parameter ADDR_WIDTH = 64,
// Request tag field width
parameter REQ_TAG_WIDTH = 8,
// Number of outstanding operations
parameter OP_TABLE_SIZE = 16,
// Operation tag field width
parameter OP_TAG_WIDTH = 8,
// Queue index width (log2 of number of queues)
parameter QUEUE_INDEX_WIDTH = 8,
// Event index width
parameter EVENT_WIDTH = 8,
// Queue element pointer width (log2 of number of elements)
parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width
parameter QUEUE_LOG_SIZE_WIDTH = $clog2(QUEUE_PTR_WIDTH),
// Queue element size
parameter CPL_SIZE = 16,
// Read pipeline stages
parameter READ_PIPELINE = 2,
// Write pipeline stages
parameter WRITE_PIPELINE = 1,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8)
)
(
@ -134,37 +148,37 @@ parameter PIPELINE = READ_PIPELINE + WRITE_PIPELINE;
// bus width assertions
initial begin
if (OP_TAG_WIDTH < CL_OP_TABLE_SIZE) begin
$error("Error: OP_TAG_WDITH insufficient for OP_TABLE_SIZE");
$error("Error: OP_TAG_WDITH insufficient for OP_TABLE_SIZE (instance %m)");
$finish;
end
if (AXIL_DATA_WIDTH != 32) begin
$error("Error: AXI lite interface width must be 32");
$error("Error: AXI lite interface width must be 32 (instance %m)");
$finish;
end
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
$error("Error: AXI lite interface requires byte (8-bit) granularity");
$error("Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXIL_ADDR_WIDTH < QUEUE_INDEX_WIDTH+5) begin
$error("Error: AXI lite address width too narrow");
$error("Error: AXI lite address width too narrow (instance %m)");
$finish;
end
if (2**$clog2(CPL_SIZE) != CPL_SIZE) begin
$error("Error: Completion size must be even power of two");
$error("Error: Completion size must be even power of two (instance %m)");
$finish;
end
if (READ_PIPELINE < 1) begin
$error("Error: READ_PIPELINE must be at least 1");
$error("Error: READ_PIPELINE must be at least 1 (instance %m)");
$finish;
end
if (WRITE_PIPELINE < 1) begin
$error("Error: WRITE_PIPELINE must be at least 1");
$error("Error: WRITE_PIPELINE must be at least 1 (instance %m)");
$finish;
end
end

4
fpga/common/rtl/event_mux.v
View File

@ -40,9 +40,13 @@ either expressed or implied, of The Regents of the University of California.
*/
module event_mux #
(
// Number of ports
parameter PORTS = 2,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 4,
// Event type field width
parameter EVENT_TYPE_WIDTH = 16,
// Event source field width
parameter EVENT_SOURCE_WIDTH = 16,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",

39
fpga/common/rtl/event_queue.v
View File

@ -40,23 +40,36 @@ either expressed or implied, of The Regents of the University of California.
*/
module event_queue #
(
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 20,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 4,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Event type field width
parameter EVENT_TYPE_WIDTH = 16,
// Event source field width
parameter EVENT_SOURCE_WIDTH = 16,
// Event table size (number of in-flight operations)
parameter EVENT_TABLE_SIZE = 8,
parameter AXI_BASE_ADDR = 16'h0000,
parameter SCRATCH_EVENT_AXI_ADDR = 16'h0000,
parameter SCRATCH_EVENT_AXI_ADDR_SHIFT = 5
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 16'h0000
)
(
input wire clk,
@ -170,32 +183,22 @@ parameter EVENT_SIZE = 32;
// bus width assertions
initial begin
if (PCIE_DMA_TAG_WIDTH < CL_EVENT_TABLE_SIZE+1) begin
$error("Error: PCIe tag width insufficient for event table size");
$error("Error: PCIe tag width insufficient for event table size (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH < EVENT_SIZE) begin
$error("Error: AXI interface width must be at least as large as one event record");
$error("Error: AXI interface width must be at least as large as one event record (instance %m)");
$finish;
end
if (SCRATCH_EVENT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: Event record scratch address must be aligned to interface width");
$finish;
end
if (SCRATCH_EVENT_AXI_ADDR_SHIFT < $clog2(AXI_STRB_WIDTH)) begin
$error("Error: Event record scratch address increment must be aligned to interface width");
$finish;
end
if (SCRATCH_EVENT_AXI_ADDR_SHIFT < $clog2(EVENT_SIZE)) begin
$error("Error: Event record scratch address increment must be at least as large as one event record");
if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
end

234
fpga/common/rtl/interface.v
View File

@ -40,47 +40,91 @@ either expressed or implied, of The Regents of the University of California.
*/
module interface #
(
// Number of ports
parameter PORTS = 1,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 16,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
//parameter REQ_TAG_WIDTH = 8,
parameter EVENT_OP_TABLE_SIZE = 16,
parameter TX_OP_TABLE_SIZE = 16,
parameter RX_OP_TABLE_SIZE = 16,
parameter TX_CPL_OP_TABLE_SIZE = 16,
parameter RX_CPL_OP_TABLE_SIZE = 16,
//parameter OP_TAG_WIDTH = 8,
// Request tag field width
parameter REQ_TAG_WIDTH = 8,
// Number of outstanding operations (event queue)
parameter EVENT_QUEUE_OP_TABLE_SIZE = 16,
// Number of outstanding operations (transmit queue)
parameter TX_QUEUE_OP_TABLE_SIZE = 16,
// Number of outstanding operations (receive queue)
parameter RX_QUEUE_OP_TABLE_SIZE = 16,
// Number of outstanding operations (transmit completion queue)
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 16,
// Number of outstanding operations (receive completion queue)
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 16,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Event queue index width
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
// Transmit queue index width
parameter TX_QUEUE_INDEX_WIDTH = 8,
// Receive queue index width
parameter RX_QUEUE_INDEX_WIDTH = 8,
// Transmit completion queue index width
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
// Receive completion queue index width
parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
// Transmit descriptor table size (number of in-flight operations)
parameter TX_DESC_TABLE_SIZE = 16,
// Transmit packet table size (number of in-progress packets)
parameter TX_PKT_TABLE_SIZE = 8,
// Receive descriptor table size (number of in-flight operations)
parameter RX_DESC_TABLE_SIZE = 16,
// Receive packet table size (number of in-progress packets)
parameter RX_PKT_TABLE_SIZE = 8,
// Transmit scheduler type
parameter TX_SCHEDULER = "RR",
// Scheduler TDMA index width
parameter TDMA_INDEX_WIDTH = 8,
// Interrupt number width
parameter INT_WIDTH = 8,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width
parameter QUEUE_LOG_SIZE_WIDTH = 4,
// RAM internal address width
parameter RAM_ADDR_WIDTH = 16,
// Packet scratch RAM size
parameter RAM_SIZE = 2**14,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1,
// Enable RX checksum offload
parameter RX_CHECKSUM_ENABLE = 1,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Maximum AXI burst length to generate
parameter AXI_MAX_BURST_LEN = 16,
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 0,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH
)
(
@ -257,12 +301,6 @@ parameter EVENT_SIZE = 32;
parameter EVENT_SOURCE_WIDTH = 16;
parameter EVENT_TYPE_WIDTH = 16;
parameter AXI_DMA_TAG_WIDTH = 8;
parameter AXI_DMA_LEN_WIDTH = 16;
parameter REQ_TAG_WIDTH = 8;
parameter OP_TAG_WIDTH = 8;
parameter PCIE_DMA_TAG_WIDTH_INT = PCIE_DMA_TAG_WIDTH - $clog2(PORTS+1);
// AXI lite connections
@ -476,38 +514,38 @@ wire [PORTS-1:0] port_pcie_axi_dma_write_desc_status_vali
// Queue management
wire [EVENT_QUEUE_INDEX_WIDTH-1:0] event_enqueue_req_queue;
wire [REQ_TAG_WIDTH-1:0] event_enqueue_req_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_req_tag;
wire event_enqueue_req_valid;
wire event_enqueue_req_ready;
wire [PCIE_ADDR_WIDTH-1:0] event_enqueue_resp_addr;
wire [REQ_TAG_WIDTH-1:0] event_enqueue_resp_tag;
wire [OP_TAG_WIDTH-1:0] event_enqueue_resp_op_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_resp_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] event_enqueue_resp_op_tag;
wire event_enqueue_resp_full;
wire event_enqueue_resp_error;
wire event_enqueue_resp_valid;
wire event_enqueue_resp_ready;
wire [OP_TAG_WIDTH-1:0] event_enqueue_commit_op_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] event_enqueue_commit_op_tag;
wire event_enqueue_commit_valid;
wire event_enqueue_commit_ready;
wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_req_queue;
wire [REQ_TAG_WIDTH-1:0] tx_desc_dequeue_req_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_desc_dequeue_req_tag;
wire tx_desc_dequeue_req_valid;
wire tx_desc_dequeue_req_ready;
wire [QUEUE_PTR_WIDTH-1:0] tx_desc_dequeue_resp_ptr;
wire [PCIE_ADDR_WIDTH-1:0] tx_desc_dequeue_resp_addr;
wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_resp_cpl;
wire [REQ_TAG_WIDTH-1:0] tx_desc_dequeue_resp_tag;
wire [OP_TAG_WIDTH-1:0] tx_desc_dequeue_resp_op_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_desc_dequeue_resp_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] tx_desc_dequeue_resp_op_tag;
wire tx_desc_dequeue_resp_empty;
wire tx_desc_dequeue_resp_error;
wire tx_desc_dequeue_resp_valid;
wire tx_desc_dequeue_resp_ready;
wire [OP_TAG_WIDTH-1:0] tx_desc_dequeue_commit_op_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] tx_desc_dequeue_commit_op_tag;
wire tx_desc_dequeue_commit_valid;
wire tx_desc_dequeue_commit_ready;
@ -515,127 +553,127 @@ wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_doorbell_queue;
wire tx_doorbell_valid;
wire [PORTS*TX_QUEUE_INDEX_WIDTH-1:0] tx_port_desc_dequeue_req_queue;
wire [PORTS*REQ_TAG_WIDTH-1:0] tx_port_desc_dequeue_req_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] tx_port_desc_dequeue_req_tag;
wire [PORTS-1:0] tx_port_desc_dequeue_req_valid;
wire [PORTS-1:0] tx_port_desc_dequeue_req_ready;
wire [PORTS*QUEUE_PTR_WIDTH-1:0] tx_port_desc_dequeue_resp_ptr;
wire [PORTS*PCIE_ADDR_WIDTH-1:0] tx_port_desc_dequeue_resp_addr;
wire [PORTS*TX_CPL_QUEUE_INDEX_WIDTH-1:0] tx_port_desc_dequeue_resp_cpl;
wire [PORTS*REQ_TAG_WIDTH-1:0] tx_port_desc_dequeue_resp_tag;
wire [PORTS*OP_TAG_WIDTH-1:0] tx_port_desc_dequeue_resp_op_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] tx_port_desc_dequeue_resp_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] tx_port_desc_dequeue_resp_op_tag;
wire [PORTS-1:0] tx_port_desc_dequeue_resp_empty;
wire [PORTS-1:0] tx_port_desc_dequeue_resp_error;
wire [PORTS-1:0] tx_port_desc_dequeue_resp_valid;
wire [PORTS-1:0] tx_port_desc_dequeue_resp_ready;
wire [PORTS*OP_TAG_WIDTH-1:0] tx_port_desc_dequeue_commit_op_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] tx_port_desc_dequeue_commit_op_tag;
wire [PORTS-1:0] tx_port_desc_dequeue_commit_valid;
wire [PORTS-1:0] tx_port_desc_dequeue_commit_ready;
wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0] tx_cpl_enqueue_req_queue;
wire [REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_req_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_req_tag;
wire tx_cpl_enqueue_req_valid;
wire tx_cpl_enqueue_req_ready;
wire [PCIE_ADDR_WIDTH-1:0] tx_cpl_enqueue_resp_addr;
wire [REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_tag;
wire [OP_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_op_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_op_tag;
wire tx_cpl_enqueue_resp_full;
wire tx_cpl_enqueue_resp_error;
wire tx_cpl_enqueue_resp_valid;
wire tx_cpl_enqueue_resp_ready;
wire [OP_TAG_WIDTH-1:0] tx_cpl_enqueue_commit_op_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] tx_cpl_enqueue_commit_op_tag;
wire tx_cpl_enqueue_commit_valid;
wire tx_cpl_enqueue_commit_ready;
wire [PORTS*TX_CPL_QUEUE_INDEX_WIDTH-1:0] tx_port_cpl_enqueue_req_queue;
wire [PORTS*REQ_TAG_WIDTH-1:0] tx_port_cpl_enqueue_req_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] tx_port_cpl_enqueue_req_tag;
wire [PORTS-1:0] tx_port_cpl_enqueue_req_valid;
wire [PORTS-1:0] tx_port_cpl_enqueue_req_ready;
wire [PORTS*PCIE_ADDR_WIDTH-1:0] tx_port_cpl_enqueue_resp_addr;
wire [PORTS*REQ_TAG_WIDTH-1:0] tx_port_cpl_enqueue_resp_tag;
wire [PORTS*OP_TAG_WIDTH-1:0] tx_port_cpl_enqueue_resp_op_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] tx_port_cpl_enqueue_resp_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] tx_port_cpl_enqueue_resp_op_tag;
wire [PORTS-1:0] tx_port_cpl_enqueue_resp_full;
wire [PORTS-1:0] tx_port_cpl_enqueue_resp_error;
wire [PORTS-1:0] tx_port_cpl_enqueue_resp_valid;
wire [PORTS-1:0] tx_port_cpl_enqueue_resp_ready;
wire [PORTS*OP_TAG_WIDTH-1:0] tx_port_cpl_enqueue_commit_op_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] tx_port_cpl_enqueue_commit_op_tag;
wire [PORTS-1:0] tx_port_cpl_enqueue_commit_valid;
wire [PORTS-1:0] tx_port_cpl_enqueue_commit_ready;
wire [TX_QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_req_queue;
wire [REQ_TAG_WIDTH-1:0] rx_desc_dequeue_req_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_desc_dequeue_req_tag;
wire rx_desc_dequeue_req_valid;
wire rx_desc_dequeue_req_ready;
wire [QUEUE_PTR_WIDTH-1:0] rx_desc_dequeue_resp_ptr;
wire [PCIE_ADDR_WIDTH-1:0] rx_desc_dequeue_resp_addr;
wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_resp_cpl;
wire [REQ_TAG_WIDTH-1:0] rx_desc_dequeue_resp_tag;
wire [OP_TAG_WIDTH-1:0] rx_desc_dequeue_resp_op_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_desc_dequeue_resp_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] rx_desc_dequeue_resp_op_tag;
wire rx_desc_dequeue_resp_empty;
wire rx_desc_dequeue_resp_error;
wire rx_desc_dequeue_resp_valid;
wire rx_desc_dequeue_resp_ready;
wire [OP_TAG_WIDTH-1:0] rx_desc_dequeue_commit_op_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] rx_desc_dequeue_commit_op_tag;
wire rx_desc_dequeue_commit_valid;
wire rx_desc_dequeue_commit_ready;
wire [PORTS*RX_QUEUE_INDEX_WIDTH-1:0] rx_port_desc_dequeue_req_queue;
wire [PORTS*REQ_TAG_WIDTH-1:0] rx_port_desc_dequeue_req_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] rx_port_desc_dequeue_req_tag;
wire [PORTS-1:0] rx_port_desc_dequeue_req_valid;
wire [PORTS-1:0] rx_port_desc_dequeue_req_ready;
wire [PORTS*QUEUE_PTR_WIDTH-1:0] rx_port_desc_dequeue_resp_ptr;
wire [PORTS*PCIE_ADDR_WIDTH-1:0] rx_port_desc_dequeue_resp_addr;
wire [PORTS*RX_CPL_QUEUE_INDEX_WIDTH-1:0] rx_port_desc_dequeue_resp_cpl;
wire [PORTS*REQ_TAG_WIDTH-1:0] rx_port_desc_dequeue_resp_tag;
wire [PORTS*OP_TAG_WIDTH-1:0] rx_port_desc_dequeue_resp_op_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] rx_port_desc_dequeue_resp_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] rx_port_desc_dequeue_resp_op_tag;
wire [PORTS-1:0] rx_port_desc_dequeue_resp_empty;
wire [PORTS-1:0] rx_port_desc_dequeue_resp_error;
wire [PORTS-1:0] rx_port_desc_dequeue_resp_valid;
wire [PORTS-1:0] rx_port_desc_dequeue_resp_ready;
wire [PORTS*OP_TAG_WIDTH-1:0] rx_port_desc_dequeue_commit_op_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] rx_port_desc_dequeue_commit_op_tag;
wire [PORTS-1:0] rx_port_desc_dequeue_commit_valid;
wire [PORTS-1:0] rx_port_desc_dequeue_commit_ready;
wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0] rx_cpl_enqueue_req_queue;
wire [REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_req_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_req_tag;
wire rx_cpl_enqueue_req_valid;
wire rx_cpl_enqueue_req_ready;
wire [PCIE_ADDR_WIDTH-1:0] rx_cpl_enqueue_resp_addr;
wire [REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_tag;
wire [OP_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_op_tag;
wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_op_tag;
wire rx_cpl_enqueue_resp_full;
wire rx_cpl_enqueue_resp_error;
wire rx_cpl_enqueue_resp_valid;
wire rx_cpl_enqueue_resp_ready;
wire [OP_TAG_WIDTH-1:0] rx_cpl_enqueue_commit_op_tag;
wire [QUEUE_OP_TAG_WIDTH-1:0] rx_cpl_enqueue_commit_op_tag;
wire rx_cpl_enqueue_commit_valid;
wire rx_cpl_enqueue_commit_ready;
wire [PORTS*RX_CPL_QUEUE_INDEX_WIDTH-1:0] rx_port_cpl_enqueue_req_queue;
wire [PORTS*REQ_TAG_WIDTH-1:0] rx_port_cpl_enqueue_req_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] rx_port_cpl_enqueue_req_tag;
wire [PORTS-1:0] rx_port_cpl_enqueue_req_valid;
wire [PORTS-1:0] rx_port_cpl_enqueue_req_ready;
wire [PORTS*PCIE_ADDR_WIDTH-1:0] rx_port_cpl_enqueue_resp_addr;
wire [PORTS*REQ_TAG_WIDTH-1:0] rx_port_cpl_enqueue_resp_tag;
wire [PORTS*OP_TAG_WIDTH-1:0] rx_port_cpl_enqueue_resp_op_tag;
wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] rx_port_cpl_enqueue_resp_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] rx_port_cpl_enqueue_resp_op_tag;
wire [PORTS-1:0] rx_port_cpl_enqueue_resp_full;
wire [PORTS-1:0] rx_port_cpl_enqueue_resp_error;
wire [PORTS-1:0] rx_port_cpl_enqueue_resp_valid;
wire [PORTS-1:0] rx_port_cpl_enqueue_resp_ready;
wire [PORTS*OP_TAG_WIDTH-1:0] rx_port_cpl_enqueue_commit_op_tag;
wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] rx_port_cpl_enqueue_commit_op_tag;
wire [PORTS-1:0] rx_port_cpl_enqueue_commit_valid;
wire [PORTS-1:0] rx_port_cpl_enqueue_commit_ready;
@ -811,9 +849,9 @@ axil_interconnect_inst (
cpl_queue_manager #(
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TABLE_SIZE(EVENT_OP_TABLE_SIZE),
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.EVENT_WIDTH(INT_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
@ -898,9 +936,9 @@ if (PORTS > 1) begin
queue_op_mux #(
.PORTS(PORTS),
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.S_REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
@ -993,9 +1031,9 @@ end
queue_manager #(
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.CPL_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
@ -1079,9 +1117,9 @@ if (PORTS > 1) begin
queue_op_mux #(
.PORTS(PORTS),
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.S_REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_INDEX_WIDTH(0),
@ -1172,9 +1210,9 @@ end
cpl_queue_manager #(
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
@ -1260,9 +1298,9 @@ if (PORTS > 1) begin
queue_op_mux #(
.PORTS(PORTS),
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.S_REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
@ -1355,9 +1393,9 @@ end
queue_manager #(
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.CPL_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
@ -1441,9 +1479,9 @@ if (PORTS > 1) begin
queue_op_mux #(
.PORTS(PORTS),
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.S_REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.S_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.M_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), // TODO
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_INDEX_WIDTH(0),
@ -1534,9 +1572,9 @@ end
cpl_queue_manager #(
.ADDR_WIDTH(PCIE_ADDR_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
@ -1848,13 +1886,12 @@ event_queue #(
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
.QUEUE_REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(OP_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.EVENT_TABLE_SIZE(16),
.AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h000000),
.SCRATCH_EVENT_AXI_ADDR(AXI_BASE_ADDR + 24'h000000)
.AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h000000)
)
event_queue_inst (
.clk(clk),
@ -2318,7 +2355,8 @@ generate
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.OP_TAG_WIDTH(OP_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
@ -2344,6 +2382,8 @@ generate
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXI_BASE_ADDR(23'h000000),
.TX_RAM_AXI_BASE_ADDR(23'h000000 + 23'h010000),
.RX_RAM_AXI_BASE_ADDR(23'h000000 + 23'h020000),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH)
)
@ -2355,7 +2395,7 @@ generate
* TX descriptor dequeue request output
*/
.m_axis_tx_desc_dequeue_req_queue(tx_port_desc_dequeue_req_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]),
.m_axis_tx_desc_dequeue_req_tag(tx_port_desc_dequeue_req_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.m_axis_tx_desc_dequeue_req_tag(tx_port_desc_dequeue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.m_axis_tx_desc_dequeue_req_valid(tx_port_desc_dequeue_req_valid[n +: 1]),
.m_axis_tx_desc_dequeue_req_ready(tx_port_desc_dequeue_req_ready[n +: 1]),
@ -2365,8 +2405,8 @@ generate
.s_axis_tx_desc_dequeue_resp_ptr(tx_port_desc_dequeue_resp_ptr[n*QUEUE_PTR_WIDTH +: QUEUE_PTR_WIDTH]),
.s_axis_tx_desc_dequeue_resp_addr(tx_port_desc_dequeue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.s_axis_tx_desc_dequeue_resp_cpl(tx_port_desc_dequeue_resp_cpl[n*TX_CPL_QUEUE_INDEX_WIDTH +: TX_CPL_QUEUE_INDEX_WIDTH]),
.s_axis_tx_desc_dequeue_resp_tag(tx_port_desc_dequeue_resp_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.s_axis_tx_desc_dequeue_resp_op_tag(tx_port_desc_dequeue_resp_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.s_axis_tx_desc_dequeue_resp_tag(tx_port_desc_dequeue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.s_axis_tx_desc_dequeue_resp_op_tag(tx_port_desc_dequeue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.s_axis_tx_desc_dequeue_resp_empty(tx_port_desc_dequeue_resp_empty[n +: 1]),
.s_axis_tx_desc_dequeue_resp_error(tx_port_desc_dequeue_resp_error[n +: 1]),
.s_axis_tx_desc_dequeue_resp_valid(tx_port_desc_dequeue_resp_valid[n +: 1]),
@ -2375,7 +2415,7 @@ generate
/*
* TX descriptor dequeue commit output
*/
.m_axis_tx_desc_dequeue_commit_op_tag(tx_port_desc_dequeue_commit_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.m_axis_tx_desc_dequeue_commit_op_tag(tx_port_desc_dequeue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.m_axis_tx_desc_dequeue_commit_valid(tx_port_desc_dequeue_commit_valid[n +: 1]),
.m_axis_tx_desc_dequeue_commit_ready(tx_port_desc_dequeue_commit_ready[n +: 1]),
@ -2389,7 +2429,7 @@ generate
* TX completion enqueue request output
*/
.m_axis_tx_cpl_enqueue_req_queue(tx_port_cpl_enqueue_req_queue[n*TX_CPL_QUEUE_INDEX_WIDTH +: TX_CPL_QUEUE_INDEX_WIDTH]),
.m_axis_tx_cpl_enqueue_req_tag(tx_port_cpl_enqueue_req_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.m_axis_tx_cpl_enqueue_req_tag(tx_port_cpl_enqueue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.m_axis_tx_cpl_enqueue_req_valid(tx_port_cpl_enqueue_req_valid[n +: 1]),
.m_axis_tx_cpl_enqueue_req_ready(tx_port_cpl_enqueue_req_ready[n +: 1]),
@ -2399,8 +2439,8 @@ generate
//.s_axis_tx_cpl_enqueue_resp_ptr(),
.s_axis_tx_cpl_enqueue_resp_addr(tx_port_cpl_enqueue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
//.s_axis_tx_cpl_enqueue_resp_event(),
.s_axis_tx_cpl_enqueue_resp_tag(tx_port_cpl_enqueue_resp_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.s_axis_tx_cpl_enqueue_resp_op_tag(tx_port_cpl_enqueue_resp_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.s_axis_tx_cpl_enqueue_resp_tag(tx_port_cpl_enqueue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.s_axis_tx_cpl_enqueue_resp_op_tag(tx_port_cpl_enqueue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.s_axis_tx_cpl_enqueue_resp_full(tx_port_cpl_enqueue_resp_full[n +: 1]),
.s_axis_tx_cpl_enqueue_resp_error(tx_port_cpl_enqueue_resp_error[n +: 1]),
.s_axis_tx_cpl_enqueue_resp_valid(tx_port_cpl_enqueue_resp_valid[n +: 1]),
@ -2409,7 +2449,7 @@ generate
/*
* TX completion enqueue commit output
*/
.m_axis_tx_cpl_enqueue_commit_op_tag(tx_port_cpl_enqueue_commit_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.m_axis_tx_cpl_enqueue_commit_op_tag(tx_port_cpl_enqueue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.m_axis_tx_cpl_enqueue_commit_valid(tx_port_cpl_enqueue_commit_valid[n +: 1]),
.m_axis_tx_cpl_enqueue_commit_ready(tx_port_cpl_enqueue_commit_ready[n +: 1]),
@ -2417,7 +2457,7 @@ generate
* RX descriptor dequeue request output
*/
.m_axis_rx_desc_dequeue_req_queue(rx_port_desc_dequeue_req_queue[n*RX_QUEUE_INDEX_WIDTH +: RX_QUEUE_INDEX_WIDTH]),
.m_axis_rx_desc_dequeue_req_tag(rx_port_desc_dequeue_req_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.m_axis_rx_desc_dequeue_req_tag(rx_port_desc_dequeue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.m_axis_rx_desc_dequeue_req_valid(rx_port_desc_dequeue_req_valid[n +: 1]),
.m_axis_rx_desc_dequeue_req_ready(rx_port_desc_dequeue_req_ready[n +: 1]),
@ -2427,8 +2467,8 @@ generate
.s_axis_rx_desc_dequeue_resp_ptr(rx_port_desc_dequeue_resp_ptr[n*QUEUE_PTR_WIDTH +: QUEUE_PTR_WIDTH]),
.s_axis_rx_desc_dequeue_resp_addr(rx_port_desc_dequeue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
.s_axis_rx_desc_dequeue_resp_cpl(rx_port_desc_dequeue_resp_cpl[n*RX_CPL_QUEUE_INDEX_WIDTH +: RX_CPL_QUEUE_INDEX_WIDTH]),
.s_axis_rx_desc_dequeue_resp_tag(rx_port_desc_dequeue_resp_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.s_axis_rx_desc_dequeue_resp_op_tag(rx_port_desc_dequeue_resp_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.s_axis_rx_desc_dequeue_resp_tag(rx_port_desc_dequeue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.s_axis_rx_desc_dequeue_resp_op_tag(rx_port_desc_dequeue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.s_axis_rx_desc_dequeue_resp_empty(rx_port_desc_dequeue_resp_empty[n +: 1]),
.s_axis_rx_desc_dequeue_resp_error(rx_port_desc_dequeue_resp_error[n +: 1]),
.s_axis_rx_desc_dequeue_resp_valid(rx_port_desc_dequeue_resp_valid[n +: 1]),
@ -2437,7 +2477,7 @@ generate
/*
* RX descriptor dequeue commit output
*/
.m_axis_rx_desc_dequeue_commit_op_tag(rx_port_desc_dequeue_commit_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.m_axis_rx_desc_dequeue_commit_op_tag(rx_port_desc_dequeue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.m_axis_rx_desc_dequeue_commit_valid(rx_port_desc_dequeue_commit_valid[n +: 1]),
.m_axis_rx_desc_dequeue_commit_ready(rx_port_desc_dequeue_commit_ready[n +: 1]),
@ -2445,7 +2485,7 @@ generate
* RX completion enqueue request output
*/
.m_axis_rx_cpl_enqueue_req_queue(rx_port_cpl_enqueue_req_queue[n*RX_CPL_QUEUE_INDEX_WIDTH +: RX_CPL_QUEUE_INDEX_WIDTH]),
.m_axis_rx_cpl_enqueue_req_tag(rx_port_cpl_enqueue_req_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.m_axis_rx_cpl_enqueue_req_tag(rx_port_cpl_enqueue_req_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.m_axis_rx_cpl_enqueue_req_valid(rx_port_cpl_enqueue_req_valid[n +: 1]),
.m_axis_rx_cpl_enqueue_req_ready(rx_port_cpl_enqueue_req_ready[n +: 1]),
@ -2455,8 +2495,8 @@ generate
//.s_axis_rx_cpl_enqueue_resp_ptr(),
.s_axis_rx_cpl_enqueue_resp_addr(rx_port_cpl_enqueue_resp_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]),
//.s_axis_rx_cpl_enqueue_resp_event(),
.s_axis_rx_cpl_enqueue_resp_tag(rx_port_cpl_enqueue_resp_tag[n*REQ_TAG_WIDTH +: REQ_TAG_WIDTH]),
.s_axis_rx_cpl_enqueue_resp_op_tag(rx_port_cpl_enqueue_resp_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.s_axis_rx_cpl_enqueue_resp_tag(rx_port_cpl_enqueue_resp_tag[n*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH]),
.s_axis_rx_cpl_enqueue_resp_op_tag(rx_port_cpl_enqueue_resp_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.s_axis_rx_cpl_enqueue_resp_full(rx_port_cpl_enqueue_resp_full[n +: 1]),
.s_axis_rx_cpl_enqueue_resp_error(rx_port_cpl_enqueue_resp_error[n +: 1]),
.s_axis_rx_cpl_enqueue_resp_valid(rx_port_cpl_enqueue_resp_valid[n +: 1]),
@ -2465,7 +2505,7 @@ generate
/*
* RX completion enqueue commit output
*/
.m_axis_rx_cpl_enqueue_commit_op_tag(rx_port_cpl_enqueue_commit_op_tag[n*OP_TAG_WIDTH +: OP_TAG_WIDTH]),
.m_axis_rx_cpl_enqueue_commit_op_tag(rx_port_cpl_enqueue_commit_op_tag[n*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH]),
.m_axis_rx_cpl_enqueue_commit_valid(rx_port_cpl_enqueue_commit_valid[n +: 1]),
.m_axis_rx_cpl_enqueue_commit_ready(rx_port_cpl_enqueue_commit_ready[n +: 1]),

86
fpga/common/rtl/port.v
View File

@ -40,37 +40,73 @@ either expressed or implied, of The Regents of the University of California.
*/
module port #
(
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 16,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// Request tag field width
parameter REQ_TAG_WIDTH = 8,
parameter OP_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Transmit queue index width
parameter TX_QUEUE_INDEX_WIDTH = 8,
// Receive queue index width
parameter RX_QUEUE_INDEX_WIDTH = 8,
// Transmit completion queue index width
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
// Receive completion queue index width
parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
// Transmit descriptor table size (number of in-flight operations)
parameter TX_DESC_TABLE_SIZE = 16,
// Transmit packet table size (number of in-progress packets)
parameter TX_PKT_TABLE_SIZE = 8,
// Receive descriptor table size (number of in-flight operations)
parameter RX_DESC_TABLE_SIZE = 16,
// Receive packet table size (number of in-progress packets)
parameter RX_PKT_TABLE_SIZE = 8,
// Transmit scheduler type
parameter TX_SCHEDULER = "RR",
// Scheduler TDMA index width
parameter TDMA_INDEX_WIDTH = 8,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
parameter QUEUE_LOG_SIZE_WIDTH = 4,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1,
// Enable RX checksum offload
parameter RX_CHECKSUM_ENABLE = 1,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Maximum AXI burst length to generate
parameter AXI_MAX_BURST_LEN = 16,
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 0,
// AXI base address of TX packet RAM (as seen by PCIe DMA and AXI DMA in this module)
parameter TX_RAM_AXI_BASE_ADDR = 0,
// AXI base address of RX packet RAM (as seen by PCIe DMA and AXI DMA in this module)
parameter RX_RAM_AXI_BASE_ADDR = 0,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH
)
(
@ -81,7 +117,7 @@ module port #
* TX descriptor dequeue request output
*/
output wire [TX_QUEUE_INDEX_WIDTH-1:0] m_axis_tx_desc_dequeue_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_desc_dequeue_req_tag,
output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_tx_desc_dequeue_req_tag,
output wire m_axis_tx_desc_dequeue_req_valid,
input wire m_axis_tx_desc_dequeue_req_ready,
@ -91,8 +127,8 @@ module port #
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_ptr,
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_addr,
input wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_cpl,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_tag,
input wire [OP_TAG_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_op_tag,
input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_tag,
input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_tx_desc_dequeue_resp_op_tag,
input wire s_axis_tx_desc_dequeue_resp_empty,
input wire s_axis_tx_desc_dequeue_resp_error,
input wire s_axis_tx_desc_dequeue_resp_valid,
@ -101,7 +137,7 @@ module port #
/*
* TX descriptor dequeue commit output
*/
output wire [OP_TAG_WIDTH-1:0] m_axis_tx_desc_dequeue_commit_op_tag,
output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_tx_desc_dequeue_commit_op_tag,
output wire m_axis_tx_desc_dequeue_commit_valid,
input wire m_axis_tx_desc_dequeue_commit_ready,
@ -115,7 +151,7 @@ module port #
* TX completion enqueue request output
*/
output wire [TX_CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_tx_cpl_enqueue_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_cpl_enqueue_req_tag,
output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_tx_cpl_enqueue_req_tag,
output wire m_axis_tx_cpl_enqueue_req_valid,
input wire m_axis_tx_cpl_enqueue_req_ready,
@ -125,8 +161,8 @@ module port #
//input wire [QUEUE_PTR_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_ptr,
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_addr,
//input wire [EVENT_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_event,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_tag,
input wire [OP_TAG_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_op_tag,
input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_tag,
input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_tx_cpl_enqueue_resp_op_tag,
input wire s_axis_tx_cpl_enqueue_resp_full,
input wire s_axis_tx_cpl_enqueue_resp_error,
input wire s_axis_tx_cpl_enqueue_resp_valid,
@ -135,7 +171,7 @@ module port #
/*
* TX completion enqueue commit output
*/
output wire [OP_TAG_WIDTH-1:0] m_axis_tx_cpl_enqueue_commit_op_tag,
output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_tx_cpl_enqueue_commit_op_tag,
output wire m_axis_tx_cpl_enqueue_commit_valid,
input wire m_axis_tx_cpl_enqueue_commit_ready,
@ -143,7 +179,7 @@ module port #
* RX descriptor dequeue request output
*/
output wire [RX_QUEUE_INDEX_WIDTH-1:0] m_axis_rx_desc_dequeue_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_rx_desc_dequeue_req_tag,
output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_rx_desc_dequeue_req_tag,
output wire m_axis_rx_desc_dequeue_req_valid,
input wire m_axis_rx_desc_dequeue_req_ready,
@ -153,8 +189,8 @@ module port #
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_ptr,
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_addr,
input wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_cpl,
input wire [REQ_TAG_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_tag,
input wire [OP_TAG_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_op_tag,
input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_tag,
input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_rx_desc_dequeue_resp_op_tag,
input wire s_axis_rx_desc_dequeue_resp_empty,
input wire s_axis_rx_desc_dequeue_resp_error,
input wire s_axis_rx_desc_dequeue_resp_valid,
@ -163,7 +199,7 @@ module port #
/*
* RX descriptor dequeue commit output
*/
output wire [OP_TAG_WIDTH-1:0] m_axis_rx_desc_dequeue_commit_op_tag,
output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_rx_desc_dequeue_commit_op_tag,
output wire m_axis_rx_desc_dequeue_commit_valid,
input wire m_axis_rx_desc_dequeue_commit_ready,
@ -171,7 +207,7 @@ module port #
* RX completion enqueue request output
*/
output wire [RX_CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_rx_cpl_enqueue_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_rx_cpl_enqueue_req_tag,
output wire [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_rx_cpl_enqueue_req_tag,
output wire m_axis_rx_cpl_enqueue_req_valid,
input wire m_axis_rx_cpl_enqueue_req_ready,
@ -181,8 +217,8 @@ module port #
//input wire [QUEUE_PTR_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_ptr,
input wire [PCIE_ADDR_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_addr,
//input wire [EVENT_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_event,
input wire [REQ_TAG_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_tag,
input wire [OP_TAG_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_op_tag,
input wire [QUEUE_REQ_TAG_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_tag,
input wire [QUEUE_OP_TAG_WIDTH-1:0] s_axis_rx_cpl_enqueue_resp_op_tag,
input wire s_axis_rx_cpl_enqueue_resp_full,
input wire s_axis_rx_cpl_enqueue_resp_error,
input wire s_axis_rx_cpl_enqueue_resp_valid,
@ -191,7 +227,7 @@ module port #
/*
* RX completion enqueue commit output
*/
output wire [OP_TAG_WIDTH-1:0] m_axis_rx_cpl_enqueue_commit_op_tag,
output wire [QUEUE_OP_TAG_WIDTH-1:0] m_axis_rx_cpl_enqueue_commit_op_tag,
output wire m_axis_rx_cpl_enqueue_commit_valid,
input wire m_axis_rx_cpl_enqueue_commit_ready,
@ -852,16 +888,15 @@ tx_engine #(
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
.AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(OP_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE),
.AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h004000),
.SCRATCH_DESC_AXI_ADDR(AXI_BASE_ADDR + 24'h004000),
.SCRATCH_PKT_AXI_ADDR(AXI_BASE_ADDR + 24'h010000),
.SCRATCH_PKT_AXI_ADDR(TX_RAM_AXI_BASE_ADDR),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE)
)
@ -1088,16 +1123,15 @@ rx_engine #(
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.PCIE_DMA_TAG_WIDTH(PCIE_DMA_TAG_WIDTH_INT),
.AXI_DMA_TAG_WIDTH(AXI_DMA_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(OP_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
.AXI_BASE_ADDR(AXI_BASE_ADDR + 24'h006000),
.SCRATCH_DESC_AXI_ADDR(AXI_BASE_ADDR + 24'h006000),
.SCRATCH_PKT_AXI_ADDR(AXI_BASE_ADDR + 24'h020000),
.SCRATCH_PKT_AXI_ADDR(RX_RAM_AXI_BASE_ADDR),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE)
)

28
fpga/common/rtl/queue_manager.v
View File

@ -40,19 +40,33 @@ either expressed or implied, of The Regents of the University of California.
*/
module queue_manager #
(
// Base address width
parameter ADDR_WIDTH = 64,
// Request tag field width
parameter REQ_TAG_WIDTH = 8,
// Number of outstanding operations
parameter OP_TABLE_SIZE = 16,
// Operation tag field width
parameter OP_TAG_WIDTH = 8,
// Queue index width (log2 of number of queues)
parameter QUEUE_INDEX_WIDTH = 8,
// Completion queue index width
parameter CPL_INDEX_WIDTH = 8,
// Queue element pointer width (log2 of number of elements)
parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width
parameter QUEUE_LOG_SIZE_WIDTH = $clog2(QUEUE_PTR_WIDTH),
// Queue element size
parameter DESC_SIZE = 16,
// Read pipeline stages
parameter READ_PIPELINE = 2,
// Write pipeline stages
parameter WRITE_PIPELINE = 1,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8)
)
(
@ -133,37 +147,37 @@ parameter PIPELINE = READ_PIPELINE + WRITE_PIPELINE;
// bus width assertions
initial begin
if (OP_TAG_WIDTH < CL_OP_TABLE_SIZE) begin
$error("Error: OP_TAG_WDITH insufficient for OP_TABLE_SIZE");
$error("Error: OP_TAG_WDITH insufficient for OP_TABLE_SIZE (instance %m)");
$finish;
end
if (AXIL_DATA_WIDTH != 32) begin
$error("Error: AXI lite interface width must be 32");
$error("Error: AXI lite interface width must be 32 (instance %m)");
$finish;
end
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
$error("Error: AXI lite interface requires byte (8-bit) granularity");
$error("Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXIL_ADDR_WIDTH < QUEUE_INDEX_WIDTH+5) begin
$error("Error: AXI lite address width too narrow");
$error("Error: AXI lite address width too narrow (instance %m)");
$finish;
end
if (2**$clog2(DESC_SIZE) != DESC_SIZE) begin
$error("Error: Descriptor size must be even power of two");
$error("Error: Descriptor size must be even power of two (instance %m)");
$finish;
end
if (READ_PIPELINE < 1) begin
$error("Error: READ_PIPELINE must be at least 1");
$error("Error: READ_PIPELINE must be at least 1 (instance %m)");
$finish;
end
if (WRITE_PIPELINE < 1) begin
$error("Error: WRITE_PIPELINE must be at least 1");
$error("Error: WRITE_PIPELINE must be at least 1 (instance %m)");
$finish;
end
end

6
fpga/common/rtl/rx_checksum.v
View File

@ -40,7 +40,9 @@ either expressed or implied, of The Regents of the University of California.
*/
module rx_checksum #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
@ -65,12 +67,12 @@ module rx_checksum #
// bus width assertions
initial begin
if (DATA_WIDTH != 256) begin
$error("Error: AXI stream interface width must be 256");
$error("Error: AXI stream interface width must be 256 (instance %m)");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity");
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end

50
fpga/common/rtl/rx_engine.v
View File

@ -40,30 +40,51 @@ either expressed or implied, of The Regents of the University of California.
*/
module rx_engine #
(
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 20,
// AXI DMA length field width
parameter AXI_DMA_LEN_WIDTH = 20,
// Receive request tag field width
parameter REQ_TAG_WIDTH = 8,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// AXI DMA tag field width
parameter AXI_DMA_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 4,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = 4,
// Descriptor table size (number of in-flight operations)
parameter DESC_TABLE_SIZE = 8,
// Packet table size (number of in-progress packets)
parameter PKT_TABLE_SIZE = 8,
// Max receive packet size
parameter MAX_RX_SIZE = 2048,
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 16'h0000,
parameter SCRATCH_DESC_AXI_ADDR = 16'h0000,
parameter SCRATCH_DESC_AXI_ADDR_SHIFT = 5,
// AXI address of packet scratchpad RAM (as seen by PCIe DMA and port AXI DMA)
parameter SCRATCH_PKT_AXI_ADDR = 16'h1000,
// Packet scratchpad RAM log segment size
parameter SCRATCH_PKT_AXI_ADDR_SHIFT = 12,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// Enable RX checksum offload
parameter RX_CHECKSUM_ENABLE = 1
)
(
@ -266,37 +287,42 @@ parameter BLOCK_SIZE = DESC_SIZE > CPL_SIZE ? DESC_SIZE : CPL_SIZE;
// bus width assertions
initial begin
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
$error("Error: PCIe tag width insufficient for descriptor table size");
$error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: AXI tag width insufficient for descriptor table size");
$error("Error: AXI tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH < BLOCK_SIZE) begin
$error("Error: AXI interface width must be at least as large as one descriptor");
$error("Error: AXI interface width must be at least as large as one descriptor (instance %m)");
$finish;
end
if (SCRATCH_DESC_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: Descriptor scratch address must be aligned to interface width");
if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_DESC_AXI_ADDR_SHIFT < $clog2(AXI_STRB_WIDTH)) begin
$error("Error: Descriptor scratch address increment must be aligned to interface width");
if (SCRATCH_PKT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_DESC_AXI_ADDR_SHIFT < $clog2(BLOCK_SIZE)) begin
$error("Error: Descriptor scratch address increment must be at least as large as one descriptor");
if (SCRATCH_PKT_AXI_ADDR_SHIFT < $clog2(AXI_STRB_WIDTH)) begin
$error("Error: Packet scratch address increment must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_PKT_AXI_ADDR_SHIFT < $clog2(MAX_RX_SIZE)) begin
$error("Error: Packet scratch address increment must be at least as large as one packet (instance %m)");
$finish;
end
end

20
fpga/common/rtl/tdma_ber.v
View File

@ -40,19 +40,33 @@ either expressed or implied, of The Regents of the University of California.
*/
module tdma_ber #
(
// Channel count
parameter COUNT = 1,
// Timeslot index width
parameter INDEX_WIDTH = 6,
// Slice index width
parameter SLICE_WIDTH = 5,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = INDEX_WIDTH+4+1+$clog2(COUNT),
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// Schedule absolute PTP start time, seconds part
parameter SCHEDULE_START_S = 48'h0,
// Schedule absolute PTP start time, nanoseconds part
parameter SCHEDULE_START_NS = 30'h0,
// Schedule period, seconds part
parameter SCHEDULE_PERIOD_S = 48'd0,
// Schedule period, nanoseconds part
parameter SCHEDULE_PERIOD_NS = 30'd1000000,
// Timeslot period, seconds part
parameter TIMESLOT_PERIOD_S = 48'd0,
// Timeslot period, nanoseconds part
parameter TIMESLOT_PERIOD_NS = 30'd100000,
// Timeslot active period, seconds part
parameter ACTIVE_PERIOD_S = 48'd0,
// Timeslot active period, nanoseconds part
parameter ACTIVE_PERIOD_NS = 30'd100000
)
(
@ -101,17 +115,17 @@ module tdma_ber #
// check configuration
initial begin
if (AXIL_ADDR_WIDTH < INDEX_WIDTH+4+1+$clog2(COUNT)) begin
$error("Error: AXI address width too narrow");
$error("Error: AXI address width too narrow (instance %m)");
$finish;
end
if (AXIL_DATA_WIDTH != 32) begin
$error("Error: AXI data width must be 32");
$error("Error: AXI data width must be 32 (instance %m)");
$finish;
end
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$error("Error: Interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end

11
fpga/common/rtl/tdma_ber_ch.v
View File

@ -40,10 +40,15 @@ either expressed or implied, of The Regents of the University of California.
*/
module tdma_ber_ch #
(
// Timeslot index width
parameter INDEX_WIDTH = 6,
// Slice index width
parameter SLICE_WIDTH = 5,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = INDEX_WIDTH+4,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8)
)
(
@ -97,17 +102,17 @@ parameter WORD_SIZE = AXIL_DATA_WIDTH/WORD_WIDTH;
// check configuration
initial begin
if (AXIL_ADDR_WIDTH < INDEX_WIDTH+4) begin
$error("Error: AXI address width too narrow");
$error("Error: AXI address width too narrow (instance %m)");
$finish;
end
if (AXIL_DATA_WIDTH != 32) begin
$error("Error: AXI data width must be 32");
$error("Error: AXI data width must be 32 (instance %m)");
$finish;
end
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$error("Error: Interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end

9
fpga/common/rtl/tdma_scheduler.v
View File

@ -40,14 +40,23 @@ either expressed or implied, of The Regents of the University of California.
*/
module tdma_scheduler #
(
// Timeslot index width
parameter INDEX_WIDTH = 8,
// Schedule absolute PTP start time, seconds part
parameter SCHEDULE_START_S = 48'h0,
// Schedule absolute PTP start time, nanoseconds part
parameter SCHEDULE_START_NS = 30'h0,
// Schedule period, seconds part
parameter SCHEDULE_PERIOD_S = 48'd0,
// Schedule period, nanoseconds part
parameter SCHEDULE_PERIOD_NS = 30'd1000000,
// Timeslot period, seconds part
parameter TIMESLOT_PERIOD_S = 48'd0,
// Timeslot period, nanoseconds part
parameter TIMESLOT_PERIOD_NS = 30'd100000,
// Timeslot active period, seconds part
parameter ACTIVE_PERIOD_S = 48'd0,
// Timeslot active period, nanoseconds part
parameter ACTIVE_PERIOD_NS = 30'd100000
)
(

44
fpga/common/rtl/tx_engine.v
View File

@ -40,29 +40,49 @@ either expressed or implied, of The Regents of the University of California.
*/
module tx_engine #
(
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = 256,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 16,
// Width of AXI wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// PCIe address width
parameter PCIE_ADDR_WIDTH = 64,
// PCIe DMA length field width
parameter PCIE_DMA_LEN_WIDTH = 20,
// AXI DMA length field width
parameter AXI_DMA_LEN_WIDTH = 20,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// PCIe DMA tag field width
parameter PCIE_DMA_TAG_WIDTH = 8,
// AXI DMA tag field width
parameter AXI_DMA_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 4,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = 4,
// Descriptor table size (number of in-flight operations)
parameter DESC_TABLE_SIZE = 8,
// Packet table size (number of in-progress packets)
parameter PKT_TABLE_SIZE = 8,
// AXI base address of this module (as seen by PCIe DMA)
parameter AXI_BASE_ADDR = 16'h0000,
parameter SCRATCH_DESC_AXI_ADDR = 16'h0000,
parameter SCRATCH_DESC_AXI_ADDR_SHIFT = 5,
// AXI address of packet scratchpad RAM (as seen by PCIe DMA and port AXI DMA)
parameter SCRATCH_PKT_AXI_ADDR = 16'h1000,
// Packet scratchpad RAM log segment size
parameter SCRATCH_PKT_AXI_ADDR_SHIFT = 12,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1
)
(
@ -257,37 +277,37 @@ parameter BLOCK_SIZE = DESC_SIZE > CPL_SIZE ? DESC_SIZE : CPL_SIZE;
// bus width assertions
initial begin
if (PCIE_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
$error("Error: PCIe tag width insufficient for descriptor table size");
$error("Error: PCIe tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
$error("Error: AXI tag width insufficient for descriptor table size");
$error("Error: AXI tag width insufficient for descriptor table size (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH < BLOCK_SIZE) begin
$error("Error: AXI interface width must be at least as large as one descriptor");
$error("Error: AXI interface width must be at least as large as one descriptor (instance %m)");
$finish;
end
if (SCRATCH_DESC_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: Descriptor scratch address must be aligned to interface width");
if (AXI_BASE_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_DESC_AXI_ADDR_SHIFT < $clog2(AXI_STRB_WIDTH)) begin
$error("Error: Descriptor scratch address increment must be aligned to interface width");
if (SCRATCH_PKT_AXI_ADDR[$clog2(AXI_STRB_WIDTH)-1:0]) begin
$error("Error: AXI base address must be aligned to interface width (instance %m)");
$finish;
end
if (SCRATCH_DESC_AXI_ADDR_SHIFT < $clog2(BLOCK_SIZE)) begin
$error("Error: Descriptor scratch address increment must be at least as large as one descriptor");
if (SCRATCH_PKT_AXI_ADDR_SHIFT < $clog2(AXI_STRB_WIDTH)) begin
$error("Error: Packet scratch address increment must be aligned to interface width (instance %m)");
$finish;
end
end

12
fpga/common/rtl/tx_scheduler_rr.v
View File

@ -40,11 +40,17 @@ either expressed or implied, of The Regents of the University of California.
*/
module tx_scheduler_rr #
(
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// AXI DMA length field width
parameter AXI_DMA_LEN_WIDTH = 16,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 6
)
(
@ -103,17 +109,17 @@ parameter WORD_SIZE = AXIL_DATA_WIDTH/WORD_WIDTH;
// check configuration
initial begin
if (AXIL_ADDR_WIDTH < 18) begin // TODO
$error("Error: AXI address width too narrow");
$error("Error: AXI address width too narrow (instance %m)");
$finish;
end
if (AXIL_DATA_WIDTH != 32) begin
$error("Error: AXI data width must be 32");
$error("Error: AXI data width must be 32 (instance %m)");
$finish;
end
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$error("Error: Interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end

21
fpga/common/rtl/tx_scheduler_tdma_rr.v
View File

@ -40,20 +40,35 @@ either expressed or implied, of The Regents of the University of California.
*/
module tx_scheduler_tdma_rr #
(
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 16,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// AXI DMA length field width
parameter AXI_DMA_LEN_WIDTH = 16,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// TDMA timeslot index width
parameter TDMA_INDEX_WIDTH = 6,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 6,
// Schedule absolute PTP start time, seconds part
parameter SCHEDULE_START_S = 48'h0,
// Schedule absolute PTP start time, nanoseconds part
parameter SCHEDULE_START_NS = 30'h0,
// Schedule period, seconds part
parameter SCHEDULE_PERIOD_S = 48'd0,
// Schedule period, nanoseconds part
parameter SCHEDULE_PERIOD_NS = 30'd1000000,
// Timeslot period, seconds part
parameter TIMESLOT_PERIOD_S = 48'd0,
// Timeslot period, nanoseconds part
parameter TIMESLOT_PERIOD_NS = 30'd100000,
// Timeslot active period, seconds part
parameter ACTIVE_PERIOD_S = 48'd0,
// Timeslot active period, nanoseconds part
parameter ACTIVE_PERIOD_NS = 30'd100000
)
(
@ -118,17 +133,17 @@ parameter WORD_SIZE = AXIL_DATA_WIDTH/WORD_WIDTH;
// check configuration
initial begin
if (AXIL_ADDR_WIDTH < 18) begin // TODO
$error("Error: AXI address width too narrow");
$error("Error: AXI address width too narrow (instance %m)");
$finish;
end
if (AXIL_DATA_WIDTH != 32) begin
$error("Error: AXI data width must be 32");
$error("Error: AXI data width must be 32 (instance %m)");
$finish;
end
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$error("Error: Interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end

18
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -287,10 +287,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 32;
parameter RX_OP_TABLE_SIZE = 32;
parameter TX_CPL_OP_TABLE_SIZE = 32;
parameter RX_CPL_OP_TABLE_SIZE = 32;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_INDEX_WIDTH = 8;
parameter RX_QUEUE_INDEX_WIDTH = 8;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8;
@ -1951,10 +1952,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),

18
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -225,10 +225,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 16;
parameter RX_OP_TABLE_SIZE = 16;
parameter TX_CPL_OP_TABLE_SIZE = 16;
parameter RX_CPL_OP_TABLE_SIZE = 16;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_INDEX_WIDTH = 6;
parameter RX_QUEUE_INDEX_WIDTH = 6;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
@ -1915,10 +1916,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),

18
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -251,10 +251,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 16;
parameter RX_OP_TABLE_SIZE = 16;
parameter TX_CPL_OP_TABLE_SIZE = 16;
parameter RX_CPL_OP_TABLE_SIZE = 16;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_INDEX_WIDTH = 6;
parameter RX_QUEUE_INDEX_WIDTH = 6;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
@ -1993,10 +1994,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),

18
fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -288,10 +288,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 32;
parameter RX_OP_TABLE_SIZE = 32;
parameter TX_CPL_OP_TABLE_SIZE = 32;
parameter RX_CPL_OP_TABLE_SIZE = 32;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_INDEX_WIDTH = 8;
parameter RX_QUEUE_INDEX_WIDTH = 8;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8;
@ -1887,10 +1888,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),

18
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -287,10 +287,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 32;
parameter RX_OP_TABLE_SIZE = 32;
parameter TX_CPL_OP_TABLE_SIZE = 32;
parameter RX_CPL_OP_TABLE_SIZE = 32;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_INDEX_WIDTH = 8;
parameter RX_QUEUE_INDEX_WIDTH = 8;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8;
@ -1951,10 +1952,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),

18
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -225,10 +225,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 16;
parameter RX_OP_TABLE_SIZE = 16;
parameter TX_CPL_OP_TABLE_SIZE = 16;
parameter RX_CPL_OP_TABLE_SIZE = 16;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_INDEX_WIDTH = 6;
parameter RX_QUEUE_INDEX_WIDTH = 6;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
@ -1915,10 +1916,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),

18
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -251,10 +251,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 16;
parameter RX_OP_TABLE_SIZE = 16;
parameter TX_CPL_OP_TABLE_SIZE = 16;
parameter RX_CPL_OP_TABLE_SIZE = 16;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 16;
parameter TX_QUEUE_INDEX_WIDTH = 6;
parameter RX_QUEUE_INDEX_WIDTH = 6;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
@ -1993,10 +1994,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),

18
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -288,10 +288,11 @@ parameter PORTS_PER_IF = 1;
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
// Queue manager parameters (interface)
parameter TX_OP_TABLE_SIZE = 32;
parameter RX_OP_TABLE_SIZE = 32;
parameter TX_CPL_OP_TABLE_SIZE = 32;
parameter RX_CPL_OP_TABLE_SIZE = 32;
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 32;
parameter TX_QUEUE_INDEX_WIDTH = 8;
parameter RX_QUEUE_INDEX_WIDTH = 8;
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8;
@ -1887,10 +1888,11 @@ generate
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH),
.PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH),
.TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE),
.RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE),
.TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE),
.RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE),
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),