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Code Issues Projects Releases Wiki Activity

Update UDP modules and example designs to utilize UDP checksum modules

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This commit is contained in:
Alex Forencich 2016-09-30 22:15:21 -07:00
parent 4e522e52af
commit 270641b7a3
30 changed files with 74 additions and 54 deletions
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1
example/ATLYS/fpga/fpga/Makefile
View File

@ -27,6 +27,7 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
SYN_FILES += lib/eth/rtl/udp_complete.v
SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
SYN_FILES += lib/eth/rtl/udp.v
SYN_FILES += lib/eth/rtl/udp_ip_rx.v
SYN_FILES += lib/eth/rtl/udp_ip_tx.v

4
example/ATLYS/fpga/rtl/fpga_core.v
View File

@ -437,9 +437,7 @@ eth_axis_tx_inst (
.busy()
);
udp_complete #(
.UDP_CHECKSUM_ENABLE(0)
)
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),

1
example/ATLYS/fpga/tb/test_fpga_core.py
View File

@ -50,6 +50,7 @@ srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx.v")
srcs.append("../lib/eth/rtl/eth_axis_tx.v")
srcs.append("../lib/eth/rtl/udp_complete.v")
srcs.append("../lib/eth/rtl/udp_checksum_gen.v")
srcs.append("../lib/eth/rtl/udp.v")
srcs.append("../lib/eth/rtl/udp_ip_rx.v")
srcs.append("../lib/eth/rtl/udp_ip_tx.v")

1
example/DE5-Net/fpga/fpga/Makefile
View File

@ -20,6 +20,7 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/rtl/udp_complete_64.v
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
SYN_FILES += lib/eth/rtl/udp_64.v
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v

4
example/DE5-Net/fpga/rtl/fpga_core.v
View File

@ -421,9 +421,7 @@ eth_axis_tx_inst (
.busy()
);
udp_complete_64 #(
.UDP_CHECKSUM_ENABLE(0)
)
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),

1
example/DE5-Net/fpga/tb/test_fpga_core.py
View File

@ -45,6 +45,7 @@ srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/rtl/udp_complete_64.v")
srcs.append("../lib/eth/rtl/udp_checksum_gen_64.v")
srcs.append("../lib/eth/rtl/udp_64.v")
srcs.append("../lib/eth/rtl/udp_ip_rx_64.v")
srcs.append("../lib/eth/rtl/udp_ip_tx_64.v")

1
example/HXT100G/fpga/fpga/Makefile
View File

@ -25,6 +25,7 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/rtl/udp_complete_64.v
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
SYN_FILES += lib/eth/rtl/udp_64.v
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v

4
example/HXT100G/fpga/rtl/fpga_core.v
View File

@ -565,9 +565,7 @@ eth_axis_tx_inst (
.busy()
);
udp_complete_64 #(
.UDP_CHECKSUM_ENABLE(0)
)
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),

1
example/HXT100G/fpga/tb/test_fpga_core.py
View File

@ -45,6 +45,7 @@ srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/rtl/udp_complete_64.v")
srcs.append("../lib/eth/rtl/udp_checksum_gen_64.v")
srcs.append("../lib/eth/rtl/udp_64.v")
srcs.append("../lib/eth/rtl/udp_ip_rx_64.v")
srcs.append("../lib/eth/rtl/udp_ip_tx_64.v")

1
example/NexysVideo/fpga/fpga/Makefile
View File

@ -23,6 +23,7 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
SYN_FILES += lib/eth/rtl/udp_complete.v
SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
SYN_FILES += lib/eth/rtl/udp.v
SYN_FILES += lib/eth/rtl/udp_ip_rx.v
SYN_FILES += lib/eth/rtl/udp_ip_tx.v

4
example/NexysVideo/fpga/rtl/fpga_core.v
View File

@ -438,9 +438,7 @@ eth_axis_tx_inst (
.busy()
);
udp_complete #(
.UDP_CHECKSUM_ENABLE(0)
)
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),

1
example/NexysVideo/fpga/tb/test_fpga_core.py
View File

@ -50,6 +50,7 @@ srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx.v")
srcs.append("../lib/eth/rtl/eth_axis_tx.v")
srcs.append("../lib/eth/rtl/udp_complete.v")
srcs.append("../lib/eth/rtl/udp_checksum_gen.v")
srcs.append("../lib/eth/rtl/udp.v")
srcs.append("../lib/eth/rtl/udp_ip_rx.v")
srcs.append("../lib/eth/rtl/udp_ip_tx.v")

1
example/VCU108/fpga_10g/fpga/Makefile
View File

@ -24,6 +24,7 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/rtl/udp_complete_64.v
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
SYN_FILES += lib/eth/rtl/udp_64.v
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v

4
example/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -687,9 +687,7 @@ eth_axis_tx_inst (
.busy()
);
udp_complete_64 #(
.UDP_CHECKSUM_ENABLE(0)
)
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),

1
example/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -52,6 +52,7 @@ srcs.append("../lib/eth/rtl/eth_axis_tx.v")
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/rtl/udp_complete_64.v")
srcs.append("../lib/eth/rtl/udp_checksum_gen_64.v")
srcs.append("../lib/eth/rtl/udp_64.v")
srcs.append("../lib/eth/rtl/udp_ip_rx_64.v")
srcs.append("../lib/eth/rtl/udp_ip_tx_64.v")

1
example/VCU108/fpga_1g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
SYN_FILES += lib/eth/rtl/udp_complete.v
SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
SYN_FILES += lib/eth/rtl/udp.v
SYN_FILES += lib/eth/rtl/udp_ip_rx.v
SYN_FILES += lib/eth/rtl/udp_ip_tx.v

4
example/VCU108/fpga_1g/rtl/fpga_core.v
View File

@ -395,9 +395,7 @@ eth_axis_tx_inst (
.busy()
);
udp_complete #(
.UDP_CHECKSUM_ENABLE(0)
)
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),

1
example/VCU108/fpga_1g/tb/test_fpga_core.py
View File

@ -45,6 +45,7 @@ srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx.v")
srcs.append("../lib/eth/rtl/eth_axis_tx.v")
srcs.append("../lib/eth/rtl/udp_complete.v")
srcs.append("../lib/eth/rtl/udp_checksum_gen.v")
srcs.append("../lib/eth/rtl/udp.v")
srcs.append("../lib/eth/rtl/udp_ip_rx.v")
srcs.append("../lib/eth/rtl/udp_ip_tx.v")

10
rtl/udp.v
View File

@ -31,7 +31,7 @@ THE SOFTWARE.
*/
module udp #
(
parameter CHECKSUM_ENABLE = 1,
parameter CHECKSUM_GEN_ENABLE = 1,
parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11,
parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3
)
@ -253,13 +253,13 @@ udp_ip_rx_inst (
generate
if (CHECKSUM_ENABLE) begin
if (CHECKSUM_GEN_ENABLE) begin
udp_checksum #(
udp_checksum_gen #(
.PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)
udp_checksum_inst (
udp_checksum_gen_inst (
.clk(clk),
.rst(rst),
// UDP frame input
@ -276,13 +276,11 @@ if (CHECKSUM_ENABLE) begin
.input_ip_flags(input_udp_ip_flags),
.input_ip_fragment_offset(input_udp_ip_fragment_offset),
.input_ip_ttl(input_udp_ip_ttl),
.input_ip_protocol(0),
.input_ip_header_checksum(input_udp_ip_header_checksum),
.input_ip_source_ip(input_udp_ip_source_ip),
.input_ip_dest_ip(input_udp_ip_dest_ip),
.input_udp_source_port(input_udp_source_port),
.input_udp_dest_port(input_udp_dest_port),
.input_udp_checksum(input_udp_checksum),
.input_udp_payload_tdata(input_udp_payload_tdata),
.input_udp_payload_tvalid(input_udp_payload_tvalid),
.input_udp_payload_tready(input_udp_payload_tready),

10
rtl/udp_64.v
View File

@ -31,7 +31,7 @@ THE SOFTWARE.
*/
module udp_64 #
(
parameter CHECKSUM_ENABLE = 1,
parameter CHECKSUM_GEN_ENABLE = 1,
parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11,
parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3
)
@ -260,13 +260,13 @@ udp_ip_rx_64_inst (
generate
if (CHECKSUM_ENABLE) begin
if (CHECKSUM_GEN_ENABLE) begin
udp_checksum_64 #(
udp_checksum_gen_64 #(
.PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)
udp_checksum_64_inst (
udp_checksum_gen_64_inst (
.clk(clk),
.rst(rst),
// UDP frame input
@ -283,13 +283,11 @@ if (CHECKSUM_ENABLE) begin
.input_ip_flags(input_udp_ip_flags),
.input_ip_fragment_offset(input_udp_ip_fragment_offset),
.input_ip_ttl(input_udp_ip_ttl),
.input_ip_protocol(0),
.input_ip_header_checksum(input_udp_ip_header_checksum),
.input_ip_source_ip(input_udp_ip_source_ip),
.input_ip_dest_ip(input_udp_ip_dest_ip),
.input_udp_source_port(input_udp_source_port),
.input_udp_dest_port(input_udp_dest_port),
.input_udp_checksum(input_udp_checksum),
.input_udp_payload_tdata(input_udp_payload_tdata),
.input_udp_payload_tkeep(input_udp_payload_tkeep),
.input_udp_payload_tvalid(input_udp_payload_tvalid),

4
rtl/udp_complete.v
View File

@ -34,7 +34,7 @@ module udp_complete #(
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2,
parameter ARP_REQUEST_TIMEOUT = 125000000*30,
parameter UDP_CHECKSUM_ENABLE = 1,
parameter UDP_CHECKSUM_GEN_ENABLE = 1,
parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11,
parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3
)
@ -524,7 +524,7 @@ ip_complete_inst (
* UDP interface
*/
udp #(
.CHECKSUM_ENABLE(UDP_CHECKSUM_ENABLE),
.CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)

4
rtl/udp_complete_64.v
View File

@ -34,7 +34,7 @@ module udp_complete_64 #(
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2,
parameter ARP_REQUEST_TIMEOUT = 125000000*30,
parameter UDP_CHECKSUM_ENABLE = 1,
parameter UDP_CHECKSUM_GEN_ENABLE = 1,
parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11,
parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3
)
@ -543,7 +543,7 @@ ip_complete_64_inst (
* UDP interface
*/
udp_64 #(
.CHECKSUM_ENABLE(UDP_CHECKSUM_ENABLE),
.CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)

12
tb/test_udp.py
View File

@ -36,8 +36,10 @@ testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/udp_checksum_gen.v")
srcs.append("../rtl/udp_ip_rx.v")
srcs.append("../rtl/udp_ip_tx.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
@ -434,9 +436,13 @@ def bench():
tx_error_payload_early_termination_asserted.next = 1
def wait_normal():
while (input_ip_payload_tvalid or input_udp_payload_tvalid or
output_ip_payload_tvalid or output_udp_payload_tvalid or
input_ip_hdr_valid or input_udp_hdr_valid):
i = 8
while i > 0:
i = max(0, i-1)
if (input_ip_payload_tvalid or input_udp_payload_tvalid or
output_ip_payload_tvalid or output_udp_payload_tvalid or
input_ip_hdr_valid or input_udp_hdr_valid):
i = 8
yield clk.posedge
@instance

4
tb/test_udp.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_udp;
// Parameters
parameter CHECKSUM_ENABLE = 0;
parameter CHECKSUM_GEN_ENABLE = 1;
parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11;
parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3;
@ -266,7 +266,7 @@ initial begin
end
udp #(
.CHECKSUM_ENABLE(CHECKSUM_ENABLE),
.CHECKSUM_GEN_ENABLE(CHECKSUM_GEN_ENABLE),
.CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.CHECKSUM_HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)

12
tb/test_udp_64.py
View File

@ -36,8 +36,10 @@ testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/udp_checksum_gen_64.v")
srcs.append("../rtl/udp_ip_rx_64.v")
srcs.append("../rtl/udp_ip_tx_64.v")
srcs.append("../lib/axis/rtl/axis_fifo_64.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
@ -446,9 +448,13 @@ def bench():
tx_error_payload_early_termination_asserted.next = 1
def wait_normal():
while (input_ip_payload_tvalid or input_udp_payload_tvalid or
output_ip_payload_tvalid or output_udp_payload_tvalid or
input_ip_hdr_valid or input_udp_hdr_valid):
i = 8
while i > 0:
i = max(0, i-1)
if (input_ip_payload_tvalid or input_udp_payload_tvalid or
output_ip_payload_tvalid or output_udp_payload_tvalid or
input_ip_hdr_valid or input_udp_hdr_valid):
i = 8
yield clk.posedge
@instance

4
tb/test_udp_64.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_udp_64;
// Parameters
parameter CHECKSUM_ENABLE = 0;
parameter CHECKSUM_GEN_ENABLE = 1;
parameter CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11;
parameter CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3;
@ -274,7 +274,7 @@ initial begin
end
udp_64 #(
.CHECKSUM_ENABLE(CHECKSUM_ENABLE),
.CHECKSUM_GEN_ENABLE(CHECKSUM_GEN_ENABLE),
.CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.CHECKSUM_HEADER_FIFO_ADDR_WIDTH(CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)

12
tb/test_udp_complete.py
View File

@ -38,6 +38,7 @@ srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/udp.v")
srcs.append("../rtl/udp_checksum_gen.v")
srcs.append("../rtl/udp_ip_rx.v")
srcs.append("../rtl/udp_ip_tx.v")
srcs.append("../rtl/ip_complete.v")
@ -54,6 +55,7 @@ srcs.append("../rtl/eth_arb_mux_2.v")
srcs.append("../rtl/eth_mux_2.v")
srcs.append("../lib/axis/rtl/arbiter.v")
srcs.append("../lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
@ -523,9 +525,13 @@ def bench():
udp_tx_error_payload_early_termination_asserted.next = 1
def wait_normal():
while (input_eth_payload_tvalid or input_ip_payload_tvalid or input_udp_payload_tvalid or
output_eth_payload_tvalid or output_ip_payload_tvalid or output_udp_payload_tvalid or
input_eth_hdr_valid or input_ip_hdr_valid or input_udp_hdr_valid):
i = 16
while i > 0:
i = max(0, i-1)
if (input_eth_payload_tvalid or input_ip_payload_tvalid or input_udp_payload_tvalid or
output_eth_payload_tvalid or output_ip_payload_tvalid or output_udp_payload_tvalid or
input_eth_hdr_valid or input_ip_hdr_valid or input_udp_hdr_valid):
i = 16
yield clk.posedge
@instance

4
tb/test_udp_complete.v
View File

@ -36,7 +36,7 @@ parameter ARP_CACHE_ADDR_WIDTH = 2;
parameter ARP_REQUEST_RETRY_COUNT = 4;
parameter ARP_REQUEST_RETRY_INTERVAL = 150;
parameter ARP_REQUEST_TIMEOUT = 400;
parameter UDP_CHECKSUM_ENABLE = 0;
parameter UDP_CHECKSUM_GEN_ENABLE = 1;
parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11;
parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3;
@ -309,7 +309,7 @@ udp_complete #(
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT),
.UDP_CHECKSUM_ENABLE(UDP_CHECKSUM_ENABLE),
.UDP_CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)

12
tb/test_udp_complete_64.py
View File

@ -38,6 +38,7 @@ srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/udp_64.v")
srcs.append("../rtl/udp_checksum_gen_64.v")
srcs.append("../rtl/udp_ip_rx_64.v")
srcs.append("../rtl/udp_ip_tx_64.v")
srcs.append("../rtl/ip_complete_64.v")
@ -54,6 +55,7 @@ srcs.append("../rtl/eth_arb_mux_64_2.v")
srcs.append("../rtl/eth_mux_64_2.v")
srcs.append("../lib/axis/rtl/arbiter.v")
srcs.append("../lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/axis/rtl/axis_fifo_64.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
@ -541,9 +543,13 @@ def bench():
udp_tx_error_payload_early_termination_asserted.next = 1
def wait_normal():
while (input_eth_payload_tvalid or input_ip_payload_tvalid or input_udp_payload_tvalid or
output_eth_payload_tvalid or output_ip_payload_tvalid or output_udp_payload_tvalid or
input_eth_hdr_valid or input_ip_hdr_valid or input_udp_hdr_valid):
i = 16
while i > 0:
i = max(0, i-1)
if (input_eth_payload_tvalid or input_ip_payload_tvalid or input_udp_payload_tvalid or
output_eth_payload_tvalid or output_ip_payload_tvalid or output_udp_payload_tvalid or
input_eth_hdr_valid or input_ip_hdr_valid or input_udp_hdr_valid):
i = 16
yield clk.posedge
@instance

4
tb/test_udp_complete_64.v
View File

@ -36,7 +36,7 @@ parameter ARP_CACHE_ADDR_WIDTH = 2;
parameter ARP_REQUEST_RETRY_COUNT = 4;
parameter ARP_REQUEST_RETRY_INTERVAL = 150;
parameter ARP_REQUEST_TIMEOUT = 400;
parameter UDP_CHECKSUM_ENABLE = 0;
parameter UDP_CHECKSUM_GEN_ENABLE = 1;
parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11;
parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3;
@ -321,7 +321,7 @@ udp_complete_64 #(
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT),
.UDP_CHECKSUM_ENABLE(UDP_CHECKSUM_ENABLE),
.UDP_CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
)