FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Prevent latch inference

Browse Source
This commit is contained in:
Alex Forencich 2021-03-30 22:23:40 -07:00
parent 31c7349f90
commit 2796e681c9
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
rtl/ptp_clock_cdc.v
View File

@ -475,6 +475,9 @@ always @* begin
time_err_int_next = time_err_int_reg;
ptp_lock_count_next = ptp_lock_count_reg;
ptp_locked_next = ptp_locked_reg;
// PTP clock
if (TS_WIDTH == 96) begin
// 96 bit timestamp
@ -668,8 +671,10 @@ always @(posedge output_clk) begin
ts_step_reg <= 0;
pps_reg <= 0;
sec_mismatch_reg <= 1'b0;
diff_valid_reg <= 1'b0;
diff_corr_valid_reg <= 1'b0;
time_err_int_reg <= 0;
ptp_lock_count_reg <= 0;