From 27999924a04b8152e2b25111b57cec9be546cc9c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 15 Jun 2019 17:35:49 -0700 Subject: [PATCH] Update VCU108 example designs --- example/VCU108/fpga_10g/fpga.xdc | 37 +- example/VCU108/fpga_10g/fpga/Makefile | 13 +- .../fpga_10g/ip/gig_ethernet_pcs_pma_0.xci | 5 +- .../fpga_10g/ip/gtwizard_ultrascale_0.xci | 1402 +++++++++++++++++ .../fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci | 203 --- example/VCU108/fpga_10g/rtl/fpga.v | 682 +++++--- example/VCU108/fpga_10g/rtl/fpga_core.v | 24 +- example/VCU108/fpga_10g/rtl/i2c_master.v | 895 ----------- example/VCU108/fpga_10g/rtl/si570_i2c_init.v | 486 ------ example/VCU108/fpga_10g/tb/test_fpga_core.py | 72 +- example/VCU108/fpga_10g/tb/test_fpga_core.v | 48 + .../fpga_1g/ip/gig_ethernet_pcs_pma_0.xci | 5 +- 12 files changed, 2058 insertions(+), 1814 deletions(-) create mode 100644 example/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci delete mode 100644 example/VCU108/fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci delete mode 100644 example/VCU108/fpga_10g/rtl/i2c_master.v delete mode 100644 example/VCU108/fpga_10g/rtl/si570_i2c_init.v diff --git a/example/VCU108/fpga_10g/fpga.xdc b/example/VCU108/fpga_10g/fpga.xdc index 049fa76fa..314bb5d00 100644 --- a/example/VCU108/fpga_10g/fpga.xdc +++ b/example/VCU108/fpga_10g/fpga.xdc @@ -73,24 +73,24 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n] create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] # QSFP+ Interface -set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AG41} [get_ports qsfp_tx3_p] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AG40} [get_ports qsfp_tx3_n] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 -#set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AG40} [get_ports qsfp_tx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG41} [get_ports qsfp_tx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340 -set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340 +#set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340 #set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328 #set_property -dict {LOC AD39} [get_ports qsfp_mgt_refclk_1_n] ;# MGTREFCLK1N_127 from U57 CKOUT2 SI5328 #set_property -dict {LOC AG34 IOSTANDARD LVDS} [get_ports qsfp_recclk_p] ;# to U57 CKIN1 SI5328 @@ -101,6 +101,9 @@ set_property -dict {LOC AL25 IOSTANDARD LVCMOS18} [get_ports qsfp_modprsl] set_property -dict {LOC AL21 IOSTANDARD LVCMOS18} [get_ports qsfp_intl] set_property -dict {LOC AM21 IOSTANDARD LVCMOS18} [get_ports qsfp_lpmode] +# 156.25 MHz MGT reference clock +create_clock -period 6.400 -name qsfp_mgt_refclk_0 [get_ports qsfp_mgt_refclk_0_p] + # I2C interface set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl] set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda] diff --git a/example/VCU108/fpga_10g/fpga/Makefile b/example/VCU108/fpga_10g/fpga/Makefile index 12d080c3e..ef2fae0eb 100644 --- a/example/VCU108/fpga_10g/fpga/Makefile +++ b/example/VCU108/fpga_10g/fpga/Makefile @@ -10,8 +10,6 @@ SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_reset.v SYN_FILES += rtl/sync_signal.v -SYN_FILES += rtl/i2c_master.v -SYN_FILES += rtl/si570_i2c_init.v SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_1g.v SYN_FILES += lib/eth/rtl/axis_gmii_rx.v @@ -20,6 +18,15 @@ SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v @@ -54,7 +61,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl # IP XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci -XCI_FILES += ip/ten_gig_eth_pcs_pma_0.xci +XCI_FILES += ip/gtwizard_ultrascale_0.xci include ../common/vivado.mk diff --git a/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci b/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci index 1db9474cb..91b324db6 100644 --- a/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci +++ b/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci @@ -309,16 +309,17 @@ MIXED -2 + E TRUE TRUE IP_Flow - 5 + 6 TRUE . . - 2018.3 + 2019.1 OUT_OF_CONTEXT diff --git a/example/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci b/example/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci new file mode 100644 index 000000000..a38021fba --- /dev/null +++ b/example/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci @@ -0,0 +1,1402 @@ + + + xilinx.com + xci + unknown + 1.0 + + + gtwizard_ultrascale_0 + + + "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111000000000000" + 1 + 2578.125 + 0 + 0 + 125 + 27 + 1 + 2 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 250 + 0 + 0 + 0 + 0 + 0 + 1 + "00000000" + "00000000" + 1 + 2 + 0 + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + "00000000" + 0 + "00000000" + 1 + 0 + 5000 + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + 0 + "1010000011" + 0 + "0101111100" + 4 + 1 + 64 + 10.3125 + 12 + 1 + 156.2500000 + 4 + 0 + 0x000000000000000000000000000000000000000000000000 + 156.25 + 0 + 0 + 0 + 1 + 1 + 0 + 64 + 156.2500000 + 156.2500000 + 0 + 257.8125 + 1 + 4 + 1 + 0 + 0 + 0 + 156.25 + 0 + 0 + 1 + 4 + 1 + 64 + 10.3125 + 12 + 1 + 156.2500000 + 4 + 0 + 156.25 + 0 + 0 + 1 + 1 + 0 + 64 + 156.2500000 + 156.2500000 + 0 + X0Y15 X0Y14 X0Y13 X0Y12 + gtwizard_ultrascale_0 + 0 + 0 + + 125 + BOTH + 0 + GTY + 2 + 20 + 96 + 2 + gtye3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + -1 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 1 + 1 + -1 + -1 + -1 + -1 + 1 + 1 + -1 + 1 + 1 + 1 + -1 + 1 + 1 + 1 + -1 + -1 + -1 + -1 + -1 + 1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 1 + 1 + 1 + 1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + -1 + -1 + 0 + -1 + -1 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + -1 + -1 + 0 + -1 + -1 + 0 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + -1 + 0 + 0 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 1 + 1 + 1 + 0 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + -1 + -1 + -1 + -1 + 0 + 0 + 0 + -1 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + -1 + -1 + -1 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + -1 + -1 + -1 + 0 + 0 + -1 + -1 + -1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + -1 + 0 + 0 + 0 + -1 + 0 + 1 + -1 + -1 + -1 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 1 + 1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 13 + 0 + 10GBASE-R + 6 + 156.2500000 + 4 + 1 + 156.2500000 + false + CORE + NONE + CORE + CORE + EXAMPLE_DESIGN + CORE + EXAMPLE_DESIGN + EXAMPLE_DESIGN + false + NAME + false + 250 + false + false + 250 + GTY-10GBASE-R + 0 + MULTI + 1 + ENABLE + DISABLE + ENABLE + 00000000 + false + false + false + false + false + false + false + false + 00000000 + false + false + false + false + false + false + false + false + 1 + 00000000 + false + false + false + false + false + false + false + false + 2 + 1 + 0 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + false + false + false + false + false + false + false + false + 00000000 + DISABLE + false + false + false + false + false + false + false + false + 1 + 00000000 + false + false + false + false + false + false + false + false + 0 + 5000 + ENABLE + 0 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 1 + false + 0000000000 + false + 1010000011 + NONE + false + 0101111100 + true + 0 + AC + 64B66B_ASYNC + true + AUTO + 64 + 6.1862627 + -20 + 10.3125 + X0Y12 + RXPROGDIVCLK + QPLL0 + 200 + 0 + + 156.25 + + OFF + 0 + PROGRAMMABLE + 800 + 64 + 15 + false + 0 + 10.3125 + 257.8125 + 1 + false + QPLL0 + 156.25 + 1 + ENABLE + 64B66B_ASYNC + CUSTOM + true + 64 + 10.3125 + X0Y12 + TXPROGDIVCLK + QPLL0 + 0 + 156.25 + + 64 + false + 1 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + true + true + false + true + true + true + false + true + true + true + false + false + false + false + false + true + false + false + false + false + false + false + false + true + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + virtexu + + + xcvu095 + ffva2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/example/VCU108/fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci b/example/VCU108/fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci deleted file mode 100644 index 644821b10..000000000 --- a/example/VCU108/fpga_10g/ip/ten_gig_eth_pcs_pma_0.xci +++ /dev/null @@ -1,203 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ten_gig_eth_pcs_pma_0 - - - 0 - 0 - 0 - 0 - 0 - - - 0 - 0.000 - - - - 0 - 0.000 - - - 100000000 - 0 - 0.000 - 0 - 0 - 0 - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - 0 - false - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - false - 0 - 0 - - - 0 - 0.000 - 0 - - - - 0 - 0.000 - - - - 0 - 0.000 - 0 - - - - 0 - 0.000 - - - - 0 - 0.000 - - 0 - 0.000 - - - - 0 - 0.000 - 0 - ten_gig_eth_pcs_pma_0 - 125.00 - virtexu - X0Y12 - 64 - 3 - false - false - false - false - false - false - clk0 - 156 - 10 - ten_gig_eth_pcs_pma_0_gt - ten_gig_eth_pcs_pma_0 - 125.00 - None - X0Y12 - false - clk0 - 156.25 - 1 - Time_of_day - false - false - false - BASE-R - 64bit - false - false - 10Gig - GTY - virtexu - - - xcvu095 - ffva2104 - VERILOG - - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 14 - TRUE - . - - . - 2018.3 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - diff --git a/example/VCU108/fpga_10g/rtl/fpga.v b/example/VCU108/fpga_10g/rtl/fpga.v index 99a9ee0e1..9792b14d3 100644 --- a/example/VCU108/fpga_10g/rtl/fpga.v +++ b/example/VCU108/fpga_10g/rtl/fpga.v @@ -60,20 +60,20 @@ module fpga ( */ input wire qsfp_rx1_p, input wire qsfp_rx1_n, - // input wire qsfp_rx2_p, - // input wire qsfp_rx2_n, - // input wire qsfp_rx3_p, - // input wire qsfp_rx3_n, - // input wire qsfp_rx4_p, - // input wire qsfp_rx4_n, + input wire qsfp_rx2_p, + input wire qsfp_rx2_n, + input wire qsfp_rx3_p, + input wire qsfp_rx3_n, + input wire qsfp_rx4_p, + input wire qsfp_rx4_n, output wire qsfp_tx1_p, output wire qsfp_tx1_n, - // output wire qsfp_tx2_p, - // output wire qsfp_tx2_n, - // output wire qsfp_tx3_p, - // output wire qsfp_tx3_n, - // output wire qsfp_tx4_p, - // output wire qsfp_tx4_n, + output wire qsfp_tx2_p, + output wire qsfp_tx2_n, + output wire qsfp_tx3_p, + output wire qsfp_tx3_n, + output wire qsfp_tx4_p, + output wire qsfp_tx4_n, input wire qsfp_mgt_refclk_0_p, input wire qsfp_mgt_refclk_0_n, // input wire qsfp_mgt_refclk_1_p, @@ -252,232 +252,510 @@ sync_signal_inst ( // SI570 I2C wire i2c_scl_i; -wire i2c_scl_o; -wire i2c_scl_t; +wire i2c_scl_o = 1'b1; +wire i2c_scl_t = 1'b1; wire i2c_sda_i; -wire i2c_sda_o; -wire i2c_sda_t; +wire i2c_sda_o = 1'b1; +wire i2c_sda_t = 1'b1; assign i2c_scl_i = i2c_scl; assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; assign i2c_sda_i = i2c_sda; assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o; -wire [6:0] si570_i2c_cmd_address; -wire si570_i2c_cmd_start; -wire si570_i2c_cmd_read; -wire si570_i2c_cmd_write; -wire si570_i2c_cmd_write_multiple; -wire si570_i2c_cmd_stop; -wire si570_i2c_cmd_valid; -wire si570_i2c_cmd_ready; - -wire [7:0] si570_i2c_data; -wire si570_i2c_data_valid; -wire si570_i2c_data_ready; -wire si570_i2c_data_last; - -wire si570_i2c_init_busy; - -// delay start by ~10 ms -reg [20:0] si570_i2c_init_start_delay = 21'd0; - -always @(posedge clk_125mhz_int) begin - if (rst_125mhz_int) begin - si570_i2c_init_start_delay <= 21'd0; - end else begin - if (!si570_i2c_init_start_delay[20]) begin - si570_i2c_init_start_delay <= si570_i2c_init_start_delay + 21'd1; - end - end -end - -si570_i2c_init -si570_i2c_init_inst ( - .clk(clk_125mhz_int), - .rst(rst_125mhz_int), - .cmd_address(si570_i2c_cmd_address), - .cmd_start(si570_i2c_cmd_start), - .cmd_read(si570_i2c_cmd_read), - .cmd_write(si570_i2c_cmd_write), - .cmd_write_multiple(si570_i2c_cmd_write_multiple), - .cmd_stop(si570_i2c_cmd_stop), - .cmd_valid(si570_i2c_cmd_valid), - .cmd_ready(si570_i2c_cmd_ready), - .data_out(si570_i2c_data), - .data_out_valid(si570_i2c_data_valid), - .data_out_ready(si570_i2c_data_ready), - .data_out_last(si570_i2c_data_last), - .busy(si570_i2c_init_busy), - .start(si570_i2c_init_start_delay[20]) -); - -i2c_master -si570_i2c_master ( - .clk(clk_125mhz_int), - .rst(rst_125mhz_int), - .cmd_address(si570_i2c_cmd_address), - .cmd_start(si570_i2c_cmd_start), - .cmd_read(si570_i2c_cmd_read), - .cmd_write(si570_i2c_cmd_write), - .cmd_write_multiple(si570_i2c_cmd_write_multiple), - .cmd_stop(si570_i2c_cmd_stop), - .cmd_valid(si570_i2c_cmd_valid), - .cmd_ready(si570_i2c_cmd_ready), - .data_in(si570_i2c_data), - .data_in_valid(si570_i2c_data_valid), - .data_in_ready(si570_i2c_data_ready), - .data_in_last(si570_i2c_data_last), - .data_out(), - .data_out_valid(), - .data_out_ready(1), - .data_out_last(), - .scl_i(i2c_scl_i), - .scl_o(i2c_scl_o), - .scl_t(i2c_scl_t), - .sda_i(i2c_sda_i), - .sda_o(i2c_sda_o), - .sda_t(i2c_sda_t), - .busy(), - .bus_control(), - .bus_active(), - .missed_ack(), - .prescale(800), - .stop_on_idle(1) -); - // XGMII 10G PHY assign qsfp_modsell = 1'b0; assign qsfp_resetl = 1'b1; assign qsfp_lpmode = 1'b0; +wire qsfp_tx_clk_1_int; +wire qsfp_tx_rst_1_int; wire [63:0] qsfp_txd_1_int; wire [7:0] qsfp_txc_1_int; +wire qsfp_rx_clk_1_int; +wire qsfp_rx_rst_1_int; wire [63:0] qsfp_rxd_1_int; wire [7:0] qsfp_rxc_1_int; +wire qsfp_tx_clk_2_int; +wire qsfp_tx_rst_2_int; wire [63:0] qsfp_txd_2_int; wire [7:0] qsfp_txc_2_int; -wire [63:0] qsfp_rxd_2_int = 64'h0707070707070707; -wire [7:0] qsfp_rxc_2_int = 8'hff; +wire qsfp_rx_clk_2_int; +wire qsfp_rx_rst_2_int; +wire [63:0] qsfp_rxd_2_int; +wire [7:0] qsfp_rxc_2_int; +wire qsfp_tx_clk_3_int; +wire qsfp_tx_rst_3_int; wire [63:0] qsfp_txd_3_int; wire [7:0] qsfp_txc_3_int; -wire [63:0] qsfp_rxd_3_int = 64'h0707070707070707; -wire [7:0] qsfp_rxc_3_int = 8'hff; +wire qsfp_rx_clk_3_int; +wire qsfp_rx_rst_3_int; +wire [63:0] qsfp_rxd_3_int; +wire [7:0] qsfp_rxc_3_int; +wire qsfp_tx_clk_4_int; +wire qsfp_tx_rst_4_int; wire [63:0] qsfp_txd_4_int; wire [7:0] qsfp_txc_4_int; -wire [63:0] qsfp_rxd_4_int = 64'h0707070707070707; -wire [7:0] qsfp_rxc_4_int = 8'hff; +wire qsfp_rx_clk_4_int; +wire qsfp_rx_rst_4_int; +wire [63:0] qsfp_rxd_4_int; +wire [7:0] qsfp_rxc_4_int; -wire [535:0] configuration_vector; -wire [447:0] status_vector; -wire [7:0] core_status; +wire qsfp_rx_block_lock_1; +wire qsfp_rx_block_lock_2; +wire qsfp_rx_block_lock_3; +wire qsfp_rx_block_lock_4; -assign configuration_vector[0] = 1'b0; // PMA Loopback Enable -assign configuration_vector[14:1] = 0; -assign configuration_vector[15] = 1'b0; // PMA Reset -assign configuration_vector[16] = 1'b0; // Global PMD TX Disable -assign configuration_vector[109:17] = 0; -assign configuration_vector[110] = 1'b0; // PCS Loopback Enable -assign configuration_vector[111] = 1'b0; // PCS Reset -assign configuration_vector[169:112] = 58'd0; // 10GBASE-R Test Pattern Seed A0-3 -assign configuration_vector[175:170] = 0; -assign configuration_vector[233:176] = 58'd0; // 10GBASE-R Test Pattern Seed B0-3 -assign configuration_vector[239:234] = 0; -assign configuration_vector[240] = 1'b0; // Data Pattern Select -assign configuration_vector[241] = 1'b0; // Test Pattern Select -assign configuration_vector[242] = 1'b0; // RX Test Pattern Checking Enable -assign configuration_vector[243] = 1'b0; // TX Test Pattern Enable -assign configuration_vector[244] = 1'b0; // PRBS31 TX Test Pattern Enable -assign configuration_vector[245] = 1'b0; // PRBS31 RX Test Pattern Checking Enable -assign configuration_vector[383:246] = 0; -assign configuration_vector[399:384] = 16'h4C4B; // 125 us timer control -assign configuration_vector[511:400] = 0; -assign configuration_vector[512] = 1'b0; // Set PMA Link Status -assign configuration_vector[513] = 1'b0; // Clear PMA/PMD Link Faults -assign configuration_vector[515:514] = 0; -assign configuration_vector[516] = 1'b0; // Set PCS Link Status -assign configuration_vector[517] = 1'b0; // Clear PCS Link Faults -assign configuration_vector[518] = 1'b0; // Clear 10GBASE-R Status 2 -assign configuration_vector[519] = 1'b0; // Clear 10GBASE-R Test Pattern Error Counter -assign configuration_vector[535:520] = 0; +wire qsfp_mgt_refclk_0; -wire drp_gnt; -wire gt_drprdy; -wire [15:0] gt_drpdo; -wire gt_drpen; -wire gt_drpwe; -wire [15:0] gt_drpaddr; -wire [15:0] gt_drpdi; +wire [3:0] gt_txclkout; +wire gt_txusrclk; -ten_gig_eth_pcs_pma_0 -ten_gig_eth_pcs_pma_inst ( - .refclk_p(qsfp_mgt_refclk_0_p), - .refclk_n(qsfp_mgt_refclk_0_n), +wire [3:0] gt_rxclkout; +wire [3:0] gt_rxusrclk; - .dclk(clk_125mhz_int), +wire gt_reset_tx_done; +wire gt_reset_rx_done; - .coreclk_out(), +wire [3:0] gt_txprgdivresetdone; +wire [3:0] gt_txpmaresetdone; +wire [3:0] gt_rxprgdivresetdone; +wire [3:0] gt_rxpmaresetdone; - .reset(rst_125mhz_int | si570_i2c_init_busy), +wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone)); +wire gt_rx_reset = ~>_rxpmaresetdone; - .sim_speedup_control(1'b0), +reg gt_userclk_tx_active = 1'b0; +reg [3:0] gt_userclk_rx_active = 1'b0; + +IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst ( + .I (qsfp_mgt_refclk_0_p), + .IB (qsfp_mgt_refclk_0_n), + .CEB (1'b0), + .O (qsfp_mgt_refclk_0), + .ODIV2 () +); + + +BUFG_GT bufg_gt_tx_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gt_tx_reset), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (gt_txclkout[0]), + .O (gt_txusrclk) +); + +assign clk_156mhz_int = gt_txusrclk; + +always @(posedge gt_txusrclk, posedge gt_tx_reset) begin + if (gt_tx_reset) begin + gt_userclk_tx_active <= 1'b0; + end else begin + gt_userclk_tx_active <= 1'b1; + end +end + +genvar n; + +generate + +for (n = 0; n < 4; n = n + 1) begin + + BUFG_GT bufg_gt_rx_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gt_rx_reset), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (gt_rxclkout[n]), + .O (gt_rxusrclk[n]) + ); + + always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin + if (gt_rx_reset) begin + gt_userclk_rx_active[n] <= 1'b0; + end else begin + gt_userclk_rx_active[n] <= 1'b1; + end + end + +end + +endgenerate + +sync_reset #( + .N(4) +) +sync_reset_156mhz_inst ( + .clk(clk_156mhz_int), + .rst(~gt_reset_tx_done), + .sync_reset_out(rst_156mhz_int) +); + +wire [5:0] qsfp_gt_txheader_1; +wire [127:0] qsfp_gt_txdata_1; +wire qsfp_gt_rxgearboxslip_1; +wire [5:0] qsfp_gt_rxheader_1; +wire [1:0] qsfp_gt_rxheadervalid_1; +wire [127:0] qsfp_gt_rxdata_1; +wire [1:0] qsfp_gt_rxdatavalid_1; + +wire [5:0] qsfp_gt_txheader_2; +wire [127:0] qsfp_gt_txdata_2; +wire qsfp_gt_rxgearboxslip_2; +wire [5:0] qsfp_gt_rxheader_2; +wire [1:0] qsfp_gt_rxheadervalid_2; +wire [127:0] qsfp_gt_rxdata_2; +wire [1:0] qsfp_gt_rxdatavalid_2; + +wire [5:0] qsfp_gt_txheader_3; +wire [127:0] qsfp_gt_txdata_3; +wire qsfp_gt_rxgearboxslip_3; +wire [5:0] qsfp_gt_rxheader_3; +wire [1:0] qsfp_gt_rxheadervalid_3; +wire [127:0] qsfp_gt_rxdata_3; +wire [1:0] qsfp_gt_rxdatavalid_3; + +wire [5:0] qsfp_gt_txheader_4; +wire [127:0] qsfp_gt_txdata_4; +wire qsfp_gt_rxgearboxslip_4; +wire [5:0] qsfp_gt_rxheader_4; +wire [1:0] qsfp_gt_rxheadervalid_4; +wire [127:0] qsfp_gt_rxdata_4; +wire [1:0] qsfp_gt_rxdatavalid_4; + +gtwizard_ultrascale_0 +qsfp_gty_inst ( + .gtwiz_userclk_tx_active_in(>_userclk_tx_active), + .gtwiz_userclk_rx_active_in(>_userclk_rx_active), + + .gtwiz_reset_clk_freerun_in(clk_125mhz_int), + .gtwiz_reset_all_in(rst_125mhz_int), + + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(1'b0), + + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(1'b0), + + .gtwiz_reset_rx_cdr_stable_out(), + + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + + .gtrefclk00_in({1{qsfp_mgt_refclk_0}}), .qpll0outclk_out(), .qpll0outrefclk_out(), - .qpll0lock_out(), - .rxrecclk_out(), + .gtyrxn_in({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}), + .gtyrxp_in({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}), - .txusrclk_out(), - .txusrclk2_out(clk_156mhz_int), + .rxusrclk_in(gt_rxusrclk), + .rxusrclk2_in(gt_rxusrclk), - .gttxreset_out(), - .gtrxreset_out(), + .txdata_in({qsfp_gt_txdata_4, qsfp_gt_txdata_3, qsfp_gt_txdata_2, qsfp_gt_txdata_1}), + .txheader_in({qsfp_gt_txheader_4, qsfp_gt_txheader_3, qsfp_gt_txheader_2, qsfp_gt_txheader_1}), + .txsequence_in({4{1'b0}}), - .txuserrdy_out(), + .txusrclk_in({4{gt_txusrclk}}), + .txusrclk2_in({4{gt_txusrclk}}), - .areset_datapathclk_out(rst_156mhz_int), - .areset_coreclk_out(), - .reset_counter_done_out(), + .gtpowergood_out(), + .gtytxn_out({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}), + .gtytxp_out({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}), + + .rxgearboxslip_in({qsfp_gt_rxgearboxslip_4, qsfp_gt_rxgearboxslip_3, qsfp_gt_rxgearboxslip_2, qsfp_gt_rxgearboxslip_1}), + .rxdata_out({qsfp_gt_rxdata_4, qsfp_gt_rxdata_3, qsfp_gt_rxdata_2, qsfp_gt_rxdata_1}), + .rxdatavalid_out({qsfp_gt_rxdatavalid_4, qsfp_gt_rxdatavalid_3, qsfp_gt_rxdatavalid_2, qsfp_gt_rxdatavalid_1}), + .rxheader_out({qsfp_gt_rxheader_4, qsfp_gt_rxheader_3, qsfp_gt_rxheader_2, qsfp_gt_rxheader_1}), + .rxheadervalid_out({qsfp_gt_rxheadervalid_4, qsfp_gt_rxheadervalid_3, qsfp_gt_rxheadervalid_2, qsfp_gt_rxheadervalid_1}), + .rxoutclk_out(gt_rxclkout), + .rxpmaresetdone_out(gt_rxpmaresetdone), + .rxprgdivresetdone_out(gt_rxprgdivresetdone), + .rxstartofseq_out(), + + .txoutclk_out(gt_txclkout), + .txpmaresetdone_out(gt_txpmaresetdone), + .txprgdivresetdone_out(gt_txprgdivresetdone) +); + +assign qsfp_tx_clk_1_int = clk_156mhz_int; +assign qsfp_tx_rst_1_int = rst_156mhz_int; + +assign qsfp_rx_clk_1_int = gt_rxusrclk[0]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_1_reset_sync_inst ( + .clk(qsfp_rx_clk_1_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_1_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp_phy_1_inst ( + .tx_clk(qsfp_tx_clk_1_int), + .tx_rst(qsfp_tx_rst_1_int), + .rx_clk(qsfp_rx_clk_1_int), + .rx_rst(qsfp_rx_rst_1_int), .xgmii_txd(qsfp_txd_1_int), .xgmii_txc(qsfp_txc_1_int), .xgmii_rxd(qsfp_rxd_1_int), .xgmii_rxc(qsfp_rxc_1_int), - - .txp(qsfp_tx1_p), - .txn(qsfp_tx1_n), - .rxp(qsfp_rx1_p), - .rxn(qsfp_rx1_n), - - .resetdone_out(), - .signal_detect(1'b1), - .tx_fault(1'b0), - - .drp_req(drp_gnt), - .drp_gnt(drp_gnt), - - .core_to_gt_drprdy(gt_drprdy), - .core_to_gt_drpdo(gt_drpdo), - .core_to_gt_drpen(gt_drpen), - .core_to_gt_drpwe(gt_drpwe), - .core_to_gt_drpaddr(gt_drpaddr), - .core_to_gt_drpdi(gt_drpdi), - - .gt_drprdy(gt_drprdy), - .gt_drpdo(gt_drpdo), - .gt_drpen(gt_drpen), - .gt_drpwe(gt_drpwe), - .gt_drpaddr(gt_drpaddr), - .gt_drpdi(gt_drpdi), - - .tx_disable(), - .configuration_vector(configuration_vector), - .status_vector(status_vector), - .pma_pmd_type(3'b101), - .core_status(core_status) + .serdes_tx_data(qsfp_gt_txdata_1), + .serdes_tx_hdr(qsfp_gt_txheader_1), + .serdes_rx_data(qsfp_gt_rxdata_1), + .serdes_rx_hdr(qsfp_gt_rxheader_1), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_1), + .rx_block_lock(qsfp_rx_block_lock_1), + .rx_high_ber() ); +assign qsfp_tx_clk_2_int = clk_156mhz_int; +assign qsfp_tx_rst_2_int = rst_156mhz_int; + +assign qsfp_rx_clk_2_int = gt_rxusrclk[1]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_2_reset_sync_inst ( + .clk(qsfp_rx_clk_2_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_2_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp_phy_2_inst ( + .tx_clk(qsfp_tx_clk_2_int), + .tx_rst(qsfp_tx_rst_2_int), + .rx_clk(qsfp_rx_clk_2_int), + .rx_rst(qsfp_rx_rst_2_int), + .xgmii_txd(qsfp_txd_2_int), + .xgmii_txc(qsfp_txc_2_int), + .xgmii_rxd(qsfp_rxd_2_int), + .xgmii_rxc(qsfp_rxc_2_int), + .serdes_tx_data(qsfp_gt_txdata_2), + .serdes_tx_hdr(qsfp_gt_txheader_2), + .serdes_rx_data(qsfp_gt_rxdata_2), + .serdes_rx_hdr(qsfp_gt_rxheader_2), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_2), + .rx_block_lock(qsfp_rx_block_lock_2), + .rx_high_ber() +); + +assign qsfp_tx_clk_3_int = clk_156mhz_int; +assign qsfp_tx_rst_3_int = rst_156mhz_int; + +assign qsfp_rx_clk_3_int = gt_rxusrclk[2]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_3_reset_sync_inst ( + .clk(qsfp_rx_clk_3_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_3_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp_phy_3_inst ( + .tx_clk(qsfp_tx_clk_3_int), + .tx_rst(qsfp_tx_rst_3_int), + .rx_clk(qsfp_rx_clk_3_int), + .rx_rst(qsfp_rx_rst_3_int), + .xgmii_txd(qsfp_txd_3_int), + .xgmii_txc(qsfp_txc_3_int), + .xgmii_rxd(qsfp_rxd_3_int), + .xgmii_rxc(qsfp_rxc_3_int), + .serdes_tx_data(qsfp_gt_txdata_3), + .serdes_tx_hdr(qsfp_gt_txheader_3), + .serdes_rx_data(qsfp_gt_rxdata_3), + .serdes_rx_hdr(qsfp_gt_rxheader_3), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_3), + .rx_block_lock(qsfp_rx_block_lock_3), + .rx_high_ber() +); + +assign qsfp_tx_clk_4_int = clk_156mhz_int; +assign qsfp_tx_rst_4_int = rst_156mhz_int; + +assign qsfp_rx_clk_4_int = gt_rxusrclk[3]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_4_reset_sync_inst ( + .clk(qsfp_rx_clk_4_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_4_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1) +) +qsfp_phy_4_inst ( + .tx_clk(qsfp_tx_clk_4_int), + .tx_rst(qsfp_tx_rst_4_int), + .rx_clk(qsfp_rx_clk_4_int), + .rx_rst(qsfp_rx_rst_4_int), + .xgmii_txd(qsfp_txd_4_int), + .xgmii_txc(qsfp_txc_4_int), + .xgmii_rxd(qsfp_rxd_4_int), + .xgmii_rxc(qsfp_rxc_4_int), + .serdes_tx_data(qsfp_gt_txdata_4), + .serdes_tx_hdr(qsfp_gt_txheader_4), + .serdes_rx_data(qsfp_gt_rxdata_4), + .serdes_rx_hdr(qsfp_gt_rxheader_4), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_4), + .rx_block_lock(qsfp_rx_block_lock_4), + .rx_high_ber() +); + +// // XGMII 10G PHY +// assign qsfp_modsell = 1'b0; +// assign qsfp_resetl = 1'b1; +// assign qsfp_lpmode = 1'b0; + +// wire [63:0] qsfp_txd_1_int; +// wire [7:0] qsfp_txc_1_int; +// wire [63:0] qsfp_rxd_1_int; +// wire [7:0] qsfp_rxc_1_int; +// wire [63:0] qsfp_txd_2_int; +// wire [7:0] qsfp_txc_2_int; +// wire [63:0] qsfp_rxd_2_int = 64'h0707070707070707; +// wire [7:0] qsfp_rxc_2_int = 8'hff; +// wire [63:0] qsfp_txd_3_int; +// wire [7:0] qsfp_txc_3_int; +// wire [63:0] qsfp_rxd_3_int = 64'h0707070707070707; +// wire [7:0] qsfp_rxc_3_int = 8'hff; +// wire [63:0] qsfp_txd_4_int; +// wire [7:0] qsfp_txc_4_int; +// wire [63:0] qsfp_rxd_4_int = 64'h0707070707070707; +// wire [7:0] qsfp_rxc_4_int = 8'hff; + +// wire [535:0] configuration_vector; +// wire [447:0] status_vector; +// wire [7:0] core_status; + +// assign configuration_vector[0] = 1'b0; // PMA Loopback Enable +// assign configuration_vector[14:1] = 0; +// assign configuration_vector[15] = 1'b0; // PMA Reset +// assign configuration_vector[16] = 1'b0; // Global PMD TX Disable +// assign configuration_vector[109:17] = 0; +// assign configuration_vector[110] = 1'b0; // PCS Loopback Enable +// assign configuration_vector[111] = 1'b0; // PCS Reset +// assign configuration_vector[169:112] = 58'd0; // 10GBASE-R Test Pattern Seed A0-3 +// assign configuration_vector[175:170] = 0; +// assign configuration_vector[233:176] = 58'd0; // 10GBASE-R Test Pattern Seed B0-3 +// assign configuration_vector[239:234] = 0; +// assign configuration_vector[240] = 1'b0; // Data Pattern Select +// assign configuration_vector[241] = 1'b0; // Test Pattern Select +// assign configuration_vector[242] = 1'b0; // RX Test Pattern Checking Enable +// assign configuration_vector[243] = 1'b0; // TX Test Pattern Enable +// assign configuration_vector[244] = 1'b0; // PRBS31 TX Test Pattern Enable +// assign configuration_vector[245] = 1'b0; // PRBS31 RX Test Pattern Checking Enable +// assign configuration_vector[383:246] = 0; +// assign configuration_vector[399:384] = 16'h4C4B; // 125 us timer control +// assign configuration_vector[511:400] = 0; +// assign configuration_vector[512] = 1'b0; // Set PMA Link Status +// assign configuration_vector[513] = 1'b0; // Clear PMA/PMD Link Faults +// assign configuration_vector[515:514] = 0; +// assign configuration_vector[516] = 1'b0; // Set PCS Link Status +// assign configuration_vector[517] = 1'b0; // Clear PCS Link Faults +// assign configuration_vector[518] = 1'b0; // Clear 10GBASE-R Status 2 +// assign configuration_vector[519] = 1'b0; // Clear 10GBASE-R Test Pattern Error Counter +// assign configuration_vector[535:520] = 0; + +// wire drp_gnt; +// wire gt_drprdy; +// wire [15:0] gt_drpdo; +// wire gt_drpen; +// wire gt_drpwe; +// wire [15:0] gt_drpaddr; +// wire [15:0] gt_drpdi; + +// ten_gig_eth_pcs_pma_0 +// ten_gig_eth_pcs_pma_inst ( +// .refclk_p(qsfp_mgt_refclk_0_p), +// .refclk_n(qsfp_mgt_refclk_0_n), + +// .dclk(clk_125mhz_int), + +// .coreclk_out(), + +// //.reset(rst_125mhz_int | si570_i2c_init_busy), +// .reset(rst_125mhz_int), + +// .sim_speedup_control(1'b0), + +// .qpll0outclk_out(), +// .qpll0outrefclk_out(), +// .qpll0lock_out(), + +// .rxrecclk_out(), + +// .txusrclk_out(), +// .txusrclk2_out(clk_156mhz_int), + +// .gttxreset_out(), +// .gtrxreset_out(), + +// .txuserrdy_out(), + +// .areset_datapathclk_out(rst_156mhz_int), +// .areset_coreclk_out(), +// .reset_counter_done_out(), + +// .xgmii_txd(qsfp_txd_1_int), +// .xgmii_txc(qsfp_txc_1_int), +// .xgmii_rxd(qsfp_rxd_1_int), +// .xgmii_rxc(qsfp_rxc_1_int), + +// .txp(qsfp_tx1_p), +// .txn(qsfp_tx1_n), +// .rxp(qsfp_rx1_p), +// .rxn(qsfp_rx1_n), + +// .resetdone_out(), +// .signal_detect(1'b1), +// .tx_fault(1'b0), + +// .drp_req(drp_gnt), +// .drp_gnt(drp_gnt), + +// .core_to_gt_drprdy(gt_drprdy), +// .core_to_gt_drpdo(gt_drpdo), +// .core_to_gt_drpen(gt_drpen), +// .core_to_gt_drpwe(gt_drpwe), +// .core_to_gt_drpaddr(gt_drpaddr), +// .core_to_gt_drpdi(gt_drpdi), + +// .gt_drprdy(gt_drprdy), +// .gt_drpdo(gt_drpdo), +// .gt_drpen(gt_drpen), +// .gt_drpwe(gt_drpwe), +// .gt_drpaddr(gt_drpaddr), +// .gt_drpdi(gt_drpdi), + +// .tx_disable(), +// .configuration_vector(configuration_vector), +// .status_vector(status_vector), +// .pma_pmd_type(3'b101), +// .core_status(core_status) +// ); + // SGMII interface to PHY wire phy_gmii_clk_int; wire phy_gmii_rst_int; @@ -581,7 +859,7 @@ gig_eth_pcspma ( wire [7:0] led_int; -assign led = sw[0] ? {7'd0, core_status[0]} : led_int; +assign led = sw[0] ? {4'd0, qsfp_rx_block_lock_4, qsfp_rx_block_lock_3, qsfp_rx_block_lock_2, qsfp_rx_block_lock_1} : led_int; fpga_core core_inst ( @@ -604,20 +882,36 @@ core_inst ( /* * Ethernet: QSFP28 */ + .qsfp_tx_clk_1(qsfp_tx_clk_1_int), + .qsfp_tx_rst_1(qsfp_tx_rst_1_int), .qsfp_txd_1(qsfp_txd_1_int), .qsfp_txc_1(qsfp_txc_1_int), + .qsfp_rx_clk_1(qsfp_rx_clk_1_int), + .qsfp_rx_rst_1(qsfp_rx_rst_1_int), .qsfp_rxd_1(qsfp_rxd_1_int), .qsfp_rxc_1(qsfp_rxc_1_int), + .qsfp_tx_clk_2(qsfp_tx_clk_2_int), + .qsfp_tx_rst_2(qsfp_tx_rst_2_int), .qsfp_txd_2(qsfp_txd_2_int), .qsfp_txc_2(qsfp_txc_2_int), + .qsfp_rx_clk_2(qsfp_rx_clk_2_int), + .qsfp_rx_rst_2(qsfp_rx_rst_2_int), .qsfp_rxd_2(qsfp_rxd_2_int), .qsfp_rxc_2(qsfp_rxc_2_int), + .qsfp_tx_clk_3(qsfp_tx_clk_3_int), + .qsfp_tx_rst_3(qsfp_tx_rst_3_int), .qsfp_txd_3(qsfp_txd_3_int), .qsfp_txc_3(qsfp_txc_3_int), + .qsfp_rx_clk_3(qsfp_rx_clk_3_int), + .qsfp_rx_rst_3(qsfp_rx_rst_3_int), .qsfp_rxd_3(qsfp_rxd_3_int), .qsfp_rxc_3(qsfp_rxc_3_int), + .qsfp_tx_clk_4(qsfp_tx_clk_4_int), + .qsfp_tx_rst_4(qsfp_tx_rst_4_int), .qsfp_txd_4(qsfp_txd_4_int), .qsfp_txc_4(qsfp_txc_4_int), + .qsfp_rx_clk_4(qsfp_rx_clk_4_int), + .qsfp_rx_rst_4(qsfp_rx_rst_4_int), .qsfp_rxd_4(qsfp_rxd_4_int), .qsfp_rxc_4(qsfp_rxc_4_int), /* diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v index 20ad98210..16284a70f 100644 --- a/example/VCU108/fpga_10g/rtl/fpga_core.v +++ b/example/VCU108/fpga_10g/rtl/fpga_core.v @@ -55,20 +55,36 @@ module fpga_core # /* * Ethernet: QSFP28 */ + input wire qsfp_tx_clk_1, + input wire qsfp_tx_rst_1, output wire [63:0] qsfp_txd_1, output wire [7:0] qsfp_txc_1, + input wire qsfp_rx_clk_1, + input wire qsfp_rx_rst_1, input wire [63:0] qsfp_rxd_1, input wire [7:0] qsfp_rxc_1, + input wire qsfp_tx_clk_2, + input wire qsfp_tx_rst_2, output wire [63:0] qsfp_txd_2, output wire [7:0] qsfp_txc_2, + input wire qsfp_rx_clk_2, + input wire qsfp_rx_rst_2, input wire [63:0] qsfp_rxd_2, input wire [7:0] qsfp_rxc_2, + input wire qsfp_tx_clk_3, + input wire qsfp_tx_rst_3, output wire [63:0] qsfp_txd_3, output wire [7:0] qsfp_txc_3, + input wire qsfp_rx_clk_3, + input wire qsfp_rx_rst_3, input wire [63:0] qsfp_rxd_3, input wire [7:0] qsfp_rxc_3, + input wire qsfp_tx_clk_4, + input wire qsfp_tx_rst_4, output wire [63:0] qsfp_txd_4, output wire [7:0] qsfp_txc_4, + input wire qsfp_rx_clk_4, + input wire qsfp_rx_rst_4, input wire [63:0] qsfp_rxd_4, input wire [7:0] qsfp_rxc_4, @@ -365,10 +381,10 @@ eth_mac_10g_fifo #( .RX_FRAME_FIFO(1) ) eth_mac_10g_fifo_inst ( - .rx_clk(clk), - .rx_rst(rst), - .tx_clk(clk), - .tx_rst(rst), + .rx_clk(qsfp_rx_clk_1), + .rx_rst(qsfp_rx_rst_1), + .tx_clk(qsfp_tx_clk_1), + .tx_rst(qsfp_tx_rst_1), .logic_clk(clk), .logic_rst(rst), diff --git a/example/VCU108/fpga_10g/rtl/i2c_master.v b/example/VCU108/fpga_10g/rtl/i2c_master.v deleted file mode 100644 index 95d3a5212..000000000 --- a/example/VCU108/fpga_10g/rtl/i2c_master.v +++ /dev/null @@ -1,895 +0,0 @@ -/* - -Copyright (c) 2015-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * I2C master - */ -module i2c_master ( - input wire clk, - input wire rst, - - /* - * Host interface - */ - input wire [6:0] cmd_address, - input wire cmd_start, - input wire cmd_read, - input wire cmd_write, - input wire cmd_write_multiple, - input wire cmd_stop, - input wire cmd_valid, - output wire cmd_ready, - - input wire [7:0] data_in, - input wire data_in_valid, - output wire data_in_ready, - input wire data_in_last, - - output wire [7:0] data_out, - output wire data_out_valid, - input wire data_out_ready, - output wire data_out_last, - - /* - * I2C interface - */ - input wire scl_i, - output wire scl_o, - output wire scl_t, - input wire sda_i, - output wire sda_o, - output wire sda_t, - - /* - * Status - */ - output wire busy, - output wire bus_control, - output wire bus_active, - output wire missed_ack, - - /* - * Configuration - */ - input wire [15:0] prescale, - input wire stop_on_idle -); - -/* - -I2C - -Read - __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ -sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/ - ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ -scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP - -Write - __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ -sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/_W_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/_N_\__/ - ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ -scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP - -Commands: - -read - read data byte - set start to force generation of a start condition - start is implied when bus is inactive or active with write or different address - set stop to issue a stop condition after reading current byte - if stop is set with read command, then data_out_last will be set - -write - write data byte - set start to force generation of a start condition - start is implied when bus is inactive or active with read or different address - set stop to issue a stop condition after writing current byte - -write multiple - write multiple data bytes (until data_in_last) - set start to force generation of a start condition - start is implied when bus is inactive or active with read or different address - set stop to issue a stop condition after writing block - -stop - issue stop condition if bus is active - -Status: - -busy - module is communicating over the bus - -bus_control - module has control of bus in active state - -bus_active - bus is active, not necessarily controlled by this module - -missed_ack - strobed when a slave ack is missed - -Parameters: - -prescale - set prescale to 1/4 of the minimum clock period in units - of input clk cycles (prescale = Fclk / (FI2Cclk * 4)) - -stop_on_idle - automatically issue stop when command input is not valid - -Example of interfacing with tristate pins: -(this will work for any tristate bus) - -assign scl_i = scl_pin; -assign scl_pin = scl_t ? 1'bz : scl_o; -assign sda_i = sda_pin; -assign sda_pin = sda_t ? 1'bz : sda_o; - -Equivalent code that does not use *_t connections: -(we can get away with this because I2C is open-drain) - -assign scl_i = scl_pin; -assign scl_pin = scl_o ? 1'bz : 1'b0; -assign sda_i = sda_pin; -assign sda_pin = sda_o ? 1'bz : 1'b0; - -Example of two interconnected I2C devices: - -assign scl_1_i = scl_1_o & scl_2_o; -assign scl_2_i = scl_1_o & scl_2_o; -assign sda_1_i = sda_1_o & sda_2_o; -assign sda_2_i = sda_1_o & sda_2_o; - -Example of two I2C devices sharing the same pins: - -assign scl_1_i = scl_pin; -assign scl_2_i = scl_pin; -assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0; -assign sda_1_i = sda_pin; -assign sda_2_i = sda_pin; -assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0; - -Notes: - -scl_o should not be connected directly to scl_i, only via AND logic or a tristate -I/O pin. This would prevent devices from stretching the clock period. - -*/ - -localparam [4:0] - STATE_IDLE = 4'd0, - STATE_ACTIVE_WRITE = 4'd1, - STATE_ACTIVE_READ = 4'd2, - STATE_START_WAIT = 4'd3, - STATE_START = 4'd4, - STATE_ADDRESS_1 = 4'd5, - STATE_ADDRESS_2 = 4'd6, - STATE_WRITE_1 = 4'd7, - STATE_WRITE_2 = 4'd8, - STATE_WRITE_3 = 4'd9, - STATE_READ = 4'd10, - STATE_STOP = 4'd11; - -reg [4:0] state_reg = STATE_IDLE, state_next; - -localparam [4:0] - PHY_STATE_IDLE = 5'd0, - PHY_STATE_ACTIVE = 5'd1, - PHY_STATE_REPEATED_START_1 = 5'd2, - PHY_STATE_REPEATED_START_2 = 5'd3, - PHY_STATE_START_1 = 5'd4, - PHY_STATE_START_2 = 5'd5, - PHY_STATE_WRITE_BIT_1 = 5'd6, - PHY_STATE_WRITE_BIT_2 = 5'd7, - PHY_STATE_WRITE_BIT_3 = 5'd8, - PHY_STATE_READ_BIT_1 = 5'd9, - PHY_STATE_READ_BIT_2 = 5'd10, - PHY_STATE_READ_BIT_3 = 5'd11, - PHY_STATE_READ_BIT_4 = 5'd12, - PHY_STATE_STOP_1 = 5'd13, - PHY_STATE_STOP_2 = 5'd14, - PHY_STATE_STOP_3 = 5'd15; - -reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next; - -reg phy_start_bit; -reg phy_stop_bit; -reg phy_write_bit; -reg phy_read_bit; -reg phy_release_bus; - -reg phy_tx_data; - -reg phy_rx_data_reg = 1'b0, phy_rx_data_next; - -reg [6:0] addr_reg = 7'd0, addr_next; -reg [7:0] data_reg = 8'd0, data_next; -reg last_reg = 1'b0, last_next; - -reg mode_read_reg = 1'b0, mode_read_next; -reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next; -reg mode_stop_reg = 1'b0, mode_stop_next; - -reg [16:0] delay_reg = 16'd0, delay_next; -reg delay_scl_reg = 1'b0, delay_scl_next; -reg delay_sda_reg = 1'b0, delay_sda_next; - -reg [3:0] bit_count_reg = 4'd0, bit_count_next; - -reg cmd_ready_reg = 1'b0, cmd_ready_next; - -reg data_in_ready_reg = 1'b0, data_in_ready_next; - -reg [7:0] data_out_reg = 8'd0, data_out_next; -reg data_out_valid_reg = 1'b0, data_out_valid_next; -reg data_out_last_reg = 1'b0, data_out_last_next; - -reg scl_i_reg = 1'b1; -reg sda_i_reg = 1'b1; - -reg scl_o_reg = 1'b1, scl_o_next; -reg sda_o_reg = 1'b1, sda_o_next; - -reg last_scl_i_reg = 1'b1; -reg last_sda_i_reg = 1'b1; - -reg busy_reg = 1'b0; -reg bus_active_reg = 1'b0; -reg bus_control_reg = 1'b0, bus_control_next; -reg missed_ack_reg = 1'b0, missed_ack_next; - -assign cmd_ready = cmd_ready_reg; - -assign data_in_ready = data_in_ready_reg; - -assign data_out = data_out_reg; -assign data_out_valid = data_out_valid_reg; -assign data_out_last = data_out_last_reg; - -assign scl_o = scl_o_reg; -assign scl_t = scl_o_reg; -assign sda_o = sda_o_reg; -assign sda_t = sda_o_reg; - -assign busy = busy_reg; -assign bus_active = bus_active_reg; -assign bus_control = bus_control_reg; -assign missed_ack = missed_ack_reg; - -wire scl_posedge = scl_i_reg & ~last_scl_i_reg; -wire scl_negedge = ~scl_i_reg & last_scl_i_reg; -wire sda_posedge = sda_i_reg & ~last_sda_i_reg; -wire sda_negedge = ~sda_i_reg & last_sda_i_reg; - -wire start_bit = sda_negedge & scl_i_reg; -wire stop_bit = sda_posedge & scl_i_reg; - -always @* begin - state_next = STATE_IDLE; - - phy_start_bit = 1'b0; - phy_stop_bit = 1'b0; - phy_write_bit = 1'b0; - phy_read_bit = 1'b0; - phy_tx_data = 1'b0; - phy_release_bus = 1'b0; - - addr_next = addr_reg; - data_next = data_reg; - last_next = last_reg; - - mode_read_next = mode_read_reg; - mode_write_multiple_next = mode_write_multiple_reg; - mode_stop_next = mode_stop_reg; - - bit_count_next = bit_count_reg; - - cmd_ready_next = 1'b0; - - data_in_ready_next = 1'b0; - - data_out_next = data_out_reg; - data_out_valid_next = data_out_valid_reg & ~data_out_ready; - data_out_last_next = data_out_last_reg; - - missed_ack_next = 1'b0; - - // generate delays - if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin - // wait for phy operation - state_next = state_reg; - end else begin - // process states - case (state_reg) - STATE_IDLE: begin - // line idle - cmd_ready_next = 1'b1; - - if (cmd_ready & cmd_valid) begin - // command valid - if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin - // read or write command - addr_next = cmd_address; - mode_read_next = cmd_read; - mode_write_multiple_next = cmd_write_multiple; - mode_stop_next = cmd_stop; - - cmd_ready_next = 1'b0; - - // start bit - if (bus_active) begin - state_next = STATE_START_WAIT; - end else begin - phy_start_bit = 1'b1; - bit_count_next = 4'd8; - state_next = STATE_ADDRESS_1; - end - end else begin - // invalid or unspecified - ignore - state_next = STATE_IDLE; - end - end else begin - state_next = STATE_IDLE; - end - end - STATE_ACTIVE_WRITE: begin - // line active with current address and read/write mode - cmd_ready_next = 1'b1; - - if (cmd_ready & cmd_valid) begin - // command valid - if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin - // read or write command - addr_next = cmd_address; - mode_read_next = cmd_read; - mode_write_multiple_next = cmd_write_multiple; - mode_stop_next = cmd_stop; - - cmd_ready_next = 1'b0; - - if (cmd_start || cmd_address != addr_reg || cmd_read) begin - // address or mode mismatch or forced start - repeated start - - // repeated start bit - phy_start_bit = 1'b1; - bit_count_next = 4'd8; - state_next = STATE_ADDRESS_1; - end else begin - // address and mode match - - // start write - data_in_ready_next = 1'b1; - state_next = STATE_WRITE_1; - end - end else if (cmd_stop && !(cmd_read || cmd_write || cmd_write_multiple)) begin - // stop command - phy_stop_bit = 1'b1; - state_next = STATE_IDLE; - end else begin - // invalid or unspecified - ignore - state_next = STATE_ACTIVE_WRITE; - end - end else begin - if (stop_on_idle & cmd_ready & ~cmd_valid) begin - // no waiting command and stop_on_idle selected, issue stop condition - phy_stop_bit = 1'b1; - state_next = STATE_IDLE; - end else begin - state_next = STATE_ACTIVE_WRITE; - end - end - end - STATE_ACTIVE_READ: begin - // line active to current address - cmd_ready_next = ~data_out_valid; - - if (cmd_ready & cmd_valid) begin - // command valid - if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin - // read or write command - addr_next = cmd_address; - mode_read_next = cmd_read; - mode_write_multiple_next = cmd_write_multiple; - mode_stop_next = cmd_stop; - - cmd_ready_next = 1'b0; - - if (cmd_start || cmd_address != addr_reg || cmd_write) begin - // address or mode mismatch or forced start - repeated start - - // write nack for previous read - phy_write_bit = 1'b1; - phy_tx_data = 1'b1; - // repeated start bit - state_next = STATE_START; - end else begin - // address and mode match - - // write ack for previous read - phy_write_bit = 1'b1; - phy_tx_data = 1'b0; - // start next read - bit_count_next = 4'd8; - data_next = 8'd0; - state_next = STATE_READ; - end - end else if (cmd_stop && !(cmd_read || cmd_write || cmd_write_multiple)) begin - // stop command - // write nack for previous read - phy_write_bit = 1'b1; - phy_tx_data = 1'b1; - // send stop bit - state_next = STATE_STOP; - end else begin - // invalid or unspecified - ignore - state_next = STATE_ACTIVE_READ; - end - end else begin - if (stop_on_idle & cmd_ready & ~cmd_valid) begin - // no waiting command and stop_on_idle selected, issue stop condition - // write ack for previous read - phy_write_bit = 1'b1; - phy_tx_data = 1'b1; - // send stop bit - state_next = STATE_STOP; - end else begin - state_next = STATE_ACTIVE_READ; - end - end - end - STATE_START_WAIT: begin - // wait for bus idle - - if (bus_active) begin - state_next = STATE_START_WAIT; - end else begin - // bus is idle, take control - phy_start_bit = 1'b1; - bit_count_next = 4'd8; - state_next = STATE_ADDRESS_1; - end - end - STATE_START: begin - // send start bit - - phy_start_bit = 1'b1; - bit_count_next = 4'd8; - state_next = STATE_ADDRESS_1; - end - STATE_ADDRESS_1: begin - // send address - bit_count_next = bit_count_reg - 1; - if (bit_count_reg > 1) begin - // send address - phy_write_bit = 1'b1; - phy_tx_data = addr_reg[bit_count_reg-2]; - state_next = STATE_ADDRESS_1; - end else if (bit_count_reg > 0) begin - // send read/write bit - phy_write_bit = 1'b1; - phy_tx_data = mode_read_reg; - state_next = STATE_ADDRESS_1; - end else begin - // read ack bit - phy_read_bit = 1'b1; - state_next = STATE_ADDRESS_2; - end - end - STATE_ADDRESS_2: begin - // read ack bit - missed_ack_next = phy_rx_data_reg; - - if (mode_read_reg) begin - // start read - bit_count_next = 4'd8; - data_next = 1'b0; - state_next = STATE_READ; - end else begin - // start write - data_in_ready_next = 1'b1; - state_next = STATE_WRITE_1; - end - end - STATE_WRITE_1: begin - data_in_ready_next = 1'b1; - - if (data_in_ready & data_in_valid) begin - // got data, start write - data_next = data_in; - last_next = data_in_last; - bit_count_next = 4'd8; - data_in_ready_next = 1'b0; - state_next = STATE_WRITE_2; - end else begin - // wait for data - state_next = STATE_WRITE_1; - end - end - STATE_WRITE_2: begin - // send data - bit_count_next = bit_count_reg - 1; - if (bit_count_reg > 0) begin - // write data bit - phy_write_bit = 1'b1; - phy_tx_data = data_reg[bit_count_reg-1]; - state_next = STATE_WRITE_2; - end else begin - // read ack bit - phy_read_bit = 1'b1; - state_next = STATE_WRITE_3; - end - end - STATE_WRITE_3: begin - // read ack bit - missed_ack_next = phy_rx_data_reg; - - if (mode_write_multiple_reg && !last_reg) begin - // more to write - state_next = STATE_WRITE_1; - end else if (mode_stop_reg) begin - // last cycle and stop selected - phy_stop_bit = 1'b1; - state_next = STATE_IDLE; - end else begin - // otherwise, return to bus active state - state_next = STATE_ACTIVE_WRITE; - end - end - STATE_READ: begin - // read data - - bit_count_next = bit_count_reg - 1; - data_next = {data_reg[6:0], phy_rx_data_reg}; - if (bit_count_reg > 0) begin - // read next bit - phy_read_bit = 1'b1; - state_next = STATE_READ; - end else begin - // output data word - data_out_next = data_next; - data_out_valid_next = 1'b1; - data_out_last_next = 1'b0; - if (mode_stop_reg) begin - // send nack and stop - data_out_last_next = 1'b1; - phy_write_bit = 1'b1; - phy_tx_data = 1'b1; - state_next = STATE_STOP; - end else begin - // return to bus active state - state_next = STATE_ACTIVE_READ; - end - end - end - STATE_STOP: begin - // send stop bit - phy_stop_bit = 1'b1; - state_next = STATE_IDLE; - end - endcase - end -end - -always @* begin - phy_state_next = PHY_STATE_IDLE; - - phy_rx_data_next = phy_rx_data_reg; - - delay_next = delay_reg; - delay_scl_next = delay_scl_reg; - delay_sda_next = delay_sda_reg; - - scl_o_next = scl_o_reg; - sda_o_next = sda_o_reg; - - bus_control_next = bus_control_reg; - - if (phy_release_bus) begin - // release bus and return to idle state - sda_o_next = 1'b1; - scl_o_next = 1'b1; - delay_scl_next = 1'b0; - delay_sda_next = 1'b0; - delay_next = 1'b0; - phy_state_next = PHY_STATE_IDLE; - end else if (delay_scl_reg) begin - // wait for SCL to match command - delay_scl_next = scl_o_reg & ~scl_i_reg; - phy_state_next = phy_state_reg; - end else if (delay_sda_reg) begin - // wait for SDA to match command - delay_sda_next = sda_o_reg & ~sda_i_reg; - phy_state_next = phy_state_reg; - end else if (delay_reg > 0) begin - // time delay - delay_next = delay_reg - 1; - phy_state_next = phy_state_reg; - end else begin - case (phy_state_reg) - PHY_STATE_IDLE: begin - // bus idle - wait for start command - sda_o_next = 1'b1; - scl_o_next = 1'b1; - if (phy_start_bit) begin - sda_o_next = 1'b0; - delay_next = prescale; - phy_state_next = PHY_STATE_START_1; - end else begin - phy_state_next = PHY_STATE_IDLE; - end - end - PHY_STATE_ACTIVE: begin - // bus active - if (phy_start_bit) begin - sda_o_next = 1'b1; - delay_next = prescale; - phy_state_next = PHY_STATE_REPEATED_START_1; - end else if (phy_write_bit) begin - sda_o_next = phy_tx_data; - delay_next = prescale; - phy_state_next = PHY_STATE_WRITE_BIT_1; - end else if (phy_read_bit) begin - sda_o_next = 1'b1; - delay_next = prescale; - phy_state_next = PHY_STATE_READ_BIT_1; - end else if (phy_stop_bit) begin - sda_o_next = 1'b0; - delay_next = prescale; - phy_state_next = PHY_STATE_STOP_1; - end else begin - phy_state_next = PHY_STATE_ACTIVE; - end - end - PHY_STATE_REPEATED_START_1: begin - // generate repeated start bit - // ______ - // sda XXX/ \_______ - // _______ - // scl ______/ \___ - // - - scl_o_next = 1'b1; - delay_scl_next = 1'b1; - delay_next = prescale; - phy_state_next = PHY_STATE_REPEATED_START_2; - end - PHY_STATE_REPEATED_START_2: begin - // generate repeated start bit - // ______ - // sda XXX/ \_______ - // _______ - // scl ______/ \___ - // - - sda_o_next = 1'b0; - delay_next = prescale; - phy_state_next = PHY_STATE_START_1; - end - PHY_STATE_START_1: begin - // generate start bit - // ___ - // sda \_______ - // _______ - // scl \___ - // - - scl_o_next = 1'b0; - delay_next = prescale; - phy_state_next = PHY_STATE_START_2; - end - PHY_STATE_START_2: begin - // generate start bit - // ___ - // sda \_______ - // _______ - // scl \___ - // - - bus_control_next = 1'b1; - phy_state_next = PHY_STATE_ACTIVE; - end - PHY_STATE_WRITE_BIT_1: begin - // write bit - // ________ - // sda X________X - // ____ - // scl __/ \__ - - scl_o_next = 1'b1; - delay_scl_next = 1'b1; - delay_next = prescale << 1; - phy_state_next = PHY_STATE_WRITE_BIT_2; - end - PHY_STATE_WRITE_BIT_2: begin - // write bit - // ________ - // sda X________X - // ____ - // scl __/ \__ - - scl_o_next = 1'b0; - delay_next = prescale; - phy_state_next = PHY_STATE_WRITE_BIT_3; - end - PHY_STATE_WRITE_BIT_3: begin - // write bit - // ________ - // sda X________X - // ____ - // scl __/ \__ - - phy_state_next = PHY_STATE_ACTIVE; - end - PHY_STATE_READ_BIT_1: begin - // read bit - // ________ - // sda X________X - // ____ - // scl __/ \__ - - scl_o_next = 1'b1; - delay_scl_next = 1'b1; - delay_next = prescale; - phy_state_next = PHY_STATE_READ_BIT_2; - end - PHY_STATE_READ_BIT_2: begin - // read bit - // ________ - // sda X________X - // ____ - // scl __/ \__ - - phy_rx_data_next = sda_i_reg; - delay_next = prescale; - phy_state_next = PHY_STATE_READ_BIT_3; - end - PHY_STATE_READ_BIT_3: begin - // read bit - // ________ - // sda X________X - // ____ - // scl __/ \__ - - scl_o_next = 1'b0; - delay_next = prescale; - phy_state_next = PHY_STATE_READ_BIT_4; - end - PHY_STATE_READ_BIT_4: begin - // read bit - // ________ - // sda X________X - // ____ - // scl __/ \__ - - phy_state_next = PHY_STATE_ACTIVE; - end - PHY_STATE_STOP_1: begin - // stop bit - // ___ - // sda XXX\_______/ - // _______ - // scl _______/ - - scl_o_next = 1'b1; - delay_scl_next = 1'b1; - delay_next = prescale; - phy_state_next = PHY_STATE_STOP_2; - end - PHY_STATE_STOP_2: begin - // stop bit - // ___ - // sda XXX\_______/ - // _______ - // scl _______/ - - sda_o_next = 1'b1; - delay_next = prescale; - phy_state_next = PHY_STATE_STOP_3; - end - PHY_STATE_STOP_3: begin - // stop bit - // ___ - // sda XXX\_______/ - // _______ - // scl _______/ - - bus_control_next = 1'b0; - phy_state_next = PHY_STATE_IDLE; - end - endcase - end -end - -always @(posedge clk) begin - if (rst) begin - state_reg <= STATE_IDLE; - phy_state_reg <= PHY_STATE_IDLE; - delay_reg <= 16'd0; - delay_scl_reg <= 1'b0; - delay_sda_reg <= 1'b0; - cmd_ready_reg <= 1'b0; - data_in_ready_reg <= 1'b0; - data_out_valid_reg <= 1'b0; - scl_o_reg <= 1'b1; - sda_o_reg <= 1'b1; - busy_reg <= 1'b0; - bus_active_reg <= 1'b0; - bus_control_reg <= 1'b0; - missed_ack_reg <= 1'b0; - end else begin - state_reg <= state_next; - phy_state_reg <= phy_state_next; - - delay_reg <= delay_next; - delay_scl_reg <= delay_scl_next; - delay_sda_reg <= delay_sda_next; - - cmd_ready_reg <= cmd_ready_next; - data_in_ready_reg <= data_in_ready_next; - data_out_valid_reg <= data_out_valid_next; - - scl_o_reg <= scl_o_next; - sda_o_reg <= sda_o_next; - - busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ); - - if (start_bit) begin - bus_active_reg <= 1'b1; - end else if (stop_bit) begin - bus_active_reg <= 1'b0; - end else begin - bus_active_reg <= bus_active_reg; - end - - bus_control_reg <= bus_control_next; - missed_ack_reg <= missed_ack_next; - end - - phy_rx_data_reg <= phy_rx_data_next; - - addr_reg <= addr_next; - data_reg <= data_next; - last_reg <= last_next; - - mode_read_reg <= mode_read_next; - mode_write_multiple_reg <= mode_write_multiple_next; - mode_stop_reg <= mode_stop_next; - - bit_count_reg <= bit_count_next; - - data_out_reg <= data_out_next; - data_out_last_reg <= data_out_last_next; - - scl_i_reg <= scl_i; - sda_i_reg <= sda_i; - last_scl_i_reg <= scl_i_reg; - last_sda_i_reg <= sda_i_reg; -end - -endmodule diff --git a/example/VCU108/fpga_10g/rtl/si570_i2c_init.v b/example/VCU108/fpga_10g/rtl/si570_i2c_init.v deleted file mode 100644 index cea21ed6e..000000000 --- a/example/VCU108/fpga_10g/rtl/si570_i2c_init.v +++ /dev/null @@ -1,486 +0,0 @@ -/* - -Copyright (c) 2015-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * si570_i2c_init - */ -module si570_i2c_init ( - input wire clk, - input wire rst, - - /* - * I2C master interface - */ - output wire [6:0] cmd_address, - output wire cmd_start, - output wire cmd_read, - output wire cmd_write, - output wire cmd_write_multiple, - output wire cmd_stop, - output wire cmd_valid, - input wire cmd_ready, - - output wire [7:0] data_out, - output wire data_out_valid, - input wire data_out_ready, - output wire data_out_last, - - /* - * Status - */ - output wire busy, - - /* - * Configuration - */ - input wire start -); - -/* - -Generic module for I2C bus initialization. Good for use when multiple devices -on an I2C bus must be initialized on system start without intervention of a -general-purpose processor. - -Copy this file and change init_data and INIT_DATA_LEN as needed. - -This module can be used in two modes: simple device initalization, or multiple -device initialization. In multiple device mode, the same initialization sequence -can be performed on multiple different device addresses. - -To use single device mode, only use the start write to address and write data commands. -The module will generate the I2C commands in sequential order. Terminate the list -with a 0 entry. - -To use the multiple device mode, use the start data and start address block commands -to set up lists of initialization data and device addresses. The module enters -multiple device mode upon seeing a start data block command. The module stores the -offset of the start of the data block and then skips ahead until it reaches a start -address block command. The module will store the offset to the address block and -read the first address in the block. Then it will jump back to the data block -and execute it, substituting the stored address for each current address write -command. Upon reaching the start address block command, the module will read out the -next address and start again at the top of the data block. If the module encounters -a start data block command while looking for an address, then it will store a new data -offset and then look for a start address block command. Terminate the list with a 0 -entry. Normal address commands will operate normally inside a data block. - -Commands: - -00 0000000 : stop -00 0000001 : exit multiple device mode -00 0000011 : start write to current address -00 0001000 : start address block -00 0001001 : start data block -00 1000001 : send I2C stop -01 aaaaaaa : start write to address -1 dddddddd : write 8-bit data - -Examples - -write 0x11223344 to register 0x0004 on device at 0x50 - -01 1010000 start write to 0x50 -1 00000000 write address 0x0004 -1 00000100 -1 00010001 write data 0x11223344 -1 00100010 -1 00110011 -1 01000100 -0 00000000 stop - -write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 - -00 0001001 start data block -00 0000011 start write to current address -1 00000100 -1 00010001 write data 0x11223344 -1 00100010 -1 00110011 -1 01000100 -00 0001000 start address block -01 1010000 address 0x50 -01 1010000 address 0x51 -01 1010000 address 0x52 -01 1010000 address 0x53 -00 0000000 stop - -*/ - -// init_data ROM -localparam INIT_DATA_LEN = 24; - -reg [8:0] init_data [INIT_DATA_LEN-1:0]; - -initial begin - // set up I2C muxes to select U32 - init_data[0] = {2'b01, 7'b1110101}; // select U80 (0x75) - init_data[1] = {1'b1, 8'b00000000}; // disconnect all outputs - init_data[2] = {2'b00, 7'b1000001}; // I2C stop - init_data[3] = {2'b01, 7'b1110100}; // select U28 (0x74) - init_data[4] = {1'b1, 8'b00000001}; // connect only output 0 to SI570 - init_data[5] = {2'b00, 7'b1000001}; // I2C stop - // set SI570 output frequency (U32) - // freeze DCO - init_data[6] = {2'b01, 7'b1011101}; - init_data[7] = {1'b1, 8'd137}; - init_data[8] = {1'b1, 8'h10}; // 137: 0x10 - // set output to 156.25 MHz (HS_DIV=4 N1=8 DCO=5000.0 RFREQ=0x02BC035168) - init_data[9] = {2'b01, 7'b1011101}; - init_data[10] = {1'b1, 8'd7}; - init_data[11] = {1'b1, 8'h01}; // 7: HS_DIV[2:0], N1[6:2] - init_data[12] = {1'b1, 8'hC2}; // 8: N1[1:0], RFREQ[37:32] - init_data[13] = {1'b1, 8'hBC}; // 9: RFREQ[31:24] - init_data[14] = {1'b1, 8'h03}; // 10: RFREQ[23:16] - init_data[15] = {1'b1, 8'h51}; // 11: RFREQ[15:8] - init_data[16] = {1'b1, 8'h68}; // 12: RFREQ[7:0] - // un-freeze DCO - init_data[17] = {2'b01, 7'b1011101}; - init_data[18] = {1'b1, 8'd137}; - init_data[19] = {1'b1, 8'h00}; // 137: 0x00 - // new frequency - init_data[20] = {2'b01, 7'b1011101}; - init_data[21] = {1'b1, 8'd135}; - init_data[22] = {1'b1, 8'h40}; // 135: 0x40 - init_data[23] = 9'd0; // stop -end - -localparam [3:0] - STATE_IDLE = 3'd0, - STATE_RUN = 3'd1, - STATE_TABLE_1 = 3'd2, - STATE_TABLE_2 = 3'd3, - STATE_TABLE_3 = 3'd4; - -reg [4:0] state_reg = STATE_IDLE, state_next; - -parameter AW = $clog2(INIT_DATA_LEN); - -reg [8:0] init_data_reg = 9'd0; - -reg [AW-1:0] address_reg = {AW{1'b0}}, address_next; -reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next; -reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next; - -reg [6:0] cur_address_reg = 7'd0, cur_address_next; - -reg [6:0] cmd_address_reg = 7'd0, cmd_address_next; -reg cmd_start_reg = 1'b0, cmd_start_next; -reg cmd_write_reg = 1'b0, cmd_write_next; -reg cmd_stop_reg = 1'b0, cmd_stop_next; -reg cmd_valid_reg = 1'b0, cmd_valid_next; - -reg [7:0] data_out_reg = 8'd0, data_out_next; -reg data_out_valid_reg = 1'b0, data_out_valid_next; - -reg start_flag_reg = 1'b0, start_flag_next; - -reg busy_reg = 1'b0; - -assign cmd_address = cmd_address_reg; -assign cmd_start = cmd_start_reg; -assign cmd_read = 1'b0; -assign cmd_write = cmd_write_reg; -assign cmd_write_multiple = 1'b0; -assign cmd_stop = cmd_stop_reg; -assign cmd_valid = cmd_valid_reg; - -assign data_out = data_out_reg; -assign data_out_valid = data_out_valid_reg; -assign data_out_last = 1'b1; - -assign busy = busy_reg; - -always @* begin - state_next = STATE_IDLE; - - address_next = address_reg; - address_ptr_next = address_ptr_reg; - data_ptr_next = data_ptr_reg; - - cur_address_next = cur_address_reg; - - cmd_address_next = cmd_address_reg; - cmd_start_next = cmd_start_reg & ~(cmd_valid & cmd_ready); - cmd_write_next = cmd_write_reg & ~(cmd_valid & cmd_ready); - cmd_stop_next = cmd_stop_reg & ~(cmd_valid & cmd_ready); - cmd_valid_next = cmd_valid_reg & ~cmd_ready; - - data_out_next = data_out_reg; - data_out_valid_next = data_out_valid_reg & ~data_out_ready; - - start_flag_next = start_flag_reg; - - if (cmd_valid | data_out_valid) begin - // wait for output registers to clear - state_next = state_reg; - end else begin - case (state_reg) - STATE_IDLE: begin - // wait for start signal - if (~start_flag_reg & start) begin - address_next = {AW{1'b0}}; - start_flag_next = 1'b1; - state_next = STATE_RUN; - end else begin - state_next = STATE_IDLE; - end - end - STATE_RUN: begin - // process commands - if (init_data_reg[8] == 1'b1) begin - // write data - cmd_write_next = 1'b1; - cmd_stop_next = 1'b0; - cmd_valid_next = 1'b1; - - data_out_next = init_data_reg[7:0]; - data_out_valid_next = 1'b1; - - address_next = address_reg + 1; - - state_next = STATE_RUN; - end else if (init_data_reg[8:7] == 2'b01) begin - // write address - cmd_address_next = init_data_reg[6:0]; - cmd_start_next = 1'b1; - - address_next = address_reg + 1; - - state_next = STATE_RUN; - end else if (init_data_reg == 9'b001000001) begin - // send stop - cmd_write_next = 1'b0; - cmd_start_next = 1'b0; - cmd_stop_next = 1'b1; - cmd_valid_next = 1'b1; - - address_next = address_reg + 1; - - state_next = STATE_RUN; - end else if (init_data_reg == 9'b000001001) begin - // data table start - data_ptr_next = address_reg + 1; - address_next = address_reg + 1; - state_next = STATE_TABLE_1; - end else if (init_data_reg == 9'd0) begin - // stop - cmd_start_next = 1'b0; - cmd_write_next = 1'b0; - cmd_stop_next = 1'b1; - cmd_valid_next = 1'b1; - - state_next = STATE_IDLE; - end else begin - // invalid command, skip - address_next = address_reg + 1; - state_next = STATE_RUN; - end - end - STATE_TABLE_1: begin - // find address table start - if (init_data_reg == 9'b000001000) begin - // address table start - address_ptr_next = address_reg + 1; - address_next = address_reg + 1; - state_next = STATE_TABLE_2; - end else if (init_data_reg == 9'b000001001) begin - // data table start - data_ptr_next = address_reg + 1; - address_next = address_reg + 1; - state_next = STATE_TABLE_1; - end else if (init_data_reg == 1) begin - // exit mode - address_next = address_reg + 1; - state_next = STATE_RUN; - end else if (init_data_reg == 9'd0) begin - // stop - cmd_start_next = 1'b0; - cmd_write_next = 1'b0; - cmd_stop_next = 1'b1; - cmd_valid_next = 1'b1; - - state_next = STATE_IDLE; - end else begin - // invalid command, skip - address_next = address_reg + 1; - state_next = STATE_TABLE_1; - end - end - STATE_TABLE_2: begin - // find next address - if (init_data_reg[8:7] == 2'b01) begin - // write address command - // store address and move to data table - cur_address_next = init_data_reg[6:0]; - address_ptr_next = address_reg + 1; - address_next = data_ptr_reg; - state_next = STATE_TABLE_3; - end else if (init_data_reg == 9'b000001001) begin - // data table start - data_ptr_next = address_reg + 1; - address_next = address_reg + 1; - state_next = STATE_TABLE_1; - end else if (init_data_reg == 9'd1) begin - // exit mode - address_next = address_reg + 1; - state_next = STATE_RUN; - end else if (init_data_reg == 9'd0) begin - // stop - cmd_start_next = 1'b0; - cmd_write_next = 1'b0; - cmd_stop_next = 1'b1; - cmd_valid_next = 1'b1; - - state_next = STATE_IDLE; - end else begin - // invalid command, skip - address_next = address_reg + 1; - state_next = STATE_TABLE_2; - end - end - STATE_TABLE_3: begin - // process data table with selected address - if (init_data_reg[8] == 1'b1) begin - // write data - cmd_write_next = 1'b1; - cmd_stop_next = 1'b0; - cmd_valid_next = 1'b1; - - data_out_next = init_data_reg[7:0]; - data_out_valid_next = 1'b1; - - address_next = address_reg + 1; - - state_next = STATE_TABLE_3; - end else if (init_data_reg[8:7] == 2'b01) begin - // write address - cmd_address_next = init_data_reg[6:0]; - cmd_start_next = 1'b1; - - address_next = address_reg + 1; - - state_next = STATE_TABLE_3; - end else if (init_data_reg == 9'b000000011) begin - // write current address - cmd_address_next = cur_address_reg; - cmd_start_next = 1'b1; - - address_next = address_reg + 1; - - state_next = STATE_TABLE_3; - end else if (init_data_reg == 9'b001000001) begin - // send stop - cmd_write_next = 1'b0; - cmd_start_next = 1'b0; - cmd_stop_next = 1'b1; - cmd_valid_next = 1'b1; - - address_next = address_reg + 1; - - state_next = STATE_TABLE_3; - end else if (init_data_reg == 9'b000001001) begin - // data table start - data_ptr_next = address_reg + 1; - address_next = address_reg + 1; - state_next = STATE_TABLE_1; - end else if (init_data_reg == 9'b000001000) begin - // address table start - address_next = address_ptr_reg; - state_next = STATE_TABLE_2; - end else if (init_data_reg == 9'd1) begin - // exit mode - address_next = address_reg + 1; - state_next = STATE_RUN; - end else if (init_data_reg == 9'd0) begin - // stop - cmd_start_next = 1'b0; - cmd_write_next = 1'b0; - cmd_stop_next = 1'b1; - cmd_valid_next = 1'b1; - - state_next = STATE_IDLE; - end else begin - // invalid command, skip - address_next = address_reg + 1; - state_next = STATE_TABLE_3; - end - end - endcase - end -end - -always @(posedge clk) begin - if (rst) begin - state_reg <= STATE_IDLE; - - init_data_reg <= 9'd0; - - address_reg <= {AW{1'b0}}; - address_ptr_reg <= {AW{1'b0}}; - data_ptr_reg <= {AW{1'b0}}; - - cur_address_reg <= 7'd0; - - cmd_valid_reg <= 1'b0; - - data_out_valid_reg <= 1'b0; - - start_flag_reg <= 1'b0; - - busy_reg <= 1'b0; - end else begin - state_reg <= state_next; - - // read init_data ROM - init_data_reg <= init_data[address_next]; - - address_reg <= address_next; - address_ptr_reg <= address_ptr_next; - data_ptr_reg <= data_ptr_next; - - cur_address_reg <= cur_address_next; - - cmd_valid_reg <= cmd_valid_next; - - data_out_valid_reg <= data_out_valid_next; - - start_flag_reg <= start & start_flag_next; - - busy_reg <= (state_reg != STATE_IDLE); - end - - cmd_address_reg <= cmd_address_next; - cmd_start_reg <= cmd_start_next; - cmd_write_reg <= cmd_write_next; - cmd_stop_reg <= cmd_stop_next; - - data_out_reg <= data_out_next; -end - -endmodule diff --git a/example/VCU108/fpga_10g/tb/test_fpga_core.py b/example/VCU108/fpga_10g/tb/test_fpga_core.py index ada6a5e36..92c8db291 100755 --- a/example/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/example/VCU108/fpga_10g/tb/test_fpga_core.py @@ -95,12 +95,28 @@ def bench(): btnr = Signal(bool(0)) btnc = Signal(bool(0)) sw = Signal(intbv(0)[4:]) + qsfp_tx_clk_1 = Signal(bool(0)) + qsfp_tx_rst_1 = Signal(bool(0)) + qsfp_rx_clk_1 = Signal(bool(0)) + qsfp_rx_rst_1 = Signal(bool(0)) qsfp_rxd_1 = Signal(intbv(0)[64:]) qsfp_rxc_1 = Signal(intbv(0)[8:]) + qsfp_tx_clk_2 = Signal(bool(0)) + qsfp_tx_rst_2 = Signal(bool(0)) + qsfp_rx_clk_2 = Signal(bool(0)) + qsfp_rx_rst_2 = Signal(bool(0)) qsfp_rxd_2 = Signal(intbv(0)[64:]) qsfp_rxc_2 = Signal(intbv(0)[8:]) + qsfp_tx_clk_3 = Signal(bool(0)) + qsfp_tx_rst_3 = Signal(bool(0)) + qsfp_rx_clk_3 = Signal(bool(0)) + qsfp_rx_rst_3 = Signal(bool(0)) qsfp_rxd_3 = Signal(intbv(0)[64:]) qsfp_rxc_3 = Signal(intbv(0)[8:]) + qsfp_tx_clk_4 = Signal(bool(0)) + qsfp_tx_rst_4 = Signal(bool(0)) + qsfp_rx_clk_4 = Signal(bool(0)) + qsfp_rx_rst_4 = Signal(bool(0)) qsfp_rxd_4 = Signal(intbv(0)[64:]) qsfp_rxc_4 = Signal(intbv(0)[8:]) phy_gmii_clk = Signal(bool(0)) @@ -132,28 +148,28 @@ def bench(): # sources and sinks qsfp_1_source = xgmii_ep.XGMIISource() - qsfp_1_source_logic = qsfp_1_source.create_logic(clk, rst, txd=qsfp_rxd_1, txc=qsfp_rxc_1, name='qsfp_1_source') + qsfp_1_source_logic = qsfp_1_source.create_logic(qsfp_rx_clk_1, qsfp_rx_rst_1, txd=qsfp_rxd_1, txc=qsfp_rxc_1, name='qsfp_1_source') qsfp_1_sink = xgmii_ep.XGMIISink() - qsfp_1_sink_logic = qsfp_1_sink.create_logic(clk, rst, rxd=qsfp_txd_1, rxc=qsfp_txc_1, name='qsfp_1_sink') + qsfp_1_sink_logic = qsfp_1_sink.create_logic(qsfp_tx_clk_1, qsfp_tx_rst_1, rxd=qsfp_txd_1, rxc=qsfp_txc_1, name='qsfp_1_sink') qsfp_2_source = xgmii_ep.XGMIISource() - qsfp_2_source_logic = qsfp_2_source.create_logic(clk, rst, txd=qsfp_rxd_2, txc=qsfp_rxc_2, name='qsfp_2_source') + qsfp_2_source_logic = qsfp_2_source.create_logic(qsfp_rx_clk_2, qsfp_rx_rst_2, txd=qsfp_rxd_2, txc=qsfp_rxc_2, name='qsfp_2_source') qsfp_2_sink = xgmii_ep.XGMIISink() - qsfp_2_sink_logic = qsfp_2_sink.create_logic(clk, rst, rxd=qsfp_txd_2, rxc=qsfp_txc_2, name='qsfp_2_sink') + qsfp_2_sink_logic = qsfp_2_sink.create_logic(qsfp_tx_clk_2, qsfp_tx_rst_2, rxd=qsfp_txd_2, rxc=qsfp_txc_2, name='qsfp_2_sink') qsfp_3_source = xgmii_ep.XGMIISource() - qsfp_3_source_logic = qsfp_3_source.create_logic(clk, rst, txd=qsfp_rxd_3, txc=qsfp_rxc_3, name='qsfp_3_source') + qsfp_3_source_logic = qsfp_3_source.create_logic(qsfp_rx_clk_3, qsfp_rx_rst_3, txd=qsfp_rxd_3, txc=qsfp_rxc_3, name='qsfp_3_source') qsfp_3_sink = xgmii_ep.XGMIISink() - qsfp_3_sink_logic = qsfp_3_sink.create_logic(clk, rst, rxd=qsfp_txd_3, rxc=qsfp_txc_3, name='qsfp_3_sink') + qsfp_3_sink_logic = qsfp_3_sink.create_logic(qsfp_tx_clk_3, qsfp_tx_rst_3, rxd=qsfp_txd_3, rxc=qsfp_txc_3, name='qsfp_3_sink') qsfp_4_source = xgmii_ep.XGMIISource() - qsfp_4_source_logic = qsfp_4_source.create_logic(clk, rst, txd=qsfp_rxd_4, txc=qsfp_rxc_4, name='qsfp_4_source') + qsfp_4_source_logic = qsfp_4_source.create_logic(qsfp_rx_clk_4, qsfp_rx_rst_4, txd=qsfp_rxd_4, txc=qsfp_rxc_4, name='qsfp_4_source') qsfp_4_sink = xgmii_ep.XGMIISink() - qsfp_4_sink_logic = qsfp_4_sink.create_logic(clk, rst, rxd=qsfp_txd_4, rxc=qsfp_txc_4, name='qsfp_4_sink') + qsfp_4_sink_logic = qsfp_4_sink.create_logic(qsfp_tx_clk_4, qsfp_tx_rst_4, rxd=qsfp_txd_4, rxc=qsfp_txc_4, name='qsfp_4_sink') gmii_source = gmii_ep.GMIISource() @@ -197,20 +213,36 @@ def bench(): sw=sw, led=led, + qsfp_tx_clk_1=qsfp_tx_clk_1, + qsfp_tx_rst_1=qsfp_tx_rst_1, qsfp_txd_1=qsfp_txd_1, qsfp_txc_1=qsfp_txc_1, + qsfp_rx_clk_1=qsfp_rx_clk_1, + qsfp_rx_rst_1=qsfp_rx_rst_1, qsfp_rxd_1=qsfp_rxd_1, qsfp_rxc_1=qsfp_rxc_1, + qsfp_tx_clk_2=qsfp_tx_clk_2, + qsfp_tx_rst_2=qsfp_tx_rst_2, qsfp_txd_2=qsfp_txd_2, qsfp_txc_2=qsfp_txc_2, + qsfp_rx_clk_2=qsfp_rx_clk_2, + qsfp_rx_rst_2=qsfp_rx_rst_2, qsfp_rxd_2=qsfp_rxd_2, qsfp_rxc_2=qsfp_rxc_2, + qsfp_tx_clk_3=qsfp_tx_clk_3, + qsfp_tx_rst_3=qsfp_tx_rst_3, qsfp_txd_3=qsfp_txd_3, qsfp_txc_3=qsfp_txc_3, + qsfp_rx_clk_3=qsfp_rx_clk_3, + qsfp_rx_rst_3=qsfp_rx_rst_3, qsfp_rxd_3=qsfp_rxd_3, qsfp_rxc_3=qsfp_rxc_3, + qsfp_tx_clk_4=qsfp_tx_clk_4, + qsfp_tx_rst_4=qsfp_tx_rst_4, qsfp_txd_4=qsfp_txd_4, qsfp_txc_4=qsfp_txc_4, + qsfp_rx_clk_4=qsfp_rx_clk_4, + qsfp_rx_rst_4=qsfp_rx_rst_4, qsfp_rxd_4=qsfp_rxd_4, qsfp_rxc_4=qsfp_rxc_4, @@ -235,6 +267,14 @@ def bench(): @always(delay(4)) def clkgen(): clk.next = not clk + qsfp_tx_clk_1.next = not qsfp_tx_clk_1 + qsfp_rx_clk_1.next = not qsfp_rx_clk_1 + qsfp_tx_clk_2.next = not qsfp_tx_clk_2 + qsfp_rx_clk_2.next = not qsfp_rx_clk_2 + qsfp_tx_clk_3.next = not qsfp_tx_clk_3 + qsfp_rx_clk_3.next = not qsfp_rx_clk_3 + qsfp_tx_clk_4.next = not qsfp_tx_clk_4 + qsfp_rx_clk_4.next = not qsfp_rx_clk_4 phy_gmii_clk.next = not phy_gmii_clk clk_enable_rate = Signal(int(0)) @@ -254,9 +294,25 @@ def bench(): yield delay(100) yield clk.posedge rst.next = 1 + qsfp_tx_rst_1.next = 1 + qsfp_rx_rst_1.next = 1 + qsfp_tx_rst_2.next = 1 + qsfp_rx_rst_2.next = 1 + qsfp_tx_rst_3.next = 1 + qsfp_rx_rst_3.next = 1 + qsfp_tx_rst_4.next = 1 + qsfp_rx_rst_4.next = 1 phy_gmii_rst.next = 1 yield clk.posedge rst.next = 0 + qsfp_tx_rst_1.next = 0 + qsfp_rx_rst_1.next = 0 + qsfp_tx_rst_2.next = 0 + qsfp_rx_rst_2.next = 0 + qsfp_tx_rst_3.next = 0 + qsfp_rx_rst_3.next = 0 + qsfp_tx_rst_4.next = 0 + qsfp_rx_rst_4.next = 0 phy_gmii_rst.next = 0 yield clk.posedge yield delay(100) diff --git a/example/VCU108/fpga_10g/tb/test_fpga_core.v b/example/VCU108/fpga_10g/tb/test_fpga_core.v index 6093a0a61..04b913f58 100644 --- a/example/VCU108/fpga_10g/tb/test_fpga_core.v +++ b/example/VCU108/fpga_10g/tb/test_fpga_core.v @@ -44,12 +44,28 @@ reg btnd = 0; reg btnr = 0; reg btnc = 0; reg [3:0] sw = 0; +reg qsfp_tx_clk_1 = 0; +reg qsfp_tx_rst_1 = 0; +reg qsfp_rx_clk_1 = 0; +reg qsfp_rx_rst_1 = 0; reg [63:0] qsfp_rxd_1 = 0; reg [7:0] qsfp_rxc_1 = 0; +reg qsfp_tx_clk_2 = 0; +reg qsfp_tx_rst_2 = 0; +reg qsfp_rx_clk_2 = 0; +reg qsfp_rx_rst_2 = 0; reg [63:0] qsfp_rxd_2 = 0; reg [7:0] qsfp_rxc_2 = 0; +reg qsfp_tx_clk_3 = 0; +reg qsfp_tx_rst_3 = 0; +reg qsfp_rx_clk_3 = 0; +reg qsfp_rx_rst_3 = 0; reg [63:0] qsfp_rxd_3 = 0; reg [7:0] qsfp_rxc_3 = 0; +reg qsfp_tx_clk_4 = 0; +reg qsfp_tx_rst_4 = 0; +reg qsfp_rx_clk_4 = 0; +reg qsfp_rx_rst_4 = 0; reg [63:0] qsfp_rxd_4 = 0; reg [7:0] qsfp_rxc_4 = 0; reg phy_gmii_clk = 0; @@ -92,12 +108,28 @@ initial begin btnr, btnc, sw, + qsfp_tx_clk_1, + qsfp_tx_rst_1, + qsfp_rx_clk_1, + qsfp_rx_rst_1, qsfp_rxd_1, qsfp_rxc_1, + qsfp_tx_clk_2, + qsfp_tx_rst_2, + qsfp_rx_clk_2, + qsfp_rx_rst_2, qsfp_rxd_2, qsfp_rxc_2, + qsfp_tx_clk_3, + qsfp_tx_rst_3, + qsfp_rx_clk_3, + qsfp_rx_rst_3, qsfp_rxd_3, qsfp_rxc_3, + qsfp_tx_clk_4, + qsfp_tx_rst_4, + qsfp_rx_clk_4, + qsfp_rx_rst_4, qsfp_rxd_4, qsfp_rxc_4, phy_gmii_clk, @@ -144,20 +176,36 @@ UUT ( .btnc(btnc), .sw(sw), .led(led), + .qsfp_tx_clk_1(qsfp_tx_clk_1), + .qsfp_tx_rst_1(qsfp_tx_rst_1), .qsfp_txd_1(qsfp_txd_1), .qsfp_txc_1(qsfp_txc_1), + .qsfp_rx_clk_1(qsfp_rx_clk_1), + .qsfp_rx_rst_1(qsfp_rx_rst_1), .qsfp_rxd_1(qsfp_rxd_1), .qsfp_rxc_1(qsfp_rxc_1), + .qsfp_tx_clk_2(qsfp_tx_clk_2), + .qsfp_tx_rst_2(qsfp_tx_rst_2), .qsfp_txd_2(qsfp_txd_2), .qsfp_txc_2(qsfp_txc_2), + .qsfp_rx_clk_2(qsfp_rx_clk_2), + .qsfp_rx_rst_2(qsfp_rx_rst_2), .qsfp_rxd_2(qsfp_rxd_2), .qsfp_rxc_2(qsfp_rxc_2), + .qsfp_tx_clk_3(qsfp_tx_clk_3), + .qsfp_tx_rst_3(qsfp_tx_rst_3), .qsfp_txd_3(qsfp_txd_3), .qsfp_txc_3(qsfp_txc_3), + .qsfp_rx_clk_3(qsfp_rx_clk_3), + .qsfp_rx_rst_3(qsfp_rx_rst_3), .qsfp_rxd_3(qsfp_rxd_3), .qsfp_rxc_3(qsfp_rxc_3), + .qsfp_tx_clk_4(qsfp_tx_clk_4), + .qsfp_tx_rst_4(qsfp_tx_rst_4), .qsfp_txd_4(qsfp_txd_4), .qsfp_txc_4(qsfp_txc_4), + .qsfp_rx_clk_4(qsfp_rx_clk_4), + .qsfp_rx_rst_4(qsfp_rx_rst_4), .qsfp_rxd_4(qsfp_rxd_4), .qsfp_rxc_4(qsfp_rxc_4), .phy_gmii_clk(phy_gmii_clk), diff --git a/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci b/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci index 1db9474cb..91b324db6 100644 --- a/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci +++ b/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci @@ -309,16 +309,17 @@ MIXED -2 + E TRUE TRUE IP_Flow - 5 + 6 TRUE . . - 2018.3 + 2019.1 OUT_OF_CONTEXT