Update readme

README.md

@@ -14,14 +14,14 @@ utilize [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi).
 
 ## Documentation
 
-### arbiter module
+### `arbiter` module
 
 General-purpose parametrizable arbiter.  Supports priority and round-robin
 arbitration.  Supports blocking until request release or acknowledge.  
 
-### axis_adapter module
+### `axis_adapter` module
 
-The axis_adapter module bridges AXI stream busses of differing widths.  The
+The `axis_adapter` module bridges AXI stream buses of differing widths.  The
 module is parametrizable, but there are certain restrictions.  First, the bus
 word widths must be identical (e.g. one 8-bit lane and eight 8-bit lanes, but
 not one 16-bit lane and one 32-bit lane).  Second, the bus widths must be
@@ -29,80 +29,80 @@ related by an integer multiple (e.g. 2 words and 6 words, but not 4 words
 and 6 words).  Wait states will be inserted on the wider bus side when
 necessary.
 
-### axis_arb_mux module
+### `axis_arb_mux` module
 
-Frame-aware AXI stream arbitrated muliplexer with parametrizable data width
+Frame-aware AXI stream arbitrated multiplexer with parametrizable data width
 and port count.  Supports priority and round-robin arbitration.
 
-Wrappers can generated with axis_arb_mux_wrap.py.
+Wrappers can generated with `axis_arb_mux_wrap.py`.
 
-### axis_async_fifo module
+### `axis_async_fifo` module
 
 Configurable word-based or frame-based asynchronous FIFO with parametrizable
 data width, depth, type, and bad frame detection.  Supports power of two
 depths only.
 
-### axis_async_fifo_adapter module
+### `axis_async_fifo_adapter` module
 
 Configurable word-based or frame-based asynchronous FIFO with parametrizable
 data width, depth, type, and bad frame detection.  Supports different input
 and output data widths, inserting an axis_adapter instance appropriately.
 Supports power of two depths only.
 
-### axis_broadcast module
+### `axis_broadcast` module
 
 AXI stream broadcaster.  Duplicates one input stream across multiple output
 streams.
 
-### axis_cobs_decode
+### `axis_cobs_decode`
 
 Consistent Overhead Byte Stuffing (COBS) decoder.  Fixed 8 bit width.
 
-### axis_cobs_encode
+### `axis_cobs_encode`
 
 Consistent Overhead Byte Stuffing (COBS) encoder.  Fixed 8 bit width.
 Configurable zero insertion.
 
-### axis_crosspoint module
+### `axis_crosspoint` module
 
-Basic crosspoint switch.  tready signal not supported.  Parametrizable data
+Basic crosspoint switch.  `tready` signal not supported.  Parametrizable data
 width.  
 
-Wrappers can generated with axis_crosspoint_wrap.py.
+Wrappers can generated with `axis_crosspoint_wrap.py`.
 
-### axis_demux module
+### `axis_demux` module
 
-Frame-aware AXI stream demuliplexer with parametrizable data width and port
+Frame-aware AXI stream demultiplexer with parametrizable data width and port
 count.
 
-### axis_fifo module
+### `axis_fifo` module
 
 Configurable word-based or frame-based synchronous FIFO with parametrizable
 data width, depth, type, and bad frame detection.  Supports power of two
 depths only.
 
-### axis_fifo_adapter module
+### `axis_fifo_adapter` module
 
 Configurable word-based or frame-based synchronous FIFO with parametrizable
 data width, depth, type, and bad frame detection.  Supports different input
 and output data widths, inserting an axis_adapter instance appropriately.
 Supports power of two depths only.
 
-### axis_frame_join module
+### `axis_frame_join` module
 
 Frame joiner with optional tag and parametrizable port count.  8 bit data path
 only.
 
-Wrappers can generated with axis_frame_join_wrap.py.
+Wrappers can generated with `axis_frame_join_wrap.py`.
 
-### axis_frame_length_adjust module
+### `axis_frame_length_adjust` module
 
 Frame length adjuster module.  Truncates or pads frames as necessary to meet
 the specified minimum and maximum length.  Reports the original and current
 lengths as well as whether the packet was truncated or padded.  Length limits
 are configurable at run time.
 
-### axis_frame_length_adjust_fifo module
+### `axis_frame_length_adjust_fifo` module
 
 Frame length adjuster module with FIFO.  Truncates or pads frames as necessary
 to meet the specified minimum and maximum length.  Reports the original and
@@ -110,75 +110,75 @@ current lengths as well as whether the packet was truncated or padded.  FIFOs
 are used so that the status information can be read before the packet itself.
 Length limits are configurable at run time.
 
-### axis_ll_bridge module
+### `axis_ll_bridge` module
 
 AXI stream to LocalLink bridge.
 
-### axis_mux module
+### `axis_mux` module
 
-Frame-aware AXI stream muliplexer with parametrizable data width and port
+Frame-aware AXI stream multiplexer with parametrizable data width and port
 count.
 
-Wrappers can generated with axis_mux_wrap.py.
+Wrappers can generated with `axis_mux_wrap.py`.
 
-### axis_pipeline_register module
+### `axis_pipeline_register` module
 
 Parametrizable register pipeline.  LENGTH parameter determines number of
 register stages.
 
-### axis_ram_switch module
+### `axis_ram_switch` module
 
 Frame-aware AXI stream RAM switch with parametrizable data width, port count,
 and FIFO size.  Uses block RAM for storing packets in transit, time-sharing
 the RAM interface between ports.  Functionally equivalent to a combination of
 per-port frame FIFOs and width converters connected to an AXI stream switch.
 
-### axis_rate_limit module
+### `axis_rate_limit` module
 
 Fractional rate limiter, supports word and frame modes.  Inserts wait states
 to limit data rate to specified ratio.  Frame mode inserts wait states at end
 of frames, word mode ignores frames and inserts wait states at any point.
 Parametrizable data width.  Rate and mode are configurable at run time.
 
-### axis_register module
+### `axis_register` module
 
 Datapath register with parameter to select between skid buffer, simple buffer,
 and bypass.  Use to improve timing for long routes.
 
-### axis_srl_fifo module
+### `axis_srl_fifo` module
 
 SRL-based FIFO.  Good for small FIFOs.  SRLs on Xilinx FPGAs have a very fast
 input setup time, so this module can be used to aid in timing closure.
 
-### axis_srl_register module
+### `axis_srl_register` module
 
 SRL-based register.  SRLs on Xilinx FPGAs have a very fast input setup time,
 so this module can be used to aid in timing closure.
 
-### axis_stat_counter module
+### `axis_stat_counter` module
 
 Statistics counter module.  Counts bytes and frames passing through monitored
 AXI stream interface.  Trigger signal used to reset and dump counts out of AXI
-interface, along with tag value.  Use with axis_frame_join_N to form a single
+interface, along with tag value.  Use with `axis_frame_join` to form a single
 monolithic frame from multiple monitored points with the same trigger.
 
-### axis_switch module
+### `axis_switch` module
 
 Frame-aware AXI stream switch with parametrizable data width and port count.
 
-Wrappers can generated with axis_switch_wrap.py.
+Wrappers can generated with `axis_switch_wrap.py`.
 
-### axis_tap module
+### `axis_tap` module
 
 AXI stream tap module.  Used to make a copy of an AXI stream bus without
 affecting the bus.  Back-pressure on the output results in truncated frames
-with tuser set.
+with `tuser` set.
 
-### ll_axis_bridge module
+### `ll_axis_bridge` module
 
 LocalLink to AXI stream bridge.
 
-### priority_encoder module
+### `priority_encoder` module
 
 Parametrizable priority encoder.