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Use new PTP time distribution subsystem

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-07 21:57:07 -08:00
parent 56887b8aed
commit 2a7d0e0947
248 changed files with 2429 additions and 1810 deletions
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2
docs/source/rb/index.rst
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@ -78,7 +78,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0x0000C040 0x00000100 :ref:`rb_sched_rr`
0x0000C050 0x00000100 :ref:`rb_sched_ctrl_tdma`
0x0000C060 0x00000100 :ref:`rb_tdma_sch`
0x0000C080 0x00000100 :ref:`rb_phc`
0x0000C080 0x00000200 :ref:`rb_phc`
0x0000C081 0x00000100 :ref:`rb_phc_perout`
0x0000C090 0x00000200 :ref:`rb_rx_queue_map`
0x0000C100 0x00000100 :ref:`rb_gpio`

175
docs/source/rb/phc.rst
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@ -4,7 +4,7 @@
PTP hardware clock register block
=================================
The PTP hardware clock register block has a header with type 0x0000C080, version 0x00000100, and carries several control registers for the PTP clock.
The PTP hardware clock register block has a header with type 0x0000C080, version 0x00000200, and carries several control registers for the PTP clock.
.. table::
@ -13,55 +13,104 @@ The PTP hardware clock register block has a header with type 0x0000C080, version
======== ============== ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C080
-------- -------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000100
RBB+0x04 Version Major Minor Patch Meta RO 0x00000200
-------- -------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- -------------- ------------------------------ -------------
RBB+0x0C Control Control RO -
RBB+0x0C Control Control RW -
-------- -------------- ------------------------------ -------------
RBB+0x10 Current time Current time (fractional ns) RO -
RBB+0x10 Current FNS Current fractional ns RO -
-------- -------------- ------------------------------ -------------
RBB+0x14 Current time Current time (ns) RO -
RBB+0x14 Current ToD Current ToD (ns) RO -
-------- -------------- ------------------------------ -------------
RBB+0x18 Current time Current time (sec, lower 32) RO -
RBB+0x18 Current ToD Current ToD (sec, lower 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x1C Current time Current time (sec, upper 32) RO -
RBB+0x1C Current ToD Current ToD (sec, upper 16) RO -
-------- -------------- ------------------------------ -------------
RBB+0x20 Get time Get time (fractional ns) RO -
RBB+0x20 Current rel Current rel. (ns, lower 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x24 Get time Get time (ns) RO -
RBB+0x24 Current rel Current rel. (ns, upper 16) RO -
-------- -------------- ------------------------------ -------------
RBB+0x28 Get time Get time (sec, lower 32) RO -
RBB+0x28 Current PTM Current PTM (ns, lower 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x2C Get time Get time (sec, upper 32) RO -
RBB+0x2C Current PTM Current PTM (ns, upper 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x30 Set time Set time (fractional ns) RW -
RBB+0x30 Snapshot FNS Snapshot fractional ns RO -
-------- -------------- ------------------------------ -------------
RBB+0x34 Set time Set time (ns) RW -
RBB+0x34 Snapshot ToD Snapshot ToD (ns) RO -
-------- -------------- ------------------------------ -------------
RBB+0x38 Set time Set time (sec, lower 32) RW -
RBB+0x38 Snapshot ToD Snapshot ToD (sec, lower 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x3C Set time Set time (sec, upper 32) RW -
RBB+0x3C Snapshot ToD Snapshot ToD (sec, upper 16) RO -
-------- -------------- ------------------------------ -------------
RBB+0x40 Period Period (fractional ns) RW -
RBB+0x40 Snapshot rel Snapshot rel. (ns, lower 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x44 Period Period (ns) RW -
RBB+0x44 Snapshot rel Snapshot rel. (ns, upper 16) RO -
-------- -------------- ------------------------------ -------------
RBB+0x48 Nominal period Nominal period (fractional ns) RO -
RBB+0x48 Snapshot PTM Snapshot PTM (ns, lower 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x4C Nominal period Nominal period (ns) RO -
RBB+0x4C Snapshot PTM Snapshot PTM (ns, upper 32) RO -
-------- -------------- ------------------------------ -------------
RBB+0x50 Adj time Adj time (fractional ns) RW -
RBB+0x50 Offset ToD Offset ToD (ns) RW -
-------- -------------- ------------------------------ -------------
RBB+0x54 Adj time Adj time (ns) RW -
RBB+0x54 Set ToD Set ToD (ns) RW -
-------- -------------- ------------------------------ -------------
RBB+0x58 Adj time count Adj time cycle count RW -
RBB+0x58 Set ToD Set ToD (sec, lower 32) RW -
-------- -------------- ------------------------------ -------------
RBB+0x5C Adj time act Adj time active RO -
RBB+0x5C Set ToD Set ToD (sec, upper 16) RW -
-------- -------------- ------------------------------ -------------
RBB+0x60 Set rel Set rel. (ns, lower 32) RW -
-------- -------------- ------------------------------ -------------
RBB+0x64 Set rel Set rel. (ns, upper 16) RW -
-------- -------------- ------------------------------ -------------
RBB+0x68 Offset rel Offset relative (ns) RW -
-------- -------------- ------------------------------ -------------
RBB+0x6C Offset FNS Offset FNS (fns) RW -
-------- -------------- ------------------------------ -------------
RBB+0x70 Nominal period Nominal period (fractional ns) RO -
-------- -------------- ------------------------------ -------------
RBB+0x74 Nominal period Nominal period (ns) RO -
-------- -------------- ------------------------------ -------------
RBB+0x78 Period Period (fractional ns) RW -
-------- -------------- ------------------------------ -------------
RBB+0x7C Period Period (ns) RW -
======== ============== ============================== =============
See :ref:`rb_overview` for definitions of the standard register block header fields.
.. object:: Control
The control register contains several control and status bits relating to the operation of the PTP hardware clock.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x0C Control RW -
======== ============================== =============
.. table::
=== ========
Bit Function
=== ========
8 PPS pulse
16 Locked
24 Set ToD pending
25 Offset ToD pending
26 Set Relative pending
27 Offset Relative pending
28 Set Period pending
29 Offset FNS pending
=== ========
The PPS pulse bit reflects the current value of the stretched PPS output (rising edge is the active edge).
The locked bit indicates that the PTP CDC logic between the PTP clock domain and the core clock domain is locked, and therefore the times in the current and snapshot registers are valid.
The pending bits indicate that a set or offset has been requested, but has not yet been applied.
.. object:: Current time
The current time registers read the current time from the PTP clock, with no double-buffering.
@ -71,16 +120,24 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x10 Current time (fractional ns) RO -
RBB+0x10 Current fractional ns RO -
-------- ------------------------------ -------------
RBB+0x14 Current time (ns) RO -
RBB+0x14 Current ToD (ns) RO -
-------- ------------------------------ -------------
RBB+0x18 Current time (sec, lower 32) RO -
RBB+0x18 Current ToD (sec, lower 32) RO -
-------- ------------------------------ -------------
RBB+0x1C Current time (sec, upper 32) RO -
RBB+0x1C Current ToD (sec, upper 16) RO -
-------- ------------------------------ -------------
RBB+0x20 Current rel. (ns, lower 32) RO -
-------- ------------------------------ -------------
RBB+0x24 Current rel. (ns, upper 16) RO -
-------- ------------------------------ -------------
RBB+0x28 Current PTM (ns, lower 32) RO -
-------- ------------------------------ -------------
RBB+0x2C Current PTM (ns, upper 32) RO -
======== ============================== =============
.. object:: Get time
.. object:: Snapshot time
The get time registers read the current time from the PTP clock, with all values latched coincident with reading the fractional ns register.
@ -89,45 +146,47 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x20 Get time (fractional ns) RO -
RBB+0x30 Snapshot fractional ns RO -
-------- ------------------------------ -------------
RBB+0x24 Get time (ns) RO -
RBB+0x34 Snapshot ToD (ns) RO -
-------- ------------------------------ -------------
RBB+0x28 Get time (sec, lower 32) RO -
RBB+0x38 Snapshot ToD (sec, lower 32) RO -
-------- ------------------------------ -------------
RBB+0x2C Get time (sec, upper 32) RO -
RBB+0x3C Snapshot ToD (sec, upper 16) RO -
-------- ------------------------------ -------------
RBB+0x40 Snapshot rel. (ns, lower 32) RO -
-------- ------------------------------ -------------
RBB+0x44 Snapshot rel. (ns, upper 16) RO -
-------- ------------------------------ -------------
RBB+0x48 Snapshot PTM (ns, lower 32) RO -
-------- ------------------------------ -------------
RBB+0x4C Snapshot PTM (ns, upper 32) RO -
======== ============================== =============
.. object:: Set time
The set time registers set the current time on the PTP clock, with all values latched coincident with writing the upper 32 bits of the seconds field.
The set time registers set the current time on the PTP clock, while the offset registers can be used to apply precise steps to the PTP clock. The ToD setting is applied when the upper 16 bits of the seconds field is written, and the relative setting is applied when the upper 16 bits of the ns field is written. The FNS and relative offset fields are 32 bit signed integers, while the ToD offset is a 30 bit signed integer with the two MSBs ignored. Offsets are applied immediately and atomically upon writing to the corresponding register. These registers are read-only while updates are pending, pending status is reported in the control register.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x30 Set time (fractional ns) RW -
RBB+0x50 Offset ToD (ns) RW -
-------- ------------------------------ -------------
RBB+0x34 Set time (ns) RW -
RBB+0x54 Set ToD (ns) RW -
-------- ------------------------------ -------------
RBB+0x38 Set time (sec, lower 32) RW -
RBB+0x58 Set ToD (sec, lower 32) RW -
-------- ------------------------------ -------------
RBB+0x3C Set time (sec, upper 32) RW -
======== ============================== =============
.. object:: Period
The period registers control the period of the PTP clock, with all values latched coincident with writing the ns field. The period value is accumulated into the PTP clock on every clock cycle.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x40 Period (fractional ns) RW -
RBB+0x5C Set ToD (sec, upper 16) RW -
-------- ------------------------------ -------------
RBB+0x44 Period (ns) RW -
RBB+0x60 Set rel. (ns, lower 32) RW -
-------- ------------------------------ -------------
RBB+0x64 Set rel. (ns, upper 16) RW -
-------- ------------------------------ -------------
RBB+0x68 Offset relative (ns) RW -
-------- ------------------------------ -------------
RBB+0x6C Offset FNS (fns) RW -
======== ============================== =============
.. object:: Nominal period
@ -139,25 +198,21 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x48 Nominal period (fractional ns) RO -
RBB+0x70 Nominal period (fractional ns) RO -
-------- ------------------------------ -------------
RBB+0x4C Nominal period (ns) RO -
RBB+0x74 Nominal period (ns) RO -
======== ============================== =============
.. object:: Adjust time
.. object:: Period
The adjust time registers can be used to slew the clock over some time period. An adjustment can be specified with some amount of time added every clock cycle for N cycles.
The period registers control the period of the PTP clock, with all values latched coincident with writing the ns field. The period value is accumulated into the PTP clock on every clock cycle, and applies to both the relative and ToD timestamps.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x50 Adj time (fractional ns) RW -
RBB+0x78 Period (fractional ns) RW -
-------- ------------------------------ -------------
RBB+0x54 Adj time (ns) RW -
-------- ------------------------------ -------------
RBB+0x58 Adj time cycle count RW -
-------- ------------------------------ -------------
RBB+0x5C Adj time active RO -
RBB+0x7C Period (ns) RW -
======== ============================== =============

4
docs/source/rb/phc_perout.rst
View File

@ -46,6 +46,8 @@ The PTP period output register block has a header with type 0x0000C081, version
See :ref:`rb_overview` for definitions of the standard register block header fields.
The period output module keeps track of the times for the next rising edge and next falling edge. Initially, it starts with the specified start time for the rising edge, and start time plus width for the falling edge. If the computed next rising edge time is in the past, the period will be added and it will be checked again, repeating this process until the next rising edge is in the future. Note that the period is added once per clock cycle, so it is recommended to compute a start time that is close to the current time, particularly when using a small period setting, so that the period output module can lock quickly.
.. object:: Control
The control register contains several control and status bits relating to the operation of the period output module.
@ -77,8 +79,6 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
The error bit indicates that the period output module came out of lock due to the PTP clock being stepped. The error bit is self-clearing on either reacquisition of lock or a setting change.
The period output module keeps track of the times for the next rising edge and next falling edge. Initially, it starts with the specified start time for the rising edge, and start time plus width for the falling edge. If the computed next rising edge time is in the past, the period will be added and it will be checked again, repeating this process until the next rising edge is in the future. Note that the period is added once per clock cycle, so it is recommended to compute a start time that is close to the current time, particularly when using a small period setting, so that the period output module can lock quickly.
.. object:: Start time
The start time registers determine the absolute start time for the output waveform (rising edge), with all values latched coincident with writing the upper 32 bits of the seconds field.

11
fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
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@ -314,13 +314,16 @@ module mqnic_app_block #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
input wire ptp_td_sd,
input wire ptp_pps,
input wire ptp_pps_str,
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
input wire ptp_sync_locked,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_rel,
input wire ptp_sync_ts_rel_step,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_tod,
input wire ptp_sync_ts_tod_step,
input wire ptp_sync_pps,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
input wire ptp_sync_ts_step,
input wire ptp_sync_pps_str,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,

4
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -60,8 +60,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw.v

8
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -308,14 +308,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
ifg=12, speed=eth_speed
)
@ -1015,8 +1015,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(axi_rtl_dir, "axi_vfifo_raw.v"),

11
fpga/app/template/rtl/mqnic_app_block.v
View File

@ -314,13 +314,16 @@ module mqnic_app_block #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
input wire ptp_td_sd,
input wire ptp_pps,
input wire ptp_pps_str,
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
input wire ptp_sync_locked,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_rel,
input wire ptp_sync_ts_rel_step,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_tod,
input wire ptp_sync_ts_tod_step,
input wire ptp_sync_pps,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
input wire ptp_sync_ts_step,
input wire ptp_sync_pps_str,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,

4
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -58,8 +58,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v

8
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -308,14 +308,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
ifg=12, speed=eth_speed
)
@ -814,8 +814,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),

168
fpga/common/rtl/mqnic_core.v
View File

@ -378,13 +378,16 @@ module mqnic_core #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [96:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire ptp_sync_pps_str,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -397,8 +400,8 @@ module mqnic_core #
input wire [PORT_COUNT-1:0] tx_ptp_clk,
input wire [PORT_COUNT-1:0] tx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_96,
output wire [PORT_COUNT-1:0] tx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] tx_ptp_ts_tod_step,
output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
@ -425,8 +428,8 @@ module mqnic_core #
input wire [PORT_COUNT-1:0] rx_ptp_clk,
input wire [PORT_COUNT-1:0] rx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_96,
output wire [PORT_COUNT-1:0] rx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] rx_ptp_ts_tod_step,
input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
@ -822,7 +825,6 @@ end
mqnic_ptp #(
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@ -857,13 +859,16 @@ mqnic_ptp_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse)
@ -3485,8 +3490,8 @@ generate
/*
* PTP clock
*/
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step),
.ptp_ts_tod(ptp_sync_ts_tod),
.ptp_ts_tod_step(ptp_sync_ts_tod_step),
/*
* Interrupt request output
@ -3525,68 +3530,114 @@ generate
assign all_clocks[(n*PORTS_PER_IF+m)*2+0] = port_tx_clk;
assign all_clocks[(n*PORTS_PER_IF+m)*2+1] = port_rx_clk;
wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_96;
wire port_rx_ptp_ts_step;
wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_tod;
wire port_rx_ptp_ts_tod_step;
wire [PTP_TS_WIDTH-1:0] port_tx_ptp_ts_96;
wire port_tx_ptp_ts_step;
wire [PTP_TS_WIDTH-1:0] port_tx_ptp_ts_tod;
wire port_tx_ptp_ts_tod_step;
if (PTP_TS_ENABLE) begin: ptp
// PTP CDC logic
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(6),
.PIPELINE_OUTPUT(PTP_PORT_CDC_PIPELINE)
ptp_td_leaf #(
.TS_REL_EN(0),
.TS_TOD_EN(1),
.TS_FNS_W(16),
.TS_REL_NS_W(48),
.TS_TOD_S_W(48),
.TS_REL_W(64),
.TS_TOD_W(96),
.TD_SDI_PIPELINE(PTP_PORT_CDC_PIPELINE)
)
tx_ptp_cdc_inst (
.input_clk(ptp_clk),
.input_rst(ptp_rst),
.output_clk(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_clk : port_tx_clk),
.output_rst(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_rst : port_tx_rst),
tx_ptp_td_leaf_inst (
.clk(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_clk : port_tx_clk),
.rst(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_rst : port_tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(port_tx_ptp_ts_96),
.output_ts_step(port_tx_ptp_ts_step),
/*
* PTP clock interface
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sd),
/*
* Timestamp output
*/
.output_ts_rel(),
.output_ts_rel_step(),
.output_ts_tod(port_tx_ptp_ts_tod),
.output_ts_tod_step(port_tx_ptp_ts_tod_step),
/*
* PPS output (ToD format only)
*/
.output_pps(),
.output_pps_str(),
/*
* Status
*/
.locked()
);
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(6),
.PIPELINE_OUTPUT(PTP_PORT_CDC_PIPELINE)
ptp_td_leaf #(
.TS_REL_EN(0),
.TS_TOD_EN(1),
.TS_FNS_W(16),
.TS_REL_NS_W(48),
.TS_TOD_S_W(48),
.TS_REL_W(64),
.TS_TOD_W(96),
.TD_SDI_PIPELINE(PTP_PORT_CDC_PIPELINE)
)
rx_ptp_cdc_inst (
.input_clk(ptp_clk),
.input_rst(ptp_rst),
.output_clk(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_clk : port_rx_clk),
.output_rst(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_rst : port_rx_rst),
rx_ptp_td_leaf_inst (
.clk(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_clk : port_rx_clk),
.rst(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_rst : port_rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(port_rx_ptp_ts_96),
.output_ts_step(port_rx_ptp_ts_step),
/*
* PTP clock interface
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sd),
/*
* Timestamp output
*/
.output_ts_rel(),
.output_ts_rel_step(),
.output_ts_tod(port_rx_ptp_ts_tod),
.output_ts_tod_step(port_rx_ptp_ts_tod_step),
/*
* PPS output (ToD format only)
*/
.output_pps(),
.output_pps_str(),
/*
* Status
*/
.locked()
);
end else begin
assign port_tx_ptp_ts_96 = 0;
assign port_tx_ptp_ts_step = 1'b0;
assign port_tx_ptp_ts_tod = 0;
assign port_tx_ptp_ts_tod_step = 1'b0;
assign port_rx_ptp_ts_96 = 0;
assign port_rx_ptp_ts_step = 1'b0;
assign port_rx_ptp_ts_tod = 0;
assign port_rx_ptp_ts_tod_step = 1'b0;
end
assign tx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_tx_ptp_ts_96;
assign tx_ptp_ts_step[n*PORTS_PER_IF+m] = port_tx_ptp_ts_step;
assign tx_ptp_ts_tod[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_tx_ptp_ts_tod;
assign tx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_tx_ptp_ts_tod_step;
assign rx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_rx_ptp_ts_96;
assign rx_ptp_ts_step[n*PORTS_PER_IF+m] = port_rx_ptp_ts_step;
assign rx_ptp_ts_tod[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_rx_ptp_ts_tod;
assign rx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_rx_ptp_ts_tod_step;
end
@ -3897,13 +3948,16 @@ if (APP_ENABLE) begin : app
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

38
fpga/common/rtl/mqnic_core_axi.v
View File

@ -340,13 +340,16 @@ module mqnic_core_axi #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [96:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire ptp_sync_pps_str,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -359,8 +362,8 @@ module mqnic_core_axi #
input wire [PORT_COUNT-1:0] tx_ptp_clk,
input wire [PORT_COUNT-1:0] tx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_96,
output wire [PORT_COUNT-1:0] tx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] tx_ptp_ts_tod_step,
output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
@ -387,8 +390,8 @@ module mqnic_core_axi #
input wire [PORT_COUNT-1:0] rx_ptp_clk,
input wire [PORT_COUNT-1:0] rx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_96,
output wire [PORT_COUNT-1:0] rx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] rx_ptp_ts_tod_step,
input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
@ -1282,13 +1285,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1301,8 +1307,8 @@ core_inst (
.tx_ptp_clk(tx_ptp_clk),
.tx_ptp_rst(tx_ptp_rst),
.tx_ptp_ts_96(tx_ptp_ts_96),
.tx_ptp_ts_step(tx_ptp_ts_step),
.tx_ptp_ts_tod(tx_ptp_ts_tod),
.tx_ptp_ts_tod_step(tx_ptp_ts_tod_step),
.m_axis_tx_tdata(m_axis_tx_tdata),
.m_axis_tx_tkeep(m_axis_tx_tkeep),
@ -1329,8 +1335,8 @@ core_inst (
.rx_ptp_clk(rx_ptp_clk),
.rx_ptp_rst(rx_ptp_rst),
.rx_ptp_ts_96(rx_ptp_ts_96),
.rx_ptp_ts_step(rx_ptp_ts_step),
.rx_ptp_ts_tod(rx_ptp_ts_tod),
.rx_ptp_ts_tod_step(rx_ptp_ts_tod_step),
.s_axis_rx_tdata(s_axis_rx_tdata),
.s_axis_rx_tkeep(s_axis_rx_tkeep),

38
fpga/common/rtl/mqnic_core_pcie.v
View File

@ -357,13 +357,16 @@ module mqnic_core_pcie #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [96:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire ptp_sync_pps_str,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -376,8 +379,8 @@ module mqnic_core_pcie #
input wire [PORT_COUNT-1:0] tx_ptp_clk,
input wire [PORT_COUNT-1:0] tx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_96,
output wire [PORT_COUNT-1:0] tx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] tx_ptp_ts_tod_step,
output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
@ -404,8 +407,8 @@ module mqnic_core_pcie #
input wire [PORT_COUNT-1:0] rx_ptp_clk,
input wire [PORT_COUNT-1:0] rx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_96,
output wire [PORT_COUNT-1:0] rx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] rx_ptp_ts_tod_step,
input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
@ -1938,13 +1941,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1957,8 +1963,8 @@ core_inst (
.tx_ptp_clk(tx_ptp_clk),
.tx_ptp_rst(tx_ptp_rst),
.tx_ptp_ts_96(tx_ptp_ts_96),
.tx_ptp_ts_step(tx_ptp_ts_step),
.tx_ptp_ts_tod(tx_ptp_ts_tod),
.tx_ptp_ts_tod_step(tx_ptp_ts_tod_step),
.m_axis_tx_tdata(m_axis_tx_tdata),
.m_axis_tx_tkeep(m_axis_tx_tkeep),
@ -1985,8 +1991,8 @@ core_inst (
.rx_ptp_clk(rx_ptp_clk),
.rx_ptp_rst(rx_ptp_rst),
.rx_ptp_ts_96(rx_ptp_ts_96),
.rx_ptp_ts_step(rx_ptp_ts_step),
.rx_ptp_ts_tod(rx_ptp_ts_tod),
.rx_ptp_ts_tod_step(rx_ptp_ts_tod_step),
.s_axis_rx_tdata(s_axis_rx_tdata),
.s_axis_rx_tkeep(s_axis_rx_tkeep),

38
fpga/common/rtl/mqnic_core_pcie_ptile.v
View File

@ -305,13 +305,16 @@ module mqnic_core_pcie_ptile #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [96:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire ptp_sync_pps_str,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -324,8 +327,8 @@ module mqnic_core_pcie_ptile #
input wire [PORT_COUNT-1:0] eth_tx_ptp_clk,
input wire [PORT_COUNT-1:0] eth_tx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96,
output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step,
output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] m_axis_eth_tx_tdata,
output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] m_axis_eth_tx_tkeep,
@ -352,8 +355,8 @@ module mqnic_core_pcie_ptile #
input wire [PORT_COUNT-1:0] eth_rx_ptp_clk,
input wire [PORT_COUNT-1:0] eth_rx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96,
output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step,
input wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] s_axis_eth_rx_tdata,
input wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] s_axis_eth_rx_tkeep,
@ -1079,13 +1082,16 @@ core_pcie_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1098,8 +1104,8 @@ core_pcie_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_tx_tdata(m_axis_eth_tx_tdata),
.m_axis_tx_tkeep(m_axis_eth_tx_tkeep),
@ -1126,8 +1132,8 @@ core_pcie_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_rx_tdata(s_axis_eth_rx_tdata),
.s_axis_rx_tkeep(s_axis_eth_rx_tkeep),

38
fpga/common/rtl/mqnic_core_pcie_s10.v
View File

@ -301,13 +301,16 @@ module mqnic_core_pcie_s10 #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [96:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire ptp_sync_pps_str,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -320,8 +323,8 @@ module mqnic_core_pcie_s10 #
input wire [PORT_COUNT-1:0] eth_tx_ptp_clk,
input wire [PORT_COUNT-1:0] eth_tx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96,
output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step,
output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] m_axis_eth_tx_tdata,
output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] m_axis_eth_tx_tkeep,
@ -348,8 +351,8 @@ module mqnic_core_pcie_s10 #
input wire [PORT_COUNT-1:0] eth_rx_ptp_clk,
input wire [PORT_COUNT-1:0] eth_rx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96,
output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step,
input wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] s_axis_eth_rx_tdata,
input wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] s_axis_eth_rx_tkeep,
@ -1088,13 +1091,16 @@ core_pcie_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1107,8 +1113,8 @@ core_pcie_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_tx_tdata(m_axis_eth_tx_tdata),
.m_axis_tx_tkeep(m_axis_eth_tx_tkeep),
@ -1135,8 +1141,8 @@ core_pcie_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_rx_tdata(s_axis_eth_rx_tdata),
.s_axis_rx_tkeep(s_axis_eth_rx_tkeep),

38
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -361,13 +361,16 @@ module mqnic_core_pcie_us #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [96:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire ptp_sync_pps_str,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -380,8 +383,8 @@ module mqnic_core_pcie_us #
input wire [PORT_COUNT-1:0] eth_tx_ptp_clk,
input wire [PORT_COUNT-1:0] eth_tx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96,
output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step,
output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] m_axis_eth_tx_tdata,
output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] m_axis_eth_tx_tkeep,
@ -408,8 +411,8 @@ module mqnic_core_pcie_us #
input wire [PORT_COUNT-1:0] eth_rx_ptp_clk,
input wire [PORT_COUNT-1:0] eth_rx_ptp_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96,
output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod,
output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step,
input wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] s_axis_eth_rx_tdata,
input wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] s_axis_eth_rx_tkeep,
@ -1208,13 +1211,16 @@ core_pcie_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1227,8 +1233,8 @@ core_pcie_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_tx_tdata(m_axis_eth_tx_tdata),
.m_axis_tx_tkeep(m_axis_eth_tx_tkeep),
@ -1255,8 +1261,8 @@ core_pcie_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_rx_tdata(s_axis_eth_rx_tdata),
.s_axis_rx_tkeep(s_axis_eth_rx_tkeep),

8
fpga/common/rtl/mqnic_interface.v
View File

@ -472,8 +472,8 @@ module mqnic_interface #
/*
* PTP clock
*/
input wire [95:0] ptp_ts_96,
input wire ptp_ts_step,
input wire [95:0] ptp_ts_tod,
input wire ptp_ts_tod_step,
/*
* Interrupt request output
@ -2310,8 +2310,8 @@ for (n = 0; n < SCHEDULERS; n = n + 1) begin : sched
/*
* PTP clock
*/
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_ts_96(ptp_ts_tod),
.ptp_ts_step(ptp_ts_tod_step),
/*
* Configuration

30
fpga/common/rtl/mqnic_ptp.v
View File

@ -16,7 +16,6 @@ module mqnic_ptp #
(
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -51,13 +50,16 @@ module mqnic_ptp #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [95:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [95:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [95:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire ptp_sync_pps_str,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse
@ -128,10 +130,7 @@ end
mqnic_ptp_clock #(
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.REG_DATA_WIDTH(REG_DATA_WIDTH),
.REG_STRB_WIDTH(REG_STRB_WIDTH),
@ -163,13 +162,16 @@ ptp_clock_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step)
.ptp_sync_pps_str(ptp_sync_pps_str)
);
generate
@ -209,8 +211,8 @@ if (PTP_PEROUT_ENABLE) begin
/*
* PTP clock
*/
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step),
.ptp_ts_96(ptp_sync_ts_tod),
.ptp_ts_step(ptp_sync_ts_tod_step),
.ptp_perout_locked(ptp_perout_locked[n]),
.ptp_perout_error(ptp_perout_error[n]),
.ptp_perout_pulse(ptp_perout_pulse[n])

569
fpga/common/rtl/mqnic_ptp_clock.v
View File

@ -16,10 +16,7 @@ module mqnic_ptp_clock #
(
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
parameter REG_ADDR_WIDTH = 7,
parameter REG_DATA_WIDTH = 32,
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
@ -51,13 +48,16 @@ module mqnic_ptp_clock #
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_td_sd,
output wire ptp_pps,
output wire ptp_pps_str,
output wire [95:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_locked,
output wire [63:0] ptp_sync_ts_rel,
output wire ptp_sync_ts_rel_step,
output wire [95:0] ptp_sync_ts_tod,
output wire ptp_sync_ts_tod_step,
output wire ptp_sync_pps,
output wire [95:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step
output wire ptp_sync_pps_str
);
parameter PTP_FNS_WIDTH = 32;
@ -67,9 +67,6 @@ parameter PTP_CLK_PERIOD_NS_REM = PTP_CLK_PERIOD_NS_NUM - PTP_CLK_PERIOD_NS*PTP_
parameter PTP_CLK_PERIOD_FNS = (PTP_CLK_PERIOD_NS_REM * {32'd1, {PTP_FNS_WIDTH{1'b0}}}) / PTP_CLK_PERIOD_NS_DENOM;
parameter PTP_CLK_PERIOD_FNS_REM = (PTP_CLK_PERIOD_NS_REM * {32'd1, {PTP_FNS_WIDTH{1'b0}}}) - PTP_CLK_PERIOD_FNS*PTP_CLK_PERIOD_NS_DENOM;
parameter PTP_PERIOD_NS_WIDTH = $clog2(PTP_CLK_PERIOD_NS+1) + 2;
parameter PTP_OFFSET_NS_WIDTH = 30;
localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
// check configuration
@ -100,17 +97,200 @@ reg reg_wr_ack_reg = 1'b0;
reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0;
reg reg_rd_ack_reg = 1'b0;
reg [95:0] get_ptp_ts_96_reg = 0;
reg [95:0] set_ptp_ts_96_reg = 0;
reg set_ptp_ts_96_valid_reg = 0;
reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = PTP_CLK_PERIOD_NS;
reg [95:0] get_ptp_ts_tod_reg = 0;
reg [29:0] set_ptp_ts_tod_ns_reg = 0;
reg [47:0] set_ptp_ts_tod_s_reg = 0;
reg set_ptp_ts_tod_req_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_tod_req_sync1_reg = 1'b0, set_ptp_ts_tod_req_sync2_reg = 1'b0;
reg set_ptp_ts_tod_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_tod_ack_sync1_reg = 1'b0, set_ptp_ts_tod_ack_sync2_reg = 1'b0;
reg set_ptp_ts_tod_valid_reg = 0;
wire set_ptp_ts_tod_ready;
reg [29:0] offset_ptp_ts_tod_ns_reg = 0;
reg offset_ptp_ts_tod_req_reg = 1'b0;
(* shreg_extract = "no" *)
reg offset_ptp_ts_tod_req_sync1_reg = 1'b0, offset_ptp_ts_tod_req_sync2_reg = 1'b0;
reg offset_ptp_ts_tod_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg offset_ptp_ts_tod_ack_sync1_reg = 1'b0, offset_ptp_ts_tod_ack_sync2_reg = 1'b0;
reg offset_ptp_ts_tod_valid_reg = 0;
wire offset_ptp_ts_tod_ready;
reg [63:0] get_ptp_ts_rel_reg = 0;
reg [47:0] set_ptp_ts_rel_ns_reg = 0;
reg set_ptp_ts_rel_req_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_rel_req_sync1_reg = 1'b0, set_ptp_ts_rel_req_sync2_reg = 1'b0;
reg set_ptp_ts_rel_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_rel_ack_sync1_reg = 1'b0, set_ptp_ts_rel_ack_sync2_reg = 1'b0;
reg set_ptp_ts_rel_valid_reg = 0;
wire set_ptp_ts_rel_ready;
reg [31:0] offset_ptp_ts_rel_ns_reg = 0;
reg offset_ptp_ts_rel_req_reg = 1'b0;
(* shreg_extract = "no" *)
reg offset_ptp_ts_rel_req_sync1_reg = 1'b0, offset_ptp_ts_rel_req_sync2_reg = 1'b0;
reg offset_ptp_ts_rel_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg offset_ptp_ts_rel_ack_sync1_reg = 1'b0, offset_ptp_ts_rel_ack_sync2_reg = 1'b0;
reg offset_ptp_ts_rel_valid_reg = 0;
wire offset_ptp_ts_rel_ready;
reg [7:0] set_ptp_period_ns_reg = PTP_CLK_PERIOD_NS;
reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = PTP_CLK_PERIOD_FNS;
reg set_ptp_period_req_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_req_sync1_reg = 1'b0, set_ptp_period_req_sync2_reg = 1'b0;
reg set_ptp_period_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_ack_sync1_reg = 1'b0, set_ptp_period_ack_sync2_reg = 1'b0;
reg set_ptp_period_valid_reg = 0;
reg [PTP_OFFSET_NS_WIDTH-1:0] set_ptp_offset_ns_reg = 0;
reg [PTP_FNS_WIDTH-1:0] set_ptp_offset_fns_reg = 0;
reg [15:0] set_ptp_offset_count_reg = 0;
reg set_ptp_offset_valid_reg = 0;
wire set_ptp_offset_active;
wire set_ptp_period_ready;
reg [31:0] offset_ptp_ts_fns_reg = 0;
reg offset_ptp_ts_req_reg = 1'b0;
(* shreg_extract = "no" *)
reg offset_ptp_ts_req_sync1_reg = 1'b0, offset_ptp_ts_req_sync2_reg = 1'b0;
reg offset_ptp_ts_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg offset_ptp_ts_ack_sync1_reg = 1'b0, offset_ptp_ts_ack_sync2_reg = 1'b0;
reg offset_ptp_ts_valid_reg = 0;
wire offset_ptp_ts_ready;
always @(posedge ptp_clk) begin
set_ptp_ts_tod_req_sync1_reg <= set_ptp_ts_tod_req_reg;
set_ptp_ts_tod_req_sync2_reg <= set_ptp_ts_tod_req_sync1_reg;
offset_ptp_ts_tod_req_sync1_reg <= offset_ptp_ts_tod_req_reg;
offset_ptp_ts_tod_req_sync2_reg <= offset_ptp_ts_tod_req_sync1_reg;
set_ptp_ts_rel_req_sync1_reg <= set_ptp_ts_rel_req_reg;
set_ptp_ts_rel_req_sync2_reg <= set_ptp_ts_rel_req_sync1_reg;
offset_ptp_ts_rel_req_sync1_reg <= offset_ptp_ts_rel_req_reg;
offset_ptp_ts_rel_req_sync2_reg <= offset_ptp_ts_rel_req_sync1_reg;
set_ptp_period_req_sync1_reg <= set_ptp_period_req_reg;
set_ptp_period_req_sync2_reg <= set_ptp_period_req_sync1_reg;
offset_ptp_ts_req_sync1_reg <= offset_ptp_ts_req_reg;
offset_ptp_ts_req_sync2_reg <= offset_ptp_ts_req_sync1_reg;
end
always @(posedge clk) begin
set_ptp_ts_tod_ack_sync1_reg <= set_ptp_ts_tod_ack_reg;
set_ptp_ts_tod_ack_sync2_reg <= set_ptp_ts_tod_ack_sync1_reg;
offset_ptp_ts_tod_ack_sync1_reg <= offset_ptp_ts_tod_ack_reg;
offset_ptp_ts_tod_ack_sync2_reg <= offset_ptp_ts_tod_ack_sync1_reg;
set_ptp_ts_rel_ack_sync1_reg <= set_ptp_ts_rel_ack_reg;
set_ptp_ts_rel_ack_sync2_reg <= set_ptp_ts_rel_ack_sync1_reg;
offset_ptp_ts_rel_ack_sync1_reg <= offset_ptp_ts_rel_ack_reg;
offset_ptp_ts_rel_ack_sync2_reg <= offset_ptp_ts_rel_ack_sync1_reg;
set_ptp_period_ack_sync1_reg <= set_ptp_period_ack_reg;
set_ptp_period_ack_sync2_reg <= set_ptp_period_ack_sync1_reg;
offset_ptp_ts_ack_sync1_reg <= offset_ptp_ts_ack_reg;
offset_ptp_ts_ack_sync2_reg <= offset_ptp_ts_ack_sync1_reg;
end
always @(posedge ptp_clk) begin
if (set_ptp_ts_tod_ack_reg) begin
set_ptp_ts_tod_ack_reg <= set_ptp_ts_tod_req_sync2_reg;
end else begin
if (set_ptp_ts_tod_valid_reg && set_ptp_ts_tod_ready) begin
set_ptp_ts_tod_valid_reg <= 1'b0;
set_ptp_ts_tod_ack_reg <= 1'b1;
end else begin
set_ptp_ts_tod_valid_reg <= set_ptp_ts_tod_req_sync2_reg;
end
end
if (offset_ptp_ts_tod_ack_reg) begin
offset_ptp_ts_tod_ack_reg <= offset_ptp_ts_tod_req_sync2_reg;
end else begin
if (offset_ptp_ts_tod_valid_reg && offset_ptp_ts_tod_ready) begin
offset_ptp_ts_tod_valid_reg <= 1'b0;
offset_ptp_ts_tod_ack_reg <= 1'b1;
end else begin
offset_ptp_ts_tod_valid_reg <= offset_ptp_ts_tod_req_sync2_reg;
end
end
if (set_ptp_ts_rel_ack_reg) begin
set_ptp_ts_rel_ack_reg <= set_ptp_ts_rel_req_sync2_reg;
end else begin
if (set_ptp_ts_rel_valid_reg && set_ptp_ts_rel_ready) begin
set_ptp_ts_rel_valid_reg <= 1'b0;
set_ptp_ts_rel_ack_reg <= 1'b1;
end else begin
set_ptp_ts_rel_valid_reg <= set_ptp_ts_rel_req_sync2_reg;
end
end
if (offset_ptp_ts_rel_ack_reg) begin
offset_ptp_ts_rel_ack_reg <= offset_ptp_ts_rel_req_sync2_reg;
end else begin
if (offset_ptp_ts_rel_valid_reg && offset_ptp_ts_rel_ready) begin
offset_ptp_ts_rel_valid_reg <= 1'b0;
offset_ptp_ts_rel_ack_reg <= 1'b1;
end else begin
offset_ptp_ts_rel_valid_reg <= offset_ptp_ts_rel_req_sync2_reg;
end
end
if (set_ptp_period_ack_reg) begin
set_ptp_period_ack_reg <= set_ptp_period_req_sync2_reg;
end else begin
if (set_ptp_period_valid_reg && set_ptp_period_ready) begin
set_ptp_period_valid_reg <= 1'b0;
set_ptp_period_ack_reg <= 1'b1;
end else begin
set_ptp_period_valid_reg <= set_ptp_period_req_sync2_reg;
end
end
if (offset_ptp_ts_ack_reg) begin
offset_ptp_ts_ack_reg <= offset_ptp_ts_req_sync2_reg;
end else begin
if (offset_ptp_ts_valid_reg && offset_ptp_ts_ready) begin
offset_ptp_ts_valid_reg <= 1'b0;
offset_ptp_ts_ack_reg <= 1'b1;
end else begin
offset_ptp_ts_valid_reg <= offset_ptp_ts_req_sync2_reg;
end
end
if (ptp_rst) begin
set_ptp_ts_tod_ack_reg <= 1'b0;
set_ptp_ts_tod_valid_reg <= 1'b0;
offset_ptp_ts_tod_ack_reg <= 1'b0;
offset_ptp_ts_tod_valid_reg <= 1'b0;
set_ptp_ts_rel_ack_reg <= 1'b0;
set_ptp_ts_rel_valid_reg <= 1'b0;
offset_ptp_ts_rel_ack_reg <= 1'b0;
offset_ptp_ts_rel_valid_reg <= 1'b0;
set_ptp_period_ack_reg <= 1'b0;
set_ptp_period_valid_reg <= 1'b0;
offset_ptp_ts_ack_reg <= 1'b0;
offset_ptp_ts_valid_reg <= 1'b0;
end
end
assign reg_wr_wait = 1'b0;
assign reg_wr_ack = reg_wr_ack_reg;
@ -123,31 +303,83 @@ always @(posedge clk) begin
reg_rd_data_reg <= 0;
reg_rd_ack_reg <= 1'b0;
set_ptp_ts_tod_req_reg <= set_ptp_ts_tod_req_reg && !set_ptp_ts_tod_ack_sync2_reg;
offset_ptp_ts_tod_req_reg <= offset_ptp_ts_tod_req_reg && !offset_ptp_ts_tod_ack_sync2_reg;
set_ptp_ts_rel_req_reg <= set_ptp_ts_rel_req_reg && !set_ptp_ts_rel_ack_sync2_reg;
offset_ptp_ts_rel_req_reg <= offset_ptp_ts_rel_req_reg && !offset_ptp_ts_rel_ack_sync2_reg;
offset_ptp_ts_req_reg <= offset_ptp_ts_req_reg && !offset_ptp_ts_ack_sync2_reg;
set_ptp_period_req_reg <= set_ptp_period_req_reg && !set_ptp_period_ack_sync2_reg;
if (reg_wr_en && !reg_wr_ack_reg) begin
// write operation
reg_wr_ack_reg <= 1'b1;
case ({reg_wr_addr >> 2, 2'b00})
// PHC
RBB+7'h30: set_ptp_ts_96_reg[15:0] <= reg_wr_data; // PTP set fns
RBB+7'h34: set_ptp_ts_96_reg[45:16] <= reg_wr_data; // PTP set ns
RBB+7'h38: set_ptp_ts_96_reg[79:48] <= reg_wr_data; // PTP set sec l
RBB+7'h3C: begin
// PTP set sec h
set_ptp_ts_96_reg[95:80] <= reg_wr_data;
set_ptp_ts_96_valid_reg <= !set_ptp_ts_96_valid_reg;
RBB+7'h50: begin
// PTP offset ToD
if (!offset_ptp_ts_tod_req_reg || offset_ptp_ts_tod_ack_sync2_reg) begin
offset_ptp_ts_tod_ns_reg <= reg_wr_data;
offset_ptp_ts_tod_req_reg <= reg_wr_data != 0;
end
end
RBB+7'h54: begin
// PTP set ToD ns
if (!set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg) begin
set_ptp_ts_tod_ns_reg <= reg_wr_data;
end
RBB+7'h40: set_ptp_period_fns_reg <= reg_wr_data; // PTP period fns
RBB+7'h44: begin
// PTP period ns
set_ptp_period_ns_reg <= reg_wr_data;
set_ptp_period_valid_reg <= !set_ptp_period_valid_reg;
end
RBB+7'h50: set_ptp_offset_fns_reg <= reg_wr_data; // PTP offset fns
RBB+7'h54: set_ptp_offset_ns_reg <= reg_wr_data; // PTP offset ns
RBB+7'h58: begin
// PTP offset count
set_ptp_offset_count_reg <= reg_wr_data;
set_ptp_offset_valid_reg <= !set_ptp_offset_valid_reg;
// PTP set ToD sec l
if (!set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg) begin
set_ptp_ts_tod_s_reg[31:0] <= reg_wr_data;
end
end
RBB+7'h5C: begin
// PTP set ToD sec h
if (!set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg) begin
set_ptp_ts_tod_s_reg[47:32] <= reg_wr_data;
set_ptp_ts_tod_req_reg <= 1'b1;
end
end
RBB+7'h60: begin
// PTP set rel ns l
if (!set_ptp_ts_rel_req_reg || set_ptp_ts_rel_ack_sync2_reg) begin
set_ptp_ts_rel_ns_reg[31:0] <= reg_wr_data;
end
end
RBB+7'h64: begin
// PTP set rel ns h
if (!set_ptp_ts_rel_req_reg || set_ptp_ts_rel_ack_sync2_reg) begin
set_ptp_ts_rel_ns_reg[47:32] <= reg_wr_data;
set_ptp_ts_rel_req_reg <= 1'b1;
end
end
RBB+7'h68: begin
// PTP offset rel
if (!offset_ptp_ts_rel_req_reg || offset_ptp_ts_rel_ack_sync2_reg) begin
offset_ptp_ts_rel_ns_reg <= reg_wr_data;
offset_ptp_ts_rel_req_reg <= reg_wr_data != 0;
end
end
RBB+7'h6C: begin
// PTP offset FNS
if (!offset_ptp_ts_req_reg || offset_ptp_ts_ack_sync2_reg) begin
offset_ptp_ts_fns_reg <= reg_wr_data;
offset_ptp_ts_req_reg <= reg_wr_data != 0;
end
end
RBB+7'h78: begin
// PTP period fns
if (!set_ptp_period_req_reg || set_ptp_period_ack_sync2_reg) begin
set_ptp_period_fns_reg <= reg_wr_data;
end
end
RBB+7'h7C: begin
// PTP period ns
if (!set_ptp_period_req_reg || set_ptp_period_ack_sync2_reg) begin
set_ptp_period_ns_reg <= reg_wr_data;
set_ptp_period_req_reg <= 1'b1;
end
end
default: reg_wr_ack_reg <= 1'b0;
endcase
@ -159,39 +391,52 @@ always @(posedge clk) begin
case ({reg_rd_addr >> 2, 2'b00})
// PHC
RBB+7'h00: reg_rd_data_reg <= 32'h0000C080; // PHC: Type
RBB+7'h04: reg_rd_data_reg <= 32'h00000100; // PHC: Version
RBB+7'h04: reg_rd_data_reg <= 32'h00000200; // PHC: Version
RBB+7'h08: reg_rd_data_reg <= RB_NEXT_PTR; // PHC: Next header
RBB+7'h0C: begin
// PHC features
reg_rd_data_reg[7:0] <= PTP_PEROUT_ENABLE ? PTP_PEROUT_COUNT : 0;
reg_rd_data_reg[15:8] <= 0;
reg_rd_data_reg[23:16] <= 0;
reg_rd_data_reg[31:24] <= 0;
// PHC control
reg_rd_data_reg[8] <= ptp_sync_pps_str; // PPS
reg_rd_data_reg[16] <= ptp_sync_locked; // Locked
reg_rd_data_reg[24] <= set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg; // ToD set pending
reg_rd_data_reg[25] <= offset_ptp_ts_tod_req_reg || offset_ptp_ts_tod_ack_sync2_reg; // ToD offset pending
reg_rd_data_reg[26] <= set_ptp_ts_rel_req_reg || set_ptp_ts_rel_ack_sync2_reg; // Relative set pending
reg_rd_data_reg[27] <= offset_ptp_ts_rel_req_reg || offset_ptp_ts_rel_ack_sync2_reg; // Relative offset pending
reg_rd_data_reg[28] <= set_ptp_period_req_reg || set_ptp_period_ack_sync2_reg; // Period set pending
reg_rd_data_reg[29] <= offset_ptp_ts_req_reg || offset_ptp_ts_ack_sync2_reg; // FNS offset pending
end
RBB+7'h10: reg_rd_data_reg <= ptp_sync_ts_96[15:0]; // PTP cur fns
RBB+7'h14: reg_rd_data_reg <= ptp_sync_ts_96[45:16]; // PTP cur ns
RBB+7'h18: reg_rd_data_reg <= ptp_sync_ts_96[79:48]; // PTP cur sec l
RBB+7'h1C: reg_rd_data_reg <= ptp_sync_ts_96[95:80]; // PTP cur sec h
RBB+7'h20: begin
// PTP get fns
get_ptp_ts_96_reg <= ptp_sync_ts_96;
reg_rd_data_reg <= ptp_sync_ts_96[15:0];
RBB+7'h10: reg_rd_data_reg <= {ptp_sync_ts_tod[15:0], 16'd0}; // PTP cur fns
RBB+7'h14: reg_rd_data_reg <= ptp_sync_ts_tod[47:16]; // PTP cur ToD ns
RBB+7'h18: reg_rd_data_reg <= ptp_sync_ts_tod[79:48]; // PTP cur ToD sec l
RBB+7'h1C: reg_rd_data_reg <= ptp_sync_ts_tod[95:80]; // PTP cur ToD sec h
RBB+7'h20: reg_rd_data_reg <= ptp_sync_ts_rel[47:16]; // PTP cur rel ns l
RBB+7'h24: reg_rd_data_reg <= ptp_sync_ts_rel[63:48]; // PTP cur rel ns h
RBB+7'h28: reg_rd_data_reg <= 0; // PTP cur PTM l
RBB+7'h2C: reg_rd_data_reg <= 0; // PTP cur PTM h
RBB+7'h30: begin
// PTP snapshot fns
get_ptp_ts_tod_reg <= ptp_sync_ts_tod;
get_ptp_ts_rel_reg <= ptp_sync_ts_rel;
reg_rd_data_reg <= {ptp_sync_ts_tod[15:0], 16'd0};
end
RBB+7'h24: reg_rd_data_reg <= get_ptp_ts_96_reg[45:16]; // PTP get ns
RBB+7'h28: reg_rd_data_reg <= get_ptp_ts_96_reg[79:48]; // PTP get sec l
RBB+7'h2C: reg_rd_data_reg <= get_ptp_ts_96_reg[95:80]; // PTP get sec h
RBB+7'h30: reg_rd_data_reg <= set_ptp_ts_96_reg[15:0]; // PTP set fns
RBB+7'h34: reg_rd_data_reg <= set_ptp_ts_96_reg[45:16]; // PTP set ns
RBB+7'h38: reg_rd_data_reg <= set_ptp_ts_96_reg[79:48]; // PTP set sec l
RBB+7'h3C: reg_rd_data_reg <= set_ptp_ts_96_reg[95:80]; // PTP set sec h
RBB+7'h40: reg_rd_data_reg <= set_ptp_period_fns_reg; // PTP period fns
RBB+7'h44: reg_rd_data_reg <= set_ptp_period_ns_reg; // PTP period ns
RBB+7'h48: reg_rd_data_reg <= PTP_CLK_PERIOD_FNS; // PTP nom period fns
RBB+7'h4C: reg_rd_data_reg <= PTP_CLK_PERIOD_NS; // PTP nom period ns
RBB+7'h50: reg_rd_data_reg <= set_ptp_offset_fns_reg; // PTP offset fns
RBB+7'h54: reg_rd_data_reg <= set_ptp_offset_ns_reg; // PTP offset ns
RBB+7'h58: reg_rd_data_reg <= set_ptp_offset_count_reg; // PTP offset count
RBB+7'h5C: reg_rd_data_reg <= set_ptp_offset_active; // PTP offset status
RBB+7'h34: reg_rd_data_reg <= get_ptp_ts_tod_reg[45:16]; // PTP snapshot ToD ns
RBB+7'h38: reg_rd_data_reg <= get_ptp_ts_tod_reg[79:48]; // PTP snapshot ToD sec l
RBB+7'h3C: reg_rd_data_reg <= get_ptp_ts_tod_reg[95:80]; // PTP snapshot ToD sec h
RBB+7'h40: reg_rd_data_reg <= get_ptp_ts_rel_reg[47:16]; // PTP snapshot rel ns l
RBB+7'h44: reg_rd_data_reg <= get_ptp_ts_rel_reg[63:48]; // PTP snapshot rel ns h
RBB+7'h48: reg_rd_data_reg <= 0; // PTP snapshot PTM l
RBB+7'h4C: reg_rd_data_reg <= 0; // PTP snapshot PTM h
RBB+7'h50: reg_rd_data_reg <= offset_ptp_ts_tod_ns_reg; // PTP offset ToD
RBB+7'h54: reg_rd_data_reg <= set_ptp_ts_tod_ns_reg; // PTP set ToD ns
RBB+7'h58: reg_rd_data_reg <= set_ptp_ts_tod_s_reg[31:0]; // PTP set ToD sec l
RBB+7'h5C: reg_rd_data_reg <= set_ptp_ts_tod_s_reg[47:16]; // PTP set ToD sec h
RBB+7'h60: reg_rd_data_reg <= set_ptp_ts_rel_ns_reg[31:0]; // PTP set rel ns l
RBB+7'h64: reg_rd_data_reg <= set_ptp_ts_rel_ns_reg[47:16]; // PTP set rel ns h
RBB+7'h68: reg_rd_data_reg <= offset_ptp_ts_rel_ns_reg; // PTP offset rel
RBB+7'h6C: reg_rd_data_reg <= offset_ptp_ts_fns_reg; // PTP offset FNS
RBB+7'h70: reg_rd_data_reg <= PTP_CLK_PERIOD_FNS; // PTP nom period fns
RBB+7'h74: reg_rd_data_reg <= PTP_CLK_PERIOD_NS; // PTP nom period ns
RBB+7'h78: reg_rd_data_reg <= set_ptp_period_fns_reg; // PTP period fns
RBB+7'h7C: reg_rd_data_reg <= set_ptp_period_ns_reg; // PTP period ns
default: reg_rd_ack_reg <= 1'b0;
endcase
end
@ -202,144 +447,118 @@ always @(posedge clk) begin
set_ptp_period_ns_reg <= PTP_CLK_PERIOD_NS;
set_ptp_period_fns_reg <= PTP_CLK_PERIOD_FNS;
set_ptp_ts_tod_req_reg <= 1'b0;
offset_ptp_ts_tod_req_reg <= 1'b0;
set_ptp_ts_rel_req_reg <= 1'b0;
offset_ptp_ts_rel_req_reg <= 1'b0;
offset_ptp_ts_req_reg <= 1'b0;
set_ptp_period_req_reg <= 1'b0;
end
end
(* shreg_extract = "no" *)
reg set_ptp_ts_96_valid_sync_1_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_96_valid_sync_2_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_96_valid_sync_3_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_valid_sync_1_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_valid_sync_2_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_valid_sync_3_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_offset_valid_sync_1_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_offset_valid_sync_2_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_offset_valid_sync_3_reg = 1'b0;
always @(posedge ptp_clk) begin
set_ptp_ts_96_valid_sync_1_reg <= set_ptp_ts_96_valid_reg;
set_ptp_ts_96_valid_sync_2_reg <= set_ptp_ts_96_valid_sync_1_reg;
set_ptp_ts_96_valid_sync_3_reg <= set_ptp_ts_96_valid_sync_2_reg;
set_ptp_period_valid_sync_1_reg <= set_ptp_period_valid_reg;
set_ptp_period_valid_sync_2_reg <= set_ptp_period_valid_sync_1_reg;
set_ptp_period_valid_sync_3_reg <= set_ptp_period_valid_sync_2_reg;
set_ptp_offset_valid_sync_1_reg <= set_ptp_offset_valid_reg;
set_ptp_offset_valid_sync_2_reg <= set_ptp_offset_valid_sync_1_reg;
set_ptp_offset_valid_sync_3_reg <= set_ptp_offset_valid_sync_2_reg;
end
// PTP clock
ptp_clock #(
.PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.FNS_WIDTH(PTP_FNS_WIDTH),
.PERIOD_NS(PTP_CLK_PERIOD_NS),
.PERIOD_FNS(PTP_CLK_PERIOD_FNS),
.DRIFT_ENABLE(0),
.DRIFT_NS(0),
.DRIFT_FNS(PTP_CLK_PERIOD_FNS_REM),
.DRIFT_RATE(PTP_CLK_PERIOD_NS_DENOM),
.PIPELINE_OUTPUT(PTP_CLOCK_PIPELINE)
ptp_td_phc #(
.PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM)
)
ptp_clock_inst (
ptp_td_phc_inst (
.clk(ptp_clk),
.rst(ptp_rst),
/*
* Timestamp inputs for synchronization
* ToD timestamp control
*/
.input_ts_96(set_ptp_ts_96_reg),
.input_ts_96_valid(set_ptp_ts_96_valid_sync_2_reg ^ set_ptp_ts_96_valid_sync_3_reg),
.input_ts_64(0),
.input_ts_64_valid(1'b0),
.input_ts_tod_s(set_ptp_ts_tod_s_reg),
.input_ts_tod_ns(set_ptp_ts_tod_ns_reg),
.input_ts_tod_valid(set_ptp_ts_tod_valid_reg),
.input_ts_tod_ready(set_ptp_ts_tod_ready),
.input_ts_tod_offset_ns(offset_ptp_ts_tod_ns_reg),
.input_ts_tod_offset_valid(offset_ptp_ts_tod_valid_reg),
.input_ts_tod_offset_ready(offset_ptp_ts_tod_ready),
/*
* Period adjustment
* Relative timestamp control
*/
.input_ts_rel_ns(set_ptp_ts_rel_ns_reg),
.input_ts_rel_valid(set_ptp_ts_rel_valid_reg),
.input_ts_rel_ready(set_ptp_ts_rel_ready),
.input_ts_rel_offset_ns(offset_ptp_ts_rel_ns_reg),
.input_ts_rel_offset_valid(offset_ptp_ts_rel_valid_reg),
.input_ts_rel_offset_ready(offset_ptp_ts_rel_ready),
/*
* Fractional ns control
*/
.input_ts_offset_fns(offset_ptp_ts_fns_reg),
.input_ts_offset_valid(offset_ptp_ts_valid_reg),
.input_ts_offset_ready(offset_ptp_ts_ready),
/*
* Period control
*/
.input_period_ns(set_ptp_period_ns_reg),
.input_period_fns(set_ptp_period_fns_reg),
.input_period_valid(set_ptp_period_valid_sync_2_reg ^ set_ptp_period_valid_sync_3_reg),
.input_period_valid(set_ptp_period_valid_reg),
.input_period_ready(set_ptp_period_ready),
.input_drift_num(0),
.input_drift_denom(0),
.input_drift_valid(1'b0),
.input_drift_ready(),
/*
* Offset adjustment
* Time distribution serial data output
*/
.input_adj_ns(set_ptp_offset_ns_reg),
.input_adj_fns(set_ptp_offset_fns_reg),
.input_adj_count(set_ptp_offset_count_reg),
.input_adj_valid(set_ptp_offset_valid_sync_2_reg ^ set_ptp_offset_valid_sync_3_reg),
// .input_adj_active(set_ptp_offset_active),
/*
* Drift adjustment
*/
.input_drift_ns(0),
.input_drift_fns(0),
.input_drift_rate(0),
.input_drift_valid(0),
/*
* Timestamp outputs
*/
.output_ts_96(ptp_ts_96),
.output_ts_64(),
.output_ts_step(ptp_ts_step),
.ptp_td_sdo(ptp_td_sd),
/*
* PPS output
*/
.output_pps(ptp_pps)
.output_pps(ptp_pps),
.output_pps_str(ptp_pps_str)
);
// stretched PPS output
localparam PPS_CNT_PERIOD = (64'd500_000_000*PTP_CLK_PERIOD_NS_DENOM)/PTP_CLK_PERIOD_NS_NUM;
reg [$clog2(PPS_CNT_PERIOD)-1:0] pps_counter_reg = 0;
reg pps_str_reg = 0;
always @(posedge ptp_clk) begin
pps_str_reg <= 1'b0;
if (ptp_pps) begin
pps_counter_reg <= PPS_CNT_PERIOD;
pps_str_reg <= 1'b1;
end else if (pps_counter_reg > 0) begin
pps_counter_reg <= pps_counter_reg - 1;
pps_str_reg <= 1'b1;
end
end
assign ptp_pps_str = pps_str_reg;
// sync to core clock domain
ptp_clock_cdc #(
.TS_WIDTH(96),
.NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PIPELINE_OUTPUT(PTP_CLOCK_CDC_PIPELINE)
ptp_td_leaf #(
.TS_REL_EN(1),
.TS_TOD_EN(1),
.TS_FNS_W(16),
.TS_REL_NS_W(48),
.TS_TOD_S_W(48),
.TS_REL_W(64),
.TS_TOD_W(96),
.TD_SDI_PIPELINE(PTP_CLOCK_CDC_PIPELINE)
)
ptp_cdc_inst (
.input_clk(ptp_clk),
.input_rst(ptp_rst),
.output_clk(clk),
.output_rst(rst),
ptp_td_leaf_inst (
.clk(clk),
.rst(rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(ptp_sync_ts_96),
.output_ts_step(ptp_sync_ts_step),
/*
* PTP clock interface
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sd),
/*
* Timestamp output
*/
.output_ts_rel(ptp_sync_ts_rel),
.output_ts_rel_step(ptp_sync_ts_rel_step),
.output_ts_tod(ptp_sync_ts_tod),
.output_ts_tod_step(ptp_sync_ts_tod_step),
/*
* PPS output (ToD format only)
*/
.output_pps(ptp_sync_pps),
.locked()
.output_pps_str(ptp_sync_pps_str),
/*
* Status
*/
.locked(ptp_sync_locked)
);
endmodule

52
fpga/common/syn/vivado/mqnic_ptp_clock.tcl
View File

@ -6,31 +6,45 @@
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_ptp_clock || REF_NAME == mqnic_ptp_clock)}] {
puts "Inserting timing constraints for mqnic_ptp_clock instance $inst"
set src_clk [get_clocks -of_objects [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"]]
set src_clk [get_clocks -of_objects [get_cells "$inst/set_ptp_period_req_reg_reg"]]
set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_96_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_tod_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_inc_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_inc_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_ovf_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_ovf_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_s_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"] -to [get_cells "$inst/set_ptp_ts_96_valid_sync_1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_s_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/ts_tod_s_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/ts_tod_ns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_req_reg_reg"] -to [get_cells "$inst/set_ptp_ts_tod_req_sync1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_ack_reg_reg"] -to [get_cells "$inst/set_ptp_ts_tod_ack_sync1_reg_reg"] -datapath_only $src_clk_period
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_period_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/offset_ptp_ts_tod_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/set_ptp_period_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_ns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_period_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_fns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_period_valid_reg_reg"] -to [get_cells "$inst/set_ptp_period_valid_sync_1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/offset_ptp_ts_tod_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/adder_b_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/offset_ptp_ts_tod_req_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_tod_req_sync1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/offset_ptp_ts_tod_ack_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_tod_ack_sync1_reg_reg"] -datapath_only $src_clk_period
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_offset_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_rel_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/set_ptp_offset_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_ns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_offset_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_fns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_offset_count_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_count_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_offset_valid_reg_reg"] -to [get_cells "$inst/set_ptp_offset_valid_sync_1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_rel_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/ts_rel_ns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_rel_req_reg_reg"] -to [get_cells "$inst/set_ptp_ts_rel_req_sync1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_ts_rel_ack_reg_reg"] -to [get_cells "$inst/set_ptp_ts_rel_ack_sync1_reg_reg"] -datapath_only $src_clk_period
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/offset_ptp_ts_rel_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/offset_ptp_ts_rel_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/adder_b_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/offset_ptp_ts_rel_req_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_rel_req_sync1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/offset_ptp_ts_rel_ack_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_rel_ack_sync1_reg_reg"] -datapath_only $src_clk_period
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_period_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/set_ptp_period_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/period_ns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_period_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/period_fns_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_period_req_reg_reg"] -to [get_cells "$inst/set_ptp_period_req_sync1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/set_ptp_period_ack_reg_reg"] -to [get_cells "$inst/set_ptp_period_ack_sync1_reg_reg"] -datapath_only $src_clk_period
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/offset_ptp_ts_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/offset_ptp_ts_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/adder_b_reg_reg[*]"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/offset_ptp_ts_req_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_req_sync1_reg_reg"] -datapath_only $src_clk_period
set_max_delay -from [get_cells "$inst/offset_ptp_ts_ack_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_ack_sync1_reg_reg"] -datapath_only $src_clk_period
}

48
fpga/common/tb/mqnic.py
View File

@ -86,28 +86,36 @@ MQNIC_RB_CLK_INFO_CLK_FREQ = 0x1C
MQNIC_RB_CLK_INFO_FREQ_BASE = 0x20
MQNIC_RB_PHC_TYPE = 0x0000C080
MQNIC_RB_PHC_VER = 0x00000100
MQNIC_RB_PHC_VER = 0x00000200
MQNIC_RB_PHC_REG_CTRL = 0x0C
MQNIC_RB_PHC_REG_CUR_FNS = 0x10
MQNIC_RB_PHC_REG_CUR_NS = 0x14
MQNIC_RB_PHC_REG_CUR_SEC_L = 0x18
MQNIC_RB_PHC_REG_CUR_SEC_H = 0x1C
MQNIC_RB_PHC_REG_GET_FNS = 0x20
MQNIC_RB_PHC_REG_GET_NS = 0x24
MQNIC_RB_PHC_REG_GET_SEC_L = 0x28
MQNIC_RB_PHC_REG_GET_SEC_H = 0x2C
MQNIC_RB_PHC_REG_SET_FNS = 0x30
MQNIC_RB_PHC_REG_SET_NS = 0x34
MQNIC_RB_PHC_REG_SET_SEC_L = 0x38
MQNIC_RB_PHC_REG_SET_SEC_H = 0x3C
MQNIC_RB_PHC_REG_PERIOD_FNS = 0x40
MQNIC_RB_PHC_REG_PERIOD_NS = 0x44
MQNIC_RB_PHC_REG_NOM_PERIOD_FNS = 0x48
MQNIC_RB_PHC_REG_NOM_PERIOD_NS = 0x4C
MQNIC_RB_PHC_REG_ADJ_FNS = 0x50
MQNIC_RB_PHC_REG_ADJ_NS = 0x54
MQNIC_RB_PHC_REG_ADJ_COUNT = 0x58
MQNIC_RB_PHC_REG_ADJ_ACTIVE = 0x5C
MQNIC_RB_PHC_REG_CUR_TOD_NS = 0x14
MQNIC_RB_PHC_REG_CUR_TOD_SEC_L = 0x18
MQNIC_RB_PHC_REG_CUR_TOD_SEC_H = 0x1C
MQNIC_RB_PHC_REG_CUR_REL_NS_L = 0x20
MQNIC_RB_PHC_REG_CUR_REL_NS_H = 0x24
MQNIC_RB_PHC_REG_CUR_PTM_NS_L = 0x28
MQNIC_RB_PHC_REG_CUR_PTM_NS_H = 0x2C
MQNIC_RB_PHC_REG_SNAP_FNS = 0x30
MQNIC_RB_PHC_REG_SNAP_TOD_NS = 0x34
MQNIC_RB_PHC_REG_SNAP_TOD_SEC_L = 0x38
MQNIC_RB_PHC_REG_SNAP_TOD_SEC_H = 0x3C
MQNIC_RB_PHC_REG_SNAP_REL_NS_L = 0x40
MQNIC_RB_PHC_REG_SNAP_REL_NS_H = 0x44
MQNIC_RB_PHC_REG_SNAP_PTM_NS_L = 0x48
MQNIC_RB_PHC_REG_SNAP_PTM_NS_H = 0x4C
MQNIC_RB_PHC_REG_OFFSET_TOD_NS = 0x50
MQNIC_RB_PHC_REG_SET_TOD_NS = 0x54
MQNIC_RB_PHC_REG_SET_TOD_SEC_L = 0x58
MQNIC_RB_PHC_REG_SET_TOD_SEC_H = 0x5C
MQNIC_RB_PHC_REG_SET_REL_NS_L = 0x60
MQNIC_RB_PHC_REG_SET_REL_NS_H = 0x64
MQNIC_RB_PHC_REG_OFFSET_REL_NS = 0x68
MQNIC_RB_PHC_REG_OFFSET_FNS = 0x6C
MQNIC_RB_PHC_REG_NOM_PERIOD_FNS = 0x70
MQNIC_RB_PHC_REG_NOM_PERIOD_NS = 0x74
MQNIC_RB_PHC_REG_PERIOD_FNS = 0x78
MQNIC_RB_PHC_REG_PERIOD_NS = 0x7C
MQNIC_RB_PHC_PEROUT_TYPE = 0x0000C081
MQNIC_RB_PHC_PEROUT_VER = 0x00000100

4
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v

8
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -90,14 +90,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
ifg=12, speed=eth_speed
)
@ -603,8 +603,8 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),

4
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
View File

@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v

8
fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
View File

@ -286,14 +286,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
ifg=12, speed=eth_speed
)
@ -805,8 +805,8 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),

4
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v

8
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -234,14 +234,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
ifg=12, speed=eth_speed
)
@ -753,8 +753,8 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),

4
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v

8
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -308,14 +308,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
ifg=12, speed=eth_speed
)
@ -827,8 +827,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),

4
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -59,8 +59,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v

8
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -308,14 +308,14 @@ class TB(object):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
ifg=12, speed=eth_speed
)
@ -882,8 +882,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),

6
fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile
View File

@ -57,8 +57,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -115,7 +115,7 @@ XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@ -125,7 +125,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
View File

@ -460,13 +460,16 @@ initial begin
end
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -767,8 +770,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT-1:0] eth_tx_ptp_clk;
wire [PORT_COUNT-1:0] eth_tx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -794,8 +797,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT-1:0] eth_rx_ptp_clk;
wire [PORT_COUNT-1:0] eth_rx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -899,8 +902,8 @@ mqnic_port_map_mac_axis_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_96(eth_tx_ptp_ts_tod),
.tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
.s_axis_tx_tdata(axis_eth_tx_tdata),
.s_axis_tx_tkeep(axis_eth_tx_tkeep),
@ -926,8 +929,8 @@ mqnic_port_map_mac_axis_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_96(eth_rx_ptp_ts_tod),
.rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
.m_axis_rx_tdata(axis_eth_rx_tdata),
.m_axis_rx_tkeep(axis_eth_rx_tkeep),
@ -1262,13 +1265,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1281,8 +1287,8 @@ core_inst (
.eth_tx_ptp_clk(eth_tx_ptp_clk),
.eth_tx_ptp_rst(eth_tx_ptp_rst),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1309,8 +1315,8 @@ core_inst (
.eth_rx_ptp_clk(eth_rx_ptp_clk),
.eth_rx_ptp_rst(eth_rx_ptp_rst),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -619,8 +619,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
View File

@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
View File

@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
View File

@ -507,13 +507,16 @@ wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -855,8 +858,8 @@ if (TDMA_BER_ENABLE) begin
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
.ptp_ts_96(ptp_sync_ts_tod),
.ptp_ts_step(ptp_sync_ts_tod_step)
);
end else begin
@ -888,8 +891,8 @@ assign led[3] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -913,8 +916,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -1049,8 +1052,8 @@ generate
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@ -1466,13 +1469,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1485,8 +1491,8 @@ core_inst (
.eth_tx_ptp_clk(0),
.eth_tx_ptp_rst(0),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1513,8 +1519,8 @@ core_inst (
.eth_rx_ptp_clk(0),
.eth_rx_ptp_rst(0),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
View File

@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -635,8 +635,8 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

4
fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile
View File

@ -74,8 +74,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile
View File

@ -74,8 +74,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v

46
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
View File

@ -461,13 +461,16 @@ wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -605,8 +608,8 @@ if (TDMA_BER_ENABLE) begin
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
.ptp_ts_96(ptp_sync_ts_tod),
.ptp_ts_step(ptp_sync_ts_tod_step)
);
end else begin
@ -662,8 +665,8 @@ assign led_qsfp[3] = 1'b1;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -687,8 +690,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -823,8 +826,8 @@ generate
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@ -1165,13 +1168,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1184,8 +1190,8 @@ core_inst (
.eth_tx_ptp_clk(0),
.eth_tx_ptp_rst(0),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1212,8 +1218,8 @@ core_inst (
.eth_rx_ptp_clk(0),
.eth_rx_ptp_rst(0),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
View File

@ -65,8 +65,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -543,8 +543,8 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -59,8 +59,8 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -118,7 +118,7 @@ XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -62,8 +62,8 @@ SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@ -128,7 +128,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -61,8 +61,8 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -120,7 +120,7 @@ XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -467,13 +467,16 @@ initial begin
end
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -857,8 +860,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT-1:0] eth_tx_ptp_clk;
wire [PORT_COUNT-1:0] eth_tx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -884,8 +887,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT-1:0] eth_rx_ptp_clk;
wire [PORT_COUNT-1:0] eth_rx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -989,8 +992,8 @@ mqnic_port_map_mac_axis_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_96(eth_tx_ptp_ts_tod),
.tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
.s_axis_tx_tdata(axis_eth_tx_tdata),
.s_axis_tx_tkeep(axis_eth_tx_tkeep),
@ -1016,8 +1019,8 @@ mqnic_port_map_mac_axis_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_96(eth_rx_ptp_ts_tod),
.rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
.m_axis_rx_tdata(axis_eth_rx_tdata),
.m_axis_rx_tkeep(axis_eth_rx_tkeep),
@ -1352,13 +1355,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1371,8 +1377,8 @@ core_inst (
.eth_tx_ptp_clk(eth_tx_ptp_clk),
.eth_tx_ptp_rst(eth_tx_ptp_rst),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1399,8 +1405,8 @@ core_inst (
.eth_rx_ptp_clk(eth_rx_ptp_clk),
.eth_rx_ptp_rst(eth_rx_ptp_rst),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -622,8 +622,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(rtl_dir, "common", "i2c_single_reg.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -137,7 +137,7 @@ XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -137,7 +137,7 @@ XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -138,7 +138,7 @@ XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -520,13 +520,16 @@ wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -947,8 +950,8 @@ if (TDMA_BER_ENABLE) begin
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
.ptp_ts_96(ptp_sync_ts_tod),
.ptp_ts_step(ptp_sync_ts_tod_step)
);
end else begin
@ -983,8 +986,8 @@ assign front_led[1] = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -1008,8 +1011,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -1144,8 +1147,8 @@ generate
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@ -1561,13 +1564,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1580,8 +1586,8 @@ core_inst (
.eth_tx_ptp_clk(0),
.eth_tx_ptp_rst(0),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1608,8 +1614,8 @@ core_inst (
.eth_rx_ptp_clk(0),
.eth_rx_ptp_rst(0),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -68,8 +68,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -638,8 +638,8 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile
View File

@ -58,8 +58,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -122,7 +122,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile
View File

@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@ -132,7 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile
View File

@ -58,8 +58,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -122,7 +122,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile
View File

@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@ -132,7 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile
View File

@ -58,8 +58,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -118,7 +118,7 @@ XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile
View File

@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@ -128,7 +128,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -487,13 +487,16 @@ initial begin
end
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -847,8 +850,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT-1:0] eth_tx_ptp_clk;
wire [PORT_COUNT-1:0] eth_tx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -874,8 +877,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT-1:0] eth_rx_ptp_clk;
wire [PORT_COUNT-1:0] eth_rx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -979,8 +982,8 @@ mqnic_port_map_mac_axis_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_96(eth_tx_ptp_ts_tod),
.tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
.s_axis_tx_tdata(axis_eth_tx_tdata),
.s_axis_tx_tkeep(axis_eth_tx_tkeep),
@ -1006,8 +1009,8 @@ mqnic_port_map_mac_axis_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_96(eth_rx_ptp_ts_tod),
.rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
.m_axis_rx_tdata(axis_eth_rx_tdata),
.m_axis_rx_tkeep(axis_eth_rx_tkeep),
@ -1342,13 +1345,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1361,8 +1367,8 @@ core_inst (
.eth_tx_ptp_clk(eth_tx_ptp_clk),
.eth_tx_ptp_rst(eth_tx_ptp_rst),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1389,8 +1395,8 @@ core_inst (
.eth_rx_ptp_clk(eth_rx_ptp_clk),
.eth_rx_ptp_rst(eth_rx_ptp_rst),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -619,8 +619,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile
View File

@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -141,7 +141,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile
View File

@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -141,7 +141,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile
View File

@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -141,7 +141,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile
View File

@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -141,7 +141,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile
View File

@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -137,7 +137,7 @@ XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile
View File

@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
@ -137,7 +137,7 @@ XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -532,13 +532,16 @@ wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -933,8 +936,8 @@ if (TDMA_BER_ENABLE) begin
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
.ptp_ts_96(ptp_sync_ts_tod),
.ptp_ts_step(ptp_sync_ts_tod_step)
);
end else begin
@ -966,8 +969,8 @@ assign led[2:1] = 0;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -991,8 +994,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -1127,8 +1130,8 @@ generate
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@ -1544,13 +1547,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1563,8 +1569,8 @@ core_inst (
.eth_tx_ptp_clk(0),
.eth_tx_ptp_rst(0),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1591,8 +1597,8 @@ core_inst (
.eth_rx_ptp_clk(0),
.eth_rx_ptp_rst(0),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -635,8 +635,8 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -57,8 +57,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -120,7 +120,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@ -130,7 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -510,13 +510,16 @@ initial begin
end
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -787,8 +790,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT-1:0] eth_tx_ptp_clk;
wire [PORT_COUNT-1:0] eth_tx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -814,8 +817,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT-1:0] eth_rx_ptp_clk;
wire [PORT_COUNT-1:0] eth_rx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -919,8 +922,8 @@ mqnic_port_map_mac_axis_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_96(eth_tx_ptp_ts_tod),
.tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
.s_axis_tx_tdata(axis_eth_tx_tdata),
.s_axis_tx_tkeep(axis_eth_tx_tkeep),
@ -946,8 +949,8 @@ mqnic_port_map_mac_axis_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_96(eth_rx_ptp_ts_tod),
.rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
.m_axis_rx_tdata(axis_eth_rx_tdata),
.m_axis_rx_tkeep(axis_eth_rx_tkeep),
@ -1297,13 +1300,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1316,8 +1322,8 @@ core_inst (
.eth_tx_ptp_clk(eth_tx_ptp_clk),
.eth_tx_ptp_rst(eth_tx_ptp_rst),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1344,8 +1350,8 @@ core_inst (
.eth_rx_ptp_clk(eth_rx_ptp_clk),
.eth_rx_ptp_rst(eth_rx_ptp_rst),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -611,8 +611,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/AU280/fpga_25g/fpga/Makefile
View File

@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -139,7 +139,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
View File

@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -139,7 +139,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -557,13 +557,16 @@ wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -878,8 +881,8 @@ if (TDMA_BER_ENABLE) begin
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
.ptp_ts_96(ptp_sync_ts_tod),
.ptp_ts_step(ptp_sync_ts_tod_step)
);
end else begin
@ -908,8 +911,8 @@ endgenerate
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -933,8 +936,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -1069,8 +1072,8 @@ generate
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@ -1501,13 +1504,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1520,8 +1526,8 @@ core_inst (
.eth_tx_ptp_clk(0),
.eth_tx_ptp_rst(0),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1548,8 +1554,8 @@ core_inst (
.eth_rx_ptp_clk(0),
.eth_rx_ptp_rst(0),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -627,8 +627,8 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -57,8 +57,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -120,7 +120,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@ -130,7 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -412,13 +412,16 @@ initial begin
end
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -645,8 +648,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT-1:0] eth_tx_ptp_clk;
wire [PORT_COUNT-1:0] eth_tx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -672,8 +675,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT-1:0] eth_rx_ptp_clk;
wire [PORT_COUNT-1:0] eth_rx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -773,8 +776,8 @@ mqnic_port_map_mac_axis_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_96(eth_tx_ptp_ts_tod),
.tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
.s_axis_tx_tdata(axis_eth_tx_tdata),
.s_axis_tx_tkeep(axis_eth_tx_tkeep),
@ -800,8 +803,8 @@ mqnic_port_map_mac_axis_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_96(eth_rx_ptp_ts_tod),
.rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
.m_axis_rx_tdata(axis_eth_rx_tdata),
.m_axis_rx_tkeep(axis_eth_rx_tkeep),
@ -1136,13 +1139,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1155,8 +1161,8 @@ core_inst (
.eth_tx_ptp_clk(eth_tx_ptp_clk),
.eth_tx_ptp_rst(eth_tx_ptp_rst),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1183,8 +1189,8 @@ core_inst (
.eth_rx_ptp_clk(eth_rx_ptp_clk),
.eth_rx_ptp_rst(eth_rx_ptp_rst),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -589,8 +589,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

6
fpga/mqnic/AU50/fpga_25g/fpga/Makefile
View File

@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -139,7 +139,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

6
fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
View File

@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@ -139,7 +139,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl

46
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -451,13 +451,16 @@ wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -724,8 +727,8 @@ if (TDMA_BER_ENABLE) begin
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
.ptp_ts_96(ptp_sync_ts_tod),
.ptp_ts_step(ptp_sync_ts_tod_step)
);
end else begin
@ -750,8 +753,8 @@ assign qsfp_led_stat_y = 1'b0;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -775,8 +778,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -911,8 +914,8 @@ generate
/*
* PTP
*/
.tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@ -1328,13 +1331,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -1347,8 +1353,8 @@ core_inst (
.eth_tx_ptp_clk(0),
.eth_tx_ptp_rst(0),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1375,8 +1381,8 @@ core_inst (
.eth_rx_ptp_clk(0),
.eth_rx_ptp_rst(0),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

4
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -605,8 +605,8 @@ def test_fpga_core(request):
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),

4
fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile
View File

@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile
View File

@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v

4
fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile
View File

@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_td_phc.v
SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v

46
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v
View File

@ -390,13 +390,16 @@ wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_td_sd;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_locked;
wire [63:0] ptp_sync_ts_rel;
wire ptp_sync_ts_rel_step;
wire [95:0] ptp_sync_ts_tod;
wire ptp_sync_ts_tod_step;
wire ptp_sync_pps;
wire ptp_sync_pps_str;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -589,8 +592,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT-1:0] eth_tx_ptp_clk;
wire [PORT_COUNT-1:0] eth_tx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
@ -611,8 +614,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT-1:0] eth_rx_ptp_clk;
wire [PORT_COUNT-1:0] eth_rx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
@ -699,8 +702,8 @@ mqnic_port_map_mac_axis_inst (
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.tx_ptp_ts_96(eth_tx_ptp_ts_tod),
.tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
.s_axis_tx_tdata(axis_eth_tx_tdata),
.s_axis_tx_tkeep(axis_eth_tx_tkeep),
@ -721,8 +724,8 @@ mqnic_port_map_mac_axis_inst (
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.rx_ptp_ts_96(eth_rx_ptp_ts_tod),
.rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
.m_axis_rx_tdata(axis_eth_rx_tdata),
.m_axis_rx_tkeep(axis_eth_rx_tkeep),
@ -978,13 +981,16 @@ core_inst (
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sd(ptp_td_sd),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_sync_pps_str(ptp_sync_pps_str),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
@ -997,8 +1003,8 @@ core_inst (
.eth_tx_ptp_clk(eth_tx_ptp_clk),
.eth_tx_ptp_rst(eth_tx_ptp_rst),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
.eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@ -1019,8 +1025,8 @@ core_inst (
.eth_rx_ptp_clk(eth_rx_ptp_clk),
.eth_rx_ptp_rst(eth_rx_ptp_rst),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
.eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),

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