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Limit scheduler pipeline to a single AXI lite operation

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This commit is contained in:
Alex Forencich 2021-11-19 16:29:16 -08:00
parent bc8a8cdc58
commit 2aa9158d5c
1 changed files with 2 additions and 2 deletions
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4
fpga/common/rtl/tx_scheduler_rr.v
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@ -521,7 +521,7 @@ always @* begin
if (init_index_reg == {QUEUE_INDEX_WIDTH{1'b1}}) begin
init_next = 1'b1;
end
end else if (s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && !op_axil_write_pipe_reg[0] && !op_axil_write_pipe_hazard) begin
end else if (s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && !op_axil_write_pipe_reg && !op_axil_write_pipe_hazard) begin
// AXIL write
op_axil_write_pipe_next[0] = 1'b1;
@ -533,7 +533,7 @@ always @* begin
queue_ram_read_ptr = s_axil_awaddr_queue;
queue_ram_addr_pipeline_next[0] = s_axil_awaddr_queue;
end else if (s_axil_arvalid && (!s_axil_rvalid || s_axil_rready) && !op_axil_read_pipe_reg[0] && !op_axil_read_pipe_hazard) begin
end else if (s_axil_arvalid && (!s_axil_rvalid || s_axil_rready) && !op_axil_read_pipe_reg && !op_axil_read_pipe_hazard) begin
// AXIL read
op_axil_read_pipe_next[0] = 1'b1;