Fix signal name

2025-01-16 08:12:53 +08:00 · 2019-05-02 20:30:37 -07:00 · 2019-05-02 20:30:37 -07:00 · 2abb413854
commit 2abb413854
parent 1d61626785
1 changed files with 1 additions and 1 deletions
--- a/example/KC705/fpga_gmii/rtl/fpga.v
+++ b/example/KC705/fpga_gmii/rtl/fpga.v
@ -80,7 +80,7 @@ wire clk_200mhz_bufg;
 wire clk_200mhz_mmcm_out;

 // Internal 125 MHz clock
-wire clk_200mhz_int;
+wire clk_int;
 wire rst_int;   

 wire mmcm_rst = reset;