FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity

More kernel module coding style updates

Browse Source
This commit is contained in:
Alex Forencich 2021-10-21 13:54:00 -07:00
parent 7ac4797336
commit 2adaf820b5
13 changed files with 134 additions and 126 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
modules/mqnic/mqnic.h
View File

@ -218,7 +218,7 @@ struct mqnic_cq_ring {
int ring_index; int ring_index;
int eq_index; int eq_index;
void (*handler)(struct mqnic_cq_ring *); void (*handler)(struct mqnic_cq_ring *ring);
u32 hw_ptr_mask; u32 hw_ptr_mask;
u8 __iomem *hw_addr; u8 __iomem *hw_addr;
@ -244,7 +244,7 @@ struct mqnic_eq_ring {
int irq; int irq;
void (*handler)(struct mqnic_eq_ring *); void (*handler)(struct mqnic_eq_ring *ring);
u32 hw_ptr_mask; u32 hw_ptr_mask;
u8 __iomem *hw_addr; u8 __iomem *hw_addr;

17
modules/mqnic/mqnic_board.c
View File

@ -453,9 +453,12 @@ static void mqnic_alveo_bmc_reg_write(struct mqnic_dev *mqnic, u32 reg, u32 val)
static int mqnic_alveo_bmc_read_mac(struct mqnic_dev *mqnic, int index, char *mac) static int mqnic_alveo_bmc_read_mac(struct mqnic_dev *mqnic, int index, char *mac)
{ {
uint32_t reg = 0x0281a0 + index * 8; uint32_t reg = 0x0281a0 + index * 8;
uint32_t val = mqnic_alveo_bmc_reg_read(mqnic, reg); uint32_t val;
val = mqnic_alveo_bmc_reg_read(mqnic, reg);
mac[0] = (val >> 8) & 0xff; mac[0] = (val >> 8) & 0xff;
mac[1] = val & 0xff; mac[1] = val & 0xff;
val = mqnic_alveo_bmc_reg_read(mqnic, reg + 4); val = mqnic_alveo_bmc_reg_read(mqnic, reg + 4);
mac[2] = (val >> 24) & 0xff; mac[2] = (val >> 24) & 0xff;
mac[3] = (val >> 16) & 0xff; mac[3] = (val >> 16) & 0xff;
@ -581,18 +584,18 @@ static int mqnic_gecko_bmc_read(struct mqnic_dev *mqnic)
if (val & BIT(18)) { if (val & BIT(18)) {
// timed out // timed out
dev_warn(mqnic->dev, "Timed out waiting for Gecko BMC response"); dev_warn(mqnic->dev, "Timed out waiting for Gecko BMC response");
msleep(10); msleep(20);
return -2; return -2;
} }
return val & 0xffff; return val & 0xffff;
} else { }
timeout--; timeout--;
if (timeout == 0) { if (timeout == 0) {
dev_warn(mqnic->dev, "Timed out waiting for Gecko BMC interface"); dev_warn(mqnic->dev, "Timed out waiting for Gecko BMC interface");
return -1; return -1;
} }
msleep(1); usleep_range(1000, 100000);
}
} }
return -1; return -1;
@ -601,6 +604,7 @@ static int mqnic_gecko_bmc_read(struct mqnic_dev *mqnic)
static int mqnic_gecko_bmc_write(struct mqnic_dev *mqnic, u16 cmd, u32 data) static int mqnic_gecko_bmc_write(struct mqnic_dev *mqnic, u16 cmd, u32 data)
{ {
int ret; int ret;
ret = mqnic_gecko_bmc_read(mqnic); ret = mqnic_gecko_bmc_read(mqnic);
if (ret == -1) if (ret == -1)
@ -627,9 +631,10 @@ static int mqnic_gecko_bmc_query(struct mqnic_dev *mqnic, u16 cmd, u32 data)
static int mqnic_gecko_bmc_read_mac(struct mqnic_dev *mqnic, int index, char *mac) static int mqnic_gecko_bmc_read_mac(struct mqnic_dev *mqnic, int index, char *mac)
{ {
int i; int i;
u16 val;
for (i = 0; i < ETH_ALEN; i += 2) { for (i = 0; i < ETH_ALEN; i += 2) {
u16 val = mqnic_gecko_bmc_query(mqnic, 0x2003, 0 + index * ETH_ALEN + i); val = mqnic_gecko_bmc_query(mqnic, 0x2003, 0 + index * ETH_ALEN + i);
if (val < 0) if (val < 0)
return val; return val;
mac[i] = val & 0xff; mac[i] = val & 0xff;

7
modules/mqnic/mqnic_eq.c
View File

@ -167,6 +167,7 @@ void mqnic_process_eq(struct net_device *ndev, struct mqnic_eq_ring *eq_ring)
{ {
struct mqnic_priv *priv = netdev_priv(ndev); struct mqnic_priv *priv = netdev_priv(ndev);
struct mqnic_event *event; struct mqnic_event *event;
struct mqnic_cq_ring *cq_ring;
u32 eq_index; u32 eq_index;
u32 eq_tail_ptr; u32 eq_tail_ptr;
int done = 0; int done = 0;
@ -192,8 +193,7 @@ void mqnic_process_eq(struct net_device *ndev, struct mqnic_eq_ring *eq_ring)
print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 1, print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 1,
event, MQNIC_EVENT_SIZE, true); event, MQNIC_EVENT_SIZE, true);
} else { } else {
struct mqnic_cq_ring *cq_ring = cq_ring = priv->tx_cpl_ring[le16_to_cpu(event->source)];
priv->tx_cpl_ring[le16_to_cpu(event->source)];
if (likely(cq_ring && cq_ring->handler)) if (likely(cq_ring && cq_ring->handler))
cq_ring->handler(cq_ring); cq_ring->handler(cq_ring);
} }
@ -206,8 +206,7 @@ void mqnic_process_eq(struct net_device *ndev, struct mqnic_eq_ring *eq_ring)
print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 1, print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 1,
event, MQNIC_EVENT_SIZE, true); event, MQNIC_EVENT_SIZE, true);
} else { } else {
struct mqnic_cq_ring *cq_ring = cq_ring = priv->rx_cpl_ring[le16_to_cpu(event->source)];
priv->rx_cpl_ring[le16_to_cpu(event->source)];
if (likely(cq_ring && cq_ring->handler)) if (likely(cq_ring && cq_ring->handler))
cq_ring->handler(cq_ring); cq_ring->handler(cq_ring);
} }

4
modules/mqnic/mqnic_ethtool.c
View File

@ -79,7 +79,7 @@ static int mqnic_get_ts_info(struct net_device *ndev,
} }
static int mqnic_read_module_eeprom(struct net_device *ndev, static int mqnic_read_module_eeprom(struct net_device *ndev,
u16 offset, u16 len, u8 * data) u16 offset, u16 len, u8 *data)
{ {
struct mqnic_priv *priv = netdev_priv(ndev); struct mqnic_priv *priv = netdev_priv(ndev);
@ -138,7 +138,7 @@ static int mqnic_get_module_info(struct net_device *ndev,
} }
static int mqnic_get_module_eeprom(struct net_device *ndev, static int mqnic_get_module_eeprom(struct net_device *ndev,
struct ethtool_eeprom *eeprom, u8 * data) struct ethtool_eeprom *eeprom, u8 *data)
{ {
struct mqnic_priv *priv = netdev_priv(ndev); struct mqnic_priv *priv = netdev_priv(ndev);
int i = 0; int i = 0;

2
modules/mqnic/mqnic_i2c.c
View File

@ -95,7 +95,7 @@ struct mqnic_i2c_bus *mqnic_i2c_bus_create(struct mqnic_dev *mqnic, u8 __iomem *
// bit-bang algorithm setup // bit-bang algorithm setup
algo = &bus->algo; algo = &bus->algo;
algo->udelay = 5; algo->udelay = 5;
algo->timeout = usecs_to_jiffies(2000);; algo->timeout = usecs_to_jiffies(2000);
algo->setsda = mqnic_i2c_set_sda; algo->setsda = mqnic_i2c_set_sda;
algo->setscl = mqnic_i2c_set_scl; algo->setscl = mqnic_i2c_set_scl;
algo->getsda = mqnic_i2c_get_sda; algo->getsda = mqnic_i2c_get_sda;

5
modules/mqnic/mqnic_main.c
View File

@ -110,6 +110,7 @@ static int mqnic_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent
{ {
int ret = 0; int ret = 0;
struct mqnic_dev *mqnic; struct mqnic_dev *mqnic;
struct mqnic_priv *priv;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
int k = 0; int k = 0;
@ -124,9 +125,11 @@ static int mqnic_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent
u16 devctl; u16 devctl;
u32 lnkcap; u32 lnkcap;
u16 lnksta; u16 lnksta;
pci_read_config_word(pdev, pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl); pci_read_config_word(pdev, pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl);
pci_read_config_dword(pdev, pdev->pcie_cap + PCI_EXP_LNKCAP, &lnkcap); pci_read_config_dword(pdev, pdev->pcie_cap + PCI_EXP_LNKCAP, &lnkcap);
pci_read_config_word(pdev, pdev->pcie_cap + PCI_EXP_LNKSTA, &lnksta); pci_read_config_word(pdev, pdev->pcie_cap + PCI_EXP_LNKSTA, &lnksta);
dev_info(dev, " Max payload size: %d bytes", dev_info(dev, " Max payload size: %d bytes",
128 << ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5)); 128 << ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5));
dev_info(dev, " Max read request size: %d bytes", dev_info(dev, " Max read request size: %d bytes",
@ -326,7 +329,7 @@ static int mqnic_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent
// pass module I2C clients to net_device instances // pass module I2C clients to net_device instances
for (k = 0; k < mqnic->if_count; k++) { for (k = 0; k < mqnic->if_count; k++) {
struct mqnic_priv *priv = netdev_priv(mqnic->ndev[k]); priv = netdev_priv(mqnic->ndev[k]);
priv->mod_i2c_client = mqnic->mod_i2c_client[k]; priv->mod_i2c_client = mqnic->mod_i2c_client[k];
} }

2
modules/mqnic/mqnic_netdev.c
View File

@ -164,7 +164,7 @@ static int mqnic_stop_port(struct net_device *ndev)
for (k = 0; k < priv->event_queue_count; k++) for (k = 0; k < priv->event_queue_count; k++)
mqnic_deactivate_eq_ring(priv, priv->event_ring[k]); mqnic_deactivate_eq_ring(priv, priv->event_ring[k]);
msleep(10); msleep(20);
// free descriptors in TX queues // free descriptors in TX queues
for (k = 0; k < priv->tx_queue_count; k++) for (k = 0; k < priv->tx_queue_count; k++)

9
modules/mqnic/mqnic_tx.c
View File

@ -218,6 +218,7 @@ int mqnic_process_tx_cq(struct net_device *ndev, struct mqnic_cq_ring *cq_ring,
struct mqnic_ring *ring = priv->tx_ring[cq_ring->ring_index]; struct mqnic_ring *ring = priv->tx_ring[cq_ring->ring_index];
struct mqnic_tx_info *tx_info; struct mqnic_tx_info *tx_info;
struct mqnic_cpl *cpl; struct mqnic_cpl *cpl;
struct skb_shared_hwtstamps hwts;
u32 cq_index; u32 cq_index;
u32 cq_tail_ptr; u32 cq_tail_ptr;
u32 ring_index; u32 ring_index;
@ -247,7 +248,6 @@ int mqnic_process_tx_cq(struct net_device *ndev, struct mqnic_cq_ring *cq_ring,
// TX hardware timestamp // TX hardware timestamp
if (unlikely(tx_info->ts_requested)) { if (unlikely(tx_info->ts_requested)) {
struct skb_shared_hwtstamps hwts;
dev_info(priv->dev, "mqnic_process_tx_cq TX TS requested"); dev_info(priv->dev, "mqnic_process_tx_cq TX TS requested");
hwts.hwtstamp = mqnic_read_cpl_ts(priv->mdev, ring, cpl); hwts.hwtstamp = mqnic_read_cpl_ts(priv->mdev, ring, cpl);
skb_tstamp_tx(tx_info->skb, &hwts); skb_tstamp_tx(tx_info->skb, &hwts);
@ -327,10 +327,11 @@ int mqnic_poll_tx_cq(struct napi_struct *napi, int budget)
} }
static bool mqnic_map_skb(struct mqnic_priv *priv, struct mqnic_ring *ring, static bool mqnic_map_skb(struct mqnic_priv *priv, struct mqnic_ring *ring,
struct mqnic_tx_info *tx_info, struct mqnic_tx_info *tx_info, struct mqnic_desc *tx_desc,
struct mqnic_desc *tx_desc, struct sk_buff *skb) struct sk_buff *skb)
{ {
struct skb_shared_info *shinfo = skb_shinfo(skb); struct skb_shared_info *shinfo = skb_shinfo(skb);
const skb_frag_t *frag;
u32 i; u32 i;
u32 len; u32 len;
dma_addr_t dma_addr; dma_addr_t dma_addr;
@ -340,7 +341,7 @@ static bool mqnic_map_skb(struct mqnic_priv *priv, struct mqnic_ring *ring,
tx_info->frag_count = 0; tx_info->frag_count = 0;
for (i = 0; i < shinfo->nr_frags; i++) { for (i = 0; i < shinfo->nr_frags; i++) {
const skb_frag_t *frag = &shinfo->frags[i]; frag = &shinfo->frags[i];
len = skb_frag_size(frag); len = skb_frag_size(frag);
dma_addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE); dma_addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(priv->dev, dma_addr))) if (unlikely(dma_mapping_error(priv->dev, dma_addr)))