From 2afbd1f15b4a47cff1b89f6ba313de94f1766a36 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 30 Mar 2021 18:53:52 -0700 Subject: [PATCH] Enable PTP in 25G designs --- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 6 +++--- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index a04a28ec4..da8a9d402 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -326,9 +326,9 @@ parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) -parameter IF_PTP_PERIOD_NS = 6'h6; -parameter IF_PTP_PERIOD_FNS = 16'h6666; -parameter PTP_TS_ENABLE = 0; +parameter IF_PTP_PERIOD_NS = 6'h2; +parameter IF_PTP_PERIOD_FNS = 16'h8F5C; +parameter PTP_TS_ENABLE = 1; parameter PTP_TS_WIDTH = 96; parameter TX_PTP_TS_FIFO_DEPTH = 32; parameter RX_PTP_TS_FIFO_DEPTH = 32; diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index d3c7d6a5c..b194ec8fe 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -333,9 +333,9 @@ parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE; parameter TDMA_INDEX_WIDTH = 6; // Timstamping parameters (port) -parameter IF_PTP_PERIOD_NS = 6'h6; -parameter IF_PTP_PERIOD_FNS = 16'h6666; -parameter PTP_TS_ENABLE = 0; +parameter IF_PTP_PERIOD_NS = 6'h2; +parameter IF_PTP_PERIOD_FNS = 16'h8F5C; +parameter PTP_TS_ENABLE = 1; parameter PTP_TS_WIDTH = 96; parameter TX_PTP_TS_FIFO_DEPTH = 32; parameter RX_PTP_TS_FIFO_DEPTH = 32;