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Enable PTP in 25G designs

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This commit is contained in:
Alex Forencich 2021-03-30 18:53:52 -07:00
parent 1aeeb0bbe2
commit 2afbd1f15b
2 changed files with 6 additions and 6 deletions
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6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
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@ -326,9 +326,9 @@ parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter IF_PTP_PERIOD_NS = 6'h2;
parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
parameter PTP_TS_ENABLE = 1;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TS_FIFO_DEPTH = 32;
parameter RX_PTP_TS_FIFO_DEPTH = 32;

6
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -333,9 +333,9 @@ parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE;
parameter TDMA_INDEX_WIDTH = 6;
// Timstamping parameters (port)
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter IF_PTP_PERIOD_NS = 6'h2;
parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
parameter PTP_TS_ENABLE = 1;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TS_FIFO_DEPTH = 32;
parameter RX_PTP_TS_FIFO_DEPTH = 32;