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Fix alignment

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-05-16 13:25:13 -07:00
parent 814a51a37c
commit 2b33698f9b
1 changed files with 9 additions and 9 deletions
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18
fpga/common/rtl/mqnic_interface.v
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@ -963,16 +963,16 @@ end
// control registers
wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr;
wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data;
wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb;
wire ctrl_reg_wr_en;
wire ctrl_reg_wr_wait;
wire ctrl_reg_wr_ack;
wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data;
wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb;
wire ctrl_reg_wr_en;
wire ctrl_reg_wr_wait;
wire ctrl_reg_wr_ack;
wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr;
wire ctrl_reg_rd_en;
wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data;
wire ctrl_reg_rd_wait;
wire ctrl_reg_rd_ack;
wire ctrl_reg_rd_en;
wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data;
wire ctrl_reg_rd_wait;
wire ctrl_reg_rd_ack;
axil_reg_if #(
.DATA_WIDTH(REG_DATA_WIDTH),