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Add RX queue mapping module

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-23 00:12:22 -07:00
parent 1b3caa1f0f
commit 2bd8350276
123 changed files with 2674 additions and 330 deletions
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16
docs/source/rb/if_ctrl.rst
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@ -4,7 +4,7 @@
Interface control register block Interface control register block
================================ ================================
The interface control register block has a header with type 0x0000C001, version 0x00000300, and contains several interface-level control registers. The interface control register block has a header with type 0x0000C001, version 0x00000400, and contains several interface-level control registers.
.. table:: .. table::
@ -34,8 +34,6 @@ The interface control register block has a header with type 0x0000C001, version
RBB+0x28 TX MTU TX MTU RW - RBB+0x28 TX MTU TX MTU RW -
-------- ------------- ------------------------------ ------------- -------- ------------- ------------------------------ -------------
RBB+0x2C RX MTU RX MTU RW - RBB+0x2C RX MTU RX MTU RW -
-------- ------------- ------------------------------ -------------
RBB+0x30 RSS mask RSS mask RW 0x00000000
======== ============= ============================== ============= ======== ============= ============================== =============
See :ref:`rb_overview` for definitions of the standard register block header fields. See :ref:`rb_overview` for definitions of the standard register block header fields.
@ -137,15 +135,3 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
======== ====== ====== ====== ====== ============= ======== ====== ====== ====== ====== =============
RBB+0x2C RX MTU RW - RBB+0x2C RX MTU RW -
======== ============================== ============= ======== ============================== =============
.. object:: RSS mask
The RSS mask field controls which receive queues will be selected by the computed RSS flow hash.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x30 RSS mask RW 0x00000000
======== ============================== =============

3
docs/source/rb/index.rst
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@ -63,7 +63,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0x00000000 \- :ref:`rb_null` 0x00000000 \- :ref:`rb_null`
0xFFFFFFFF 0x00000100 :ref:`rb_fw_id` 0xFFFFFFFF 0x00000100 :ref:`rb_fw_id`
0x0000C000 0x00000100 :ref:`rb_if` 0x0000C000 0x00000100 :ref:`rb_if`
0x0000C001 0x00000300 :ref:`rb_if_ctrl` 0x0000C001 0x00000400 :ref:`rb_if_ctrl`
0x0000C002 0x00000200 port 0x0000C002 0x00000200 port
0x0000C003 0x00000100 :ref:`rb_sched_block` 0x0000C003 0x00000100 :ref:`rb_sched_block`
0x0000C004 0x00000200 application 0x0000C004 0x00000200 application
@ -78,6 +78,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0x0000C060 0x00000100 :ref:`rb_tdma_sch` 0x0000C060 0x00000100 :ref:`rb_tdma_sch`
0x0000C080 0x00000100 :ref:`rb_phc` 0x0000C080 0x00000100 :ref:`rb_phc`
0x0000C081 0x00000100 :ref:`rb_phc_perout` 0x0000C081 0x00000100 :ref:`rb_phc_perout`
0x0000C090 0x00000100 RX queue map
0x0000C100 0x00000100 :ref:`rb_gpio` 0x0000C100 0x00000100 :ref:`rb_gpio`
0x0000C110 0x00000100 :ref:`rb_i2c` 0x0000C110 0x00000100 :ref:`rb_i2c`
0x0000C120 0x00000200 :ref:`rb_flash_spi` 0x0000C120 0x00000200 :ref:`rb_flash_spi`

1
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -48,6 +48,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

64
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -428,6 +428,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -514,6 +569,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
for k in range(block.interface.tx_queue_count): for k in range(block.interface.tx_queue_count):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
@ -526,6 +582,8 @@ async def run_test_nic(dut):
tb.loopback_enable = True tb.loopback_enable = True
queues = set()
for k, p in enumerate(pkts): for k, p in enumerate(pkts):
await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks)) await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks))
@ -536,10 +594,15 @@ async def run_test_nic(dut):
# assert pkt.data == pkts[k] # assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == len(tb.driver.interfaces[0].sched_blocks)
tb.loopback_enable = False tb.loopback_enable = False
for block in tb.driver.interfaces[0].sched_blocks[1:]: for block in tb.driver.interfaces[0].sched_blocks[1:]:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024) mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0) mem_base = mem.get_absolute_address(0)
@ -760,6 +823,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -48,6 +48,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

64
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -428,6 +428,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -514,6 +569,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
for k in range(block.interface.tx_queue_count): for k in range(block.interface.tx_queue_count):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
@ -526,6 +582,8 @@ async def run_test_nic(dut):
tb.loopback_enable = True tb.loopback_enable = True
queues = set()
for k, p in enumerate(pkts): for k, p in enumerate(pkts):
await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks)) await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks))
@ -536,10 +594,15 @@ async def run_test_nic(dut):
# assert pkt.data == pkts[k] # assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == len(tb.driver.interfaces[0].sched_blocks)
tb.loopback_enable = False tb.loopback_enable = False
for block in tb.driver.interfaces[0].sched_blocks[1:]: for block in tb.driver.interfaces[0].sched_blocks[1:]:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
@ -600,6 +663,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

271
fpga/common/rtl/mqnic_ingress.v
View File

@ -61,7 +61,9 @@ module mqnic_ingress #
// AXI stream tdest signal width // AXI stream tdest signal width
parameter AXIS_DEST_WIDTH = 8, parameter AXIS_DEST_WIDTH = 8,
// AXI stream tuser signal width // AXI stream tuser signal width
parameter AXIS_USER_WIDTH = 1, parameter S_AXIS_USER_WIDTH = 1,
// AXI stream tuser signal width
parameter M_AXIS_USER_WIDTH = S_AXIS_USER_WIDTH,
// Max receive packet size // Max receive packet size
parameter MAX_RX_SIZE = 2048 parameter MAX_RX_SIZE = 2048
) )
@ -79,7 +81,7 @@ module mqnic_ingress #
input wire s_axis_tlast, input wire s_axis_tlast,
input wire [AXIS_ID_WIDTH-1:0] s_axis_tid, input wire [AXIS_ID_WIDTH-1:0] s_axis_tid,
input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest, input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest,
input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser, input wire [S_AXIS_USER_WIDTH-1:0] s_axis_tuser,
/* /*
* Receive data output * Receive data output
@ -91,45 +93,35 @@ module mqnic_ingress #
output wire m_axis_tlast, output wire m_axis_tlast,
output wire [AXIS_ID_WIDTH-1:0] m_axis_tid, output wire [AXIS_ID_WIDTH-1:0] m_axis_tid,
output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest, output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest,
output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser, output wire [M_AXIS_USER_WIDTH-1:0] m_axis_tuser,
/*
* RX command output
*/
output wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue,
output wire [REQ_TAG_WIDTH-1:0] rx_req_tag,
output wire rx_req_valid,
input wire rx_req_ready,
/*
* RX hash output
*/
output wire [31:0] rx_hash,
output wire [3:0] rx_hash_type,
output wire rx_hash_valid,
input wire rx_hash_ready,
/* /*
* RX checksum output * RX checksum output
*/ */
output wire [15:0] rx_csum, output wire [15:0] rx_csum,
output wire rx_csum_valid, output wire rx_csum_valid,
input wire rx_csum_ready, input wire rx_csum_ready
/*
* Configuration
*/
input wire [31:0] rss_mask
); );
localparam RX_HASH_WIDTH = 32;
localparam RX_HASH_TYPE_WIDTH = 4;
localparam TUSER_HASH_OFFSET = S_AXIS_USER_WIDTH;
localparam TUSER_HASH_TYPE_OFFSET = TUSER_HASH_OFFSET + (RX_HASH_ENABLE ? RX_HASH_WIDTH : 0);
localparam INT_TUSER_WIDTH = TUSER_HASH_TYPE_OFFSET + (RX_HASH_ENABLE ? RX_HASH_TYPE_WIDTH : 0);
generate generate
wire [31:0] rx_hash_int; wire [31:0] rx_fifo_hash;
wire [3:0] rx_hash_type_int; wire [3:0] rx_fifo_hash_type;
wire rx_hash_valid_int; wire rx_fifo_hash_ready;
wire rx_fifo_hash_valid;
if (RX_HASH_ENABLE) begin if (RX_HASH_ENABLE) begin
wire [31:0] rx_hash_int;
wire [3:0] rx_hash_type_int;
wire rx_hash_valid_int;
rx_hash #( rx_hash #(
.DATA_WIDTH(AXIS_DATA_WIDTH) .DATA_WIDTH(AXIS_DATA_WIDTH)
@ -172,10 +164,10 @@ if (RX_HASH_ENABLE) begin
.s_axis_tuser(0), .s_axis_tuser(0),
// AXI output // AXI output
.m_axis_tdata({rx_hash_type, rx_hash}), .m_axis_tdata({rx_fifo_hash_type, rx_fifo_hash}),
.m_axis_tkeep(), .m_axis_tkeep(),
.m_axis_tvalid(rx_hash_valid), .m_axis_tvalid(rx_fifo_hash_valid),
.m_axis_tready(rx_hash_ready), .m_axis_tready(rx_fifo_hash_ready),
.m_axis_tlast(), .m_axis_tlast(),
.m_axis_tid(), .m_axis_tid(),
.m_axis_tdest(), .m_axis_tdest(),
@ -189,137 +181,9 @@ if (RX_HASH_ENABLE) begin
end else begin end else begin
assign rx_hash = 32'd0; assign rx_fifo_hash = 32'd0;
assign rx_hash_type = 4'd0; assign rx_fifo_hash_type = 4'd0;
assign rx_hash_valid = 1'b0; assign rx_fifo_hash_valid = 1'b0;
end
if (RX_RSS_ENABLE && RX_HASH_ENABLE) begin
axis_fifo #(
.DEPTH(AXIS_KEEP_WIDTH*32),
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(1),
.ID_WIDTH(AXIS_ID_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(AXIS_DEST_WIDTH),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_USER_WIDTH),
.FRAME_FIFO(0)
)
rx_hash_data_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
// Generate RX requests (RSS)
assign rx_req_tag = 0;
axis_fifo #(
.DEPTH(32),
.DATA_WIDTH(RX_QUEUE_INDEX_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_req_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_hash_int & rss_mask),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_hash_valid_int),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(rx_req_queue),
.m_axis_tkeep(),
.m_axis_tvalid(rx_req_valid),
.m_axis_tready(rx_req_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
end else begin
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tid = s_axis_tid;
assign m_axis_tdest = s_axis_tdest;
assign m_axis_tuser = s_axis_tuser;
// Generate RX requests (no RSS)
reg rx_frame_reg = 1'b0;
reg rx_req_valid_reg = 1'b0;
assign rx_req_queue = 0;
assign rx_req_tag = 0;
assign rx_req_valid = s_axis_tvalid && !rx_frame_reg;
always @(posedge clk) begin
if (rx_req_ready) begin
rx_req_valid_reg <= 1'b0;
end
if (s_axis_tready && s_axis_tvalid) begin
if (!rx_frame_reg) begin
rx_req_valid_reg <= 1'b1;
end
rx_frame_reg <= !s_axis_tlast;
end
if (rst) begin
rx_frame_reg <= 1'b0;
rx_req_valid_reg <= 1'b0;
end
end
end end
@ -389,6 +253,89 @@ end else begin
end end
if (RX_HASH_ENABLE) begin
wire [AXIS_DATA_WIDTH-1:0] fifo_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire [AXIS_ID_WIDTH-1:0] fifo_axis_tid;
wire [AXIS_DEST_WIDTH-1:0] fifo_axis_tdest;
wire [S_AXIS_USER_WIDTH-1:0] fifo_axis_tuser;
axis_fifo #(
.DEPTH(AXIS_KEEP_WIDTH*32),
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(1),
.ID_WIDTH(AXIS_ID_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(AXIS_DEST_WIDTH),
.USER_ENABLE(1),
.USER_WIDTH(S_AXIS_USER_WIDTH),
.FRAME_FIFO(0)
)
rx_hash_data_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(fifo_axis_tdata),
.m_axis_tkeep(fifo_axis_tkeep),
.m_axis_tvalid(fifo_axis_tvalid),
.m_axis_tready(fifo_axis_tready),
.m_axis_tlast(fifo_axis_tlast),
.m_axis_tid(fifo_axis_tid),
.m_axis_tdest(fifo_axis_tdest),
.m_axis_tuser(fifo_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
wire sideband_valid = rx_fifo_hash_valid;
assign rx_fifo_hash_ready = fifo_axis_tready && fifo_axis_tvalid && fifo_axis_tlast;
assign fifo_axis_tready = m_axis_tready && sideband_valid;
assign m_axis_tdata = fifo_axis_tdata;
assign m_axis_tkeep = fifo_axis_tkeep;
assign m_axis_tvalid = fifo_axis_tvalid && sideband_valid;
assign m_axis_tlast = fifo_axis_tlast;
assign m_axis_tid = fifo_axis_tid;
assign m_axis_tdest = fifo_axis_tdest;
assign m_axis_tuser = {rx_fifo_hash_type, rx_fifo_hash, fifo_axis_tuser};
end else begin
// bypass
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tid = s_axis_tid;
assign m_axis_tdest = s_axis_tdest;
assign m_axis_tuser = s_axis_tuser;
end
endgenerate endgenerate
endmodule endmodule

51
fpga/common/rtl/mqnic_interface.v
View File

@ -426,6 +426,8 @@ parameter AXIL_SCHED_BASE_ADDR = AXIL_RX_CQM_BASE_ADDR + 2**AXIL_RX_CQM_ADDR_WID
localparam RB_BASE_ADDR = AXIL_CTRL_BASE_ADDR; localparam RB_BASE_ADDR = AXIL_CTRL_BASE_ADDR;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
localparam RX_RB_BASE_ADDR = RB_BASE_ADDR + 16'h100;
localparam SCHED_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000; localparam SCHED_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000;
localparam SCHED_RB_STRIDE = 16'h1000; localparam SCHED_RB_STRIDE = 16'h1000;
@ -899,6 +901,12 @@ reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_DATA_WIDTH{1'b0}}; reg [AXIL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0; reg ctrl_reg_rd_ack_reg = 1'b0;
wire if_rx_ctrl_reg_wr_wait;
wire if_rx_ctrl_reg_wr_ack;
wire [AXIL_DATA_WIDTH-1:0] if_rx_ctrl_reg_rd_data;
wire if_rx_ctrl_reg_rd_wait;
wire if_rx_ctrl_reg_rd_ack;
wire port_ctrl_reg_wr_wait[PORTS-1:0]; wire port_ctrl_reg_wr_wait[PORTS-1:0];
wire port_ctrl_reg_wr_ack[PORTS-1:0]; wire port_ctrl_reg_wr_ack[PORTS-1:0];
wire [AXIL_DATA_WIDTH-1:0] port_ctrl_reg_rd_data[PORTS-1:0]; wire [AXIL_DATA_WIDTH-1:0] port_ctrl_reg_rd_data[PORTS-1:0];
@ -920,11 +928,11 @@ assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_cmb;
integer k; integer k;
always @* begin always @* begin
ctrl_reg_wr_wait_cmb = 1'b0; ctrl_reg_wr_wait_cmb = if_rx_ctrl_reg_wr_wait;
ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_reg; ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_reg | if_rx_ctrl_reg_wr_ack;
ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_reg; ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_reg | if_rx_ctrl_reg_rd_data;
ctrl_reg_rd_wait_cmb = 1'b0; ctrl_reg_rd_wait_cmb = if_rx_ctrl_reg_rd_wait;
ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_reg; ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_reg | if_rx_ctrl_reg_rd_ack;
for (k = 0; k < PORTS; k = k + 1) begin for (k = 0; k < PORTS; k = k + 1) begin
ctrl_reg_wr_wait_cmb = ctrl_reg_wr_wait_cmb | port_ctrl_reg_wr_wait[k]; ctrl_reg_wr_wait_cmb = ctrl_reg_wr_wait_cmb | port_ctrl_reg_wr_wait[k];
@ -938,8 +946,6 @@ end
reg [DMA_CLIENT_LEN_WIDTH-1:0] tx_mtu_reg = MAX_TX_SIZE; reg [DMA_CLIENT_LEN_WIDTH-1:0] tx_mtu_reg = MAX_TX_SIZE;
reg [DMA_CLIENT_LEN_WIDTH-1:0] rx_mtu_reg = MAX_RX_SIZE; reg [DMA_CLIENT_LEN_WIDTH-1:0] rx_mtu_reg = MAX_RX_SIZE;
reg [RX_QUEUE_INDEX_WIDTH-1:0] rss_mask_reg = 0;
always @(posedge clk) begin always @(posedge clk) begin
ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_data_reg <= {AXIL_DATA_WIDTH{1'b0}}; ctrl_reg_rd_data_reg <= {AXIL_DATA_WIDTH{1'b0}};
@ -952,7 +958,6 @@ always @(posedge clk) begin
// Interface control // Interface control
RBB+8'h28: tx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: TX MTU RBB+8'h28: tx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: TX MTU
RBB+8'h2C: rx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: RX MTU RBB+8'h2C: rx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: RX MTU
RBB+8'h30: rss_mask_reg <= ctrl_reg_wr_data; // IF ctrl: RSS mask
default: ctrl_reg_wr_ack_reg <= 1'b0; default: ctrl_reg_wr_ack_reg <= 1'b0;
endcase endcase
end end
@ -963,7 +968,7 @@ always @(posedge clk) begin
case ({ctrl_reg_rd_addr >> 2, 2'b00}) case ({ctrl_reg_rd_addr >> 2, 2'b00})
// Interface control // Interface control
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C001; // IF ctrl: Type RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C001; // IF ctrl: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000300; // IF ctrl: Version RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000400; // IF ctrl: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // IF ctrl: Next header RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // IF ctrl: Next header
RBB+8'h0C: begin RBB+8'h0C: begin
// IF ctrl: features // IF ctrl: features
@ -979,7 +984,6 @@ always @(posedge clk) begin
RBB+8'h24: ctrl_reg_rd_data_reg <= MAX_RX_SIZE; // IF ctrl: Max RX MTU RBB+8'h24: ctrl_reg_rd_data_reg <= MAX_RX_SIZE; // IF ctrl: Max RX MTU
RBB+8'h28: ctrl_reg_rd_data_reg <= tx_mtu_reg; // IF ctrl: TX MTU RBB+8'h28: ctrl_reg_rd_data_reg <= tx_mtu_reg; // IF ctrl: TX MTU
RBB+8'h2C: ctrl_reg_rd_data_reg <= rx_mtu_reg; // IF ctrl: RX MTU RBB+8'h2C: ctrl_reg_rd_data_reg <= rx_mtu_reg; // IF ctrl: RX MTU
RBB+8'h30: ctrl_reg_rd_data_reg <= rss_mask_reg; // IF ctrl: RSS mask
// Queue manager (Event) // Queue manager (Event)
RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C010; // Event QM: Type RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C010; // Event QM: Type
RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // Event QM: Version RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // Event QM: Version
@ -1011,7 +1015,7 @@ always @(posedge clk) begin
// Queue manager (RX CPL) // Queue manager (RX CPL)
RBB+8'hC0: ctrl_reg_rd_data_reg <= 32'h0000C031; // RX CPL QM: Type RBB+8'hC0: ctrl_reg_rd_data_reg <= 32'h0000C031; // RX CPL QM: Type
RBB+8'hC4: ctrl_reg_rd_data_reg <= 32'h00000100; // RX CPL QM: Version RBB+8'hC4: ctrl_reg_rd_data_reg <= 32'h00000100; // RX CPL QM: Version
RBB+8'hC8: ctrl_reg_rd_data_reg <= SCHED_RB_BASE_ADDR; // RX CPL QM: Next header RBB+8'hC8: ctrl_reg_rd_data_reg <= RX_RB_BASE_ADDR; // RX CPL QM: Next header
RBB+8'hCC: ctrl_reg_rd_data_reg <= AXIL_RX_CQM_BASE_ADDR; // RX CPL QM: Offset RBB+8'hCC: ctrl_reg_rd_data_reg <= AXIL_RX_CQM_BASE_ADDR; // RX CPL QM: Offset
RBB+8'hD0: ctrl_reg_rd_data_reg <= 2**RX_CPL_QUEUE_INDEX_WIDTH; // RX CPL QM: Count RBB+8'hD0: ctrl_reg_rd_data_reg <= 2**RX_CPL_QUEUE_INDEX_WIDTH; // RX CPL QM: Count
RBB+8'hD4: ctrl_reg_rd_data_reg <= 32; // RX CPL QM: Stride RBB+8'hD4: ctrl_reg_rd_data_reg <= 32; // RX CPL QM: Stride
@ -1025,8 +1029,6 @@ always @(posedge clk) begin
tx_mtu_reg <= MAX_TX_SIZE; tx_mtu_reg <= MAX_TX_SIZE;
rx_mtu_reg <= MAX_RX_SIZE; rx_mtu_reg <= MAX_RX_SIZE;
rss_mask_reg <= 0;
end end
end end
@ -2364,6 +2366,11 @@ assign m_axis_data_dma_read_desc_ram_sel = 0;
mqnic_interface_rx #( mqnic_interface_rx #(
.PORTS(PORTS), .PORTS(PORTS),
.REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_STRB_WIDTH),
.RB_BASE_ADDR(RX_RB_BASE_ADDR),
.RB_NEXT_PTR(SCHED_RB_BASE_ADDR),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH), .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
@ -2409,6 +2416,21 @@ interface_rx_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
/*
* Control register interface
*/
.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
.ctrl_reg_wr_data(ctrl_reg_wr_data),
.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
.ctrl_reg_wr_en(ctrl_reg_wr_en),
.ctrl_reg_wr_wait(if_rx_ctrl_reg_wr_wait),
.ctrl_reg_wr_ack(if_rx_ctrl_reg_wr_ack),
.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
.ctrl_reg_rd_en(ctrl_reg_rd_en),
.ctrl_reg_rd_data(if_rx_ctrl_reg_rd_data),
.ctrl_reg_rd_wait(if_rx_ctrl_reg_rd_wait),
.ctrl_reg_rd_ack(if_rx_ctrl_reg_rd_ack),
/* /*
* Descriptor request output * Descriptor request output
*/ */
@ -2504,8 +2526,7 @@ interface_rx_inst (
/* /*
* Configuration * Configuration
*/ */
.mtu(rx_mtu_reg), .mtu(rx_mtu_reg)
.rss_mask(rss_mask_reg)
); );
assign m_axis_data_dma_write_desc_ram_sel = 0; assign m_axis_data_dma_write_desc_ram_sel = 0;

165
fpga/common/rtl/mqnic_interface_rx.v
View File

@ -44,6 +44,16 @@ module mqnic_interface_rx #
( (
// Number of ports // Number of ports
parameter PORTS = 1, parameter PORTS = 1,
// Control register interface address width
parameter REG_ADDR_WIDTH = 7,
// Control register interface data width
parameter REG_DATA_WIDTH = 32,
// Control register interface byte enable width
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
// Register block base address
parameter RB_BASE_ADDR = 0,
// Register block next block address
parameter RB_NEXT_PTR = 0,
// DMA address width // DMA address width
parameter DMA_ADDR_WIDTH = 64, parameter DMA_ADDR_WIDTH = 64,
// DMA length field width // DMA length field width
@ -129,6 +139,21 @@ module mqnic_interface_rx #
input wire clk, input wire clk,
input wire rst, input wire rst,
/*
* Control register interface
*/
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data,
input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
input wire ctrl_reg_wr_en,
output wire ctrl_reg_wr_wait,
output wire ctrl_reg_wr_ack,
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
input wire ctrl_reg_rd_en,
output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data,
output wire ctrl_reg_rd_wait,
output wire ctrl_reg_rd_ack,
/* /*
* Descriptor request output * Descriptor request output
*/ */
@ -224,8 +249,7 @@ module mqnic_interface_rx #
/* /*
* Configuration * Configuration
*/ */
input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu, input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
input wire [31:0] rss_mask
); );
parameter DMA_CLIENT_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE); parameter DMA_CLIENT_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
@ -233,6 +257,13 @@ parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;
parameter REQ_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE); parameter REQ_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
localparam RX_HASH_WIDTH = 32;
localparam RX_HASH_TYPE_WIDTH = 4;
localparam TUSER_HASH_OFFSET = AXIS_RX_USER_WIDTH;
localparam TUSER_HASH_TYPE_OFFSET = TUSER_HASH_OFFSET + (RX_HASH_ENABLE ? RX_HASH_WIDTH : 0);
localparam INT_AXIS_RX_USER_WIDTH = TUSER_HASH_TYPE_OFFSET + (RX_HASH_ENABLE ? RX_HASH_TYPE_WIDTH : 0);
wire [AXIS_DESC_DATA_WIDTH-1:0] rx_fifo_desc_tdata; wire [AXIS_DESC_DATA_WIDTH-1:0] rx_fifo_desc_tdata;
wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_fifo_desc_tkeep; wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_fifo_desc_tkeep;
wire rx_fifo_desc_tvalid; wire rx_fifo_desc_tvalid;
@ -283,16 +314,6 @@ rx_desc_fifo (
.status_good_frame() .status_good_frame()
); );
wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue;
wire [REQ_TAG_WIDTH-1:0] rx_req_tag;
wire rx_req_valid;
wire rx_req_ready;
wire [31:0] rx_hash;
wire [3:0] rx_hash_type;
wire rx_hash_valid;
wire rx_hash_ready;
wire [15:0] rx_csum; wire [15:0] rx_csum;
wire rx_csum_valid; wire rx_csum_valid;
wire rx_csum_ready; wire rx_csum_ready;
@ -303,16 +324,50 @@ wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_tag;
wire dma_rx_desc_valid; wire dma_rx_desc_valid;
wire dma_rx_desc_ready; wire dma_rx_desc_ready;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len; wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag; wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag;
wire [AXIS_RX_ID_WIDTH-1:0] dma_rx_desc_status_id; wire [AXIS_RX_ID_WIDTH-1:0] dma_rx_desc_status_id;
wire [AXIS_RX_DEST_WIDTH-1:0] dma_rx_desc_status_dest; wire [AXIS_RX_DEST_WIDTH-1:0] dma_rx_desc_status_dest;
wire [AXIS_RX_USER_WIDTH-1:0] dma_rx_desc_status_user; wire [INT_AXIS_RX_USER_WIDTH-1:0] dma_rx_desc_status_user;
wire [3:0] dma_rx_desc_status_error; wire [3:0] dma_rx_desc_status_error;
wire dma_rx_desc_status_valid; wire dma_rx_desc_status_valid;
// Generate RX requests
reg rx_frame_reg = 1'b0;
reg [5:0] rx_req_cnt_reg = 0;
wire rx_req_valid = rx_req_cnt_reg != 0;
wire rx_req_ready;
always @(posedge clk) begin
if (rx_req_valid && rx_req_ready) begin
rx_req_cnt_reg <= rx_req_cnt_reg - 1;
end
if (rx_axis_tready && rx_axis_tvalid) begin
if (!rx_frame_reg) begin
if (rx_req_valid && rx_req_ready) begin
rx_req_cnt_reg <= rx_req_cnt_reg;
end else begin
rx_req_cnt_reg <= rx_req_cnt_reg + 1;
end
end
rx_frame_reg <= !rx_axis_tlast;
end
if (rst) begin
rx_frame_reg <= 1'b0;
rx_req_cnt_reg <= 0;
end
end
rx_engine #( rx_engine #(
.PORTS(PORTS), .PORTS(PORTS),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.REG_DATA_WIDTH(REG_DATA_WIDTH),
.REG_STRB_WIDTH(REG_STRB_WIDTH),
.RB_BASE_ADDR(RB_BASE_ADDR),
.RB_NEXT_PTR(RB_NEXT_PTR),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH), .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
@ -343,17 +398,31 @@ rx_engine #(
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH), .AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH),
.AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH), .AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH) .AXIS_RX_USER_WIDTH(INT_AXIS_RX_USER_WIDTH)
) )
rx_engine_inst ( rx_engine_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
/*
* Control register interface
*/
.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
.ctrl_reg_wr_data(ctrl_reg_wr_data),
.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
.ctrl_reg_wr_en(ctrl_reg_wr_en),
.ctrl_reg_wr_wait(ctrl_reg_wr_wait),
.ctrl_reg_wr_ack(ctrl_reg_wr_ack),
.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
.ctrl_reg_rd_en(ctrl_reg_rd_en),
.ctrl_reg_rd_data(ctrl_reg_rd_data),
.ctrl_reg_rd_wait(ctrl_reg_rd_wait),
.ctrl_reg_rd_ack(ctrl_reg_rd_ack),
/* /*
* Receive request input (queue index) * Receive request input (queue index)
*/ */
.s_axis_rx_req_queue(rx_req_queue), .s_axis_rx_req_tag(0),
.s_axis_rx_req_tag(rx_req_tag),
.s_axis_rx_req_valid(rx_req_valid), .s_axis_rx_req_valid(rx_req_valid),
.s_axis_rx_req_ready(rx_req_ready), .s_axis_rx_req_ready(rx_req_ready),
@ -448,14 +517,6 @@ rx_engine_inst (
.s_axis_rx_desc_status_error(dma_rx_desc_status_error), .s_axis_rx_desc_status_error(dma_rx_desc_status_error),
.s_axis_rx_desc_status_valid(dma_rx_desc_status_valid), .s_axis_rx_desc_status_valid(dma_rx_desc_status_valid),
/*
* Receive hash input
*/
.s_axis_rx_hash(rx_hash),
.s_axis_rx_hash_type(rx_hash_type),
.s_axis_rx_hash_valid(rx_hash_valid),
.s_axis_rx_hash_ready(rx_hash_ready),
/* /*
* Receive checksum input * Receive checksum input
*/ */
@ -510,14 +571,14 @@ dma_psdpram_rx_inst (
.rd_resp_ready(dma_ram_rd_resp_ready) .rd_resp_ready(dma_ram_rd_resp_ready)
); );
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_int; wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_int;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_int; wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_int;
wire rx_axis_tvalid_int; wire rx_axis_tvalid_int;
wire rx_axis_tready_int; wire rx_axis_tready_int;
wire rx_axis_tlast_int; wire rx_axis_tlast_int;
wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid_int; wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid_int;
wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest_int; wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest_int;
wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser_int; wire [INT_AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser_int;
mqnic_ingress #( mqnic_ingress #(
.REQ_TAG_WIDTH(REQ_TAG_WIDTH), .REQ_TAG_WIDTH(REQ_TAG_WIDTH),
@ -529,7 +590,8 @@ mqnic_ingress #(
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH), .AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH),
.AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH), .AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH), .S_AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH),
.M_AXIS_USER_WIDTH(INT_AXIS_RX_USER_WIDTH),
.MAX_RX_SIZE(MAX_RX_SIZE) .MAX_RX_SIZE(MAX_RX_SIZE)
) )
ingress_inst ( ingress_inst (
@ -560,33 +622,12 @@ ingress_inst (
.m_axis_tdest(rx_axis_tdest_int), .m_axis_tdest(rx_axis_tdest_int),
.m_axis_tuser(rx_axis_tuser_int), .m_axis_tuser(rx_axis_tuser_int),
/*
* RX command output
*/
.rx_req_queue(rx_req_queue),
.rx_req_tag(rx_req_tag),
.rx_req_valid(rx_req_valid),
.rx_req_ready(rx_req_ready),
/*
* RX hash output
*/
.rx_hash(rx_hash),
.rx_hash_type(rx_hash_type),
.rx_hash_valid(rx_hash_valid),
.rx_hash_ready(rx_hash_ready),
/* /*
* RX checksum output * RX checksum output
*/ */
.rx_csum(rx_csum), .rx_csum(rx_csum),
.rx_csum_valid(rx_csum_valid), .rx_csum_valid(rx_csum_valid),
.rx_csum_ready(rx_csum_ready), .rx_csum_ready(rx_csum_ready)
/*
* Configuration
*/
.rss_mask(rss_mask)
); );
dma_client_axis_sink #( dma_client_axis_sink #(
@ -604,7 +645,7 @@ dma_client_axis_sink #(
.AXIS_DEST_ENABLE(1), .AXIS_DEST_ENABLE(1),
.AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH), .AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.AXIS_USER_ENABLE(1), .AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH), .AXIS_USER_WIDTH(INT_AXIS_RX_USER_WIDTH),
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH) .TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
) )

232
fpga/common/rtl/mqnic_rx_queue_map.v Normal file
View File

@ -0,0 +1,232 @@
/*
Copyright 2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* RX queue port mapping
*/
module mqnic_rx_queue_map #
(
// Number of ports
parameter PORTS = 1,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 10,
// AXI stream tid signal width (source port)
parameter ID_WIDTH = $clog2(PORTS),
// AXI stream tdest signal width (from application)
parameter DEST_WIDTH = QUEUE_INDEX_WIDTH,
// Flow hash width
parameter HASH_WIDTH = 32,
// Tag width
parameter TAG_WIDTH = 8,
// Control register interface address width
parameter REG_ADDR_WIDTH = $clog2(16 + PORTS*16),
// Control register interface data width
parameter REG_DATA_WIDTH = 32,
// Control register interface byte enable width
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
// Register block base address
parameter RB_BASE_ADDR = 0,
// Register block next block address
parameter RB_NEXT_PTR = 0
)
(
input wire clk,
input wire rst,
/*
* Register interface
*/
input wire [REG_ADDR_WIDTH-1:0] reg_wr_addr,
input wire [REG_DATA_WIDTH-1:0] reg_wr_data,
input wire [REG_STRB_WIDTH-1:0] reg_wr_strb,
input wire reg_wr_en,
output wire reg_wr_wait,
output wire reg_wr_ack,
input wire [REG_ADDR_WIDTH-1:0] reg_rd_addr,
input wire reg_rd_en,
output wire [REG_DATA_WIDTH-1:0] reg_rd_data,
output wire reg_rd_wait,
output wire reg_rd_ack,
/*
* Request input
*/
input wire [ID_WIDTH-1:0] req_id,
input wire [DEST_WIDTH-1:0] req_dest,
input wire [HASH_WIDTH-1:0] req_hash,
input wire [TAG_WIDTH-1:0] req_tag,
input wire req_valid,
/*
* Response output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] resp_queue,
output wire [TAG_WIDTH-1:0] resp_tag,
output wire resp_valid
);
localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
// check configuration
initial begin
if (REG_DATA_WIDTH != 32) begin
$error("Error: Register interface width must be 32 (instance %m)");
$finish;
end
if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (REG_ADDR_WIDTH < $clog2(16 + PORTS*16)) begin
$error("Error: Register address width too narrow (instance %m)");
$finish;
end
if (RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 16 + PORTS*16) begin
$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
$finish;
end
end
// control registers
reg reg_wr_ack_reg = 1'b0;
reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0;
reg reg_rd_ack_reg = 1'b0;
reg [QUEUE_INDEX_WIDTH-1:0] offset_reg[PORTS-1:0];
reg [QUEUE_INDEX_WIDTH-1:0] hash_mask_reg[PORTS-1:0];
reg [QUEUE_INDEX_WIDTH-1:0] app_mask_reg[PORTS-1:0];
reg [QUEUE_INDEX_WIDTH-1:0] resp_queue_reg = 0;
reg [TAG_WIDTH-1:0] resp_tag_reg = 0;
reg resp_valid_reg = 1'b0;
assign reg_wr_wait = 1'b0;
assign reg_wr_ack = reg_wr_ack_reg;
assign reg_rd_data = reg_rd_data_reg;
assign reg_rd_wait = 1'b0;
assign reg_rd_ack = reg_rd_ack_reg;
assign resp_queue = resp_queue_reg;
assign resp_tag = resp_tag_reg;
assign resp_valid = resp_valid_reg;
integer k;
initial begin
for (k = 0; k < PORTS; k = k + 1) begin
offset_reg[k] = 0;
hash_mask_reg[k] = 0;
app_mask_reg[k] = 0;
end
end
always @(posedge clk) begin
reg_wr_ack_reg <= 1'b0;
reg_rd_data_reg <= 0;
reg_rd_ack_reg <= 1'b0;
if (reg_wr_en && !reg_wr_ack_reg) begin
// write operation
reg_wr_ack_reg <= 1'b0;
for (k = 0; k < PORTS; k = k + 1) begin
if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h10 + k*16) begin
offset_reg[k] <= reg_wr_data;
reg_wr_ack_reg <= 1'b1;
end
if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h14 + k*16) begin
hash_mask_reg[k] <= reg_wr_data;
reg_wr_ack_reg <= 1'b1;
end
if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h18 + k*16) begin
app_mask_reg[k] <= reg_wr_data;
reg_wr_ack_reg <= 1'b1;
end
end
end
if (reg_rd_en && !reg_rd_ack_reg) begin
// read operation
reg_rd_ack_reg <= 1'b1;
case ({reg_rd_addr >> 2, 2'b00})
RBB+7'h00: reg_rd_data_reg <= 32'h0000C090; // Type
RBB+7'h04: reg_rd_data_reg <= 32'h00000100; // Version
RBB+7'h08: reg_rd_data_reg <= RB_NEXT_PTR; // Next header
RBB+7'h0C: reg_rd_data_reg <= PORTS; // Port count
default: reg_rd_ack_reg <= 1'b0;
endcase
for (k = 0; k < PORTS; k = k + 1) begin
if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h10 + k*16) begin
reg_rd_data_reg <= offset_reg[k];
reg_rd_ack_reg <= 1'b1;
end
if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h14 + k*16) begin
reg_rd_data_reg <= hash_mask_reg[k];
reg_rd_ack_reg <= 1'b1;
end
if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h18 + k*16) begin
reg_rd_data_reg <= app_mask_reg[k];
reg_rd_ack_reg <= 1'b1;
end
end
end
resp_queue_reg <= (req_dest & app_mask_reg[req_id]) + (req_hash & hash_mask_reg[req_id]) + offset_reg[req_id];
resp_tag_reg <= req_tag;
resp_valid_reg <= req_valid;
if (rst) begin
reg_wr_ack_reg <= 1'b0;
reg_rd_ack_reg <= 1'b0;
for (k = 0; k < PORTS; k = k + 1) begin
offset_reg[k] <= 0;
hash_mask_reg[k] <= 0;
app_mask_reg[k] <= 0;
end
resp_valid_reg <= 1'b0;
end
end
endmodule
`resetall

168
fpga/common/rtl/rx_engine.v
View File

@ -44,6 +44,16 @@ module rx_engine #
( (
// Number of ports // Number of ports
parameter PORTS = 1, parameter PORTS = 1,
// Control register interface address width
parameter REG_ADDR_WIDTH = 7,
// Control register interface data width
parameter REG_DATA_WIDTH = 32,
// Control register interface byte enable width
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
// Register block base address
parameter RB_BASE_ADDR = 0,
// Register block next block address
parameter RB_NEXT_PTR = 0,
// DMA RAM address width // DMA RAM address width
parameter RAM_ADDR_WIDTH = 16, parameter RAM_ADDR_WIDTH = 16,
// DMA address width // DMA address width
@ -111,10 +121,24 @@ module rx_engine #
input wire clk, input wire clk,
input wire rst, input wire rst,
/*
* Control register interface
*/
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data,
input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
input wire ctrl_reg_wr_en,
output wire ctrl_reg_wr_wait,
output wire ctrl_reg_wr_ack,
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
input wire ctrl_reg_rd_en,
output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data,
output wire ctrl_reg_rd_wait,
output wire ctrl_reg_rd_ack,
/* /*
* Receive request input (queue index) * Receive request input (queue index)
*/ */
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_rx_req_queue,
input wire [REQ_TAG_WIDTH-1:0] s_axis_rx_req_tag, input wire [REQ_TAG_WIDTH-1:0] s_axis_rx_req_tag,
input wire s_axis_rx_req_valid, input wire s_axis_rx_req_valid,
output wire s_axis_rx_req_ready, output wire s_axis_rx_req_ready,
@ -210,14 +234,6 @@ module rx_engine #
input wire [3:0] s_axis_rx_desc_status_error, input wire [3:0] s_axis_rx_desc_status_error,
input wire s_axis_rx_desc_status_valid, input wire s_axis_rx_desc_status_valid,
/*
* Receive hash input
*/
input wire [31:0] s_axis_rx_hash,
input wire [3:0] s_axis_rx_hash_type,
input wire s_axis_rx_hash_valid,
output wire s_axis_rx_hash_ready,
/* /*
* Receive checksum input * Receive checksum input
*/ */
@ -243,6 +259,14 @@ parameter RX_BUFFER_PTR_MASK_UPPER = RX_BUFFER_PTR_MASK & ~RX_BUFFER_PTR_MASK_LO
parameter CL_MAX_DESC_REQ = $clog2(MAX_DESC_REQ); parameter CL_MAX_DESC_REQ = $clog2(MAX_DESC_REQ);
localparam RX_HASH_WIDTH = 32;
localparam RX_HASH_TYPE_WIDTH = 4;
localparam TUSER_PTP_TS_OFFSET = 1;
localparam TUSER_HASH_OFFSET = TUSER_PTP_TS_OFFSET + (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0);
localparam TUSER_HASH_TYPE_OFFSET = TUSER_HASH_OFFSET + (RX_HASH_ENABLE ? RX_HASH_WIDTH : 0);
localparam INT_TUSER_WIDTH = TUSER_HASH_TYPE_OFFSET + (RX_HASH_ENABLE ? RX_HASH_TYPE_WIDTH : 0);
// bus width assertions // bus width assertions
initial begin initial begin
if (DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin if (DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
@ -355,7 +379,6 @@ reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_write_count_start[DESC_TABLE_
reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_write_count_finish[DESC_TABLE_SIZE-1:0]; reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_write_count_finish[DESC_TABLE_SIZE-1:0];
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0;
reg [QUEUE_INDEX_WIDTH-1:0] desc_table_start_queue;
reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag; reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag;
reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_start_buf_ptr; reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_start_buf_ptr;
reg desc_table_start_en; reg desc_table_start_en;
@ -363,7 +386,12 @@ reg [CL_DESC_TABLE_SIZE-1:0] desc_table_rx_finish_ptr;
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_rx_finish_len; reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_rx_finish_len;
reg [AXIS_RX_ID_WIDTH-1:0] desc_table_rx_finish_id; reg [AXIS_RX_ID_WIDTH-1:0] desc_table_rx_finish_id;
reg [PTP_TS_WIDTH-1:0] desc_table_rx_finish_ptp_ts; reg [PTP_TS_WIDTH-1:0] desc_table_rx_finish_ptp_ts;
reg [31:0] desc_table_rx_finish_hash;
reg [3:0] desc_table_rx_finish_hash_type;
reg desc_table_rx_finish_en; reg desc_table_rx_finish_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_store_queue_ptr;
reg [QUEUE_INDEX_WIDTH-1:0] desc_table_store_queue;
reg desc_table_store_queue_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_dequeue_start_ptr_reg = 0; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_dequeue_start_ptr_reg = 0;
reg desc_table_dequeue_start_en; reg desc_table_dequeue_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr;
@ -376,10 +404,6 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
reg desc_table_desc_fetched_en; reg desc_table_desc_fetched_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_data_written_ptr; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_data_written_ptr;
reg desc_table_data_written_en; reg desc_table_data_written_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_hash_ptr_reg = 0;
reg [31:0] desc_table_store_hash;
reg [3:0] desc_table_store_hash_type;
reg desc_table_store_hash_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_csum_ptr_reg = 0; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_csum_ptr_reg = 0;
reg [15:0] desc_table_store_csum; reg [15:0] desc_table_store_csum;
reg desc_table_store_csum_en; reg desc_table_store_csum_en;
@ -424,8 +448,6 @@ assign m_axis_rx_desc_len = m_axis_rx_desc_len_reg;
assign m_axis_rx_desc_tag = m_axis_rx_desc_tag_reg; assign m_axis_rx_desc_tag = m_axis_rx_desc_tag_reg;
assign m_axis_rx_desc_valid = m_axis_rx_desc_valid_reg; assign m_axis_rx_desc_valid = m_axis_rx_desc_valid_reg;
assign s_axis_rx_hash_ready = s_axis_rx_hash_ready_reg;
assign s_axis_rx_csum_ready = s_axis_rx_csum_ready_reg; assign s_axis_rx_csum_ready = s_axis_rx_csum_ready_reg;
// reg [15:0] stall_cnt = 0; // reg [15:0] stall_cnt = 0;
@ -463,6 +485,59 @@ assign s_axis_rx_csum_ready = s_axis_rx_csum_ready_reg;
// .probe5(0) // .probe5(0)
// ); // );
wire [QUEUE_INDEX_WIDTH-1:0] queue_map_resp_queue;
wire [CL_DESC_TABLE_SIZE+1-1:0] queue_map_resp_tag;
wire queue_map_resp_valid;
mqnic_rx_queue_map #(
.PORTS(PORTS),
.QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
.ID_WIDTH(AXIS_RX_ID_WIDTH),
.DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.HASH_WIDTH(RX_HASH_WIDTH),
.TAG_WIDTH(CL_DESC_TABLE_SIZE+1),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.REG_DATA_WIDTH(REG_DATA_WIDTH),
.REG_STRB_WIDTH(REG_STRB_WIDTH),
.RB_BASE_ADDR(RB_BASE_ADDR),
.RB_NEXT_PTR(RB_NEXT_PTR)
)
mqnic_rx_queue_map_inst (
.clk(clk),
.rst(rst),
/*
* Register interface
*/
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(ctrl_reg_wr_wait),
.reg_wr_ack(ctrl_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(ctrl_reg_rd_data),
.reg_rd_wait(ctrl_reg_rd_wait),
.reg_rd_ack(ctrl_reg_rd_ack),
/*
* Request input
*/
.req_id(s_axis_rx_desc_status_id),
.req_dest(s_axis_rx_desc_status_dest),
.req_hash(s_axis_rx_desc_status_user >> TUSER_HASH_OFFSET),
.req_tag(s_axis_rx_desc_status_tag),
.req_valid(s_axis_rx_desc_status_valid),
/*
* Response output
*/
.resp_queue(queue_map_resp_queue),
.resp_tag(queue_map_resp_tag),
.resp_valid(queue_map_resp_valid)
);
integer i; integer i;
initial begin initial begin
@ -530,14 +605,18 @@ always @* begin
dec_active_desc_req_2 = 1'b0; dec_active_desc_req_2 = 1'b0;
desc_table_start_tag = s_axis_rx_req_tag; desc_table_start_tag = s_axis_rx_req_tag;
desc_table_start_queue = s_axis_rx_req_queue;
desc_table_start_buf_ptr = buf_wr_ptr_reg; desc_table_start_buf_ptr = buf_wr_ptr_reg;
desc_table_start_en = 1'b0; desc_table_start_en = 1'b0;
desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag; desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag;
desc_table_rx_finish_len = s_axis_rx_desc_status_len; desc_table_rx_finish_len = s_axis_rx_desc_status_len;
desc_table_rx_finish_id = s_axis_rx_desc_status_id; desc_table_rx_finish_id = s_axis_rx_desc_status_id;
desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> 1; desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> TUSER_PTP_TS_OFFSET;
desc_table_rx_finish_hash = s_axis_rx_desc_status_user >> TUSER_HASH_OFFSET;
desc_table_rx_finish_hash_type = s_axis_rx_desc_status_user >> TUSER_HASH_TYPE_OFFSET;
desc_table_rx_finish_en = 1'b0; desc_table_rx_finish_en = 1'b0;
desc_table_store_queue_ptr = queue_map_resp_tag;
desc_table_store_queue = queue_map_resp_queue;
desc_table_store_queue_en = 1'b0;
desc_table_dequeue_start_en = 1'b0; desc_table_dequeue_start_en = 1'b0;
desc_table_dequeue_ptr = s_axis_desc_req_status_tag; desc_table_dequeue_ptr = s_axis_desc_req_status_tag;
desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr; desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
@ -549,9 +628,6 @@ always @* begin
desc_table_desc_fetched_en = 1'b0; desc_table_desc_fetched_en = 1'b0;
desc_table_data_written_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK; desc_table_data_written_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_data_written_en = 1'b0; desc_table_data_written_en = 1'b0;
desc_table_store_hash = s_axis_rx_hash;
desc_table_store_hash_type = s_axis_rx_hash_type;
desc_table_store_hash_en = 1'b0;
desc_table_store_csum = s_axis_rx_csum; desc_table_store_csum = s_axis_rx_csum;
desc_table_store_csum_en = 1'b0; desc_table_store_csum_en = 1'b0;
desc_table_cpl_enqueue_start_en = 1'b0; desc_table_cpl_enqueue_start_en = 1'b0;
@ -573,7 +649,6 @@ always @* begin
// store in descriptor table // store in descriptor table
desc_table_start_tag = s_axis_rx_req_tag; desc_table_start_tag = s_axis_rx_req_tag;
desc_table_start_queue = s_axis_rx_req_queue;
desc_table_start_buf_ptr = buf_wr_ptr_reg; desc_table_start_buf_ptr = buf_wr_ptr_reg;
desc_table_start_en = 1'b1; desc_table_start_en = 1'b1;
@ -592,17 +667,25 @@ always @* begin
end end
// receive done // receive done
// wait for receive completion // wait for DMA completion
if (s_axis_rx_desc_status_valid) begin if (s_axis_rx_desc_status_valid) begin
// update entry in descriptor table // update entry in descriptor table
desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag; desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag;
desc_table_rx_finish_len = s_axis_rx_desc_status_len; desc_table_rx_finish_len = s_axis_rx_desc_status_len;
desc_table_rx_finish_id = s_axis_rx_desc_status_id; desc_table_rx_finish_id = s_axis_rx_desc_status_id;
// desc_table_rx_finish_queue = s_axis_rx_desc_status_dest; desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> TUSER_PTP_TS_OFFSET;
desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> 1; desc_table_rx_finish_hash = s_axis_rx_desc_status_user >> TUSER_HASH_OFFSET;
desc_table_rx_finish_hash_type = s_axis_rx_desc_status_user >> TUSER_HASH_TYPE_OFFSET;
desc_table_rx_finish_en = 1'b1; desc_table_rx_finish_en = 1'b1;
end end
// store queue
if (queue_map_resp_valid) begin
desc_table_store_queue_ptr = queue_map_resp_tag;
desc_table_store_queue = queue_map_resp_queue;
desc_table_store_queue_en = 1'b1;
end
// descriptor fetch // descriptor fetch
if (desc_table_active[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && desc_table_dequeue_start_ptr_reg != desc_table_start_ptr_reg) begin if (desc_table_active[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && desc_table_dequeue_start_ptr_reg != desc_table_start_ptr_reg) begin
if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_req_valid && active_desc_req_count_reg < MAX_DESC_REQ) begin if (desc_table_rx_done[desc_table_dequeue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_desc_req_valid && active_desc_req_count_reg < MAX_DESC_REQ) begin
@ -708,24 +791,6 @@ always @* begin
desc_table_write_finish_en = 1'b1; desc_table_write_finish_en = 1'b1;
end end
// store RX hash
if (desc_table_active[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] && desc_table_store_hash_ptr_reg != desc_table_start_ptr_reg && RX_HASH_ENABLE) begin
s_axis_rx_hash_ready_next = 1'b1;
if (desc_table_invalid[desc_table_store_hash_ptr_reg & DESC_PTR_MASK]) begin
// invalid entry; skip
desc_table_store_hash_en = 1'b1;
s_axis_rx_hash_ready_next = 1'b0;
end else if (s_axis_rx_hash_ready && s_axis_rx_hash_valid) begin
// update entry in descriptor table
desc_table_store_hash = s_axis_rx_hash;
desc_table_store_hash_type = s_axis_rx_hash_type;
desc_table_store_hash_en = 1'b1;
s_axis_rx_hash_ready_next = 1'b0;
end
end
// store RX checksum // store RX checksum
if (desc_table_active[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] && desc_table_store_csum_ptr_reg != desc_table_start_ptr_reg && RX_CHECKSUM_ENABLE) begin if (desc_table_active[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] && desc_table_store_csum_ptr_reg != desc_table_start_ptr_reg && RX_CHECKSUM_ENABLE) begin
s_axis_rx_csum_ready_next = 1'b1; s_axis_rx_csum_ready_next = 1'b1;
@ -747,7 +812,6 @@ always @* begin
if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] &&
desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg &&
desc_table_cpl_enqueue_start_ptr_reg != desc_table_dequeue_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_dequeue_start_ptr_reg &&
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_hash_ptr_reg || !RX_HASH_ENABLE) &&
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_csum_ptr_reg || !RX_CHECKSUM_ENABLE)) begin (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_csum_ptr_reg || !RX_CHECKSUM_ENABLE)) begin
if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin
// invalid entry; skip // invalid entry; skip
@ -876,7 +940,6 @@ always @(posedge clk) begin
desc_table_desc_fetched[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; desc_table_desc_fetched[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_data_written[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; desc_table_data_written[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_cpl_write_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; desc_table_cpl_write_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_queue[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue;
desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag; desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
desc_table_buf_ptr[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_buf_ptr; desc_table_buf_ptr[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_buf_ptr;
desc_table_start_ptr_reg <= desc_table_start_ptr_reg + 1; desc_table_start_ptr_reg <= desc_table_start_ptr_reg + 1;
@ -886,7 +949,13 @@ always @(posedge clk) begin
desc_table_dma_len[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_len; desc_table_dma_len[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_len;
desc_table_id[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_id; desc_table_id[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_id;
desc_table_ptp_ts[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_ptp_ts; desc_table_ptp_ts[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_ptp_ts;
desc_table_rx_done[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= 1'b1; desc_table_hash[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_hash;
desc_table_hash_type[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_hash_type;
end
if (desc_table_store_queue_en) begin
desc_table_queue[desc_table_store_queue_ptr & DESC_PTR_MASK] <= desc_table_store_queue;
desc_table_rx_done[desc_table_store_queue_ptr & DESC_PTR_MASK] <= 1'b1;
end end
if (desc_table_dequeue_start_en) begin if (desc_table_dequeue_start_en) begin
@ -910,12 +979,6 @@ always @(posedge clk) begin
desc_table_data_written[desc_table_data_written_ptr & DESC_PTR_MASK] <= 1'b1; desc_table_data_written[desc_table_data_written_ptr & DESC_PTR_MASK] <= 1'b1;
end end
if (desc_table_store_hash_en) begin
desc_table_hash[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash;
desc_table_hash_type[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash_type;
desc_table_store_hash_ptr_reg <= desc_table_store_hash_ptr_reg + 1;
end
if (desc_table_store_csum_en) begin if (desc_table_store_csum_en) begin
desc_table_csum[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] <= desc_table_store_csum; desc_table_csum[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] <= desc_table_store_csum;
desc_table_store_csum_ptr_reg <= desc_table_store_csum_ptr_reg + 1; desc_table_store_csum_ptr_reg <= desc_table_store_csum_ptr_reg + 1;
@ -980,7 +1043,6 @@ always @(posedge clk) begin
desc_table_start_ptr_reg <= 0; desc_table_start_ptr_reg <= 0;
desc_table_dequeue_start_ptr_reg <= 0; desc_table_dequeue_start_ptr_reg <= 0;
desc_table_store_hash_ptr_reg <= 0;
desc_table_store_csum_ptr_reg <= 0; desc_table_store_csum_ptr_reg <= 0;
desc_table_cpl_enqueue_start_ptr_reg <= 0; desc_table_cpl_enqueue_start_ptr_reg <= 0;
desc_table_finish_ptr_reg <= 0; desc_table_finish_ptr_reg <= 0;

45
fpga/common/tb/mqnic.py
View File

@ -153,7 +153,7 @@ MQNIC_RB_IF_REG_STRIDE = 0x14
MQNIC_RB_IF_REG_CSR_OFFSET = 0x18 MQNIC_RB_IF_REG_CSR_OFFSET = 0x18
MQNIC_RB_IF_CTRL_TYPE = 0x0000C001 MQNIC_RB_IF_CTRL_TYPE = 0x0000C001
MQNIC_RB_IF_CTRL_VER = 0x00000300 MQNIC_RB_IF_CTRL_VER = 0x00000400
MQNIC_RB_IF_CTRL_REG_FEATURES = 0x0C MQNIC_RB_IF_CTRL_REG_FEATURES = 0x0C
MQNIC_RB_IF_CTRL_REG_PORT_COUNT = 0x10 MQNIC_RB_IF_CTRL_REG_PORT_COUNT = 0x10
MQNIC_RB_IF_CTRL_REG_SCHED_COUNT = 0x14 MQNIC_RB_IF_CTRL_REG_SCHED_COUNT = 0x14
@ -161,7 +161,6 @@ MQNIC_RB_IF_CTRL_REG_MAX_TX_MTU = 0x20
MQNIC_RB_IF_CTRL_REG_MAX_RX_MTU = 0x24 MQNIC_RB_IF_CTRL_REG_MAX_RX_MTU = 0x24
MQNIC_RB_IF_CTRL_REG_TX_MTU = 0x28 MQNIC_RB_IF_CTRL_REG_TX_MTU = 0x28
MQNIC_RB_IF_CTRL_REG_RX_MTU = 0x2C MQNIC_RB_IF_CTRL_REG_RX_MTU = 0x2C
MQNIC_RB_IF_CTRL_REG_RSS_MASK = 0x30
MQNIC_IF_FEATURE_RSS = (1 << 0) MQNIC_IF_FEATURE_RSS = (1 << 0)
MQNIC_IF_FEATURE_PTP_TS = (1 << 4) MQNIC_IF_FEATURE_PTP_TS = (1 << 4)
@ -169,6 +168,15 @@ MQNIC_IF_FEATURE_TX_CSUM = (1 << 8)
MQNIC_IF_FEATURE_RX_CSUM = (1 << 9) MQNIC_IF_FEATURE_RX_CSUM = (1 << 9)
MQNIC_IF_FEATURE_RX_HASH = (1 << 10) MQNIC_IF_FEATURE_RX_HASH = (1 << 10)
MQNIC_RB_RX_QUEUE_MAP_TYPE = 0x0000C090
MQNIC_RB_RX_QUEUE_MAP_VER = 0x00000100
MQNIC_RB_RX_QUEUE_MAP_REG_PORTS = 0x0C
MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET = 0x10
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE = 0x10
MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET = 0x00
MQNIC_RB_RX_QUEUE_MAP_CH_REG_RSS_MASK = 0x04
MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK = 0x08
MQNIC_RB_EVENT_QM_TYPE = 0x0000C010 MQNIC_RB_EVENT_QM_TYPE = 0x0000C010
MQNIC_RB_EVENT_QM_VER = 0x00000100 MQNIC_RB_EVENT_QM_VER = 0x00000100
MQNIC_RB_EVENT_QM_REG_OFFSET = 0x0C MQNIC_RB_EVENT_QM_REG_OFFSET = 0x0C
@ -808,6 +816,7 @@ class Interface:
self.tx_cpl_queue_rb = None self.tx_cpl_queue_rb = None
self.rx_queue_rb = None self.rx_queue_rb = None
self.rx_cpl_queue_rb = None self.rx_cpl_queue_rb = None
self.rx_queue_map_rb = None
self.if_features = None self.if_features = None
@ -929,6 +938,13 @@ class Interface:
self.rx_cpl_queue_count = min(self.rx_cpl_queue_count, MQNIC_MAX_RX_CPL_RINGS) self.rx_cpl_queue_count = min(self.rx_cpl_queue_count, MQNIC_MAX_RX_CPL_RINGS)
self.rx_queue_map_rb = self.reg_blocks.find(MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER)
for k in range(self.port_count):
await self.set_rx_queue_map_offset(k, 0)
await self.set_rx_queue_map_rss_mask(k, 0)
await self.set_rx_queue_map_app_mask(k, 0)
self.event_queues = [] self.event_queues = []
self.tx_queues = [] self.tx_queues = []
@ -1225,8 +1241,29 @@ class Interface:
await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_TX_MTU, mtu) await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_TX_MTU, mtu)
await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_RX_MTU, mtu) await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_RX_MTU, mtu)
async def set_rss_mask(self, mask): async def get_rx_queue_map_offset(self, port):
await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_RSS_MASK, mask) return await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET)
async def set_rx_queue_map_offset(self, port, val):
await self.rx_queue_map_rb.write_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET, val)
async def get_rx_queue_map_rss_mask(self, port):
return await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_RSS_MASK)
async def set_rx_queue_map_rss_mask(self, port, val):
await self.rx_queue_map_rb.write_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_RSS_MASK, val)
async def get_rx_queue_map_app_mask(self, port):
return await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK)
async def set_rx_queue_map_app_mask(self, port, val):
await self.rx_queue_map_rb.write_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK, val)
async def recv(self): async def recv(self):
if not self.pkt_rx_queue: if not self.pkt_rx_queue:

1
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -47,6 +47,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v

64
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -242,6 +242,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -328,6 +383,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
for k in range(block.interface.tx_queue_count): for k in range(block.interface.tx_queue_count):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
@ -340,6 +396,8 @@ async def run_test_nic(dut):
tb.loopback_enable = True tb.loopback_enable = True
queues = set()
for k, p in enumerate(pkts): for k, p in enumerate(pkts):
await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks)) await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks))
@ -350,10 +408,15 @@ async def run_test_nic(dut):
# assert pkt.data == pkts[k] # assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == len(tb.driver.interfaces[0].sched_blocks)
tb.loopback_enable = False tb.loopback_enable = False
for block in tb.driver.interfaces[0].sched_blocks[1:]: for block in tb.driver.interfaces[0].sched_blocks[1:]:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
@ -404,6 +467,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"), os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"),

1
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -48,6 +48,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v

64
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -353,6 +353,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -439,6 +494,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
for k in range(block.interface.tx_queue_count): for k in range(block.interface.tx_queue_count):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
@ -451,6 +507,8 @@ async def run_test_nic(dut):
tb.loopback_enable = True tb.loopback_enable = True
queues = set()
for k, p in enumerate(pkts): for k, p in enumerate(pkts):
await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks)) await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks))
@ -461,10 +519,15 @@ async def run_test_nic(dut):
# assert pkt.data == pkts[k] # assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == len(tb.driver.interfaces[0].sched_blocks)
tb.loopback_enable = False tb.loopback_enable = False
for block in tb.driver.interfaces[0].sched_blocks[1:]: for block in tb.driver.interfaces[0].sched_blocks[1:]:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
@ -519,6 +582,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"), os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"),

1
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -48,6 +48,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v

64
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -428,6 +428,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -514,6 +569,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
for k in range(block.interface.tx_queue_count): for k in range(block.interface.tx_queue_count):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
@ -526,6 +582,8 @@ async def run_test_nic(dut):
tb.loopback_enable = True tb.loopback_enable = True
queues = set()
for k, p in enumerate(pkts): for k, p in enumerate(pkts):
await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks)) await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks))
@ -536,10 +594,15 @@ async def run_test_nic(dut):
# assert pkt.data == pkts[k] # assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == len(tb.driver.interfaces[0].sched_blocks)
tb.loopback_enable = False tb.loopback_enable = False
for block in tb.driver.interfaces[0].sched_blocks[1:]: for block in tb.driver.interfaces[0].sched_blocks[1:]:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
tb.log.info("Read statistics counters") tb.log.info("Read statistics counters")
@ -594,6 +657,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"), os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"),

1
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -48,6 +48,7 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v

64
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -428,6 +428,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -514,6 +569,7 @@ async def run_test_nic(dut):
for block in tb.driver.interfaces[0].sched_blocks: for block in tb.driver.interfaces[0].sched_blocks:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
for k in range(block.interface.tx_queue_count): for k in range(block.interface.tx_queue_count):
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
@ -526,6 +582,8 @@ async def run_test_nic(dut):
tb.loopback_enable = True tb.loopback_enable = True
queues = set()
for k, p in enumerate(pkts): for k, p in enumerate(pkts):
await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks)) await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks))
@ -536,10 +594,15 @@ async def run_test_nic(dut):
# assert pkt.data == pkts[k] # assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == len(tb.driver.interfaces[0].sched_blocks)
tb.loopback_enable = False tb.loopback_enable = False
for block in tb.driver.interfaces[0].sched_blocks[1:]: for block in tb.driver.interfaces[0].sched_blocks[1:]:
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
await Timer(1000, 'ns') await Timer(1000, 'ns')
@ -647,6 +710,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"), os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"),

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -436,6 +436,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -529,6 +584,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -508,6 +508,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -581,6 +636,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -436,6 +436,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -529,6 +584,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -508,6 +508,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -581,6 +636,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -436,6 +436,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -529,6 +584,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU250/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -508,6 +508,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -581,6 +636,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -425,6 +425,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -518,6 +573,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU280/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -497,6 +497,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -570,6 +625,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -386,6 +386,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -479,6 +534,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/AU50/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -422,6 +422,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -495,6 +550,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -492,6 +492,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -565,6 +620,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -410,6 +410,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -483,6 +538,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -419,6 +419,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -492,6 +547,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
View File

@ -21,6 +21,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -420,6 +420,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -493,6 +548,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
View File

@ -20,6 +20,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
View File

@ -20,6 +20,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -417,6 +417,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -490,6 +545,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -429,6 +429,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -502,6 +557,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -440,6 +440,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -533,6 +588,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -512,6 +512,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -585,6 +640,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -434,6 +434,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -527,6 +582,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -506,6 +506,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -579,6 +634,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -502,6 +502,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -595,6 +650,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

1
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v

56
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -646,6 +646,61 @@ async def run_test_nic(dut):
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build() assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets") tb.log.info("Multiple small packets")
count = 64 count = 64
@ -719,6 +774,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),

1
fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
View File

@ -19,6 +19,7 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v SYN_FILES += rtl/common/mqnic_ptp_perout.v

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