From 2c038c9b7bdf68a99099d49a0351765a8f5ee097 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 13 Oct 2021 16:44:05 -0700 Subject: [PATCH] Update FIFO instance --- fpga/common/rtl/mqnic_core.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 1b3ad90e8..502e146b8 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -2454,10 +2454,9 @@ generate .FRAME_FIFO(0) ) tx_ptp_ts_fifo_inst ( - .async_rst(rst | tx_rst[n*PORTS_PER_IF+m]), - // AXI input .s_clk(tx_clk[n*PORTS_PER_IF+m]), + .s_rst(tx_rst[n*PORTS_PER_IF+m]), .s_axis_tdata(axis_tx_in_ptp_ts), .s_axis_tkeep(0), .s_axis_tvalid(axis_tx_in_ptp_ts_valid), @@ -2469,6 +2468,7 @@ generate // AXI output .m_clk(clk), + .m_rst(rst), .m_axis_tdata(axis_tx_fifo_ptp_ts), .m_axis_tkeep(), .m_axis_tvalid(axis_tx_fifo_ptp_ts_valid),