FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Update FIFO instance

Browse Source
This commit is contained in:
Alex Forencich 2021-10-13 16:44:05 -07:00
parent 74a7cc08e5
commit 2c038c9b7b
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/common/rtl/mqnic_core.v
View File

@ -2454,10 +2454,9 @@ generate
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo_inst (
.async_rst(rst | tx_rst[n*PORTS_PER_IF+m]),
// AXI input
.s_clk(tx_clk[n*PORTS_PER_IF+m]),
.s_rst(tx_rst[n*PORTS_PER_IF+m]),
.s_axis_tdata(axis_tx_in_ptp_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_in_ptp_ts_valid),
@ -2469,6 +2468,7 @@ generate
// AXI output
.m_clk(clk),
.m_rst(rst),
.m_axis_tdata(axis_tx_fifo_ptp_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_fifo_ptp_ts_valid),