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Update testbenches

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This commit is contained in:
Alex Forencich 2021-11-17 17:21:35 -08:00
parent 63e7df0044
commit 2c3a5f4bda
19 changed files with 194 additions and 179 deletions
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10
tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py
View File

@ -164,7 +164,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.requester_id <= tb.dev.bus_num << 8
tb.dut.enable <= 1
@ -177,9 +178,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
ram_addr = ram_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.dma_ram.write(ram_addr-256, b'\xaa'*(len(test_data)+512))
@ -218,7 +219,8 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.requester_id <= tb.dev.bus_num << 8
tb.dut.enable <= 1

19
tb/dma_if_pcie_us/test_dma_if_pcie_us.py
View File

@ -179,7 +179,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.write_enable.value = 1
@ -192,7 +193,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
test_data = bytearray([x % 256 for x in range(length)])
tb.dma_ram.write(ram_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
tb.dma_ram.write(ram_addr, test_data)
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
@ -209,9 +210,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count
@ -236,7 +237,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.read_enable.value = 1
@ -248,9 +250,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
ram_addr = ram_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.dma_ram.write(ram_addr-256, b'\xaa'*(len(test_data)+512))
@ -290,7 +292,8 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.read_enable.value = 1

10
tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py
View File

@ -175,7 +175,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable.value = 1
@ -187,9 +188,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
ram_addr = ram_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.dma_ram.write(ram_addr-256, b'\xaa'*(len(test_data)+512))
@ -229,7 +230,8 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable.value = 1

9
tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py
View File

@ -163,7 +163,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable.value = 1
@ -176,7 +177,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
test_data = bytearray([x % 256 for x in range(length)])
tb.dma_ram.write(ram_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
tb.dma_ram.write(ram_addr, test_data)
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
@ -192,9 +193,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count

9
tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py
View File

@ -144,7 +144,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable <= 1
@ -157,7 +158,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
test_data = bytearray([x % 256 for x in range(length)])
tb.dma_ram.write(ram_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
tb.dma_ram.write(ram_addr, test_data)
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
@ -173,9 +174,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count

16
tb/pcie_axi_master/test_pcie_axi_master.py
View File

@ -154,7 +154,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -166,7 +166,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(length*4+150, 'ns')
@ -194,7 +194,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -209,7 +209,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -233,8 +233,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -247,7 +247,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Unsuccessful completion"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
await Timer(100, 'ns')
@ -273,7 +273,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted

14
tb/pcie_axi_master_rd/test_pcie_axi_master_rd.py
View File

@ -154,7 +154,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -169,7 +169,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -193,8 +193,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -206,7 +206,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(100, 'ns')
@ -229,7 +229,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Unsuccessful completion"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
await Timer(100, 'ns')
@ -255,7 +255,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted

14
tb/pcie_axi_master_wr/test_pcie_axi_master_wr.py
View File

@ -140,7 +140,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
for length in list(range(0, byte_lanes*2))+[1024]:
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
@ -150,7 +150,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(length*4+150, 'ns')
@ -175,8 +175,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.log.info("Test read")
@ -190,7 +190,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Timeout"):
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_uncor_asserted
@ -205,7 +205,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Timeout"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
await Timer(100, 'ns')
@ -229,7 +229,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Timeout"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_uncor_asserted

18
tb/pcie_axil_master/test_pcie_axil_master.py
View File

@ -156,7 +156,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -168,10 +168,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
# wait for write to complete
val = await tb.rc.mem_read(dev_bar0, 4, 10000, 'ns')
val = await dev_bar0.read(0, 4, timeout=10000, timeout_unit='ns')
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
@ -198,7 +198,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -213,7 +213,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 10000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -237,8 +237,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -251,7 +251,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Unsuccessful completion"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=10000, timeout_unit='ns')
await Timer(100, 'ns')
@ -277,7 +277,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted

22
tb/pcie_axil_master_minimal/test_pcie_axil_master_minimal.py
View File

@ -153,7 +153,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -165,10 +165,10 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
# wait for write to complete
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
@ -192,7 +192,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -207,7 +207,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -231,8 +231,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.dut.completer_id.value = int(tb.dev.functions[0].pcie_id)
@ -245,7 +245,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Unsuccessful completion"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
await Timer(100, 'ns')
@ -271,7 +271,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted
@ -287,7 +287,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(100, 'ns')
@ -313,7 +313,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted

63
tb/pcie_s10_if/test_pcie_s10_if.py
View File

@ -229,46 +229,43 @@ async def run_test_mem(dut, idle_inserter=None, backpressure_inserter=None):
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
tb.test_dev.dev_bus_num = tb.dev.bus_num
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar3 = tb.rc.tree[0][0].bar_addr[3]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
dev_bar3 = tb.rc.tree[0][0].bar_window[3]
for length in list(range(0, 8)):
for offset in list(range(8)):
tb.log.info("IO operation length: %d offset: %d", length, offset)
addr = dev_bar3+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.rc.io_write(addr, test_data, 5000)
await dev_bar3.write(offset, test_data, timeout=5000)
assert tb.test_dev.regions[3][1][offset:offset+length] == test_data
assert await tb.rc.io_read(addr, length, 5000) == test_data
assert await dev_bar3.read(offset, length, timeout=5000) == test_data
for length in list(range(0, 32))+[1024]:
for offset in list(range(8))+list(range(4096-8, 4096)):
tb.log.info("Memory operation (32-bit BAR) length: %d offset: %d", length, offset)
addr = dev_bar0+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.rc.mem_write(addr, test_data, 100)
await dev_bar0.write(offset, test_data, timeout=100)
# wait for write to complete
await tb.rc.mem_read(addr, 1, 5000)
await dev_bar0.read(offset, 1, timeout=5000)
assert tb.test_dev.regions[0][1][offset:offset+length] == test_data
assert await tb.rc.mem_read(addr, length, 5000) == test_data
assert await dev_bar0.read(offset, length, timeout=5000) == test_data
for length in list(range(0, 32))+[1024]:
for offset in list(range(8))+list(range(4096-8, 4096)):
tb.log.info("Memory operation (64-bit BAR) length: %d offset: %d", length, offset)
addr = dev_bar1+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.rc.mem_write(addr, test_data, 100)
await dev_bar1.write(offset, test_data, timeout=100)
# wait for write to complete
await tb.rc.mem_read(addr, 1, 5000)
await dev_bar1.read(offset, 1, timeout=5000)
assert tb.test_dev.regions[1][1][offset:offset+length] == test_data
assert await tb.rc.mem_read(addr, length, 5000) == test_data
assert await dev_bar1.read(offset, length, timeout=5000) == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
@ -278,8 +275,11 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
io_base, io_data = tb.rc.alloc_io_region(1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
io = tb.rc.io_pool.alloc_region(1024)
io_base = io.get_absolute_address(0)
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
@ -299,14 +299,14 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
addr = mem_base+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.test_dev.dma_mem_write(addr, test_data, 5000, 'ns')
await tb.test_dev.dma_mem_write(addr, test_data, timeout=5000, timeout_unit='ns')
# wait for write to complete
while not tb.test_dev.tx_wr_req_tlp_source.empty() or tb.test_dev.tx_wr_req_tlp_source.active:
await RisingEdge(dut.clk)
await tb.test_dev.dma_mem_read(addr, length, 5000, 'ns')
assert mem_data[offset:offset+length] == test_data
await tb.test_dev.dma_mem_read(addr, length, timeout=5000, timeout_unit='ns')
assert mem[offset:offset+length] == test_data
assert await tb.test_dev.dma_mem_read(addr, length, 5000, 'ns') == test_data
assert await tb.test_dev.dma_mem_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
for length in list(range(0, 8)):
for offset in list(range(8)):
@ -314,10 +314,10 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
addr = io_base+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.test_dev.dma_io_write(addr, test_data, 5000, 'ns')
assert io_data[offset:offset+length] == test_data
await tb.test_dev.dma_io_write(addr, test_data, timeout=5000, timeout_unit='ns')
assert io[offset:offset+length] == test_data
assert await tb.test_dev.dma_io_read(addr, length, 5000, 'ns') == test_data
assert await tb.test_dev.dma_io_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
@ -335,7 +335,8 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
await tb.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.test_dev.dev_max_payload = tb.dev.functions[0].pcie_cap.max_payload_size
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
@ -344,7 +345,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
tb.log.info("Memory operation (DMA) bad read (UR) short")
try:
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, 5000, 'ns')
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, timeout=5000, timeout_unit='ns')
except Exception:
pass
else:
@ -353,7 +354,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
tb.log.info("Memory operation (DMA) bad read (UR) first")
try:
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, 5000, 'ns')
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, timeout=5000, timeout_unit='ns')
except Exception:
pass
else:
@ -362,7 +363,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
tb.log.info("Memory operation (DMA) bad read (UR) last")
try:
await tb.test_dev.dma_mem_read(mem_base + 1024*1024 - 512, 1024, 5000, 'ns')
await tb.test_dev.dma_mem_read(mem_base + mem.size - 512, 1024, timeout=5000, timeout_unit='ns')
except Exception:
pass
else:
@ -416,17 +417,15 @@ async def run_test_fifos(dut, idle_inserter=None, backpressure_inserter=None):
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
tb.test_dev.dev_bus_num = tb.dev.bus_num
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
test_data = bytearray([x for x in range(256)])
for k in range(64):
addr = dev_bar0+k*256
await tb.rc.mem_write(addr, test_data, 100)
await dev_bar0.write(k*256, test_data, timeout=100)
for k in range(64):
addr = dev_bar0+k*256
assert await tb.rc.mem_read(addr, len(test_data), 50000) == test_data
assert await dev_bar0.read(k*256, len(test_data), timeout=50000) == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

19
tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py
View File

@ -171,7 +171,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.write_enable.value = 1
@ -184,7 +185,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
tb.axi_ram.write(axi_addr, test_data)
tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
@ -200,9 +201,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count
@ -227,7 +228,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.read_enable.value = 1
@ -239,9 +241,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
axi_addr = axi_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.axi_ram.write(axi_addr-256, b'\xaa'*(len(test_data)+512))
@ -281,7 +283,8 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.read_enable.value = 1

10
tb/pcie_us_axi_dma_rd/test_pcie_us_axi_dma_rd.py
View File

@ -166,7 +166,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable.value = 1
@ -178,9 +179,9 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
axi_addr = axi_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data
mem[pcie_addr:pcie_addr+len(test_data)] = test_data
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.axi_ram.write(axi_addr-256, b'\xaa'*(len(test_data)+512))
@ -220,7 +221,8 @@ async def run_test_read_errors(dut, idle_inserter=None, backpressure_inserter=No
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable.value = 1

9
tb/pcie_us_axi_dma_wr/test_pcie_us_axi_dma_wr.py
View File

@ -152,7 +152,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate(enable_bus_mastering=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.dut.enable.value = 1
@ -165,7 +166,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
mem[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
tb.axi_ram.write(axi_addr, test_data)
tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
@ -181,9 +182,9 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe "))
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
assert mem[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count

16
tb/pcie_us_axi_master/test_pcie_us_axi_master.py
View File

@ -155,7 +155,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
for length in list(range(0, byte_lanes*2))+[1024]:
for pcie_offset in range(byte_lanes):
@ -165,7 +165,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(length*4+150, 'ns')
@ -194,7 +194,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
for length in list(range(0, byte_lanes*2))+[1024]:
for pcie_offset in range(byte_lanes):
@ -207,7 +207,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -232,8 +232,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.log.info("Test IO write")
@ -244,7 +244,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Unsuccessful completion"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
await Timer(100, 'ns')
@ -270,7 +270,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted

14
tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py
View File

@ -152,7 +152,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
for length in list(range(0, byte_lanes*2))+[1024]:
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
@ -165,7 +165,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -190,8 +190,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.log.info("Test write")
@ -201,7 +201,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(100, 'ns')
@ -224,7 +224,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Unsuccessful completion"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
await Timer(100, 'ns')
@ -250,7 +250,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted

14
tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py
View File

@ -137,7 +137,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
for length in list(range(0, byte_lanes*2))+[1024]:
for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)):
@ -147,7 +147,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(length*4+150, 'ns')
@ -173,8 +173,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.log.info("Test read")
@ -188,7 +188,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Timeout"):
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_uncor_asserted
@ -203,7 +203,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axi_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
with assert_raises(Exception, "Timeout"):
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
await Timer(100, 'ns')
@ -227,7 +227,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Timeout"):
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_uncor_asserted

32
tb/pcie_us_axil_master/test_pcie_us_axil_master.py
View File

@ -151,8 +151,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
for length in range(0, 5):
for pcie_offset in range(4-length+1):
@ -162,7 +162,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(100, 'ns')
@ -189,8 +189,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
for length in range(0, 5):
for pcie_offset in range(4-length+1):
@ -203,7 +203,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48))
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -228,8 +228,8 @@ async def run_test_io_write(dut, idle_inserter=None, backpressure_inserter=None)
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
for length in range(1, 5):
for pcie_offset in range(4-length+1):
@ -239,7 +239,7 @@ async def run_test_io_write(dut, idle_inserter=None, backpressure_inserter=None)
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.io_write(dev_bar1+pcie_addr, test_data, 1000, 'ns')
await dev_bar1.write(pcie_addr, test_data, timeout=1000, timeout_unit='ns')
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
@ -264,8 +264,8 @@ async def run_test_io_read(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
for length in range(1, 5):
for pcie_offset in range(4-length+1):
@ -278,7 +278,7 @@ async def run_test_io_read(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
val = await tb.rc.io_read(dev_bar1+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar1.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
tb.log.debug("read data: %s", val)
@ -303,8 +303,8 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
await tb.rc.enumerate()
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
tb.log.info("Test bad write")
@ -314,7 +314,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.axil_ram.write(pcie_addr-128, b'\x55'*(len(test_data)+256))
await tb.rc.mem_write(dev_bar0+pcie_addr, test_data)
await dev_bar0.write(pcie_addr, test_data)
await Timer(100, 'ns')
@ -340,7 +340,7 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None):
tb.log.debug("%s", tb.axil_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
with assert_raises(Exception, "Unsuccessful completion"):
val = await tb.rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000, 'ns')
val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
assert tb.status_error_cor_asserted
assert not tb.status_error_uncor_asserted

55
tb/pcie_us_if/test_pcie_us_if.py
View File

@ -309,46 +309,43 @@ async def run_test_mem(dut, idle_inserter=None, backpressure_inserter=None):
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
tb.test_dev.dev_bus_num = tb.dev.bus_num
dev_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_bar1 = tb.rc.tree[0][0].bar_addr[1]
dev_bar3 = tb.rc.tree[0][0].bar_addr[3]
dev_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_bar1 = tb.rc.tree[0][0].bar_window[1]
dev_bar3 = tb.rc.tree[0][0].bar_window[3]
for length in list(range(0, 8)):
for offset in list(range(8)):
tb.log.info("IO operation length: %d offset: %d", length, offset)
addr = dev_bar3+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.rc.io_write(addr, test_data, 5000)
await dev_bar3.write(offset, test_data, timeout=5000)
assert tb.test_dev.regions[3][1][offset:offset+length] == test_data
assert await tb.rc.io_read(addr, length, 5000) == test_data
assert await dev_bar3.read(offset, length, timeout=5000) == test_data
for length in list(range(0, 32))+[1024]:
for offset in list(range(8))+list(range(4096-8, 4096)):
tb.log.info("Memory operation (32-bit BAR) length: %d offset: %d", length, offset)
addr = dev_bar0+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.rc.mem_write(addr, test_data, 100)
await dev_bar0.write(offset, test_data, timeout=100)
# wait for write to complete
await tb.rc.mem_read(addr, 1, 5000)
await dev_bar0.read(offset, 1, timeout=5000)
assert tb.test_dev.regions[0][1][offset:offset+length] == test_data
assert await tb.rc.mem_read(addr, length, 5000) == test_data
assert await dev_bar0.read(offset, length, timeout=5000) == test_data
for length in list(range(0, 32))+[1024]:
for offset in list(range(8))+list(range(4096-8, 4096)):
tb.log.info("Memory operation (64-bit BAR) length: %d offset: %d", length, offset)
addr = dev_bar1+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.rc.mem_write(addr, test_data, 100)
await dev_bar1.write(offset, test_data, timeout=100)
# wait for write to complete
await tb.rc.mem_read(addr, 1, 5000)
await dev_bar1.read(offset, 1, timeout=5000)
assert tb.test_dev.regions[1][1][offset:offset+length] == test_data
assert await tb.rc.mem_read(addr, length, 5000) == test_data
assert await dev_bar1.read(offset, length, timeout=5000) == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
@ -358,8 +355,11 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
io_base, io_data = tb.rc.alloc_io_region(1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
io = tb.rc.io_pool.alloc_region(1024)
io_base = io.get_absolute_address(0)
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
@ -379,14 +379,14 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
addr = mem_base+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.test_dev.dma_mem_write(addr, test_data, 5000, 'ns')
await tb.test_dev.dma_mem_write(addr, test_data, timeout=5000, timeout_unit='ns')
# wait for write to complete
while not tb.test_dev.tx_wr_req_tlp_source.empty() or tb.test_dev.tx_wr_req_tlp_source.active:
await RisingEdge(dut.clk)
await tb.test_dev.dma_mem_read(addr, 1, 5000, 'ns')
assert mem_data[offset:offset+length] == test_data
await tb.test_dev.dma_mem_read(addr, 1, timeout=5000, timeout_unit='ns')
assert mem[offset:offset+length] == test_data
assert await tb.test_dev.dma_mem_read(addr, length, 5000, 'ns') == test_data
assert await tb.test_dev.dma_mem_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
for length in list(range(0, 8)):
for offset in list(range(8)):
@ -394,10 +394,10 @@ async def run_test_dma(dut, idle_inserter=None, backpressure_inserter=None):
addr = io_base+offset
test_data = bytearray([x % 256 for x in range(length)])
await tb.test_dev.dma_io_write(addr, test_data, 5000, 'ns')
assert io_data[offset:offset+length] == test_data
await tb.test_dev.dma_io_write(addr, test_data, timeout=5000, timeout_unit='ns')
assert io[offset:offset+length] == test_data
assert await tb.test_dev.dma_io_read(addr, length, 5000, 'ns') == test_data
assert await tb.test_dev.dma_io_read(addr, length, timeout=5000, timeout_unit='ns') == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
@ -415,7 +415,8 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
await tb.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
mem_base, mem_data = tb.rc.alloc_region(1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
tb.test_dev.dev_max_payload = tb.dev.functions[0].pcie_cap.max_payload_size
tb.test_dev.dev_max_read_req = tb.dev.functions[0].pcie_cap.max_read_request_size
@ -424,7 +425,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
tb.log.info("Memory operation (DMA) bad read (UR) short")
try:
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, 5000, 'ns')
await tb.test_dev.dma_mem_read(mem_base - 1024, 8, timeout=5000, timeout_unit='ns')
except Exception:
pass
else:
@ -433,7 +434,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
tb.log.info("Memory operation (DMA) bad read (UR) first")
try:
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, 5000, 'ns')
await tb.test_dev.dma_mem_read(mem_base - 512, 1024, timeout=5000, timeout_unit='ns')
except Exception:
pass
else:
@ -442,7 +443,7 @@ async def run_test_dma_errors(dut, idle_inserter=None, backpressure_inserter=Non
tb.log.info("Memory operation (DMA) bad read (UR) last")
try:
await tb.test_dev.dma_mem_read(mem_base + 1024*1024 - 512, 1024, 5000, 'ns')
await tb.test_dev.dma_mem_read(mem_base + mem.size - 512, 1024, timeout=5000, timeout_unit='ns')
except Exception:
pass
else: