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https://github.com/corundum/corundum.git
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Add 25g mqnic design for Stratix 10 DX dev kit
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
549e60bdd1
commit
2c602b6368
@ -32,6 +32,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
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* BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG)
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* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)
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* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100)
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* Intel Stratix 10 DX dev kit (Intel Stratix 10 DX 2800)
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* Terasic DE10-Agilex (Intel Agilex F 014)
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* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
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* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)
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@ -27,6 +27,7 @@ This section details PCIe form-factor targets, which interface with a separate h
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BittWare 250-SoC XCZU19EG-2FFVD1760E 0x198a250e
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Intel DK-DEV-1SMX-H-A 1SM21BHU2F53E1VG 0x11720001
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Intel DK-DEV-1SMC-H-A 1SM21CHU1F53E1VG 0x11720001
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Intel DK-DEV-1SDX-P-A 1SD280PT2F55E1VG 0x1172a00d
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Terasic DE10-Agilex AGFB014R24B2E2V 0x1172b00a
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Xilinx Alveo U50 XCU50-2FSVH2104E 0x10ee9032
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Xilinx Alveo U200 XCU200-2FSGD2104E 0x10ee90c8
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@ -52,8 +53,9 @@ This section details PCIe form-factor targets, which interface with a separate h
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NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \-
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250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2400 (512M x72) \-
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XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \-
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DK-DEV-1SMX-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB
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DK-DEV-1SMC-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB
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DK-DEV-1SMX-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB
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DK-DEV-1SMC-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB
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DK-DEV-1SDX-P-A Gen 4 x16 2x QSFP28 2x 4GB DDR4 512M x72, 2x DIMM \-
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DE10-Agilex Gen 4 x16 2x QSFP-DD 4x 8GB DDR4 3200 DIMM (4x 72) \-
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Alveo U50 Gen 3 x16 1x QSFP28 \- 8 GB
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Alveo U200 Gen 3 x16 2x QSFP28 64 GB DDR4 2400 (4x 2G x72) \-
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@ -81,6 +83,7 @@ This section details PCIe form-factor targets, which interface with a separate h
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XUP-P3R Y Y Y
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DK-DEV-1SMX-H-A N N N
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DK-DEV-1SMC-H-A N N N
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DK-DEV-1SDX-P-A N N N :sup:`10`
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DE10-Agilex Y N N
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Alveo U50 N :sup:`4` Y Y
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Alveo U200 Y Y Y
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@ -99,8 +102,9 @@ This section details PCIe form-factor targets, which interface with a separate h
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- :sup:`5` Can read MAC from I2C EEPROM, but EEPROM is blank from factory
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- :sup:`6` MAC available from BMC, but accessing BMC is not yet implemented
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- :sup:`7` No on-board EEPROM
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- :sup:`8` Flash sits behind CPLD, not currently exposed via PCIe
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- :sup:`8` Flash sits behind board management controller, not currently exposed via PCIe
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- :sup:`9` Flash sits behind Zynq SoC, not currently exposed via PCIe
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- :sup:`10` Flash sits behind board management controller, inaccessible
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.. table:: Summary of the board-specific design variants and some important configuration parameters.
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@ -133,6 +137,8 @@ This section details PCIe form-factor targets, which interface with a separate h
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XUP-P3R mqnic/fpga_100g/fpga 4x1 256/8K 100G RR
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DK-DEV-1SMX-H-A mqnic/fpga_10g/fpga_1sm21b 2x1 256/1K 10G RR
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DK-DEV-1SMC-H-A mqnic/fpga_10g/fpga_1sm21c 2x1 256/1K 10G RR
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DK-DEV-1SDX-P-A mqnic/fpga_25g/fpga 2x1 256/1K 25G RR
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DK-DEV-1SDX-P-A mqnic/fpga_25g/fpga_10g 2x1 256/1K 10G RR
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DE10-Agilex mqnic/fpga_25g/fpga 2x1 256/1K 25G RR
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DE10-Agilex mqnic/fpga_25g/fpga_10g 2x1 256/1K 10G RR
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DE10-Agilex mqnic/fpga_100g/fpga 2x1 256/1K 100G RR
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@ -24,6 +24,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
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* BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG)
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* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)
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* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100)
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* Intel Stratix 10 DX dev kit (Intel Stratix 10 DX 2800)
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* Terasic DE10-Agilex (Intel Agilex F 014)
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* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
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* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)
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18
fpga/mqnic/S10DX_DK/fpga_25g/README.md
Normal file
18
fpga/mqnic/S10DX_DK/fpga_25g/README.md
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@ -0,0 +1,18 @@
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# Corundum mqnic for Stratix 10 DX
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## Introduction
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This design targets the Intel Stratix 10 DX FPGA development board.
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* FPGA: 1SD280PT2F55E1VG
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* PHY: E-Tile
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## How to build
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Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
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Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
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## How to test
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Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
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1
fpga/mqnic/S10DX_DK/fpga_25g/app
Symbolic link
1
fpga/mqnic/S10DX_DK/fpga_25g/app
Symbolic link
@ -0,0 +1 @@
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../../../app/
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188
fpga/mqnic/S10DX_DK/fpga_25g/common/quartus_pro.mk
Normal file
188
fpga/mqnic/S10DX_DK/fpga_25g/common/quartus_pro.mk
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@ -0,0 +1,188 @@
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###################################################################
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#
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# Makefile for Intel Quartus Prime Pro
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#
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# Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX)
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# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG)
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# SYN_FILES - space-separated list of source files
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# IP_FILES - space-separated list of IP files
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# IP_TCL_FILES - space-separated list of TCL files for qsys-script
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# QSF_FILES - space-separated list of settings files
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# SDC_FILES - space-separated list of timing constraint files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = "Stratix 10 DX"
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# FPGA_DEVICE = 1SD280PT2F55E1VG
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# SYN_FILES = rtl/fpga.v
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# QSF_FILES = fpga.qsf
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# SDC_FILES = fpga.sdc
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# include ../common/quartus_pro.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# output files to hang on to
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.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt
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.SECONDARY:
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# any project specific settings
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
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IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES))
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IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES)))
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IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
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IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES)))
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IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES)))
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CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
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ifdef QSF_FILES
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QSF_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(QSF_FILES))) $(filter /% ./%,$(QSF_FILES))
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else
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QSF_FILES_REL = ../$(FPGA_TOP).qsf
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endif
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SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES))
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ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and database
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).sof
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quartus: $(FPGA_TOP).qpf
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quartus $(FPGA_TOP).qpf
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tmpclean::
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-rm -rf defines.v
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-rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp
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-rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit
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-rm -rf create_project.tcl update_config.tcl update_ip_*.tcl
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clean:: tmpclean
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-rm -rf *.sof *.pof *.jdi *.jic *.map
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distclean:: clean
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-rm -rf rev
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syn: smart.log output_files/$(PROJECT).syn.rpt
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fit: smart.log output_files/$(PROJECT).fit.rpt
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asm: smart.log output_files/$(PROJECT).asm.rpt
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sta: smart.log output_files/$(PROJECT).sta.rpt
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smart: smart.log
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###################################################################
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# Executable Configuration
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###################################################################
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IP_ARGS = --run_default_mode_op
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SYN_ARGS = --read_settings_files=on --write_settings_files=off
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FIT_ARGS = --read_settings_files=on --write_settings_files=off
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ASM_ARGS = --read_settings_files=on --write_settings_files=off
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STA_ARGS =
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###################################################################
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# Target implementations
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###################################################################
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STAMP = echo done >
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define COPY_IP_RULE
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$(patsubst %, ip/%, $(notdir $(1))): $(1)
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@mkdir -p ip
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@cp -pv $(1) ip/
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endef
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$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l))))
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define TCL_IP_GEN_RULE
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$(patsubst %.tcl,%.ip,$(1)): $(1)
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cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf}
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cd ip && qsys-script --script=$(notdir $(1))
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endef
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$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l))))
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%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
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quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP)
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%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL)
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quartus_syn $(SYN_ARGS) $(FPGA_TOP)
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%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL)
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quartus_fit $(FIT_ARGS) $(FPGA_TOP)
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%.sta.rpt: sta.chg %.fit.rpt
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quartus_sta $(STA_ARGS) $(FPGA_TOP)
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%.asm.rpt: asm.chg %.sta.rpt
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quartus_asm $(ASM_ARGS) $(FPGA_TOP)
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mkdir -p rev
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EXT=sof; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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%.sof: smart.log %.asm.rpt
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smart.log: $(ASSIGNMENT_FILES)
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quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log
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###################################################################
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# Project initialization
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###################################################################
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create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
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rm -f update_config.tcl
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echo "project_new $(FPGA_TOP) -overwrite" > $@
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echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@
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echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@
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for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \
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case $${x##*.} in \
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v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\
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vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\
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qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\
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ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\
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*) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\
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esac; \
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done
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for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done
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for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL)
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echo "project_open $(FPGA_TOP)" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done
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$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl
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for x in $?; do quartus_sh -t "$$x"; done
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touch -c $(ASSIGNMENT_FILES)
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syn.chg:
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$(STAMP) syn.chg
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fit.chg:
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$(STAMP) fit.chg
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sta.chg:
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$(STAMP) sta.chg
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asm.chg:
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$(STAMP) asm.chg
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1421
fpga/mqnic/S10DX_DK/fpga_25g/fpga.qsf
Normal file
1421
fpga/mqnic/S10DX_DK/fpga_25g/fpga.qsf
Normal file
File diff suppressed because it is too large
Load Diff
125
fpga/mqnic/S10DX_DK/fpga_25g/fpga.sdc
Normal file
125
fpga/mqnic/S10DX_DK/fpga_25g/fpga.sdc
Normal file
@ -0,0 +1,125 @@
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# Timing constraints for the Intel Stratix 10 DX FPGA development board
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set_time_format -unit ns -decimal_places 3
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# Clock constraints
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create_clock -period 7.519 -name "clk_133m_ddr4_1" [ get_ports "clk_133m_ddr4_1_p" ]
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create_clock -period 7.519 -name "clk_133m_ddr4_0" [ get_ports "clk_133m_ddr4_0_p" ]
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create_clock -period 7.519 -name "clk_133m_dimm_1" [ get_ports "clk_133m_dimm_1_p" ]
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create_clock -period 7.519 -name "clk_133m_dimm_0" [ get_ports "clk_133m_dimm_0_p" ]
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create_clock -period 10.000 -name "clk2_100m_fpga_2i" [ get_ports "clk2_100m_fpga_2i_p" ]
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create_clock -period 10.000 -name "clk2_100m_fpga_2j_0" [ get_ports "clk2_100m_fpga_2j_0_p" ]
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create_clock -period 10.000 -name "clk2_100m_fpga_2j_1" [ get_ports "clk2_100m_fpga_2j_1_p" ]
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create_clock -period 10.000 -name "clk_100m_fpga_3h" [ get_ports "clk_100m_fpga_3h_p" ]
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create_clock -period 10.000 -name "clk_100m_fpga_3l_0" [ get_ports "clk_100m_fpga_3l_0_p" ]
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create_clock -period 10.000 -name "clk_100m_fpga_3l_1" [ get_ports "clk_100m_fpga_3l_1_p" ]
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create_clock -period 20.000 -name "clk2_fpga_50m" [ get_ports "clk2_fpga_50m" ]
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create_clock -period 10.000 -name "clk_100m_pcie_0" [ get_ports "clk_100m_pcie_0_p" ]
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create_clock -period 10.000 -name "clk_100m_pcie_1" [ get_ports "clk_100m_pcie_1_p" ]
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create_clock -period 10.000 -name "clk_100m_upi0_0" [ get_ports "clk_100m_upi0_0_p" ]
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create_clock -period 10.000 -name "clk_100m_upi0_1" [ get_ports "clk_100m_upi0_1_p" ]
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create_clock -period 10.000 -name "clk_100m_upi1_0" [ get_ports "clk_100m_upi1_0_p" ]
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create_clock -period 10.000 -name "clk_100m_upi1_1" [ get_ports "clk_100m_upi1_1_p" ]
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create_clock -period 10.000 -name "clk_100m_upi2_0" [ get_ports "clk_100m_upi2_0_p" ]
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create_clock -period 10.000 -name "clk_100m_upi2_1" [ get_ports "clk_100m_upi2_1_p" ]
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create_clock -period 3.2 -name "clk_312p5m_qsfp0" [ get_ports "clk_312p5m_qsfp0_p" ]
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create_clock -period 6.4 -name "clk_156p25m_qsfp0" [ get_ports "clk_156p25m_qsfp0_p" ]
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create_clock -period 3.2 -name "clk_312p5m_qsfp1" [ get_ports "clk_312p5m_qsfp1_p" ]
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create_clock -period 6.4 -name "clk_156p25m_qsfp1" [ get_ports "clk_156p25m_qsfp1_p" ]
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create_clock -period 3.2 -name "clk_312p5m_qsfp2" [ get_ports "clk_312p5m_qsfp2_p" ]
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derive_clock_uncertainty
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set_clock_groups -asynchronous -group [ get_clocks "clk_133m_ddr4_1" ]
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set_clock_groups -asynchronous -group [ get_clocks "clk_133m_ddr4_0" ]
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set_clock_groups -asynchronous -group [ get_clocks "clk_133m_dimm_1" ]
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set_clock_groups -asynchronous -group [ get_clocks "clk_133m_dimm_0" ]
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set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2i" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2j_0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2j_1" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3h" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3l_0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3l_1" ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk2_fpga_50m" ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_pcie_0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_pcie_1" ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi0_0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi0_1" ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi1_0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi1_1" ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi2_0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi2_1" ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_156p25m_qsfp0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp1" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_156p25m_qsfp1" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp2" ]
|
||||
|
||||
# JTAG constraints
|
||||
create_clock -name "altera_reserved_tck" -period 40.800 "altera_reserved_tck"
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks "altera_reserved_tck"]
|
||||
|
||||
# IO constraints
|
||||
set_false_path -from "cpu_resetn"
|
||||
set_false_path -to "user_led_g[*]"
|
||||
|
||||
set_false_path -from "pcie_rst_n"
|
||||
|
||||
|
||||
source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
|
||||
|
||||
# clocking infrastructure
|
||||
constrain_sync_reset_inst "sync_reset_100mhz_inst"
|
||||
constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
|
||||
|
||||
# PCIe clock
|
||||
set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|rx_pcs_x2_clk|ch15" ]
|
||||
|
||||
# PTP ref clock
|
||||
set_clock_groups -asynchronous -group [ get_clocks "ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div2" ]
|
||||
|
||||
# E-Tile MACs
|
||||
set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ]
|
||||
|
||||
proc constrain_etile_mac_quad { inst } {
|
||||
puts "Inserting timing constraints for MAC quad $inst"
|
||||
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout2|ch${i}" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout|ch${i}" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout2|ch${i}" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout|ch${i}" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout2|ch${i}" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout|ch${i}" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout2|ch${i}" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout|ch${i}" ]
|
||||
}
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ]
|
||||
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst"
|
||||
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst"
|
||||
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst"
|
||||
}
|
||||
}
|
||||
|
||||
constrain_etile_mac_quad "qsfp1_mac_inst"
|
||||
constrain_etile_mac_quad "qsfp2_mac_inst"
|
||||
129
fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile
Normal file
129
fpga/mqnic/S10DX_DK/fpga_25g/fpga/Makefile
Normal file
@ -0,0 +1,129 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_TOP = fpga
|
||||
FPGA_FAMILY = "Stratix 10 DX"
|
||||
FPGA_DEVICE = 1SD280PT2F55E1VG
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/eth_mac_quad_wrapper.v
|
||||
SYN_FILES += rtl/xcvr_ctrl.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_ptile.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_port_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_port_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_fifo.v
|
||||
SYN_FILES += rtl/common/rx_fifo.v
|
||||
SYN_FILES += rtl/common/tx_req_mux.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/avst2axis.v
|
||||
SYN_FILES += rtl/common/axis2avst.v
|
||||
SYN_FILES += rtl/common/mac_ts_insert.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_demux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# IP files
|
||||
IP_TCL_FILES += ip/reset_release.tcl
|
||||
IP_TCL_FILES += ip/pcie.tcl
|
||||
IP_TCL_FILES += ip/25g/mac_rsfec.tcl
|
||||
IP_TCL_FILES += ip/iopll_etile_ptp.tcl
|
||||
IP_TCL_FILES += ip/ref_div.tcl
|
||||
|
||||
# QSF files
|
||||
QSF_FILES = fpga.qsf
|
||||
|
||||
# SDC files
|
||||
SDC_FILES = fpga.sdc
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/quartus_pro.mk
|
||||
|
||||
program: fpga
|
||||
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@2"
|
||||
244
fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl
Normal file
244
fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl
Normal file
@ -0,0 +1,244 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0xC32450DD]
|
||||
set fw_id [expr 0x00000000]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x1172]
|
||||
set board_device_id [expr 0xA00D]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0x1001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
|
||||
dict set params PORT_MASK "0"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_CLOCK_PIPELINE "0"
|
||||
dict set params PTP_CLOCK_CDC_PIPELINE "0"
|
||||
dict set params PTP_PORT_CDC_PIPELINE "1"
|
||||
dict set params PTP_PEROUT_ENABLE "1"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "10"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Interface configuration
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_CPL_FIFO_DEPTH "32"
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_IMM_ENABLE "0"
|
||||
dict set params DMA_IMM_WIDTH "32"
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params SEG_COUNT "2"
|
||||
dict set params SEG_DATA_WIDTH "256"
|
||||
dict set params SEG_EMPTY_WIDTH [expr int(ceil(log([dict get $params SEG_DATA_WIDTH]/32.0)/log(2)))]
|
||||
dict set params TX_SEQ_NUM_WIDTH "6"
|
||||
dict set params PCIE_TAG_COUNT "256"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
|
||||
|
||||
# Interrupt configuration
|
||||
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "1"
|
||||
dict set params AXIS_ETH_TX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
|
||||
dict set params MAC_RSFEC "1"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "0"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie intel_pcie_ptile_ast_0
|
||||
set pcie_ip pcie
|
||||
set core core16
|
||||
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
|
||||
|
||||
puts $fp "package require qsys"
|
||||
puts $fp "load_system ip/${pcie_ip}.ip"
|
||||
|
||||
# PCIe IDs
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_class_code_hwtcl} {$pcie_class_code}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_revision_id_hwtcl} {$pcie_revision_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
|
||||
|
||||
# PCIe IP core configuration
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {fp pcie core pf bar aperture} {
|
||||
if {$aperture > 0} {
|
||||
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
|
||||
|
||||
return
|
||||
}
|
||||
puts "PF${pf} BAR${bar}: disabled"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $fp $pcie $core 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $fp $pcie $core 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
puts $fp "save_system"
|
||||
close $fp
|
||||
|
||||
# apply parameters to PCIe IP core
|
||||
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
|
||||
|
||||
# apply parameters to top-level
|
||||
dict for {name value} $params {
|
||||
set_parameter -name $name $value
|
||||
}
|
||||
129
fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile
Normal file
129
fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/Makefile
Normal file
@ -0,0 +1,129 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_TOP = fpga
|
||||
FPGA_FAMILY = "Stratix 10 DX"
|
||||
FPGA_DEVICE = 1SD280PT2F55E1VG
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/eth_mac_quad_wrapper.v
|
||||
SYN_FILES += rtl/xcvr_ctrl.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_ptile.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_port_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_port_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_fifo.v
|
||||
SYN_FILES += rtl/common/rx_fifo.v
|
||||
SYN_FILES += rtl/common/tx_req_mux.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/avst2axis.v
|
||||
SYN_FILES += rtl/common/axis2avst.v
|
||||
SYN_FILES += rtl/common/mac_ts_insert.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_demux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# IP files
|
||||
IP_TCL_FILES += ip/reset_release.tcl
|
||||
IP_TCL_FILES += ip/pcie.tcl
|
||||
IP_TCL_FILES += ip/10g/mac.tcl
|
||||
IP_TCL_FILES += ip/iopll_etile_ptp.tcl
|
||||
IP_TCL_FILES += ip/ref_div.tcl
|
||||
|
||||
# QSF files
|
||||
QSF_FILES = fpga.qsf
|
||||
|
||||
# SDC files
|
||||
SDC_FILES = fpga.sdc
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/quartus_pro.mk
|
||||
|
||||
program: fpga
|
||||
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@2"
|
||||
244
fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl
Normal file
244
fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl
Normal file
@ -0,0 +1,244 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0xC32450DD]
|
||||
set fw_id [expr 0x00000000]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x1172]
|
||||
set board_device_id [expr 0xA00D]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0x1001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
|
||||
dict set params PORT_MASK "0"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_CLOCK_PIPELINE "0"
|
||||
dict set params PTP_CLOCK_CDC_PIPELINE "0"
|
||||
dict set params PTP_PORT_CDC_PIPELINE "0"
|
||||
dict set params PTP_PEROUT_ENABLE "1"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "10"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Interface configuration
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_CPL_FIFO_DEPTH "32"
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_IMM_ENABLE "0"
|
||||
dict set params DMA_IMM_WIDTH "32"
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params SEG_COUNT "2"
|
||||
dict set params SEG_DATA_WIDTH "256"
|
||||
dict set params SEG_EMPTY_WIDTH [expr int(ceil(log([dict get $params SEG_DATA_WIDTH]/32.0)/log(2)))]
|
||||
dict set params TX_SEQ_NUM_WIDTH "6"
|
||||
dict set params PCIE_TAG_COUNT "256"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
|
||||
|
||||
# Interrupt configuration
|
||||
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "0"
|
||||
dict set params AXIS_ETH_TX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
|
||||
dict set params MAC_RSFEC "0"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "0"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie intel_pcie_ptile_ast_0
|
||||
set pcie_ip pcie
|
||||
set core core16
|
||||
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
|
||||
|
||||
puts $fp "package require qsys"
|
||||
puts $fp "load_system ip/${pcie_ip}.ip"
|
||||
|
||||
# PCIe IDs
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_class_code_hwtcl} {$pcie_class_code}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_revision_id_hwtcl} {$pcie_revision_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
|
||||
|
||||
# PCIe IP core configuration
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {fp pcie core pf bar aperture} {
|
||||
if {$aperture > 0} {
|
||||
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
|
||||
|
||||
return
|
||||
}
|
||||
puts "PF${pf} BAR${bar}: disabled"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $fp $pcie $core 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $fp $pcie $core 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
puts $fp "save_system"
|
||||
close $fp
|
||||
|
||||
# apply parameters to PCIe IP core
|
||||
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
|
||||
|
||||
# apply parameters to top-level
|
||||
dict for {name value} $params {
|
||||
set_parameter -name $name $value
|
||||
}
|
||||
291
fpga/mqnic/S10DX_DK/fpga_25g/ip/10g/mac.tcl
Normal file
291
fpga/mqnic/S10DX_DK/fpga_25g/ip/10g/mac.tcl
Normal file
@ -0,0 +1,291 @@
|
||||
package require -exact qsys 21.3
|
||||
|
||||
# create the system "mac"
|
||||
proc do_create_mac {} {
|
||||
# create the system
|
||||
create_system mac
|
||||
set_project_property DEVICE {1SD280PT2F55E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance alt_ehipc3_0 alt_ehipc3
|
||||
set_instance_parameter_value alt_ehipc3_0 {AIB_test_sl} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AN_CHAN} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AN_PAUSE_C0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AN_PAUSE_C1} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AVMM_test} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AVMM_test_sl} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {CR_MODE} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {DEV_BOARD} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {EHIP_LOCATION} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ADME} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ADME_PTP_CHANNEL} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_AN} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ANLT} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ASYNC_ADAPTERS} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ASYNC_ADAPTERS_SL} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_JTAG_AVMM} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_LT} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PPM_TODSYNC} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_PPM} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_RX_DESKEW} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_TOG} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_RSFEC} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_SYNCE} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENHANCED_PTP_ACCURACY} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENHANCED_PTP_DBG} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {EN_DYN_FEC} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {EXAMPLE_DESIGN} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {GEN_SIM} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {GEN_SYNTH} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {HDL_FORMAT} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {LINK_TIMER_KR} {504}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PHY_REFCLK} {156.250000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PHY_REFCLK_sl_0} {156.250000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PPM_VALUE_RX} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PPM_VALUE_TX} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {RECONFIG_1025} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {REQUEST_RSFEC} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {RSFEC_CLOCKING_MODE} {ehip_common_clk}
|
||||
set_instance_parameter_value alt_ehipc3_0 {RSFEC_FIRST_LANE_SEL} {first_lane0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {SL_OPT} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {STATUS_CLK_MHZ} {100.0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {USE_PTP_PLLCH} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {XCVR_test} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {active_channel} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {additional_ipg_removed} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {additional_ipg_removed_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_multi_enable} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_cnt} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data0} {ctle_lf_val_a 999 ctle_lf_val_ada_a adaptable ctle_lf_min_a 999 ctle_lf_max_a 2 ctle_hf_val_a 999 ctle_hf_val_ada_a adaptable ctle_hf_min_a 999 ctle_hf_max_a 999 rf_p2_val_a 999 rf_p2_val_ada_a fix rf_p2_min_a 999 rf_p2_max_a 999 rf_p1_val_a 999 rf_p1_val_ada_a adaptable rf_p1_min_a 999 rf_p1_max_a 999 rf_reserved0_a 999 rf_p0_val_a 999 rf_p0_val_ada_a adaptable rf_reserved1_a 999 rf_b0t_a 999 ctle_gs1_val_a 2 ctle_gs2_val_a 1 rf_b1_a 5 rf_b1_ada_a fix rf_b0_a 1 rf_b0_ada_a fix rf_a_a 999 ctle_lf_val_b 999 ctle_lf_val_ada_b adaptable ctle_lf_min_b 999 ctle_lf_max_b 2 ctle_hf_val_b 999 ctle_hf_val_ada_b adaptable ctle_hf_min_b 999 ctle_hf_max_b 999 rf_p2_val_b 999 rf_p2_val_ada_b fix rf_p2_min_b 999 rf_p2_max_b 999 rf_p1_val_b 999 rf_p1_val_ada_b adaptable rf_p1_min_b 999 rf_p1_max_b 999 rf_reserved0_b 999 rf_p0_val_b 999 rf_p0_val_ada_b adaptable rf_reserved1_b 999 rf_b0t_b 999 ctle_gs1_val_b 2 ctle_gs2_val_b 1 rf_b1_b 5 rf_b1_ada_b fix rf_b0_b 1 rf_b0_ada_b fix rf_a_b 999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data1} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data2} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data3} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data4} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data5} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data6} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data7} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_select} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cal_recipe_sel} {NRZ_10Gbps}
|
||||
set_instance_parameter_value alt_ehipc3_0 {core_variant} {3}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_PHY_REFCLK} {184.320000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_ehip_rate_gui} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_enable_custom_sl_0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_include_alternate_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_include_refclk_mux_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_number_of_channel} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs1_val_a} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs1_val_b} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs2_val_a} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs2_val_b} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_max_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_max_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_max_a} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_max_b} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_PHY_REFCLK} {250.000000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_ehip_mode_gui} {PCS_Only}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_ehip_rate_gui} {25000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_enable_custom} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_fibre_channel_mode} {disable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_include_alternate_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_modulation} {NRZ}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_number_of_channel} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {disable_internal_dr} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {dr_25g_cpri} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {duplex_mode} {enable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_mode_gui} {MAC+PCS}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_mode_gui_sl_0} {MAC+PTP+PCS}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_rate_gui} {100G}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_rate_gui_sl_0} {10G}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_aib_latency_adj_ena_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_custom_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_external_aib_clocking} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_internal_options} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_rsfec_rst_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enforce_max_frame_size_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enforce_max_frame_size_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {flow_control_gui} {No}
|
||||
set_instance_parameter_value alt_ehipc3_0 {flow_control_gui_sl_0} {No}
|
||||
set_instance_parameter_value alt_ehipc3_0 {forward_rx_pause_requests_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {forward_rx_pause_requests_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {include_alternate_ports_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {include_dlat_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {include_refclk_mux_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {link_fault_mode_gui} {Bidirectional}
|
||||
set_instance_parameter_value alt_ehipc3_0 {link_fault_mode_gui_sl_0} {OFF}
|
||||
set_instance_parameter_value alt_ehipc3_0 {number_of_channel} {3}
|
||||
set_instance_parameter_value alt_ehipc3_0 {preamble_passthrough_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {preamble_passthrough_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {preserve_unused_xcvr_channels} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rcp_load_enable} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ready_latency} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ready_latency_sl} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_a_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_a_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_a} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_ada_a} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_ada_b} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_b} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0t_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0t_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_a} {5}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_ada_a} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_ada_b} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_b} {5}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_max_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_max_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_max_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_max_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_ada_a} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_ada_b} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved0_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved0_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved1_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved1_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_bytes_to_remove} {Remove CRC bytes}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_bytes_to_remove_sl_0} {Remove CRC bytes}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_max_frame_size_gui} {1518}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_max_frame_size_gui_sl_0} {9214}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_vlan_detection_gui} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_vlan_detection_gui_sl_0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {source_address_insertion_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {source_address_insertion_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_preamble_checking_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_preamble_checking_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_sfd_checking_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_sfd_checking_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_ipg_size_gui} {12}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_ipg_size_gui_sl_0} {12}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_max_frame_size_gui} {1518}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_max_frame_size_gui_sl_0} {9214}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_vlan_detection_gui} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_vlan_detection_gui_sl_0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {txmac_saddr_gui} {73588229205}
|
||||
set_instance_parameter_value alt_ehipc3_0 {user_bti_refclk_freq_mhz} {125}
|
||||
set_instance_property alt_ehipc3_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property o_cdr_lock EXPORT_OF alt_ehipc3_0.o_cdr_lock
|
||||
set_interface_property o_tx_pll_locked EXPORT_OF alt_ehipc3_0.o_tx_pll_locked
|
||||
set_interface_property i_eth_reconfig_addr EXPORT_OF alt_ehipc3_0.i_eth_reconfig_addr
|
||||
set_interface_property i_eth_reconfig_read EXPORT_OF alt_ehipc3_0.i_eth_reconfig_read
|
||||
set_interface_property i_eth_reconfig_write EXPORT_OF alt_ehipc3_0.i_eth_reconfig_write
|
||||
set_interface_property o_eth_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_eth_reconfig_readdata
|
||||
set_interface_property o_eth_reconfig_readdata_valid EXPORT_OF alt_ehipc3_0.o_eth_reconfig_readdata_valid
|
||||
set_interface_property i_eth_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_eth_reconfig_writedata
|
||||
set_interface_property o_eth_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_eth_reconfig_waitrequest
|
||||
set_interface_property i_ptp_reconfig_address EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_address
|
||||
set_interface_property i_ptp_reconfig_read EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_read
|
||||
set_interface_property i_ptp_reconfig_write EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_write
|
||||
set_interface_property o_ptp_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_ptp_reconfig_readdata
|
||||
set_interface_property i_ptp_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_writedata
|
||||
set_interface_property o_ptp_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_ptp_reconfig_waitrequest
|
||||
set_interface_property i_clk_ref EXPORT_OF alt_ehipc3_0.i_clk_ref
|
||||
set_interface_property o_clk_pll_div64 EXPORT_OF alt_ehipc3_0.o_clk_pll_div64
|
||||
set_interface_property o_clk_pll_div66 EXPORT_OF alt_ehipc3_0.o_clk_pll_div66
|
||||
set_interface_property o_clk_rec_div64 EXPORT_OF alt_ehipc3_0.o_clk_rec_div64
|
||||
set_interface_property o_clk_rec_div66 EXPORT_OF alt_ehipc3_0.o_clk_rec_div66
|
||||
set_interface_property i_csr_rst_n EXPORT_OF alt_ehipc3_0.i_csr_rst_n
|
||||
set_interface_property serial_p EXPORT_OF alt_ehipc3_0.serial_p
|
||||
set_interface_property serial_n EXPORT_OF alt_ehipc3_0.serial_n
|
||||
set_interface_property i_reconfig_clk EXPORT_OF alt_ehipc3_0.i_reconfig_clk
|
||||
set_interface_property i_reconfig_reset EXPORT_OF alt_ehipc3_0.i_reconfig_reset
|
||||
set_interface_property i_xcvr_reconfig_address EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_address
|
||||
set_interface_property i_xcvr_reconfig_read EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_read
|
||||
set_interface_property i_xcvr_reconfig_write EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_write
|
||||
set_interface_property o_xcvr_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_xcvr_reconfig_readdata
|
||||
set_interface_property i_xcvr_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_writedata
|
||||
set_interface_property o_xcvr_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_xcvr_reconfig_waitrequest
|
||||
set_interface_property i_sl_stats_snapshot EXPORT_OF alt_ehipc3_0.i_sl_stats_snapshot
|
||||
set_interface_property o_sl_rx_hi_ber EXPORT_OF alt_ehipc3_0.o_sl_rx_hi_ber
|
||||
set_interface_property i_sl_eth_reconfig_addr EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_addr
|
||||
set_interface_property i_sl_eth_reconfig_read EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_read
|
||||
set_interface_property i_sl_eth_reconfig_write EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_write
|
||||
set_interface_property o_sl_eth_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_sl_eth_reconfig_readdata
|
||||
set_interface_property o_sl_eth_reconfig_readdata_valid EXPORT_OF alt_ehipc3_0.o_sl_eth_reconfig_readdata_valid
|
||||
set_interface_property i_sl_eth_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_writedata
|
||||
set_interface_property o_sl_eth_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_sl_eth_reconfig_waitrequest
|
||||
set_interface_property o_sl_tx_lanes_stable EXPORT_OF alt_ehipc3_0.o_sl_tx_lanes_stable
|
||||
set_interface_property o_sl_rx_pcs_ready EXPORT_OF alt_ehipc3_0.o_sl_rx_pcs_ready
|
||||
set_interface_property o_sl_ehip_ready EXPORT_OF alt_ehipc3_0.o_sl_ehip_ready
|
||||
set_interface_property o_sl_rx_block_lock EXPORT_OF alt_ehipc3_0.o_sl_rx_block_lock
|
||||
set_interface_property o_sl_local_fault_status EXPORT_OF alt_ehipc3_0.o_sl_local_fault_status
|
||||
set_interface_property o_sl_remote_fault_status EXPORT_OF alt_ehipc3_0.o_sl_remote_fault_status
|
||||
set_interface_property i_sl_clk_tx EXPORT_OF alt_ehipc3_0.i_sl_clk_tx
|
||||
set_interface_property i_sl_clk_rx EXPORT_OF alt_ehipc3_0.i_sl_clk_rx
|
||||
set_interface_property i_sl_clk_tx_tod EXPORT_OF alt_ehipc3_0.i_sl_clk_tx_tod
|
||||
set_interface_property i_sl_clk_rx_tod EXPORT_OF alt_ehipc3_0.i_sl_clk_rx_tod
|
||||
set_interface_property i_sl_csr_rst_n EXPORT_OF alt_ehipc3_0.i_sl_csr_rst_n
|
||||
set_interface_property i_sl_tx_rst_n EXPORT_OF alt_ehipc3_0.i_sl_tx_rst_n
|
||||
set_interface_property i_sl_rx_rst_n EXPORT_OF alt_ehipc3_0.i_sl_rx_rst_n
|
||||
set_interface_property sl_xcvr_fifo_ports EXPORT_OF alt_ehipc3_0.sl_xcvr_fifo_ports
|
||||
set_interface_property sl_nonpcs_ports EXPORT_OF alt_ehipc3_0.sl_nonpcs_ports
|
||||
set_interface_property sl_pfc_ports EXPORT_OF alt_ehipc3_0.sl_pfc_ports
|
||||
set_interface_property sl_pause_ports EXPORT_OF alt_ehipc3_0.sl_pause_ports
|
||||
set_interface_property ptp_tod_ports_1p5ns EXPORT_OF alt_ehipc3_0.ptp_tod_ports_1p5ns
|
||||
set_interface_property sl_ptp_ports EXPORT_OF alt_ehipc3_0.sl_ptp_ports
|
||||
set_interface_property sl_ptp_ports_1p5ns EXPORT_OF alt_ehipc3_0.sl_ptp_ports_1p5ns
|
||||
set_interface_property sl_ptp_1step_ports EXPORT_OF alt_ehipc3_0.sl_ptp_1step_ports
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="alt_ehipc3_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {mac.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {mac}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system mac
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_mac
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
297
fpga/mqnic/S10DX_DK/fpga_25g/ip/25g/mac_rsfec.tcl
Normal file
297
fpga/mqnic/S10DX_DK/fpga_25g/ip/25g/mac_rsfec.tcl
Normal file
@ -0,0 +1,297 @@
|
||||
package require -exact qsys 21.3
|
||||
|
||||
# create the system "mac_rsfec"
|
||||
proc do_create_mac_rsfec {} {
|
||||
# create the system
|
||||
create_system mac_rsfec
|
||||
set_project_property DEVICE {1SD280PT2F55E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance alt_ehipc3_0 alt_ehipc3
|
||||
set_instance_parameter_value alt_ehipc3_0 {AIB_test_sl} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AN_CHAN} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AN_PAUSE_C0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AN_PAUSE_C1} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AVMM_test} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {AVMM_test_sl} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {CR_MODE} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {DEV_BOARD} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {EHIP_LOCATION} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ADME} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ADME_PTP_CHANNEL} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_AN} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ANLT} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ASYNC_ADAPTERS} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ASYNC_ADAPTERS_SL} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_JTAG_AVMM} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_LT} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PPM_TODSYNC} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_PPM} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_RX_DESKEW} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_TOG} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_RSFEC} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENABLE_SYNCE} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENHANCED_PTP_ACCURACY} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ENHANCED_PTP_DBG} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {EN_DYN_FEC} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {EXAMPLE_DESIGN} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {GEN_SIM} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {GEN_SYNTH} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {HDL_FORMAT} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {LINK_TIMER_KR} {504}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PHY_REFCLK} {156.250000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PHY_REFCLK_sl_0} {156.250000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PPM_VALUE_RX} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {PPM_VALUE_TX} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {RECONFIG_1025} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {REQUEST_RSFEC} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {RSFEC_CLOCKING_MODE} {ehip_common_clk}
|
||||
set_instance_parameter_value alt_ehipc3_0 {RSFEC_FIRST_LANE_SEL} {first_lane0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {SL_OPT} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {STATUS_CLK_MHZ} {100.0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {USE_PTP_PLLCH} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {XCVR_test} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {active_channel} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {additional_ipg_removed} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {additional_ipg_removed_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_multi_enable} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_cnt} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data0} {ctle_lf_val_a 999 ctle_lf_val_ada_a adaptable ctle_lf_min_a 999 ctle_lf_max_a 2 ctle_hf_val_a 999 ctle_hf_val_ada_a adaptable ctle_hf_min_a 999 ctle_hf_max_a 999 rf_p2_val_a 999 rf_p2_val_ada_a fix rf_p2_min_a 999 rf_p2_max_a 999 rf_p1_val_a 999 rf_p1_val_ada_a adaptable rf_p1_min_a 999 rf_p1_max_a 999 rf_reserved0_a 999 rf_p0_val_a 999 rf_p0_val_ada_a adaptable rf_reserved1_a 999 rf_b0t_a 999 ctle_gs1_val_a 2 ctle_gs2_val_a 1 rf_b1_a 5 rf_b1_ada_a fix rf_b0_a 1 rf_b0_ada_a fix rf_a_a 999 ctle_lf_val_b 999 ctle_lf_val_ada_b adaptable ctle_lf_min_b 999 ctle_lf_max_b 2 ctle_hf_val_b 999 ctle_hf_val_ada_b adaptable ctle_hf_min_b 999 ctle_hf_max_b 999 rf_p2_val_b 999 rf_p2_val_ada_b fix rf_p2_min_b 999 rf_p2_max_b 999 rf_p1_val_b 999 rf_p1_val_ada_b adaptable rf_p1_min_b 999 rf_p1_max_b 999 rf_reserved0_b 999 rf_p0_val_b 999 rf_p0_val_ada_b adaptable rf_reserved1_b 999 rf_b0t_b 999 ctle_gs1_val_b 2 ctle_gs2_val_b 1 rf_b1_b 5 rf_b1_ada_b fix rf_b0_b 1 rf_b0_ada_b fix rf_a_b 999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data1} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data2} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data3} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data4} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data5} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data6} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data7} {}
|
||||
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_select} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cal_recipe_sel} {NRZ_10Gbps}
|
||||
set_instance_parameter_value alt_ehipc3_0 {core_variant} {3}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_PHY_REFCLK} {184.320000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_ehip_rate_gui} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_enable_custom_sl_0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_include_alternate_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_include_refclk_mux_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {cpri_number_of_channel} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs1_val_a} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs1_val_b} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs2_val_a} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_gs2_val_b} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_max_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_max_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_max_a} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_max_b} {2}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_PHY_REFCLK} {250.000000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_ehip_mode_gui} {PCS_Only}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_ehip_rate_gui} {25000}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_enable_custom} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_fibre_channel_mode} {disable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_include_alternate_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_modulation} {NRZ}
|
||||
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_number_of_channel} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {disable_internal_dr} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {dr_25g_cpri} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {duplex_mode} {enable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_mode_gui} {MAC+PCS}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_mode_gui_sl_0} {MAC+PTP+PCS+RSFEC}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_rate_gui} {100G}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ehip_rate_gui_sl_0} {25G}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_aib_latency_adj_ena_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_custom_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_external_aib_clocking} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_internal_options} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enable_rsfec_rst_ports} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enforce_max_frame_size_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {enforce_max_frame_size_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {flow_control_gui} {No}
|
||||
set_instance_parameter_value alt_ehipc3_0 {flow_control_gui_sl_0} {No}
|
||||
set_instance_parameter_value alt_ehipc3_0 {forward_rx_pause_requests_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {forward_rx_pause_requests_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {include_alternate_ports_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {include_dlat_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {include_refclk_mux_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {link_fault_mode_gui} {Bidirectional}
|
||||
set_instance_parameter_value alt_ehipc3_0 {link_fault_mode_gui_sl_0} {OFF}
|
||||
set_instance_parameter_value alt_ehipc3_0 {number_of_channel} {3}
|
||||
set_instance_parameter_value alt_ehipc3_0 {preamble_passthrough_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {preamble_passthrough_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {preserve_unused_xcvr_channels} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rcp_load_enable} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ready_latency} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {ready_latency_sl} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_a_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_a_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_a} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_ada_a} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_ada_b} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0_b} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0t_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b0t_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_a} {5}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_ada_a} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_ada_b} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_b1_b} {5}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_max_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_max_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_ada_a} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_ada_b} {adaptable}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_max_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_max_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_min_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_min_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_ada_a} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_ada_b} {fix}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved0_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved0_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved1_a} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rf_reserved1_b} {999}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_bytes_to_remove} {Remove CRC bytes}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_bytes_to_remove_sl_0} {Remove CRC bytes}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_max_frame_size_gui} {1518}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_max_frame_size_gui_sl_0} {9214}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_vlan_detection_gui} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {rx_vlan_detection_gui_sl_0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {source_address_insertion_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {source_address_insertion_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_preamble_checking_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_preamble_checking_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_sfd_checking_gui} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {strict_sfd_checking_gui_sl_0} {0}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_ipg_size_gui} {12}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_ipg_size_gui_sl_0} {12}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_max_frame_size_gui} {1518}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_max_frame_size_gui_sl_0} {9214}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_vlan_detection_gui} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {tx_vlan_detection_gui_sl_0} {1}
|
||||
set_instance_parameter_value alt_ehipc3_0 {txmac_saddr_gui} {73588229205}
|
||||
set_instance_parameter_value alt_ehipc3_0 {user_bti_refclk_freq_mhz} {125}
|
||||
set_instance_property alt_ehipc3_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property o_cdr_lock EXPORT_OF alt_ehipc3_0.o_cdr_lock
|
||||
set_interface_property o_tx_pll_locked EXPORT_OF alt_ehipc3_0.o_tx_pll_locked
|
||||
set_interface_property i_eth_reconfig_addr EXPORT_OF alt_ehipc3_0.i_eth_reconfig_addr
|
||||
set_interface_property i_eth_reconfig_read EXPORT_OF alt_ehipc3_0.i_eth_reconfig_read
|
||||
set_interface_property i_eth_reconfig_write EXPORT_OF alt_ehipc3_0.i_eth_reconfig_write
|
||||
set_interface_property o_eth_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_eth_reconfig_readdata
|
||||
set_interface_property o_eth_reconfig_readdata_valid EXPORT_OF alt_ehipc3_0.o_eth_reconfig_readdata_valid
|
||||
set_interface_property i_eth_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_eth_reconfig_writedata
|
||||
set_interface_property o_eth_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_eth_reconfig_waitrequest
|
||||
set_interface_property i_rsfec_reconfig_addr EXPORT_OF alt_ehipc3_0.i_rsfec_reconfig_addr
|
||||
set_interface_property i_rsfec_reconfig_read EXPORT_OF alt_ehipc3_0.i_rsfec_reconfig_read
|
||||
set_interface_property i_rsfec_reconfig_write EXPORT_OF alt_ehipc3_0.i_rsfec_reconfig_write
|
||||
set_interface_property o_rsfec_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_rsfec_reconfig_readdata
|
||||
set_interface_property i_rsfec_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_rsfec_reconfig_writedata
|
||||
set_interface_property o_rsfec_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_rsfec_reconfig_waitrequest
|
||||
set_interface_property i_ptp_reconfig_address EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_address
|
||||
set_interface_property i_ptp_reconfig_read EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_read
|
||||
set_interface_property i_ptp_reconfig_write EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_write
|
||||
set_interface_property o_ptp_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_ptp_reconfig_readdata
|
||||
set_interface_property i_ptp_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_writedata
|
||||
set_interface_property o_ptp_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_ptp_reconfig_waitrequest
|
||||
set_interface_property i_clk_ref EXPORT_OF alt_ehipc3_0.i_clk_ref
|
||||
set_interface_property o_clk_pll_div64 EXPORT_OF alt_ehipc3_0.o_clk_pll_div64
|
||||
set_interface_property o_clk_pll_div66 EXPORT_OF alt_ehipc3_0.o_clk_pll_div66
|
||||
set_interface_property o_clk_rec_div64 EXPORT_OF alt_ehipc3_0.o_clk_rec_div64
|
||||
set_interface_property o_clk_rec_div66 EXPORT_OF alt_ehipc3_0.o_clk_rec_div66
|
||||
set_interface_property i_csr_rst_n EXPORT_OF alt_ehipc3_0.i_csr_rst_n
|
||||
set_interface_property serial_p EXPORT_OF alt_ehipc3_0.serial_p
|
||||
set_interface_property serial_n EXPORT_OF alt_ehipc3_0.serial_n
|
||||
set_interface_property i_reconfig_clk EXPORT_OF alt_ehipc3_0.i_reconfig_clk
|
||||
set_interface_property i_reconfig_reset EXPORT_OF alt_ehipc3_0.i_reconfig_reset
|
||||
set_interface_property i_xcvr_reconfig_address EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_address
|
||||
set_interface_property i_xcvr_reconfig_read EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_read
|
||||
set_interface_property i_xcvr_reconfig_write EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_write
|
||||
set_interface_property o_xcvr_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_xcvr_reconfig_readdata
|
||||
set_interface_property i_xcvr_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_writedata
|
||||
set_interface_property o_xcvr_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_xcvr_reconfig_waitrequest
|
||||
set_interface_property i_sl_stats_snapshot EXPORT_OF alt_ehipc3_0.i_sl_stats_snapshot
|
||||
set_interface_property o_sl_rx_hi_ber EXPORT_OF alt_ehipc3_0.o_sl_rx_hi_ber
|
||||
set_interface_property i_sl_eth_reconfig_addr EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_addr
|
||||
set_interface_property i_sl_eth_reconfig_read EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_read
|
||||
set_interface_property i_sl_eth_reconfig_write EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_write
|
||||
set_interface_property o_sl_eth_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_sl_eth_reconfig_readdata
|
||||
set_interface_property o_sl_eth_reconfig_readdata_valid EXPORT_OF alt_ehipc3_0.o_sl_eth_reconfig_readdata_valid
|
||||
set_interface_property i_sl_eth_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_sl_eth_reconfig_writedata
|
||||
set_interface_property o_sl_eth_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_sl_eth_reconfig_waitrequest
|
||||
set_interface_property o_sl_tx_lanes_stable EXPORT_OF alt_ehipc3_0.o_sl_tx_lanes_stable
|
||||
set_interface_property o_sl_rx_pcs_ready EXPORT_OF alt_ehipc3_0.o_sl_rx_pcs_ready
|
||||
set_interface_property o_sl_ehip_ready EXPORT_OF alt_ehipc3_0.o_sl_ehip_ready
|
||||
set_interface_property o_sl_rx_block_lock EXPORT_OF alt_ehipc3_0.o_sl_rx_block_lock
|
||||
set_interface_property o_sl_local_fault_status EXPORT_OF alt_ehipc3_0.o_sl_local_fault_status
|
||||
set_interface_property o_sl_remote_fault_status EXPORT_OF alt_ehipc3_0.o_sl_remote_fault_status
|
||||
set_interface_property i_sl_clk_tx EXPORT_OF alt_ehipc3_0.i_sl_clk_tx
|
||||
set_interface_property i_sl_clk_rx EXPORT_OF alt_ehipc3_0.i_sl_clk_rx
|
||||
set_interface_property i_sl_clk_tx_tod EXPORT_OF alt_ehipc3_0.i_sl_clk_tx_tod
|
||||
set_interface_property i_sl_clk_rx_tod EXPORT_OF alt_ehipc3_0.i_sl_clk_rx_tod
|
||||
set_interface_property i_sl_csr_rst_n EXPORT_OF alt_ehipc3_0.i_sl_csr_rst_n
|
||||
set_interface_property i_sl_tx_rst_n EXPORT_OF alt_ehipc3_0.i_sl_tx_rst_n
|
||||
set_interface_property i_sl_rx_rst_n EXPORT_OF alt_ehipc3_0.i_sl_rx_rst_n
|
||||
set_interface_property sl_xcvr_fifo_ports EXPORT_OF alt_ehipc3_0.sl_xcvr_fifo_ports
|
||||
set_interface_property sl_nonpcs_ports EXPORT_OF alt_ehipc3_0.sl_nonpcs_ports
|
||||
set_interface_property sl_pfc_ports EXPORT_OF alt_ehipc3_0.sl_pfc_ports
|
||||
set_interface_property sl_pause_ports EXPORT_OF alt_ehipc3_0.sl_pause_ports
|
||||
set_interface_property ptp_tod_ports_1p5ns EXPORT_OF alt_ehipc3_0.ptp_tod_ports_1p5ns
|
||||
set_interface_property sl_ptp_ports EXPORT_OF alt_ehipc3_0.sl_ptp_ports
|
||||
set_interface_property sl_ptp_ports_1p5ns EXPORT_OF alt_ehipc3_0.sl_ptp_ports_1p5ns
|
||||
set_interface_property sl_ptp_1step_ports EXPORT_OF alt_ehipc3_0.sl_ptp_1step_ports
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="alt_ehipc3_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {mac_rsfec.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {mac_rsfec}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system mac_rsfec
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_mac_rsfec
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
304
fpga/mqnic/S10DX_DK/fpga_25g/ip/iopll_etile_ptp.tcl
Normal file
304
fpga/mqnic/S10DX_DK/fpga_25g/ip/iopll_etile_ptp.tcl
Normal file
@ -0,0 +1,304 @@
|
||||
package require -exact qsys 21.3
|
||||
|
||||
# create the system "iopll_etile_ptp"
|
||||
proc do_create_iopll_etile_ptp {} {
|
||||
# create the system
|
||||
create_system iopll_etile_ptp
|
||||
set_project_property DEVICE {1SD280PT2F55E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance iopll_0 altera_iopll
|
||||
set_instance_parameter_value iopll_0 {gui_active_clk} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src2} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src3} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src4} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src5} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src6} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src7} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src8} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_cal_code_hex_file} {iossm.hex}
|
||||
set_instance_parameter_value iopll_0 {gui_cal_converge} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter10} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter11} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter12} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter13} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter14} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter15} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter16} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter17} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter2} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter3} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter4} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter5} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter6} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter7} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter8} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_counter9} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_clk_bad} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_global} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string10} {outclk10}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string11} {outclk11}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string12} {outclk12}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string13} {outclk13}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string14} {outclk14}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string15} {outclk15}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string16} {outclk16}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string17} {outclk17}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string3} {outclk3}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string4} {outclk4}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string5} {outclk5}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string6} {outclk6}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string7} {outclk7}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string8} {outclk8}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_name_string9} {outclk9}
|
||||
set_instance_parameter_value iopll_0 {gui_clock_to_compensate} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_debug_mode} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c10} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c11} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c12} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c13} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c14} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c15} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c16} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c17} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c3} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c4} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c5} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c6} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c7} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c8} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_c9} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_divide_factor_n} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0}
|
||||
set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive}
|
||||
set_instance_parameter_value iopll_0 {gui_dps_num} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle10} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle11} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle12} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle13} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle14} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle15} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle16} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle17} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle2} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle3} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle4} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle5} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle6} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle7} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle8} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_duty_cycle9} {50.0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_adv_params} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_iossm_reconf} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_lvds_ports} {Disabled}
|
||||
set_instance_parameter_value iopll_0 {gui_en_periphery_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_en_reconf} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_cascade_in} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_cascade_out} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_mif_dps} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_output_counter_cascading} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_permit_cal} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_enable_upstream_out_clk} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_existing_mif_file_path} {~/pll.mif}
|
||||
set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0}
|
||||
set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0}
|
||||
set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock}
|
||||
set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0}
|
||||
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1667.0}
|
||||
set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0}
|
||||
set_instance_parameter_value iopll_0 {gui_fractional_cout} {32}
|
||||
set_instance_parameter_value iopll_0 {gui_include_iossm} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_location_type} {I/O Bank}
|
||||
set_instance_parameter_value iopll_0 {gui_lock_setting} {Low Lock Time}
|
||||
set_instance_parameter_value iopll_0 {gui_mif_config_name} {unnamed}
|
||||
set_instance_parameter_value iopll_0 {gui_mif_gen_options} {Generate New MIF File}
|
||||
set_instance_parameter_value iopll_0 {gui_multiply_factor} {6}
|
||||
set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif}
|
||||
set_instance_parameter_value iopll_0 {gui_number_of_clocks} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_operation_mode} {direct}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {114.285714}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency12} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency13} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency14} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency15} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency16} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency17} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency3} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency4} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency5} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency6} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {8750.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps12} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps13} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps14} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps15} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps16} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps17} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps3} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps4} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps5} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps6} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps7} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps8} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps9} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift10} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift11} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift12} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift13} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift14} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift15} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift16} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift17} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift2} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift3} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift4} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift5} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift6} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift7} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift8} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift9} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg0} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg1} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg10} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg11} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg12} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg13} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg14} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg15} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg16} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg17} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg2} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg3} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg4} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg5} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg6} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg7} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg8} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phase_shift_deg9} {0.0}
|
||||
set_instance_parameter_value iopll_0 {gui_phout_division} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Low}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_cal_done} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_cascading_mode} {adjpllin}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_freqcal_req_flag} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_band18}
|
||||
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_band18}
|
||||
set_instance_parameter_value iopll_0 {gui_prot_mode} {UNUSED}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units0} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units1} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units10} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units11} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units12} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units13} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units14} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units15} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units16} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units17} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units2} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units3} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units4} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units5} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units6} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units7} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units8} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_ps_units9} {ps}
|
||||
set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_refclk_might_change} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_refclk_switch} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {100.0}
|
||||
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {10000.0}
|
||||
set_instance_parameter_value iopll_0 {gui_simulation_type} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_skip_sdc_generation} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_switchover_delay} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_switchover_mode} {Automatic Switchover}
|
||||
set_instance_parameter_value iopll_0 {gui_use_NDFB_modes} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_use_coreclk} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_use_locked} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_use_logical} {0}
|
||||
set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1}
|
||||
set_instance_parameter_value iopll_0 {gui_vco_frequency} {600.0}
|
||||
set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0}
|
||||
set_instance_parameter_value iopll_0 {system_info_device_iobank_rev} {}
|
||||
set_instance_property iopll_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property reset EXPORT_OF iopll_0.reset
|
||||
set_interface_property refclk EXPORT_OF iopll_0.refclk
|
||||
set_interface_property locked EXPORT_OF iopll_0.locked
|
||||
set_interface_property outclk0 EXPORT_OF iopll_0.outclk0
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="iopll_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {iopll_etile_ptp.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {iopll_etile_ptp}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system iopll_etile_ptp
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_iopll_etile_ptp
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
2294
fpga/mqnic/S10DX_DK/fpga_25g/ip/pcie.tcl
Normal file
2294
fpga/mqnic/S10DX_DK/fpga_25g/ip/pcie.tcl
Normal file
File diff suppressed because it is too large
Load Diff
61
fpga/mqnic/S10DX_DK/fpga_25g/ip/ref_div.tcl
Normal file
61
fpga/mqnic/S10DX_DK/fpga_25g/ip/ref_div.tcl
Normal file
@ -0,0 +1,61 @@
|
||||
package require -exact qsys 21.3
|
||||
|
||||
# create the system "ref_div"
|
||||
proc do_create_ref_div {} {
|
||||
# create the system
|
||||
create_system ref_div
|
||||
set_project_property DEVICE {1SD280PT2F55E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance stratix10_clkctrl_0 stratix10_clkctrl
|
||||
set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER} {1}
|
||||
set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER_OUTPUTS} {3}
|
||||
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE} {0}
|
||||
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_REGISTER_TYPE} {1}
|
||||
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_TYPE} {2}
|
||||
set_instance_parameter_value stratix10_clkctrl_0 {GLITCH_FREE_SWITCHOVER} {0}
|
||||
set_instance_parameter_value stratix10_clkctrl_0 {NUM_CLOCKS} {1}
|
||||
set_instance_property stratix10_clkctrl_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property inclk EXPORT_OF stratix10_clkctrl_0.inclk
|
||||
set_interface_property clock_div1x EXPORT_OF stratix10_clkctrl_0.clock_div1x
|
||||
set_interface_property clock_div2x EXPORT_OF stratix10_clkctrl_0.clock_div2x
|
||||
set_interface_property clock_div4x EXPORT_OF stratix10_clkctrl_0.clock_div4x
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="stratix10_clkctrl_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {ref_div.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {ref_div}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system ref_div
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_ref_div
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
52
fpga/mqnic/S10DX_DK/fpga_25g/ip/reset_release.tcl
Normal file
52
fpga/mqnic/S10DX_DK/fpga_25g/ip/reset_release.tcl
Normal file
@ -0,0 +1,52 @@
|
||||
package require -exact qsys 21.3
|
||||
|
||||
# create the system "reset_release"
|
||||
proc do_create_reset_release {} {
|
||||
# create the system
|
||||
create_system reset_release
|
||||
set_project_property DEVICE {1SD280PT2F55E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate
|
||||
set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface}
|
||||
set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="s10_user_rst_clkgate_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {reset_release.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {reset_release}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system reset_release
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_reset_release
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
1
fpga/mqnic/S10DX_DK/fpga_25g/lib
Symbolic link
1
fpga/mqnic/S10DX_DK/fpga_25g/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
1
fpga/mqnic/S10DX_DK/fpga_25g/rtl/common
Symbolic link
1
fpga/mqnic/S10DX_DK/fpga_25g/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
775
fpga/mqnic/S10DX_DK/fpga_25g/rtl/eth_mac_quad_wrapper.v
Normal file
775
fpga/mqnic/S10DX_DK/fpga_25g/rtl/eth_mac_quad_wrapper.v
Normal file
@ -0,0 +1,775 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2022 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Quad Ethernet MAC wrapper
|
||||
*/
|
||||
module eth_mac_quad_wrapper #
|
||||
(
|
||||
parameter PTP_TS_WIDTH = 96,
|
||||
parameter PTP_TAG_WIDTH = 8,
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter KEEP_WIDTH = DATA_WIDTH/8,
|
||||
parameter TX_USER_WIDTH = PTP_TAG_WIDTH+1,
|
||||
parameter RX_USER_WIDTH = PTP_TS_WIDTH+1,
|
||||
parameter MAC_RSFEC = 0
|
||||
)
|
||||
(
|
||||
input wire ctrl_clk,
|
||||
input wire ctrl_rst,
|
||||
|
||||
output wire [3:0] tx_serial_data_p,
|
||||
output wire [3:0] tx_serial_data_n,
|
||||
input wire [3:0] rx_serial_data_p,
|
||||
input wire [3:0] rx_serial_data_n,
|
||||
input wire ref_clk,
|
||||
input wire ptp_sample_clk,
|
||||
|
||||
output wire mac_1_tx_clk,
|
||||
output wire mac_1_tx_rst,
|
||||
|
||||
output wire mac_1_tx_ptp_clk,
|
||||
output wire mac_1_tx_ptp_rst,
|
||||
input wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_time,
|
||||
|
||||
output wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_ts,
|
||||
output wire [PTP_TAG_WIDTH-1:0] mac_1_tx_ptp_ts_tag,
|
||||
output wire mac_1_tx_ptp_ts_valid,
|
||||
|
||||
input wire [DATA_WIDTH-1:0] mac_1_tx_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] mac_1_tx_axis_tkeep,
|
||||
input wire mac_1_tx_axis_tvalid,
|
||||
output wire mac_1_tx_axis_tready,
|
||||
input wire mac_1_tx_axis_tlast,
|
||||
input wire [TX_USER_WIDTH-1:0] mac_1_tx_axis_tuser,
|
||||
|
||||
output wire mac_1_rx_clk,
|
||||
output wire mac_1_rx_rst,
|
||||
|
||||
output wire mac_1_rx_ptp_clk,
|
||||
output wire mac_1_rx_ptp_rst,
|
||||
input wire [PTP_TS_WIDTH-1:0] mac_1_rx_ptp_time,
|
||||
|
||||
output wire [DATA_WIDTH-1:0] mac_1_rx_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] mac_1_rx_axis_tkeep,
|
||||
output wire mac_1_rx_axis_tvalid,
|
||||
output wire mac_1_rx_axis_tlast,
|
||||
output wire [RX_USER_WIDTH-1:0] mac_1_rx_axis_tuser,
|
||||
|
||||
output wire mac_1_rx_status,
|
||||
|
||||
output wire mac_2_tx_clk,
|
||||
output wire mac_2_tx_rst,
|
||||
|
||||
output wire mac_2_tx_ptp_clk,
|
||||
output wire mac_2_tx_ptp_rst,
|
||||
input wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_time,
|
||||
|
||||
output wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_ts,
|
||||
output wire [PTP_TAG_WIDTH-1:0] mac_2_tx_ptp_ts_tag,
|
||||
output wire mac_2_tx_ptp_ts_valid,
|
||||
|
||||
input wire [DATA_WIDTH-1:0] mac_2_tx_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] mac_2_tx_axis_tkeep,
|
||||
input wire mac_2_tx_axis_tvalid,
|
||||
output wire mac_2_tx_axis_tready,
|
||||
input wire mac_2_tx_axis_tlast,
|
||||
input wire [TX_USER_WIDTH-1:0] mac_2_tx_axis_tuser,
|
||||
|
||||
output wire mac_2_rx_clk,
|
||||
output wire mac_2_rx_rst,
|
||||
|
||||
output wire mac_2_rx_ptp_clk,
|
||||
output wire mac_2_rx_ptp_rst,
|
||||
input wire [PTP_TS_WIDTH-1:0] mac_2_rx_ptp_time,
|
||||
|
||||
output wire [DATA_WIDTH-1:0] mac_2_rx_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] mac_2_rx_axis_tkeep,
|
||||
output wire mac_2_rx_axis_tvalid,
|
||||
output wire mac_2_rx_axis_tlast,
|
||||
output wire [RX_USER_WIDTH-1:0] mac_2_rx_axis_tuser,
|
||||
|
||||
output wire mac_2_rx_status,
|
||||
|
||||
output wire mac_3_tx_clk,
|
||||
output wire mac_3_tx_rst,
|
||||
|
||||
output wire mac_3_tx_ptp_clk,
|
||||
output wire mac_3_tx_ptp_rst,
|
||||
input wire [PTP_TS_WIDTH-1:0] mac_3_tx_ptp_time,
|
||||
|
||||
output wire [PTP_TS_WIDTH-1:0] mac_3_tx_ptp_ts,
|
||||
output wire [PTP_TAG_WIDTH-1:0] mac_3_tx_ptp_ts_tag,
|
||||
output wire mac_3_tx_ptp_ts_valid,
|
||||
|
||||
input wire [DATA_WIDTH-1:0] mac_3_tx_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] mac_3_tx_axis_tkeep,
|
||||
input wire mac_3_tx_axis_tvalid,
|
||||
output wire mac_3_tx_axis_tready,
|
||||
input wire mac_3_tx_axis_tlast,
|
||||
input wire [TX_USER_WIDTH-1:0] mac_3_tx_axis_tuser,
|
||||
|
||||
output wire mac_3_rx_clk,
|
||||
output wire mac_3_rx_rst,
|
||||
|
||||
output wire mac_3_rx_ptp_clk,
|
||||
output wire mac_3_rx_ptp_rst,
|
||||
input wire [PTP_TS_WIDTH-1:0] mac_3_rx_ptp_time,
|
||||
|
||||
output wire [DATA_WIDTH-1:0] mac_3_rx_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] mac_3_rx_axis_tkeep,
|
||||
output wire mac_3_rx_axis_tvalid,
|
||||
output wire mac_3_rx_axis_tlast,
|
||||
output wire [RX_USER_WIDTH-1:0] mac_3_rx_axis_tuser,
|
||||
|
||||
output wire mac_3_rx_status,
|
||||
|
||||
output wire mac_4_tx_clk,
|
||||
output wire mac_4_tx_rst,
|
||||
|
||||
output wire mac_4_tx_ptp_clk,
|
||||
output wire mac_4_tx_ptp_rst,
|
||||
input wire [PTP_TS_WIDTH-1:0] mac_4_tx_ptp_time,
|
||||
|
||||
output wire [PTP_TS_WIDTH-1:0] mac_4_tx_ptp_ts,
|
||||
output wire [PTP_TAG_WIDTH-1:0] mac_4_tx_ptp_ts_tag,
|
||||
output wire mac_4_tx_ptp_ts_valid,
|
||||
|
||||
input wire [DATA_WIDTH-1:0] mac_4_tx_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] mac_4_tx_axis_tkeep,
|
||||
input wire mac_4_tx_axis_tvalid,
|
||||
output wire mac_4_tx_axis_tready,
|
||||
input wire mac_4_tx_axis_tlast,
|
||||
input wire [TX_USER_WIDTH-1:0] mac_4_tx_axis_tuser,
|
||||
|
||||
output wire mac_4_rx_clk,
|
||||
output wire mac_4_rx_rst,
|
||||
|
||||
output wire mac_4_rx_ptp_clk,
|
||||
output wire mac_4_rx_ptp_rst,
|
||||
output wire [PTP_TS_WIDTH-1:0] mac_4_rx_ptp_time,
|
||||
|
||||
output wire [DATA_WIDTH-1:0] mac_4_rx_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] mac_4_rx_axis_tkeep,
|
||||
output wire mac_4_rx_axis_tvalid,
|
||||
output wire mac_4_rx_axis_tlast,
|
||||
output wire [RX_USER_WIDTH-1:0] mac_4_rx_axis_tuser,
|
||||
|
||||
output wire mac_4_rx_status
|
||||
);
|
||||
|
||||
parameter N_CH = 4;
|
||||
|
||||
wire [5:0] mac_pll_clk_d64;
|
||||
wire [5:0] mac_pll_clk_d66;
|
||||
wire [5:0] mac_rec_clk_d64;
|
||||
wire [5:0] mac_rec_clk_d66;
|
||||
|
||||
wire [N_CH-1:0] mac_tx_pll_locked;
|
||||
|
||||
wire [N_CH-1:0] mac_rx_clk;
|
||||
wire [N_CH-1:0] mac_rx_rst;
|
||||
wire [N_CH-1:0] mac_tx_clk;
|
||||
wire [N_CH-1:0] mac_tx_rst;
|
||||
|
||||
wire [N_CH-1:0] mac_rx_ptp_clk;
|
||||
wire [N_CH-1:0] mac_rx_ptp_rst;
|
||||
wire [N_CH-1:0] mac_tx_ptp_clk;
|
||||
wire [N_CH-1:0] mac_tx_ptp_rst;
|
||||
|
||||
wire [N_CH*19-1:0] xcvr_reconfig_address;
|
||||
wire [N_CH-1:0] xcvr_reconfig_read;
|
||||
wire [N_CH-1:0] xcvr_reconfig_write;
|
||||
wire [N_CH*8-1:0] xcvr_reconfig_readdata;
|
||||
wire [N_CH*8-1:0] xcvr_reconfig_writedata;
|
||||
wire [N_CH-1:0] xcvr_reconfig_waitrequest;
|
||||
|
||||
wire [N_CH-1:0] mac_tx_lanes_stable;
|
||||
wire [N_CH-1:0] mac_rx_pcs_ready;
|
||||
wire [N_CH-1:0] mac_ehip_ready;
|
||||
|
||||
wire [N_CH*PTP_TS_WIDTH-1:0] mac_ptp_tx_tod;
|
||||
wire [N_CH*PTP_TS_WIDTH-1:0] mac_ptp_rx_tod;
|
||||
wire [N_CH*PTP_TAG_WIDTH-1:0] mac_ptp_fp;
|
||||
wire [N_CH-1:0] mac_ptp_ets_valid;
|
||||
wire [N_CH*PTP_TS_WIDTH-1:0] mac_ptp_ets;
|
||||
wire [N_CH*PTP_TAG_WIDTH-1:0] mac_ptp_ets_fp;
|
||||
wire [N_CH*PTP_TS_WIDTH-1:0] mac_ptp_rx_its;
|
||||
|
||||
wire [N_CH-1:0] mac_tx_ready;
|
||||
wire [N_CH-1:0] mac_tx_valid;
|
||||
wire [N_CH*DATA_WIDTH-1:0] mac_tx_data;
|
||||
wire [N_CH-1:0] mac_tx_error;
|
||||
wire [N_CH-1:0] mac_tx_startofpacket;
|
||||
wire [N_CH-1:0] mac_tx_endofpacket;
|
||||
wire [N_CH*3-1:0] mac_tx_empty;
|
||||
|
||||
wire [N_CH-1:0] mac_rx_valid;
|
||||
wire [N_CH*DATA_WIDTH-1:0] mac_rx_data;
|
||||
wire [N_CH-1:0] mac_rx_startofpacket;
|
||||
wire [N_CH-1:0] mac_rx_endofpacket;
|
||||
wire [N_CH*3-1:0] mac_rx_empty;
|
||||
wire [N_CH*6-1:0] mac_rx_error;
|
||||
|
||||
generate
|
||||
|
||||
if (MAC_RSFEC) begin
|
||||
|
||||
mac_rsfec mac_inst (
|
||||
.o_cdr_lock (),
|
||||
.o_tx_pll_locked (mac_tx_pll_locked),
|
||||
.i_eth_reconfig_addr (21'd0),
|
||||
.i_eth_reconfig_read (1'b0),
|
||||
.i_eth_reconfig_write (1'b0),
|
||||
.o_eth_reconfig_readdata (),
|
||||
.o_eth_reconfig_readdata_valid (),
|
||||
.i_eth_reconfig_writedata (32'd0),
|
||||
.o_eth_reconfig_waitrequest (),
|
||||
.i_rsfec_reconfig_addr (11'd0),
|
||||
.i_rsfec_reconfig_read (1'b0),
|
||||
.i_rsfec_reconfig_write (1'b0),
|
||||
.o_rsfec_reconfig_readdata (),
|
||||
.i_rsfec_reconfig_writedata (8'd0),
|
||||
.o_rsfec_reconfig_waitrequest (),
|
||||
.i_ptp_reconfig_address ({2{19'd0}}),
|
||||
.i_ptp_reconfig_read ({2{1'b0}}),
|
||||
.i_ptp_reconfig_write ({2{1'b0}}),
|
||||
.o_ptp_reconfig_readdata (),
|
||||
.i_ptp_reconfig_writedata ({2{8'd0}}),
|
||||
.o_ptp_reconfig_waitrequest (),
|
||||
.i_clk_ref ({4{ref_clk}}),
|
||||
.o_clk_pll_div64 (mac_pll_clk_d64),
|
||||
.o_clk_pll_div66 (mac_pll_clk_d66),
|
||||
.o_clk_rec_div64 (mac_rec_clk_d64),
|
||||
.o_clk_rec_div66 (mac_rec_clk_d66),
|
||||
.i_csr_rst_n (~ctrl_rst),
|
||||
.o_tx_serial (tx_serial_data_p),
|
||||
.i_rx_serial (rx_serial_data_p),
|
||||
.o_tx_serial_n (tx_serial_data_n),
|
||||
.i_rx_serial_n (rx_serial_data_n),
|
||||
.i_reconfig_clk (ctrl_clk),
|
||||
.i_reconfig_reset (ctrl_rst),
|
||||
.i_xcvr_reconfig_address (xcvr_reconfig_address),
|
||||
.i_xcvr_reconfig_read (xcvr_reconfig_read),
|
||||
.i_xcvr_reconfig_write (xcvr_reconfig_write),
|
||||
.o_xcvr_reconfig_readdata (xcvr_reconfig_readdata),
|
||||
.i_xcvr_reconfig_writedata (xcvr_reconfig_writedata),
|
||||
.o_xcvr_reconfig_waitrequest (xcvr_reconfig_waitrequest),
|
||||
.i_sl_stats_snapshot ({4{1'b0}}),
|
||||
.o_sl_rx_hi_ber (),
|
||||
.i_sl_eth_reconfig_addr ({4{19'd0}}),
|
||||
.i_sl_eth_reconfig_read ({4{1'b0}}),
|
||||
.i_sl_eth_reconfig_write ({4{1'b0}}),
|
||||
.o_sl_eth_reconfig_readdata (),
|
||||
.o_sl_eth_reconfig_readdata_valid (),
|
||||
.i_sl_eth_reconfig_writedata ({4{32'd0}}),
|
||||
.o_sl_eth_reconfig_waitrequest (),
|
||||
.o_sl_tx_lanes_stable (mac_tx_lanes_stable),
|
||||
.o_sl_rx_pcs_ready (mac_rx_pcs_ready),
|
||||
.o_sl_ehip_ready (mac_ehip_ready),
|
||||
.o_sl_rx_block_lock (),
|
||||
.o_sl_local_fault_status (),
|
||||
.o_sl_remote_fault_status (),
|
||||
.i_sl_clk_tx (mac_tx_clk),
|
||||
.i_sl_clk_rx (mac_rx_clk),
|
||||
.i_sl_clk_tx_tod (mac_tx_ptp_clk),
|
||||
.i_sl_clk_rx_tod (mac_rx_ptp_clk),
|
||||
.i_sl_csr_rst_n ({4{!ctrl_rst}}),
|
||||
.i_sl_tx_rst_n (mac_tx_pll_locked),
|
||||
.i_sl_rx_rst_n (mac_tx_pll_locked),
|
||||
.o_sl_txfifo_pfull (),
|
||||
.o_sl_txfifo_pempty (),
|
||||
.o_sl_txfifo_overflow (),
|
||||
.o_sl_txfifo_underflow (),
|
||||
.o_sl_tx_ready (mac_tx_ready),
|
||||
.o_sl_rx_valid (mac_rx_valid),
|
||||
.i_sl_tx_valid (mac_tx_valid),
|
||||
.i_sl_tx_data (mac_tx_data),
|
||||
.o_sl_rx_data (mac_rx_data),
|
||||
.i_sl_tx_error (mac_tx_error),
|
||||
.i_sl_tx_startofpacket (mac_tx_startofpacket),
|
||||
.i_sl_tx_endofpacket (mac_tx_endofpacket),
|
||||
.i_sl_tx_empty (mac_tx_empty),
|
||||
.i_sl_tx_skip_crc ({4{1'b0}}),
|
||||
.o_sl_rx_startofpacket (mac_rx_startofpacket),
|
||||
.o_sl_rx_endofpacket (mac_rx_endofpacket),
|
||||
.o_sl_rx_empty (mac_rx_empty),
|
||||
.o_sl_rx_error (mac_rx_error),
|
||||
.o_sl_rxstatus_data (),
|
||||
.o_sl_rxstatus_valid (),
|
||||
.i_sl_tx_pfc ({4{8'd0}}),
|
||||
.o_sl_rx_pfc (),
|
||||
.i_sl_tx_pause ({4{1'b0}}),
|
||||
.o_sl_rx_pause (),
|
||||
.i_sl_ptp_tx_tod (mac_ptp_tx_tod),
|
||||
.i_sl_ptp_rx_tod (mac_ptp_rx_tod),
|
||||
.i_sl_ptp_ts_req ({4{1'b1}}),
|
||||
.i_sl_ptp_fp (mac_ptp_fp),
|
||||
.o_sl_ptp_ets_valid (mac_ptp_ets_valid),
|
||||
.o_sl_ptp_ets (mac_ptp_ets),
|
||||
.o_sl_ptp_ets_fp (mac_ptp_ets_fp),
|
||||
.o_sl_ptp_rx_its (mac_ptp_rx_its),
|
||||
.o_sl_tx_ptp_ready (),
|
||||
.o_sl_rx_ptp_ready (),
|
||||
.i_clk_ptp_sample (ptp_sample_clk),
|
||||
.i_sl_ptp_ins_ets ({4{1'b0}}),
|
||||
.i_sl_ptp_ins_cf ({4{1'b0}}),
|
||||
.i_sl_ptp_zero_csum ({4{1'b0}}),
|
||||
.i_sl_ptp_update_eb ({4{1'b0}}),
|
||||
.i_sl_ptp_ts_format ({4{1'b0}}),
|
||||
.i_sl_ptp_ts_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_cf_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_csum_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_eb_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_tx_its ({4{96'd0}})
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
mac mac_inst (
|
||||
.o_cdr_lock (),
|
||||
.o_tx_pll_locked (mac_tx_pll_locked),
|
||||
.i_eth_reconfig_addr (21'd0),
|
||||
.i_eth_reconfig_read (1'b0),
|
||||
.i_eth_reconfig_write (1'b0),
|
||||
.o_eth_reconfig_readdata (),
|
||||
.o_eth_reconfig_readdata_valid (),
|
||||
.i_eth_reconfig_writedata (32'd0),
|
||||
.o_eth_reconfig_waitrequest (),
|
||||
.i_ptp_reconfig_address ({2{19'd0}}),
|
||||
.i_ptp_reconfig_read ({2{1'b0}}),
|
||||
.i_ptp_reconfig_write ({2{1'b0}}),
|
||||
.o_ptp_reconfig_readdata (),
|
||||
.i_ptp_reconfig_writedata ({2{8'd0}}),
|
||||
.o_ptp_reconfig_waitrequest (),
|
||||
.i_clk_ref ({4{ref_clk}}),
|
||||
.o_clk_pll_div64 (mac_pll_clk_d64),
|
||||
.o_clk_pll_div66 (mac_pll_clk_d66),
|
||||
.o_clk_rec_div64 (mac_rec_clk_d64),
|
||||
.o_clk_rec_div66 (mac_rec_clk_d66),
|
||||
.i_csr_rst_n (~ctrl_rst),
|
||||
.o_tx_serial (tx_serial_data_p),
|
||||
.i_rx_serial (rx_serial_data_p),
|
||||
.o_tx_serial_n (tx_serial_data_n),
|
||||
.i_rx_serial_n (rx_serial_data_n),
|
||||
.i_reconfig_clk (ctrl_clk),
|
||||
.i_reconfig_reset (ctrl_rst),
|
||||
.i_xcvr_reconfig_address (xcvr_reconfig_address),
|
||||
.i_xcvr_reconfig_read (xcvr_reconfig_read),
|
||||
.i_xcvr_reconfig_write (xcvr_reconfig_write),
|
||||
.o_xcvr_reconfig_readdata (xcvr_reconfig_readdata),
|
||||
.i_xcvr_reconfig_writedata (xcvr_reconfig_writedata),
|
||||
.o_xcvr_reconfig_waitrequest (xcvr_reconfig_waitrequest),
|
||||
.i_sl_stats_snapshot ({4{1'b0}}),
|
||||
.o_sl_rx_hi_ber (),
|
||||
.i_sl_eth_reconfig_addr ({4{19'd0}}),
|
||||
.i_sl_eth_reconfig_read ({4{1'b0}}),
|
||||
.i_sl_eth_reconfig_write ({4{1'b0}}),
|
||||
.o_sl_eth_reconfig_readdata (),
|
||||
.o_sl_eth_reconfig_readdata_valid (),
|
||||
.i_sl_eth_reconfig_writedata ({4{32'd0}}),
|
||||
.o_sl_eth_reconfig_waitrequest (),
|
||||
.o_sl_tx_lanes_stable (mac_tx_lanes_stable),
|
||||
.o_sl_rx_pcs_ready (mac_rx_pcs_ready),
|
||||
.o_sl_ehip_ready (mac_ehip_ready),
|
||||
.o_sl_rx_block_lock (),
|
||||
.o_sl_local_fault_status (),
|
||||
.o_sl_remote_fault_status (),
|
||||
.i_sl_clk_tx (mac_tx_clk),
|
||||
.i_sl_clk_rx (mac_rx_clk),
|
||||
.i_sl_clk_tx_tod (mac_tx_ptp_clk),
|
||||
.i_sl_clk_rx_tod (mac_rx_ptp_clk),
|
||||
.i_sl_csr_rst_n ({4{!ctrl_rst}}),
|
||||
.i_sl_tx_rst_n (mac_tx_pll_locked),
|
||||
.i_sl_rx_rst_n (mac_tx_pll_locked),
|
||||
.o_sl_txfifo_pfull (),
|
||||
.o_sl_txfifo_pempty (),
|
||||
.o_sl_txfifo_overflow (),
|
||||
.o_sl_txfifo_underflow (),
|
||||
.o_sl_tx_ready (mac_tx_ready),
|
||||
.o_sl_rx_valid (mac_rx_valid),
|
||||
.i_sl_tx_valid (mac_tx_valid),
|
||||
.i_sl_tx_data (mac_tx_data),
|
||||
.o_sl_rx_data (mac_rx_data),
|
||||
.i_sl_tx_error (mac_tx_error),
|
||||
.i_sl_tx_startofpacket (mac_tx_startofpacket),
|
||||
.i_sl_tx_endofpacket (mac_tx_endofpacket),
|
||||
.i_sl_tx_empty (mac_tx_empty),
|
||||
.i_sl_tx_skip_crc ({4{1'b0}}),
|
||||
.o_sl_rx_startofpacket (mac_rx_startofpacket),
|
||||
.o_sl_rx_endofpacket (mac_rx_endofpacket),
|
||||
.o_sl_rx_empty (mac_rx_empty),
|
||||
.o_sl_rx_error (mac_rx_error),
|
||||
.o_sl_rxstatus_data (),
|
||||
.o_sl_rxstatus_valid (),
|
||||
.i_sl_tx_pfc ({4{8'd0}}),
|
||||
.o_sl_rx_pfc (),
|
||||
.i_sl_tx_pause ({4{1'b0}}),
|
||||
.o_sl_rx_pause (),
|
||||
.i_sl_ptp_tx_tod (mac_ptp_tx_tod),
|
||||
.i_sl_ptp_rx_tod (mac_ptp_rx_tod),
|
||||
.i_sl_ptp_ts_req ({4{1'b1}}),
|
||||
.i_sl_ptp_fp (mac_ptp_fp),
|
||||
.o_sl_ptp_ets_valid (mac_ptp_ets_valid),
|
||||
.o_sl_ptp_ets (mac_ptp_ets),
|
||||
.o_sl_ptp_ets_fp (mac_ptp_ets_fp),
|
||||
.o_sl_ptp_rx_its (mac_ptp_rx_its),
|
||||
.o_sl_tx_ptp_ready (),
|
||||
.o_sl_rx_ptp_ready (),
|
||||
.i_clk_ptp_sample (ptp_sample_clk),
|
||||
.i_sl_ptp_ins_ets ({4{1'b0}}),
|
||||
.i_sl_ptp_ins_cf ({4{1'b0}}),
|
||||
.i_sl_ptp_zero_csum ({4{1'b0}}),
|
||||
.i_sl_ptp_update_eb ({4{1'b0}}),
|
||||
.i_sl_ptp_ts_format ({4{1'b0}}),
|
||||
.i_sl_ptp_ts_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_cf_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_csum_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_eb_offset ({4{16'd0}}),
|
||||
.i_sl_ptp_tx_its ({4{96'd0}})
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata;
|
||||
wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep;
|
||||
wire [N_CH-1:0] mac_rx_axis_tvalid;
|
||||
wire [N_CH-1:0] mac_rx_axis_tlast;
|
||||
wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser;
|
||||
|
||||
wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata;
|
||||
wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep;
|
||||
wire [N_CH-1:0] mac_tx_axis_tvalid;
|
||||
wire [N_CH-1:0] mac_tx_axis_tready;
|
||||
wire [N_CH-1:0] mac_tx_axis_tlast;
|
||||
wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser;
|
||||
|
||||
assign mac_tx_clk[3:0] = {4{mac_pll_clk_d64[4]}};
|
||||
assign mac_rx_clk[3:0] = mac_tx_clk[3:0];
|
||||
|
||||
assign mac_tx_ptp_clk[3:0] = mac_pll_clk_d66[3:0];
|
||||
assign mac_rx_ptp_clk[3:0] = mac_rec_clk_d66[3:0];
|
||||
|
||||
assign mac_1_tx_clk = mac_tx_clk[0];
|
||||
assign mac_1_tx_rst = mac_tx_rst[0];
|
||||
|
||||
assign mac_1_tx_ptp_clk = mac_tx_ptp_clk[0];
|
||||
assign mac_1_tx_ptp_rst = mac_tx_ptp_rst[0];
|
||||
assign mac_ptp_tx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_tx_ptp_time;
|
||||
|
||||
assign mac_1_tx_ptp_ts = mac_ptp_ets[0*PTP_TS_WIDTH +: PTP_TS_WIDTH];
|
||||
assign mac_1_tx_ptp_ts_tag = mac_ptp_ets_fp[0*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
|
||||
assign mac_1_tx_ptp_ts_valid = mac_ptp_ets_valid[0];
|
||||
|
||||
assign mac_tx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH] = mac_1_tx_axis_tdata;
|
||||
assign mac_tx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH] = mac_1_tx_axis_tkeep;
|
||||
assign mac_tx_axis_tvalid[0] = mac_1_tx_axis_tvalid;
|
||||
assign mac_1_tx_axis_tready = mac_tx_axis_tready[0];
|
||||
assign mac_tx_axis_tlast[0] = mac_1_tx_axis_tlast;
|
||||
assign mac_tx_axis_tuser[0*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_1_tx_axis_tuser;
|
||||
|
||||
assign mac_1_rx_clk = mac_rx_clk[0];
|
||||
assign mac_1_rx_rst = mac_rx_rst[0];
|
||||
|
||||
assign mac_1_rx_ptp_clk = mac_rx_ptp_clk[0];
|
||||
assign mac_1_rx_ptp_rst = mac_rx_ptp_rst[0];
|
||||
assign mac_ptp_rx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_rx_ptp_time;
|
||||
|
||||
assign mac_1_rx_axis_tdata = mac_rx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH];
|
||||
assign mac_1_rx_axis_tkeep = mac_rx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH];
|
||||
assign mac_1_rx_axis_tvalid = mac_rx_axis_tvalid[0];
|
||||
assign mac_1_rx_axis_tlast = mac_rx_axis_tlast[0];
|
||||
assign mac_1_rx_axis_tuser = mac_rx_axis_tuser[0*RX_USER_WIDTH +: RX_USER_WIDTH];
|
||||
|
||||
assign mac_1_rx_status = mac_rx_pcs_ready[0];
|
||||
|
||||
assign mac_2_tx_clk = mac_tx_clk[1];
|
||||
assign mac_2_tx_rst = mac_tx_rst[1];
|
||||
|
||||
assign mac_2_tx_ptp_clk = mac_tx_ptp_clk[1];
|
||||
assign mac_2_tx_ptp_rst = mac_tx_ptp_rst[1];
|
||||
assign mac_ptp_tx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_tx_ptp_time;
|
||||
|
||||
assign mac_2_tx_ptp_ts = mac_ptp_ets[1*PTP_TS_WIDTH +: PTP_TS_WIDTH];
|
||||
assign mac_2_tx_ptp_ts_tag = mac_ptp_ets_fp[1*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
|
||||
assign mac_2_tx_ptp_ts_valid = mac_ptp_ets_valid[1];
|
||||
|
||||
assign mac_tx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH] = mac_2_tx_axis_tdata;
|
||||
assign mac_tx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH] = mac_2_tx_axis_tkeep;
|
||||
assign mac_tx_axis_tvalid[1] = mac_2_tx_axis_tvalid;
|
||||
assign mac_2_tx_axis_tready = mac_tx_axis_tready[1];
|
||||
assign mac_tx_axis_tlast[1] = mac_2_tx_axis_tlast;
|
||||
assign mac_tx_axis_tuser[1*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_2_tx_axis_tuser;
|
||||
|
||||
assign mac_2_rx_clk = mac_rx_clk[1];
|
||||
assign mac_2_rx_rst = mac_rx_rst[1];
|
||||
|
||||
assign mac_2_rx_ptp_clk = mac_rx_ptp_clk[1];
|
||||
assign mac_2_rx_ptp_rst = mac_rx_ptp_rst[1];
|
||||
assign mac_ptp_rx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_rx_ptp_time;
|
||||
|
||||
assign mac_2_rx_axis_tdata = mac_rx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH];
|
||||
assign mac_2_rx_axis_tkeep = mac_rx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH];
|
||||
assign mac_2_rx_axis_tvalid = mac_rx_axis_tvalid[1];
|
||||
assign mac_2_rx_axis_tlast = mac_rx_axis_tlast[1];
|
||||
assign mac_2_rx_axis_tuser = mac_rx_axis_tuser[1*RX_USER_WIDTH +: RX_USER_WIDTH];
|
||||
|
||||
assign mac_2_rx_status = mac_rx_pcs_ready[1];
|
||||
|
||||
assign mac_3_tx_clk = mac_tx_clk[2];
|
||||
assign mac_3_tx_rst = mac_tx_rst[2];
|
||||
|
||||
assign mac_3_tx_ptp_clk = mac_tx_ptp_clk[2];
|
||||
assign mac_3_tx_ptp_rst = mac_tx_ptp_rst[2];
|
||||
assign mac_ptp_tx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_tx_ptp_time;
|
||||
|
||||
assign mac_3_tx_ptp_ts = mac_ptp_ets[2*PTP_TS_WIDTH +: PTP_TS_WIDTH];
|
||||
assign mac_3_tx_ptp_ts_tag = mac_ptp_ets_fp[2*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
|
||||
assign mac_3_tx_ptp_ts_valid = mac_ptp_ets_valid[2];
|
||||
|
||||
assign mac_tx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH] = mac_3_tx_axis_tdata;
|
||||
assign mac_tx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH] = mac_3_tx_axis_tkeep;
|
||||
assign mac_tx_axis_tvalid[2] = mac_3_tx_axis_tvalid;
|
||||
assign mac_3_tx_axis_tready = mac_tx_axis_tready[2];
|
||||
assign mac_tx_axis_tlast[2] = mac_3_tx_axis_tlast;
|
||||
assign mac_tx_axis_tuser[2*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_3_tx_axis_tuser;
|
||||
|
||||
assign mac_3_rx_clk = mac_rx_clk[2];
|
||||
assign mac_3_rx_rst = mac_rx_rst[2];
|
||||
|
||||
assign mac_3_rx_ptp_clk = mac_rx_ptp_clk[2];
|
||||
assign mac_3_rx_ptp_rst = mac_rx_ptp_rst[2];
|
||||
assign mac_ptp_rx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_rx_ptp_time;
|
||||
|
||||
assign mac_3_rx_axis_tdata = mac_rx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH];
|
||||
assign mac_3_rx_axis_tkeep = mac_rx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH];
|
||||
assign mac_3_rx_axis_tvalid = mac_rx_axis_tvalid[2];
|
||||
assign mac_3_rx_axis_tlast = mac_rx_axis_tlast[2];
|
||||
assign mac_3_rx_axis_tuser = mac_rx_axis_tuser[2*RX_USER_WIDTH +: RX_USER_WIDTH];
|
||||
|
||||
assign mac_3_rx_status = mac_rx_pcs_ready[2];
|
||||
|
||||
assign mac_4_tx_clk = mac_tx_clk[3];
|
||||
assign mac_4_tx_rst = mac_tx_rst[3];
|
||||
|
||||
assign mac_4_tx_ptp_clk = mac_tx_ptp_clk[3];
|
||||
assign mac_4_tx_ptp_rst = mac_tx_ptp_rst[3];
|
||||
assign mac_ptp_tx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_tx_ptp_time;
|
||||
|
||||
assign mac_4_tx_ptp_ts = mac_ptp_ets[3*PTP_TS_WIDTH +: PTP_TS_WIDTH];
|
||||
assign mac_4_tx_ptp_ts_tag = mac_ptp_ets_fp[3*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
|
||||
assign mac_4_tx_ptp_ts_valid = mac_ptp_ets_valid[3];
|
||||
|
||||
assign mac_tx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH] = mac_4_tx_axis_tdata;
|
||||
assign mac_tx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH] = mac_4_tx_axis_tkeep;
|
||||
assign mac_tx_axis_tvalid[3] = mac_4_tx_axis_tvalid;
|
||||
assign mac_4_tx_axis_tready = mac_tx_axis_tready[3];
|
||||
assign mac_tx_axis_tlast[3] = mac_4_tx_axis_tlast;
|
||||
assign mac_tx_axis_tuser[3*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_4_tx_axis_tuser;
|
||||
|
||||
assign mac_4_rx_clk = mac_rx_clk[3];
|
||||
assign mac_4_rx_rst = mac_rx_rst[3];
|
||||
|
||||
assign mac_4_rx_ptp_clk = mac_rx_ptp_clk[3];
|
||||
assign mac_4_rx_ptp_rst = mac_rx_ptp_rst[3];
|
||||
assign mac_ptp_rx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_rx_ptp_time;
|
||||
|
||||
assign mac_4_rx_axis_tdata = mac_rx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH];
|
||||
assign mac_4_rx_axis_tkeep = mac_rx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH];
|
||||
assign mac_4_rx_axis_tvalid = mac_rx_axis_tvalid[3];
|
||||
assign mac_4_rx_axis_tlast = mac_rx_axis_tlast[3];
|
||||
assign mac_4_rx_axis_tuser = mac_rx_axis_tuser[3*RX_USER_WIDTH +: RX_USER_WIDTH];
|
||||
|
||||
assign mac_4_rx_status = mac_rx_pcs_ready[3];
|
||||
|
||||
generate
|
||||
|
||||
genvar n;
|
||||
|
||||
for (n = 0; n < N_CH; n = n + 1) begin : mac_ch
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
mac_tx_reset_sync_inst (
|
||||
.clk(mac_tx_clk[n]),
|
||||
.rst(ctrl_rst || !mac_tx_lanes_stable[n] || !mac_ehip_ready[n]),
|
||||
.out(mac_tx_rst[n])
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
mac_rx_reset_sync_inst (
|
||||
.clk(mac_rx_clk[n]),
|
||||
.rst(ctrl_rst || !mac_rx_pcs_ready[n]),
|
||||
.out(mac_rx_rst[n])
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
mac_tx_ptp_reset_sync_inst (
|
||||
.clk(mac_tx_ptp_clk[n]),
|
||||
.rst(ctrl_rst || !mac_tx_lanes_stable[n]),
|
||||
.out(mac_tx_ptp_rst[n])
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
mac_rx_ptp_reset_sync_inst (
|
||||
.clk(mac_rx_ptp_clk[n]),
|
||||
.rst(ctrl_rst || !mac_rx_pcs_ready[n]),
|
||||
.out(mac_rx_ptp_rst[n])
|
||||
);
|
||||
|
||||
xcvr_ctrl xcvr_ctrl_inst (
|
||||
.reconfig_clk(ctrl_clk),
|
||||
.reconfig_rst(ctrl_rst),
|
||||
|
||||
.pll_locked_in(mac_tx_pll_locked[n]),
|
||||
|
||||
.xcvr_reconfig_address(xcvr_reconfig_address[n*19 +: 19]),
|
||||
.xcvr_reconfig_read(xcvr_reconfig_read[n]),
|
||||
.xcvr_reconfig_write(xcvr_reconfig_write[n]),
|
||||
.xcvr_reconfig_readdata(xcvr_reconfig_readdata[n*8 +: 8]),
|
||||
.xcvr_reconfig_writedata(xcvr_reconfig_writedata[n*8 +: 8]),
|
||||
.xcvr_reconfig_waitrequest(xcvr_reconfig_waitrequest[n])
|
||||
);
|
||||
|
||||
axis2avst #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.KEEP_ENABLE(1),
|
||||
.EMPTY_WIDTH(3),
|
||||
.BYTE_REVERSE(1)
|
||||
)
|
||||
mac_tx_axis2avst (
|
||||
.clk(mac_tx_clk[n]),
|
||||
.rst(mac_tx_rst[n]),
|
||||
|
||||
.axis_tdata(mac_tx_axis_tdata[n*DATA_WIDTH +: DATA_WIDTH]),
|
||||
.axis_tkeep(mac_tx_axis_tkeep[n*KEEP_WIDTH +: KEEP_WIDTH]),
|
||||
.axis_tvalid(mac_tx_axis_tvalid[n]),
|
||||
.axis_tready(mac_tx_axis_tready[n]),
|
||||
.axis_tlast(mac_tx_axis_tlast[n]),
|
||||
.axis_tuser(mac_tx_axis_tuser[n*TX_USER_WIDTH +: 1]),
|
||||
|
||||
.avst_ready(mac_tx_ready[n]),
|
||||
.avst_valid(mac_tx_valid[n]),
|
||||
.avst_data(mac_tx_data[n*DATA_WIDTH +: DATA_WIDTH]),
|
||||
.avst_startofpacket(mac_tx_startofpacket[n]),
|
||||
.avst_endofpacket(mac_tx_endofpacket[n]),
|
||||
.avst_empty(mac_tx_empty[n*3 +: 3]),
|
||||
.avst_error(mac_tx_error[n])
|
||||
);
|
||||
|
||||
assign mac_ptp_fp[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = mac_tx_axis_tuser[n*TX_USER_WIDTH+1 +: PTP_TAG_WIDTH];
|
||||
|
||||
wire [DATA_WIDTH-1:0] mac_rx_axis_tdata_int;
|
||||
wire [KEEP_WIDTH-1:0] mac_rx_axis_tkeep_int;
|
||||
wire mac_rx_axis_tvalid_int;
|
||||
wire mac_rx_axis_tlast_int;
|
||||
wire mac_rx_axis_tuser_int;
|
||||
|
||||
avst2axis #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.KEEP_ENABLE(1),
|
||||
.EMPTY_WIDTH(3),
|
||||
.BYTE_REVERSE(1)
|
||||
)
|
||||
mac_rx_avst2axis (
|
||||
.clk(mac_rx_clk[n]),
|
||||
.rst(mac_rx_rst[n]),
|
||||
|
||||
.avst_ready(),
|
||||
.avst_valid(mac_rx_valid[n]),
|
||||
.avst_data(mac_rx_data[n*DATA_WIDTH +: DATA_WIDTH]),
|
||||
.avst_startofpacket(mac_rx_startofpacket[n]),
|
||||
.avst_endofpacket(mac_rx_endofpacket[n]),
|
||||
.avst_empty(mac_rx_empty[n*3 +: 3]),
|
||||
.avst_error(mac_rx_error[n*6 +: 6] != 0),
|
||||
|
||||
.axis_tdata(mac_rx_axis_tdata_int),
|
||||
.axis_tkeep(mac_rx_axis_tkeep_int),
|
||||
.axis_tvalid(mac_rx_axis_tvalid_int),
|
||||
.axis_tready(1'b1),
|
||||
.axis_tlast(mac_rx_axis_tlast_int),
|
||||
.axis_tuser(mac_rx_axis_tuser_int)
|
||||
);
|
||||
|
||||
mac_ts_insert #(
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.S_USER_WIDTH(1),
|
||||
.M_USER_WIDTH(RX_USER_WIDTH)
|
||||
)
|
||||
mac_ts_insert_inst (
|
||||
.clk(mac_rx_clk[n]),
|
||||
.rst(mac_rx_rst[n]),
|
||||
|
||||
/*
|
||||
* PTP TS input
|
||||
*/
|
||||
.ptp_ts(mac_ptp_rx_its[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
|
||||
|
||||
/*
|
||||
* AXI input
|
||||
*/
|
||||
.s_axis_tdata(mac_rx_axis_tdata_int),
|
||||
.s_axis_tkeep(mac_rx_axis_tkeep_int),
|
||||
.s_axis_tvalid(mac_rx_axis_tvalid_int),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tlast(mac_rx_axis_tlast_int),
|
||||
.s_axis_tuser(mac_rx_axis_tuser_int),
|
||||
|
||||
/*
|
||||
* AXI output
|
||||
*/
|
||||
.m_axis_tdata(mac_rx_axis_tdata[n*DATA_WIDTH +: DATA_WIDTH]),
|
||||
.m_axis_tkeep(mac_rx_axis_tkeep[n*KEEP_WIDTH +: KEEP_WIDTH]),
|
||||
.m_axis_tvalid(mac_rx_axis_tvalid[n]),
|
||||
.m_axis_tready(1'b1),
|
||||
.m_axis_tlast(mac_rx_axis_tlast[n]),
|
||||
.m_axis_tuser(mac_rx_axis_tuser[n*RX_USER_WIDTH +: RX_USER_WIDTH])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
1462
fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v
Normal file
1462
fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v
Normal file
File diff suppressed because it is too large
Load Diff
1215
fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v
Normal file
1215
fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
62
fpga/mqnic/S10DX_DK/fpga_25g/rtl/sync_signal.v
Normal file
62
fpga/mqnic/S10DX_DK/fpga_25g/rtl/sync_signal.v
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`resetall
|
||||
`timescale 1 ns / 1 ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
268
fpga/mqnic/S10DX_DK/fpga_25g/rtl/xcvr_ctrl.v
Normal file
268
fpga/mqnic/S10DX_DK/fpga_25g/rtl/xcvr_ctrl.v
Normal file
@ -0,0 +1,268 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Transceiver control
|
||||
*/
|
||||
module xcvr_ctrl (
|
||||
input wire reconfig_clk,
|
||||
input wire reconfig_rst,
|
||||
|
||||
input wire pll_locked_in,
|
||||
|
||||
output wire [18:0] xcvr_reconfig_address,
|
||||
output wire xcvr_reconfig_read,
|
||||
output wire xcvr_reconfig_write,
|
||||
input wire [7:0] xcvr_reconfig_readdata,
|
||||
output wire [7:0] xcvr_reconfig_writedata,
|
||||
input wire xcvr_reconfig_waitrequest
|
||||
);
|
||||
|
||||
localparam [3:0]
|
||||
STATE_IDLE = 4'd0,
|
||||
STATE_LOAD_PMA_1 = 4'd1,
|
||||
STATE_LOAD_PMA_2 = 4'd2,
|
||||
STATE_INIT_ADAPT_1 = 4'd3,
|
||||
STATE_INIT_ADAPT_2 = 4'd4,
|
||||
STATE_INIT_ADAPT_3 = 4'd5,
|
||||
STATE_INIT_ADAPT_4 = 4'd6,
|
||||
STATE_CONT_ADAPT_1 = 4'd7,
|
||||
STATE_CONT_ADAPT_2 = 4'd8,
|
||||
STATE_CONT_ADAPT_3 = 4'd9,
|
||||
STATE_CONT_ADAPT_4 = 4'd10,
|
||||
STATE_DONE = 4'd11;
|
||||
|
||||
reg [3:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
reg [18:0] xcvr_reconfig_address_reg = 19'd0, xcvr_reconfig_address_next;
|
||||
reg xcvr_reconfig_read_reg = 1'b0, xcvr_reconfig_read_next;
|
||||
reg xcvr_reconfig_write_reg = 1'b0, xcvr_reconfig_write_next;
|
||||
reg [7:0] xcvr_reconfig_writedata_reg = 8'd0, xcvr_reconfig_writedata_next;
|
||||
|
||||
reg [7:0] read_data_reg = 8'd0, read_data_next;
|
||||
reg read_data_valid_reg = 1'b0, read_data_valid_next;
|
||||
|
||||
reg [15:0] delay_count_reg = 0, delay_count_next;
|
||||
|
||||
reg pll_locked_sync_1_reg = 0;
|
||||
reg pll_locked_sync_2_reg = 0;
|
||||
reg pll_locked_sync_3_reg = 0;
|
||||
|
||||
assign xcvr_reconfig_address = xcvr_reconfig_address_reg;
|
||||
assign xcvr_reconfig_read = xcvr_reconfig_read_reg;
|
||||
assign xcvr_reconfig_write = xcvr_reconfig_write_reg;
|
||||
assign xcvr_reconfig_writedata = xcvr_reconfig_writedata_reg;
|
||||
|
||||
always @(posedge reconfig_clk) begin
|
||||
pll_locked_sync_1_reg <= pll_locked_in;
|
||||
pll_locked_sync_2_reg <= pll_locked_sync_1_reg;
|
||||
pll_locked_sync_3_reg <= pll_locked_sync_2_reg;
|
||||
end
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
xcvr_reconfig_address_next = xcvr_reconfig_address_reg;
|
||||
xcvr_reconfig_read_next = 1'b0;
|
||||
xcvr_reconfig_write_next = 1'b0;
|
||||
xcvr_reconfig_writedata_next = xcvr_reconfig_writedata_reg;
|
||||
|
||||
read_data_next = read_data_reg;
|
||||
read_data_valid_next = read_data_valid_reg;
|
||||
|
||||
delay_count_next = delay_count_reg;
|
||||
|
||||
if (xcvr_reconfig_read_reg || xcvr_reconfig_write_reg) begin
|
||||
// operation in progress
|
||||
if (xcvr_reconfig_waitrequest) begin
|
||||
// wait state, hold command
|
||||
xcvr_reconfig_read_next = xcvr_reconfig_read_reg;
|
||||
xcvr_reconfig_write_next = xcvr_reconfig_write_reg;
|
||||
end else begin
|
||||
// release command
|
||||
xcvr_reconfig_read_next = 1'b0;
|
||||
xcvr_reconfig_write_next = 1'b0;
|
||||
|
||||
if (xcvr_reconfig_read_reg) begin
|
||||
// latch read data
|
||||
read_data_next = xcvr_reconfig_readdata;
|
||||
read_data_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
state_next = state_reg;
|
||||
end else if (delay_count_reg != 0) begin
|
||||
// stall for delay
|
||||
delay_count_next = delay_count_reg - 1;
|
||||
state_next = state_reg;
|
||||
end else begin
|
||||
read_data_valid_next = 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// wait for PLL to lock
|
||||
if (pll_locked_sync_3_reg) begin
|
||||
delay_count_next = 16'hffff;
|
||||
state_next = STATE_LOAD_PMA_1;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_LOAD_PMA_1: begin
|
||||
// load PMA config
|
||||
xcvr_reconfig_address_next = 19'h40143;
|
||||
xcvr_reconfig_writedata_next = 8'h80;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_LOAD_PMA_2;
|
||||
end
|
||||
STATE_LOAD_PMA_2: begin
|
||||
// check status
|
||||
if (read_data_valid_reg && read_data_reg[0]) begin
|
||||
// start initial adaptation
|
||||
xcvr_reconfig_address_next = 19'h200;
|
||||
xcvr_reconfig_writedata_next = 8'hD2;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_INIT_ADAPT_1;
|
||||
end else begin
|
||||
// read status
|
||||
xcvr_reconfig_address_next = 19'h40144;
|
||||
xcvr_reconfig_read_next = 1'b1;
|
||||
state_next = STATE_LOAD_PMA_2;
|
||||
end
|
||||
end
|
||||
STATE_INIT_ADAPT_1: begin
|
||||
// start initial adaptation
|
||||
xcvr_reconfig_address_next = 19'h201;
|
||||
xcvr_reconfig_writedata_next = 8'h02;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_INIT_ADAPT_2;
|
||||
end
|
||||
STATE_INIT_ADAPT_2: begin
|
||||
// start initial adaptation
|
||||
xcvr_reconfig_address_next = 19'h202;
|
||||
xcvr_reconfig_writedata_next = 8'h01;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_INIT_ADAPT_3;
|
||||
end
|
||||
STATE_INIT_ADAPT_3: begin
|
||||
// start initial adaptation
|
||||
xcvr_reconfig_address_next = 19'h203;
|
||||
xcvr_reconfig_writedata_next = 8'h96;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_INIT_ADAPT_4;
|
||||
end
|
||||
STATE_INIT_ADAPT_4: begin
|
||||
// check status
|
||||
if (read_data_valid_reg && read_data_reg == 8'h80) begin
|
||||
// start continuous adaptation
|
||||
xcvr_reconfig_address_next = 19'h200;
|
||||
xcvr_reconfig_writedata_next = 8'hF6;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_CONT_ADAPT_1;
|
||||
end else begin
|
||||
// read status
|
||||
xcvr_reconfig_address_next = 19'h207;
|
||||
xcvr_reconfig_read_next = 1'b1;
|
||||
state_next = STATE_INIT_ADAPT_4;
|
||||
end
|
||||
end
|
||||
STATE_CONT_ADAPT_1: begin
|
||||
// start continuous adaptation
|
||||
xcvr_reconfig_address_next = 19'h201;
|
||||
xcvr_reconfig_writedata_next = 8'h01;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_CONT_ADAPT_2;
|
||||
end
|
||||
STATE_CONT_ADAPT_2: begin
|
||||
// start continuous adaptation
|
||||
xcvr_reconfig_address_next = 19'h202;
|
||||
xcvr_reconfig_writedata_next = 8'h03;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_CONT_ADAPT_3;
|
||||
end
|
||||
STATE_CONT_ADAPT_3: begin
|
||||
// start continuous adaptation
|
||||
xcvr_reconfig_address_next = 19'h203;
|
||||
xcvr_reconfig_writedata_next = 8'h96;
|
||||
xcvr_reconfig_write_next = 1'b1;
|
||||
state_next = STATE_CONT_ADAPT_4;
|
||||
end
|
||||
STATE_CONT_ADAPT_4: begin
|
||||
// check status
|
||||
if (read_data_valid_reg && read_data_reg == 8'h80) begin
|
||||
// done
|
||||
state_next = STATE_DONE;
|
||||
end else begin
|
||||
// read status
|
||||
xcvr_reconfig_address_next = 19'h207;
|
||||
xcvr_reconfig_read_next = 1'b1;
|
||||
state_next = STATE_CONT_ADAPT_4;
|
||||
end
|
||||
end
|
||||
STATE_DONE: begin
|
||||
// done with operation
|
||||
state_next = STATE_DONE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
if (!pll_locked_sync_3_reg) begin
|
||||
// go back to idle if PLL is unlocked
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge reconfig_clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
xcvr_reconfig_address_reg <= xcvr_reconfig_address_next;
|
||||
xcvr_reconfig_read_reg <= xcvr_reconfig_read_next;
|
||||
xcvr_reconfig_write_reg <= xcvr_reconfig_write_next;
|
||||
xcvr_reconfig_writedata_reg <= xcvr_reconfig_writedata_next;
|
||||
|
||||
read_data_reg <= read_data_next;
|
||||
read_data_valid_reg <= read_data_valid_next;
|
||||
|
||||
delay_count_reg <= delay_count_next;
|
||||
|
||||
if (reconfig_rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
xcvr_reconfig_read_reg <= 1'b0;
|
||||
xcvr_reconfig_write_reg <= 1'b0;
|
||||
|
||||
read_data_valid_reg <= 1'b0;
|
||||
|
||||
delay_count_reg <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
460
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile
Normal file
460
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile
Normal file
@ -0,0 +1,460 @@
|
||||
# Copyright 2020-2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_rx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_tx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT ?= 2
|
||||
export PARAM_PORTS_PER_IF ?= 1
|
||||
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
|
||||
export PARAM_PORT_MASK ?= 0
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_CLK_PERIOD_NS_NUM = 4096
|
||||
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 825
|
||||
export PARAM_PTP_CLOCK_PIPELINE ?= 0
|
||||
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
|
||||
export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
|
||||
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
|
||||
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_PEROUT_ENABLE ?= 1
|
||||
export PARAM_PTP_PEROUT_COUNT ?= 1
|
||||
|
||||
# Queue manager configuration
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
|
||||
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
|
||||
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
|
||||
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE ?= 32
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH ?= 6
|
||||
|
||||
# Interface configuration
|
||||
export PARAM_PTP_TS_ENABLE ?= 1
|
||||
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
|
||||
export PARAM_TX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_RX_RSS_ENABLE ?= 1
|
||||
export PARAM_RX_HASH_ENABLE ?= 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_TX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_RX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_MAX_TX_SIZE ?= 9214
|
||||
export PARAM_MAX_RX_SIZE ?= 9214
|
||||
export PARAM_TX_RAM_SIZE ?= 32768
|
||||
export PARAM_RX_RAM_SIZE ?= 32768
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ID ?= $(shell echo $$((0x00000000)) )
|
||||
export PARAM_APP_ENABLE ?= 0
|
||||
export PARAM_APP_CTRL_ENABLE ?= 1
|
||||
export PARAM_APP_DMA_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE ?= 1
|
||||
export PARAM_APP_STAT_ENABLE ?= 1
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_IMM_ENABLE ?= 0
|
||||
export PARAM_DMA_IMM_WIDTH ?= 32
|
||||
export PARAM_DMA_LEN_WIDTH ?= 16
|
||||
export PARAM_DMA_TAG_WIDTH ?= 16
|
||||
export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
|
||||
export PARAM_RAM_PIPELINE ?= 2
|
||||
|
||||
# PCIe interface configuration
|
||||
export PARAM_SEG_COUNT ?= 2
|
||||
export PARAM_SEG_DATA_WIDTH ?= 256
|
||||
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
|
||||
export PARAM_TX_SEQ_NUM_WIDTH ?= 6
|
||||
export PARAM_PF_COUNT ?= 1
|
||||
export PARAM_VF_COUNT ?= 0
|
||||
export PARAM_PCIE_TAG_COUNT ?= 256
|
||||
export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
|
||||
export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
|
||||
export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
|
||||
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
|
||||
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
|
||||
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
|
||||
|
||||
# Interrupt configuration
|
||||
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE ?= 1
|
||||
export PARAM_STAT_DMA_ENABLE ?= 1
|
||||
export PARAM_STAT_PCIE_ENABLE ?= 1
|
||||
export PARAM_STAT_INC_WIDTH ?= 24
|
||||
export PARAM_STAT_ID_WIDTH ?= 12
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GAPP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT)
|
||||
COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GSEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
|
||||
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
1
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/mqnic.py
Symbolic link
1
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../../common/tb/mqnic.py
|
||||
977
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py
Normal file
977
fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py
Normal file
@ -0,0 +1,977 @@
|
||||
"""
|
||||
|
||||
Copyright 2020-2022, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import scapy.utils
|
||||
from scapy.layers.l2 import Ether
|
||||
from scapy.layers.inet import IP, UDP
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, FallingEdge, Timer
|
||||
|
||||
from cocotbext.axi import AxiStreamBus
|
||||
from cocotbext.eth import EthMac
|
||||
from cocotbext.pcie.core import RootComplex
|
||||
from cocotbext.pcie.intel.ptile import PTilePcieDevice, PTileRxBus, PTileTxBus
|
||||
|
||||
try:
|
||||
import mqnic
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
import mqnic
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut, msix_count=32):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
# PCIe
|
||||
self.rc = RootComplex()
|
||||
|
||||
self.rc.max_payload_size = 0x1 # 256 bytes
|
||||
self.rc.max_read_request_size = 0x2 # 512 bytes
|
||||
|
||||
self.dev = PTilePcieDevice(
|
||||
# configuration options
|
||||
pcie_generation=3,
|
||||
pcie_link_width=16,
|
||||
pld_clk_frequency=250e6,
|
||||
pf_count=1,
|
||||
max_payload_size=512,
|
||||
enable_extended_tag=True,
|
||||
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=msix_count-1,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00010000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00018000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and reset
|
||||
reset_status=dut.rst_250mhz,
|
||||
# reset_status_n=dut.reset_status_n,
|
||||
coreclkout_hip=dut.clk_250mhz,
|
||||
# refclk0=dut.refclk0,
|
||||
# refclk1=dut.refclk1,
|
||||
# pin_perst_n=dut.pin_perst_n,
|
||||
|
||||
# RX interface
|
||||
rx_bus=PTileRxBus.from_prefix(dut, "rx_st"),
|
||||
# rx_par_err=dut.rx_par_err,
|
||||
|
||||
# TX interface
|
||||
tx_bus=PTileTxBus.from_prefix(dut, "tx_st"),
|
||||
# tx_par_err=dut.tx_par_err,
|
||||
|
||||
# RX flow control
|
||||
rx_buffer_limit=dut.rx_buffer_limit,
|
||||
rx_buffer_limit_tdm_idx=dut.rx_buffer_limit_tdm_idx,
|
||||
|
||||
# TX flow control
|
||||
tx_cdts_limit=dut.tx_cdts_limit,
|
||||
tx_cdts_limit_tdm_idx=dut.tx_cdts_limit_tdm_idx,
|
||||
|
||||
# Power management and hard IP status interface
|
||||
# link_up=dut.link_up,
|
||||
# dl_up=dut.dl_up,
|
||||
# surprise_down_err=dut.surprise_down_err,
|
||||
# ltssm_state=dut.ltssm_state,
|
||||
# pm_state=dut.pm_state,
|
||||
# pm_dstate=dut.pm_dstate,
|
||||
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
|
||||
# app_req_retry_en=dut.app_req_retry_en,
|
||||
|
||||
# Interrupt interface
|
||||
# app_int=dut.app_int,
|
||||
# msi_pnd_func=dut.msi_pnd_func,
|
||||
# msi_pnd_byte=dut.msi_pnd_byte,
|
||||
# msi_pnd_addr=dut.msi_pnd_addr,
|
||||
|
||||
# Error interface
|
||||
# serr_out=dut.serr_out,
|
||||
# hip_enter_err_mode=dut.hip_enter_err_mode,
|
||||
# app_err_valid=dut.app_err_valid,
|
||||
# app_err_hdr=dut.app_err_hdr,
|
||||
# app_err_info=dut.app_err_info,
|
||||
# app_err_func_num=dut.app_err_func_num,
|
||||
|
||||
# Completion timeout interface
|
||||
# cpl_timeout=dut.cpl_timeout,
|
||||
# cpl_timeout_avmm_clk=dut.cpl_timeout_avmm_clk,
|
||||
# cpl_timeout_avmm_address=dut.cpl_timeout_avmm_address,
|
||||
# cpl_timeout_avmm_read=dut.cpl_timeout_avmm_read,
|
||||
# cpl_timeout_avmm_readdata=dut.cpl_timeout_avmm_readdata,
|
||||
# cpl_timeout_avmm_readdatavalid=dut.cpl_timeout_avmm_readdatavalid,
|
||||
# cpl_timeout_avmm_write=dut.cpl_timeout_avmm_write,
|
||||
# cpl_timeout_avmm_writedata=dut.cpl_timeout_avmm_writedata,
|
||||
# cpl_timeout_avmm_waitrequest=dut.cpl_timeout_avmm_waitrequest,
|
||||
|
||||
# Configuration output
|
||||
tl_cfg_func=dut.tl_cfg_func,
|
||||
tl_cfg_add=dut.tl_cfg_add,
|
||||
tl_cfg_ctl=dut.tl_cfg_ctl,
|
||||
# dl_timer_update=dut.dl_timer_update,
|
||||
|
||||
# Configuration intercept interface
|
||||
# cii_req=dut.cii_req,
|
||||
# cii_hdr_poisoned=dut.cii_hdr_poisoned,
|
||||
# cii_hdr_first_be=dut.cii_hdr_first_be,
|
||||
# cii_func_num=dut.cii_func_num,
|
||||
# cii_wr_vf_active=dut.cii_wr_vf_active,
|
||||
# cii_vf_num=dut.cii_vf_num,
|
||||
# cii_wr=dut.cii_wr,
|
||||
# cii_addr=dut.cii_addr,
|
||||
# cii_dout=dut.cii_dout,
|
||||
# cii_override_en=dut.cii_override_en,
|
||||
# cii_override_din=dut.cii_override_din,
|
||||
# cii_halt=dut.cii_halt,
|
||||
|
||||
# Hard IP reconfiguration interface
|
||||
# hip_reconfig_clk=dut.hip_reconfig_clk,
|
||||
# hip_reconfig_address=dut.hip_reconfig_address,
|
||||
# hip_reconfig_read=dut.hip_reconfig_read,
|
||||
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
|
||||
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
|
||||
# hip_reconfig_write=dut.hip_reconfig_write,
|
||||
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
|
||||
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
|
||||
|
||||
# Page request service
|
||||
# prs_event_valid=dut.prs_event_valid,
|
||||
# prs_event_func=dut.prs_event_func,
|
||||
# prs_event=dut.prs_event,
|
||||
|
||||
# SR-IOV (VF error)
|
||||
# vf_err_ur_posted_s0=dut.vf_err_ur_posted_s0,
|
||||
# vf_err_ur_posted_s1=dut.vf_err_ur_posted_s1,
|
||||
# vf_err_ur_posted_s2=dut.vf_err_ur_posted_s2,
|
||||
# vf_err_ur_posted_s3=dut.vf_err_ur_posted_s3,
|
||||
# vf_err_func_num_s0=dut.vf_err_func_num_s0,
|
||||
# vf_err_func_num_s1=dut.vf_err_func_num_s1,
|
||||
# vf_err_func_num_s2=dut.vf_err_func_num_s2,
|
||||
# vf_err_func_num_s3=dut.vf_err_func_num_s3,
|
||||
# vf_err_ca_postedreq_s0=dut.vf_err_ca_postedreq_s0,
|
||||
# vf_err_ca_postedreq_s1=dut.vf_err_ca_postedreq_s1,
|
||||
# vf_err_ca_postedreq_s2=dut.vf_err_ca_postedreq_s2,
|
||||
# vf_err_ca_postedreq_s3=dut.vf_err_ca_postedreq_s3,
|
||||
# vf_err_vf_num_s0=dut.vf_err_vf_num_s0,
|
||||
# vf_err_vf_num_s1=dut.vf_err_vf_num_s1,
|
||||
# vf_err_vf_num_s2=dut.vf_err_vf_num_s2,
|
||||
# vf_err_vf_num_s3=dut.vf_err_vf_num_s3,
|
||||
# vf_err_poisonedwrreq_s0=dut.vf_err_poisonedwrreq_s0,
|
||||
# vf_err_poisonedwrreq_s1=dut.vf_err_poisonedwrreq_s1,
|
||||
# vf_err_poisonedwrreq_s2=dut.vf_err_poisonedwrreq_s2,
|
||||
# vf_err_poisonedwrreq_s3=dut.vf_err_poisonedwrreq_s3,
|
||||
# vf_err_poisonedcompl_s0=dut.vf_err_poisonedcompl_s0,
|
||||
# vf_err_poisonedcompl_s1=dut.vf_err_poisonedcompl_s1,
|
||||
# vf_err_poisonedcompl_s2=dut.vf_err_poisonedcompl_s2,
|
||||
# vf_err_poisonedcompl_s3=dut.vf_err_poisonedcompl_s3,
|
||||
# user_vfnonfatalmsg_func_num=dut.user_vfnonfatalmsg_func_num,
|
||||
# user_vfnonfatalmsg_vfnum=dut.user_vfnonfatalmsg_vfnum,
|
||||
# user_sent_vfnonfatalmsg=dut.user_sent_vfnonfatalmsg,
|
||||
# vf_err_overflow=dut.vf_err_overflow,
|
||||
|
||||
# FLR
|
||||
# flr_rcvd_pf=dut.flr_rcvd_pf,
|
||||
# flr_rcvd_vf=dut.flr_rcvd_vf,
|
||||
# flr_rcvd_pf_num=dut.flr_rcvd_pf_num,
|
||||
# flr_rcvd_vf_num=dut.flr_rcvd_vf_num,
|
||||
# flr_completed_pf=dut.flr_completed_pf,
|
||||
# flr_completed_vf=dut.flr_completed_vf,
|
||||
# flr_completed_pf_num=dut.flr_completed_pf_num,
|
||||
# flr_completed_vf_num=dut.flr_completed_vf_num,
|
||||
|
||||
# VirtIO
|
||||
# virtio_pcicfg_vfaccess=dut.virtio_pcicfg_vfaccess,
|
||||
# virtio_pcicfg_vfnum=dut.virtio_pcicfg_vfnum,
|
||||
# virtio_pcicfg_pfnum=dut.virtio_pcicfg_pfnum,
|
||||
# virtio_pcicfg_bar=dut.virtio_pcicfg_bar,
|
||||
# virtio_pcicfg_length=dut.virtio_pcicfg_length,
|
||||
# virtio_pcicfg_baroffset=dut.virtio_pcicfg_baroffset,
|
||||
# virtio_pcicfg_cfgdata=dut.virtio_pcicfg_cfgdata,
|
||||
# virtio_pcicfg_cfgwr=dut.virtio_pcicfg_cfgwr,
|
||||
# virtio_pcicfg_cfgrd=dut.virtio_pcicfg_cfgrd,
|
||||
# virtio_pcicfg_appvfnum=dut.virtio_pcicfg_appvfnum,
|
||||
# virtio_pcicfg_apppfnum=dut.virtio_pcicfg_apppfnum,
|
||||
# virtio_pcicfg_rdack=dut.virtio_pcicfg_rdack,
|
||||
# virtio_pcicfg_rdbe=dut.virtio_pcicfg_rdbe,
|
||||
# virtio_pcicfg_data=dut.virtio_pcicfg_data,
|
||||
)
|
||||
|
||||
# self.dev.log.setLevel(logging.DEBUG)
|
||||
|
||||
self.rc.make_port().connect(self.dev)
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, 4.964, units="ns").start())
|
||||
dut.ptp_rst.setimmediatevalue(0)
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 10, units="ns").start())
|
||||
|
||||
# Ethernet
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_1_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_1_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp1_mac_1 = EthMac(
|
||||
tx_clk=dut.qsfp1_mac_1_tx_clk,
|
||||
tx_rst=dut.qsfp1_mac_1_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_1_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp1_mac_1_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp1_mac_1_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp1_mac_1_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp1_mac_1_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp1_mac_1_rx_clk,
|
||||
rx_rst=dut.qsfp1_mac_1_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_1_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp1_mac_1_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_2_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_2_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp1_mac_2 = EthMac(
|
||||
tx_clk=dut.qsfp1_mac_2_tx_clk,
|
||||
tx_rst=dut.qsfp1_mac_2_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_2_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp1_mac_2_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp1_mac_2_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp1_mac_2_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp1_mac_2_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp1_mac_2_rx_clk,
|
||||
rx_rst=dut.qsfp1_mac_2_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_2_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp1_mac_2_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_3_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_3_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp1_mac_3 = EthMac(
|
||||
tx_clk=dut.qsfp1_mac_3_tx_clk,
|
||||
tx_rst=dut.qsfp1_mac_3_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_3_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp1_mac_3_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp1_mac_3_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp1_mac_3_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp1_mac_3_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp1_mac_3_rx_clk,
|
||||
rx_rst=dut.qsfp1_mac_3_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_3_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp1_mac_3_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_4_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mac_4_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp1_mac_4 = EthMac(
|
||||
tx_clk=dut.qsfp1_mac_4_tx_clk,
|
||||
tx_rst=dut.qsfp1_mac_4_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_4_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp1_mac_4_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp1_mac_4_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp1_mac_4_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp1_mac_4_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp1_mac_4_rx_clk,
|
||||
rx_rst=dut.qsfp1_mac_4_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_4_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp1_mac_4_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_1_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_1_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp2_mac_1 = EthMac(
|
||||
tx_clk=dut.qsfp2_mac_1_tx_clk,
|
||||
tx_rst=dut.qsfp2_mac_1_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_1_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp2_mac_1_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp2_mac_1_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp2_mac_1_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp2_mac_1_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp2_mac_1_rx_clk,
|
||||
rx_rst=dut.qsfp2_mac_1_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_1_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp2_mac_1_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_2_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_2_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp2_mac_2 = EthMac(
|
||||
tx_clk=dut.qsfp2_mac_2_tx_clk,
|
||||
tx_rst=dut.qsfp2_mac_2_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_2_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp2_mac_2_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp2_mac_2_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp2_mac_2_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp2_mac_2_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp2_mac_2_rx_clk,
|
||||
rx_rst=dut.qsfp2_mac_2_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_2_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp2_mac_2_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_3_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_3_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp2_mac_3 = EthMac(
|
||||
tx_clk=dut.qsfp2_mac_3_tx_clk,
|
||||
tx_rst=dut.qsfp2_mac_3_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_3_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp2_mac_3_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp2_mac_3_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp2_mac_3_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp2_mac_3_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp2_mac_3_rx_clk,
|
||||
rx_rst=dut.qsfp2_mac_3_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_3_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp2_mac_3_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_4_rx_clk, 2.482, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mac_4_tx_clk, 2.482, units="ns").start())
|
||||
|
||||
self.qsfp2_mac_4 = EthMac(
|
||||
tx_clk=dut.qsfp2_mac_4_tx_clk,
|
||||
tx_rst=dut.qsfp2_mac_4_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_4_tx_axis"),
|
||||
tx_ptp_time=dut.qsfp2_mac_4_tx_ptp_time,
|
||||
tx_ptp_ts=dut.qsfp2_mac_4_tx_ptp_ts,
|
||||
tx_ptp_ts_tag=dut.qsfp2_mac_4_tx_ptp_ts_tag,
|
||||
tx_ptp_ts_valid=dut.qsfp2_mac_4_tx_ptp_ts_valid,
|
||||
rx_clk=dut.qsfp2_mac_4_rx_clk,
|
||||
rx_rst=dut.qsfp2_mac_4_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_4_rx_axis"),
|
||||
rx_ptp_time=dut.qsfp2_mac_4_rx_ptp_time,
|
||||
ifg=12, speed=10e9
|
||||
)
|
||||
|
||||
dut.qsfp1_mac_1_rx_status.setimmediatevalue(1)
|
||||
dut.qsfp1_mac_2_rx_status.setimmediatevalue(1)
|
||||
dut.qsfp1_mac_3_rx_status.setimmediatevalue(1)
|
||||
dut.qsfp1_mac_4_rx_status.setimmediatevalue(1)
|
||||
|
||||
dut.qsfp2_mac_1_rx_status.setimmediatevalue(1)
|
||||
dut.qsfp2_mac_2_rx_status.setimmediatevalue(1)
|
||||
dut.qsfp2_mac_3_rx_status.setimmediatevalue(1)
|
||||
dut.qsfp2_mac_4_rx_status.setimmediatevalue(1)
|
||||
|
||||
dut.user_pb.setimmediatevalue(0)
|
||||
|
||||
# dut.qsfp0_i2c_scl_i.setimmediatevalue(1)
|
||||
# dut.qsfp0_i2c_sda_i.setimmediatevalue(1)
|
||||
# dut.qsfp0_intr_n.setimmediatevalue(1)
|
||||
# dut.qsfp0_mod_prsnt_n.setimmediatevalue(0)
|
||||
|
||||
# dut.qsfp0_rx_error_count_0.setimmediatevalue(0)
|
||||
# dut.qsfp0_rx_error_count_1.setimmediatevalue(0)
|
||||
# dut.qsfp0_rx_error_count_2.setimmediatevalue(0)
|
||||
# dut.qsfp0_rx_error_count_3.setimmediatevalue(0)
|
||||
|
||||
# dut.qsfp1_i2c_scl_i.setimmediatevalue(1)
|
||||
# dut.qsfp1_i2c_sda_i.setimmediatevalue(1)
|
||||
# dut.qsfp1_intr_n.setimmediatevalue(1)
|
||||
# dut.qsfp1_mod_prsnt_n.setimmediatevalue(0)
|
||||
|
||||
# dut.qsfp1_rx_error_count_0.setimmediatevalue(0)
|
||||
# dut.qsfp1_rx_error_count_1.setimmediatevalue(0)
|
||||
# dut.qsfp1_rx_error_count_2.setimmediatevalue(0)
|
||||
# dut.qsfp1_rx_error_count_3.setimmediatevalue(0)
|
||||
|
||||
# dut.qspi_dq_i.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_1_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_2_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_3_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_3_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_4_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_4_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_1_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_2_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_3_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_3_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_4_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_4_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_1_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_1_tx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_2_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_2_tx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_3_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_3_tx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_4_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp1_mac_4_tx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_1_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_1_tx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_2_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_2_tx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_3_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_3_tx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_4_rx_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp2_mac_4_tx_rst.setimmediatevalue(1)
|
||||
|
||||
await FallingEdge(self.dut.rst_250mhz)
|
||||
await Timer(100, 'ns')
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_1_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_2_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_3_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_3_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_4_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_mac_4_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_1_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_2_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_3_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_3_tx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_4_rx_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp2_mac_4_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
if self.loopback_enable:
|
||||
if not self.qsfp1_mac_1.tx.empty():
|
||||
await self.qsfp1_mac_1.rx.send(await self.qsfp1_mac_1.tx.recv())
|
||||
if not self.qsfp1_mac_2.tx.empty():
|
||||
await self.qsfp1_mac_2.rx.send(await self.qsfp1_mac_2.tx.recv())
|
||||
if not self.qsfp1_mac_3.tx.empty():
|
||||
await self.qsfp1_mac_3.rx.send(await self.qsfp1_mac_3.tx.recv())
|
||||
if not self.qsfp1_mac_4.tx.empty():
|
||||
await self.qsfp1_mac_4.rx.send(await self.qsfp1_mac_4.tx.recv())
|
||||
if not self.qsfp2_mac_1.tx.empty():
|
||||
await self.qsfp2_mac_1.rx.send(await self.qsfp2_mac_1.tx.recv())
|
||||
if not self.qsfp2_mac_2.tx.empty():
|
||||
await self.qsfp2_mac_2.rx.send(await self.qsfp2_mac_2.tx.recv())
|
||||
if not self.qsfp2_mac_3.tx.empty():
|
||||
await self.qsfp2_mac_3.rx.send(await self.qsfp2_mac_3.tx.recv())
|
||||
if not self.qsfp2_mac_4.tx.empty():
|
||||
await self.qsfp2_mac_4.rx.send(await self.qsfp2_mac_4.tx.recv())
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test_nic(dut):
|
||||
|
||||
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
# enable queues
|
||||
tb.log.info("Enable queues")
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
for k in range(tb.driver.interfaces[0].tx_queue_count):
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
|
||||
# wait for all writes to complete
|
||||
await tb.driver.hw_regs.read_dword(0)
|
||||
tb.log.info("Init complete")
|
||||
|
||||
tb.log.info("Send and receive single packet")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.qsfp1_mac_1.tx.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.qsfp1_mac_1.rx.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
# await tb.driver.interfaces[1].start_xmit(data, 0)
|
||||
|
||||
# pkt = await tb.qsfp2_mac_1.tx.recv()
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
|
||||
# await tb.qsfp2_mac_1.rx.send(pkt)
|
||||
|
||||
# pkt = await tb.driver.interfaces[1].recv()
|
||||
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
# assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.log.info("RX and TX checksum tests")
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=2)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
pkt = await tb.qsfp1_mac_1.tx.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.qsfp1_mac_1.rx.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert Ether(pkt.data).build() == test_pkt.build()
|
||||
|
||||
tb.log.info("Queue mapping offset test")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert pkt.queue == k
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
|
||||
for k in range(64):
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=k+0)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
for k in range(64):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
queues.add(pkt.queue)
|
||||
|
||||
assert len(queues) == 4
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
|
||||
os.path.join(eth_rtl_dir, "lfsr.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_perout.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "arbiter.v"),
|
||||
os.path.join(axi_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_demux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_if_rx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_if_tx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = 2
|
||||
parameters['PORTS_PER_IF'] = 1
|
||||
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
|
||||
parameters['PORT_MASK'] = 0
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_CLK_PERIOD_NS_NUM'] = 4096
|
||||
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
|
||||
parameters['PTP_CLOCK_PIPELINE'] = 0
|
||||
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
|
||||
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
|
||||
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
|
||||
parameters['PTP_PORT_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_PEROUT_ENABLE'] = 1
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
|
||||
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
|
||||
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
|
||||
parameters['EVENT_QUEUE_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
|
||||
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Interface configuration
|
||||
parameters['PTP_TS_ENABLE'] = 1
|
||||
parameters['TX_CPL_FIFO_DEPTH'] = 32
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_RSS_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 32768
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 32768
|
||||
parameters['RX_RAM_SIZE'] = 32768
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ID'] = 0x00000000
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_IMM_ENABLE'] = 0
|
||||
parameters['DMA_IMM_WIDTH'] = 32
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
# PCIe interface configuration
|
||||
parameters['SEG_COUNT'] = 2
|
||||
parameters['SEG_DATA_WIDTH'] = 256
|
||||
parameters['SEG_EMPTY_WIDTH'] = ((parameters['SEG_DATA_WIDTH'] // 32) - 1).bit_length()
|
||||
parameters['TX_SEQ_NUM_WIDTH'] = 6
|
||||
parameters['PF_COUNT'] = 1
|
||||
parameters['VF_COUNT'] = 0
|
||||
parameters['PCIE_TAG_COUNT'] = 256
|
||||
parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
|
||||
parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
|
||||
parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
|
||||
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
|
||||
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
|
||||
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
|
||||
|
||||
# Interrupt configuration
|
||||
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 1
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_PCIE_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 12
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user