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fpga/mqnic/520N_MX: Add 25G mqnic design for BittWare 520N-MX

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-06-12 15:36:26 -07:00
parent 9f808c65b2
commit 2c8b1d0e29
32 changed files with 9643 additions and 0 deletions
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# Corundum mqnic for 520N-MX
## Introduction
This design targets the BittWare 520N-MX FPGA development board.
* FPGA: 1SM21CHU2F53E2VG
* PHY: Transceiver in 10G BASE-R native mode
## How to build
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
## How to test
Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.

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../../../app/

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###################################################################
#
# Makefile for Intel Quartus Prime Pro
#
# Alex Forencich
#
###################################################################
#
# Parameters:
# FPGA_TOP - Top module name
# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX)
# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG)
# SYN_FILES - space-separated list of source files
# IP_FILES - space-separated list of IP files
# IP_TCL_FILES - space-separated list of TCL files for qsys-script
# QSF_FILES - space-separated list of settings files
# SDC_FILES - space-separated list of timing constraint files
#
# Example:
#
# FPGA_TOP = fpga
# FPGA_FAMILY = "Stratix 10 DX"
# FPGA_DEVICE = 1SD280PT2F55E1VG
# SYN_FILES = rtl/fpga.v
# QSF_FILES = fpga.qsf
# SDC_FILES = fpga.sdc
# include ../common/quartus_pro.mk
#
###################################################################
# phony targets
.PHONY: clean fpga
# output files to hang on to
.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt
.SECONDARY:
# any project specific settings
CONFIG ?= config.mk
-include ../$(CONFIG)
SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES))
IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES)))
IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES)))
IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES)))
CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
ifdef QSF_FILES
QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p))
else
QSF_FILES_REL = ../$(FPGA_TOP).qsf
endif
SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf
###################################################################
# Main Targets
#
# all: build everything
# clean: remove output files and database
###################################################################
all: fpga
fpga: $(FPGA_TOP).sof
quartus: $(FPGA_TOP).qpf
quartus $(FPGA_TOP).qpf
tmpclean::
-rm -rf defines.v
-rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp
-rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit
-rm -rf create_project.tcl update_config.tcl update_ip_*.tcl
clean:: tmpclean
-rm -rf *.sof *.pof *.jdi *.jic *.map
distclean:: clean
-rm -rf rev
syn: smart.log output_files/$(PROJECT).syn.rpt
fit: smart.log output_files/$(PROJECT).fit.rpt
asm: smart.log output_files/$(PROJECT).asm.rpt
sta: smart.log output_files/$(PROJECT).sta.rpt
smart: smart.log
###################################################################
# Executable Configuration
###################################################################
IP_ARGS = --run_default_mode_op
SYN_ARGS = --read_settings_files=on --write_settings_files=off
FIT_ARGS = --read_settings_files=on --write_settings_files=off
ASM_ARGS = --read_settings_files=on --write_settings_files=off
STA_ARGS =
###################################################################
# Target implementations
###################################################################
STAMP = echo done >
define COPY_IP_RULE
$(patsubst %, ip/%, $(notdir $(1))): $(1)
@mkdir -p ip
@cp -pv $(1) ip/
endef
$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l))))
define TCL_IP_GEN_RULE
$(patsubst %.tcl,%.ip,$(1)): $(1)
cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf}
cd ip && qsys-script --script=$(notdir $(1))
endef
$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l))))
%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP)
%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL)
quartus_syn $(SYN_ARGS) $(FPGA_TOP)
%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL)
quartus_fit $(FIT_ARGS) $(FPGA_TOP)
%.sta.rpt: sta.chg %.fit.rpt
quartus_sta $(STA_ARGS) $(FPGA_TOP)
%.asm.rpt: asm.chg %.sta.rpt
quartus_asm $(ASM_ARGS) $(FPGA_TOP)
mkdir -p rev
EXT=sof; COUNT=100; \
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
do let COUNT=COUNT+1; done; \
cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \
echo "Output: rev/$*_rev$$COUNT.$$EXT";
%.sof: smart.log %.asm.rpt
smart.log: $(ASSIGNMENT_FILES)
quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log
###################################################################
# Project initialization
###################################################################
create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
rm -f update_config.tcl
echo "project_new $(FPGA_TOP) -overwrite" > $@
echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@
echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@
for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \
case $${x##*.} in \
v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\
vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\
qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\
ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\
*) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\
esac; \
done
for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done
for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done
update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL)
echo "project_open $(FPGA_TOP)" > $@
for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done
$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl
for x in $?; do quartus_sh -t "$$x"; done
touch -c $(ASSIGNMENT_FILES)
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg

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# Timing constraints for BittWare 520N-MX
set_time_format -unit ns -decimal_places 3
# Clock constraints
create_clock -name {config_clk} -period 20.000 [ get_ports {config_clk} ]
create_clock -name {usr_refclk0} -period 3.333 [ get_ports {usr_refclk0} ]
create_clock -name {usr_refclk1} -period 3.333 [ get_ports {usr_refclk1} ]
create_clock -name {mem0_refclk} -period 3.333 [ get_ports {mem0_refclk} ]
create_clock -name {mem1_refclk} -period 3.333 [ get_ports {mem1_refclk} ]
create_clock -name {esram_0_refclk} -period 5.000 [ get_ports {esram_0_refclk} ]
create_clock -name {esram_1_refclk} -period 5.000 [ get_ports {esram_1_refclk} ]
create_clock -name {hbm_top_refclk} -period 5.000 [ get_ports {hbm_top_refclk} ]
create_clock -name {hbm_bottom_refclk} -period 5.000 [ get_ports {hbm_bottom_refclk} ]
create_clock -name {pcie_refclk} -period 10.000 [ get_ports {pcie_refclk} ]
create_clock -name {qsfp0_refclk} -period 1.551 [ get_ports {qsfp0_refclk} ]
create_clock -name {qsfp1_refclk} -period 1.551 [ get_ports {qsfp1_refclk} ]
create_clock -name {qsfp2_refclk} -period 1.551 [ get_ports {qsfp2_refclk} ]
create_clock -name {qsfp3_refclk} -period 1.551 [ get_ports {qsfp3_refclk} ]
derive_clock_uncertainty
set_clock_groups -asynchronous -group [ get_clocks {config_clk} ]
set_clock_groups -asynchronous -group [ get_clocks {usr_refclk0} ]
set_clock_groups -asynchronous -group [ get_clocks {usr_refclk1} ]
set_clock_groups -asynchronous -group [ get_clocks {mem0_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {mem1_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {esram_0_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {esram_1_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {hbm_top_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {hbm_bottom_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {pcie_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {qsfp2_refclk} ]
set_clock_groups -asynchronous -group [ get_clocks {qsfp3_refclk} ]
# JTAG constraints
create_clock -name {altera_reserved_tck} -period 62.500 {altera_reserved_tck}
set_clock_groups -asynchronous -group {altera_reserved_tck}
# IO constraints
set_false_path -to "led_user_red[*]"
set_false_path -to "led_user_grn[*]"
set_false_path -to "led_qsfp[*]"
set_false_path -to "uart_rx"
set_false_path -from "uart_tx"
set_false_path -to "fpga_i2c_sda"
set_false_path -from "fpga_i2c_sda"
set_false_path -to "fpga_i2c_scl"
set_false_path -from "fpga_i2c_scl"
set_false_path -to "fpga_i2c_req_l"
set_false_path -from "fpga_i2c_mux_gnt"
set_false_path -from "fpga_gpio_1"
set_false_path -from "fpga_rst_n"
set_false_path -from "pcie_perstn"
set_false_path -from "qsfp_irq_n[*]"
set_false_path -to "oc0_gpio[*]"
set_false_path -from "oc0_gpio[*]"
set_false_path -to "oc0_gpio_dir[*]"
set_false_path -to "oc0_buff_en_n[*]"
set_false_path -to "oc1_gpio[*]"
set_false_path -from "oc1_gpio[*]"
set_false_path -to "oc1_gpio_dir[*]"
set_false_path -to "oc1_buff_en_n[*]"
set_false_path -from "oc2_perst_n"
set_false_path -to "oc2_buff_in_sel"
set_false_path -from "oc3_perst_n"
set_false_path -to "oc3_buff_in_sel"
source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc
source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
# 100 MHz clock
set_clock_groups -asynchronous -group [ get_clocks "iopll_100mhz_inst|iopll_0_outclk0" ]
# clocking infrastructure
constrain_sync_reset_inst "sync_reset_100mhz_inst"
constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
# PTP ref clock
set_clock_groups -asynchronous -group [ get_clocks "ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div4" ]
# PHYs
proc constrain_phy { inst } {
puts "Inserting timing constraints for PHY $inst"
set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|rx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile0|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile0|rx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile1|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile1|rx_clkout|ch0" ]
constrain_sync_reset_inst "$inst|phy_tx_rst_reset_sync_inst"
constrain_sync_reset_inst "$inst|phy_rx_rst_reset_sync_inst"
}
proc constrain_phy_quad { inst } {
puts "Inserting timing constraints for PHY quad $inst"
constrain_phy "${inst}|eth_xcvr_phy_1"
constrain_phy "${inst}|eth_xcvr_phy_2"
constrain_phy "${inst}|eth_xcvr_phy_3"
constrain_phy "${inst}|eth_xcvr_phy_4"
}
constrain_phy_quad "qsfp0_eth_xcvr_phy_quad"
constrain_phy_quad "qsfp1_eth_xcvr_phy_quad"
constrain_phy_quad "qsfp2_eth_xcvr_phy_quad"
constrain_phy_quad "qsfp3_eth_xcvr_phy_quad"

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# FPGA settings
FPGA_TOP = fpga
FPGA_FAMILY = "Stratix 10 MX"
FPGA_DEVICE = 1SM21CHU2F53E2VG
# Files for synthesis
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
SYN_FILES += rtl/common/rx_hash.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += rtl/common/stats_counter.v
SYN_FILES += rtl/common/stats_collect.v
SYN_FILES += rtl/common/stats_pcie_if.v
SYN_FILES += rtl/common/stats_pcie_tlp.v
SYN_FILES += rtl/common/stats_dma_if_pcie.v
SYN_FILES += rtl/common/stats_dma_latency.v
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axil_reg_if.v
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
SYN_FILES += lib/axi/rtl/axil_register_rd.v
SYN_FILES += lib/axi/rtl/axil_register_wr.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
# Workaround for Quartus MLAB RAM read enable bug
# https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html
SYN_FILES += rtl/axis_fifo.v
# SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/irq_rate_limit.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# IP files
IP_TCL_FILES += ip/reset_release.tcl
IP_TCL_FILES += ip/iopll_100mhz.tcl
IP_TCL_FILES += ip/pcie.tcl
IP_TCL_FILES += ip/eth_xcvr_gxt.tcl
IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl
IP_TCL_FILES += ip/eth_xcvr_gxt_pll.tcl
IP_TCL_FILES += ip/eth_xcvr_gxt_buf.tcl
IP_TCL_FILES += ip/eth_xcvr_reset.tcl
IP_TCL_FILES += ip/ref_div.tcl
# QSF files
QSF_FILES = fpga.qsf
# SDC files
SDC_FILES = fpga.sdc
# Configuration
CONFIG_TCL_FILES = ./config.tcl
include ../common/quartus_pro.mk
program: fpga
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"

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# Copyright 2023, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
set params [dict create]
# collect build information
set build_date [clock seconds]
set git_hash 00000000
set git_tag ""
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
puts "Error running git or project not under version control"
}
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
puts "Error running git, project not under version control, or no tag found"
}
puts "Build date: ${build_date}"
puts "Git hash: ${git_hash}"
puts "Git tag: ${git_tag}"
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
puts "Failed to extract version from git tag"
set tag_ver 0.0.1
}
puts "Tag version: ${tag_ver}"
# FW and board IDs
set fpga_id [expr 0x432AC0DD]
set fw_id [expr 0x00000000]
set fw_ver $tag_ver
set board_vendor_id [expr 0x198A]
set board_device_id [expr 0x0521]
set board_ver 1.0
set release_info [expr 0x00000000]
# PCIe IDs
set pcie_vendor_id [expr 0x1234]
set pcie_device_id [expr 0x1001]
set pcie_class_code [expr 0x020000]
set pcie_revision_id [expr 0x00]
set pcie_subsystem_vendor_id $board_vendor_id
set pcie_subsystem_device_id $board_device_id
# FW ID block
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
dict set params FW_ID [format "32'h%08x" $fw_id]
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
dict set params BUILD_DATE "32'd${build_date}"
dict set params GIT_HASH "32'h${git_hash}"
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
# Board configuration
dict set params TDMA_BER_ENABLE "0"
# Structural configuration
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
dict set params PORT_MASK "0"
# Clock configuration
dict set params CLK_PERIOD_NS_NUM "8"
dict set params CLK_PERIOD_NS_DENOM "1"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5"
dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"
dict set params MAX_RX_SIZE "9214"
dict set params TX_RAM_SIZE "32768"
dict set params RX_RAM_SIZE "32768"
# Application block configuration
dict set params APP_ID "32'h00000000"
dict set params APP_ENABLE "0"
dict set params APP_CTRL_ENABLE "1"
dict set params APP_DMA_ENABLE "1"
dict set params APP_AXIS_DIRECT_ENABLE "1"
dict set params APP_AXIS_SYNC_ENABLE "1"
dict set params APP_AXIS_IF_ENABLE "1"
dict set params APP_STAT_ENABLE "1"
# DMA interface configuration
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24"
# AXI lite interface configuration (application control)
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
# Ethernet interface configuration
dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "1"
dict set params AXIS_ETH_TX_PIPELINE "0"
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_XCVR_GXT "1"
# Statistics counter subsystem
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# PCIe IP core settings
set pcie pcie_s10_hip_ast_0
set pcie_ip pcie
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
puts $fp "package require qsys"
puts $fp "load_system ip/${pcie_ip}.ip"
# PCIe IDs
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {$pcie_class_code}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {$pcie_revision_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
# PCIe IP core configuration
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
# configure BAR settings
proc configure_bar {fp pcie pf bar aperture} {
if {$aperture > 0} {
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
return
}
puts "PF${pf} BAR${bar}: disabled"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
}
# Control BAR (BAR 0)
configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
# Application BAR (BAR 2)
configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
puts $fp "sync_sysinfo_parameters"
puts $fp "save_system"
close $fp
# apply parameters to PCIe IP core
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
# apply parameters to top-level
dict for {name value} $params {
set_parameter -name $name $value
}

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# FPGA settings
FPGA_TOP = fpga
FPGA_FAMILY = "Stratix 10 MX"
FPGA_DEVICE = 1SM21CHU2F53E2VG
# Files for synthesis
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
SYN_FILES += rtl/common/rx_hash.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += rtl/common/stats_counter.v
SYN_FILES += rtl/common/stats_collect.v
SYN_FILES += rtl/common/stats_pcie_if.v
SYN_FILES += rtl/common/stats_pcie_tlp.v
SYN_FILES += rtl/common/stats_dma_if_pcie.v
SYN_FILES += rtl/common/stats_dma_latency.v
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axil_reg_if.v
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
SYN_FILES += lib/axi/rtl/axil_register_rd.v
SYN_FILES += lib/axi/rtl/axil_register_wr.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
# Workaround for Quartus MLAB RAM read enable bug
# https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html
SYN_FILES += rtl/axis_fifo.v
# SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/irq_rate_limit.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# IP files
IP_TCL_FILES += ip/reset_release.tcl
IP_TCL_FILES += ip/iopll_100mhz.tcl
IP_TCL_FILES += ip/pcie.tcl
IP_TCL_FILES += ip/eth_xcvr_gx.tcl
IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl
IP_TCL_FILES += ip/eth_xcvr_reset.tcl
IP_TCL_FILES += ip/ref_div.tcl
# QSF files
QSF_FILES = fpga.qsf
# SDC files
SDC_FILES = fpga.sdc
# Configuration
CONFIG_TCL_FILES = ./config.tcl
include ../common/quartus_pro.mk
program: fpga
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"

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# Copyright 2021, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
set params [dict create]
# collect build information
set build_date [clock seconds]
set git_hash 00000000
set git_tag ""
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
puts "Error running git or project not under version control"
}
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
puts "Error running git, project not under version control, or no tag found"
}
puts "Build date: ${build_date}"
puts "Git hash: ${git_hash}"
puts "Git tag: ${git_tag}"
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
puts "Failed to extract version from git tag"
set tag_ver 0.0.1
}
puts "Tag version: ${tag_ver}"
# FW and board IDs
set fpga_id [expr 0x432AC0DD]
set fw_id [expr 0x00000000]
set fw_ver $tag_ver
set board_vendor_id [expr 0x198A]
set board_device_id [expr 0x0521]
set board_ver 1.0
set release_info [expr 0x00000000]
# PCIe IDs
set pcie_vendor_id [expr 0x1234]
set pcie_device_id [expr 0x1001]
set pcie_class_code [expr 0x020000]
set pcie_revision_id [expr 0x00]
set pcie_subsystem_vendor_id $board_vendor_id
set pcie_subsystem_device_id $board_device_id
# FW ID block
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
dict set params FW_ID [format "32'h%08x" $fw_id]
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
dict set params BUILD_DATE "32'd${build_date}"
dict set params GIT_HASH "32'h${git_hash}"
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
# Board configuration
dict set params TDMA_BER_ENABLE "0"
# Structural configuration
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
dict set params PORT_MASK "0"
# Clock configuration
dict set params CLK_PERIOD_NS_NUM "8"
dict set params CLK_PERIOD_NS_DENOM "1"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5"
dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Interface configuration
dict set params PTP_TS_ENABLE "1"
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "32768"
dict set params MAX_TX_SIZE "9214"
dict set params MAX_RX_SIZE "9214"
dict set params TX_RAM_SIZE "32768"
dict set params RX_RAM_SIZE "32768"
# Application block configuration
dict set params APP_ID "32'h00000000"
dict set params APP_ENABLE "0"
dict set params APP_CTRL_ENABLE "1"
dict set params APP_DMA_ENABLE "1"
dict set params APP_AXIS_DIRECT_ENABLE "1"
dict set params APP_AXIS_SYNC_ENABLE "1"
dict set params APP_AXIS_IF_ENABLE "1"
dict set params APP_STAT_ENABLE "1"
# DMA interface configuration
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24"
# AXI lite interface configuration (application control)
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
# Ethernet interface configuration
dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "0"
dict set params AXIS_ETH_TX_PIPELINE "0"
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_XCVR_GXT "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# PCIe IP core settings
set pcie pcie_s10_hip_ast_0
set pcie_ip pcie
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
puts $fp "package require qsys"
puts $fp "load_system ip/${pcie_ip}.ip"
# PCIe IDs
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {$pcie_class_code}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {$pcie_revision_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
# PCIe IP core configuration
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
# configure BAR settings
proc configure_bar {fp pcie pf bar aperture} {
if {$aperture > 0} {
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
return
}
puts "PF${pf} BAR${bar}: disabled"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}"
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
}
# Control BAR (BAR 0)
configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
# Application BAR (BAR 2)
configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
puts $fp "sync_sysinfo_parameters"
puts $fp "save_system"
close $fp
# apply parameters to PCIe IP core
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
# apply parameters to top-level
dict for {name value} $params {
set_parameter -name $name $value
}

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package require -exact qsys 21.3
# create the system "eth_xcvr_gx"
proc do_create_eth_xcvr_gx {} {
# create the system
create_system eth_xcvr_gx
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance xcvr_native_s10_htile_0 altera_xcvr_native_s10_htile
set_instance_parameter_value xcvr_native_s10_htile_0 {adapter_ehip_mode} {disable_hip}
set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_link} {lr}
set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_voltage} {1_1V}
set_instance_parameter_value xcvr_native_s10_htile_0 {avmm_ehip_mode} {disable_hip}
set_instance_parameter_value xcvr_native_s10_htile_0 {base_device} {Unknown}
set_instance_parameter_value xcvr_native_s10_htile_0 {bonded_mode} {not_bonded}
set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_cnt} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_select} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {channel_type} {GX}
set_instance_parameter_value xcvr_native_s10_htile_0 {channels} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout2_sel} {clock_delay_measurement_clkout}
set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout_sel} {clock_delay_measurement_clkout}
set_instance_parameter_value xcvr_native_s10_htile_0 {design_environment} {NATIVE}
set_instance_parameter_value xcvr_native_s10_htile_0 {design_example_filename} {dexample}
set_instance_parameter_value xcvr_native_s10_htile_0 {disable_digital_reset_sequencer} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {disable_reset_sequencer} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {duplex_mode} {duplex}
set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t1} {60}
set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t2} {150}
set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t3} {1000}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_advanced_user_mode} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_background_cal_gui} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_channel_powerdown} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_de_hardware_debug} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_debug_ports} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_direct_reset_control} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_double_rate_transfer} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_early_spd_chng} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ehip} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_fast_sim} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hard_reset} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hip} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_insert_eios_err} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_mac_total_control} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_manual_bonding_settings} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_clock_delay_measurement} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame_diag_status} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_tx_enh_frame} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_latency_measurement} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2_hioint} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout_hioint} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_data_valid} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_bitslip} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_blk_lock} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_clr_errblk_count} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_crc32_err} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_diag_status} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_lock} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber_clr_cnt} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_align_clr} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_del} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_empty} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_full} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_insert} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_latency_adj_ena} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pempty} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pfull} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_rd_en} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtodata} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtoref} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_empty} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_full} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_clkslip} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_iqtxrx_clkout} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_qpipulldn} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_polinv} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_seriallpbken} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitrev_ena} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslip} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslipboundarysel} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_byterev_ena} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_empty} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_full} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_signaldetect} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_a1a2size} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_patternalign} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2_hioint} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout_hioint} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_dll_lock} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_bitslip} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_burst_en} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_diag_status} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_empty} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_full} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_latency_adj_ena} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pempty} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pfull} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_empty} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_full} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_elecidle} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_iqtxrx_clkout} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipulldn} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipullup} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_rxfound} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_txdetectrx} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_polinv} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_std_bitslipboundarysel} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_adaptation} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_hclk} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_rx_elecidle} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_sw} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_manual_cdr_mode} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_prbs} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_async_transfer} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_mode} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rcfg_tx_digitalreset_release_ctrl} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rx_fast_pipeln_reg} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_simple_interface} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_split_interface} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_transparent_pcs} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_coreclkin2} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_fast_pipeln_reg} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_workaround_rules} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_advanced_user_mode} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_low_latency_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pcs_pma_width} {64}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pld_pcs_width} {66}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_64b66b_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_bitslip_enable} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_blksync_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_crcchk_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_descram_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_dispchk_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_mfrm_length} {2048}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_type} {10G}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_polinv_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_64b66b_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_bitslip_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcerr_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcgen_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_dispgen_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_burst_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_mfrm_length} {2048}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_len} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_polinv_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_randomdispbit_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_sh_err} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {generate_add_hdl_instance_example} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {generate_docs} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {hip_channels} {x1}
set_instance_parameter_value xcvr_native_s10_htile_0 {hip_mode} {disable_hip}
set_instance_parameter_value xcvr_native_s10_htile_0 {hip_prot_mode} {gen1}
set_instance_parameter_value xcvr_native_s10_htile_0 {loopback_tx_clk_sel} {internal_clk}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_comp_cnt} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_mode} {individual}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_comp_cnt} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_mode} {individual}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_indv} {indv_en}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_comp_cnt} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_mode} {individual}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_indv} {indv_en}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_comp_cnt} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_mode} {individual}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_indv} {indv_en}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_comp_cnt} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_mode} {individual}
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_indv} {indv_en}
set_instance_parameter_value xcvr_native_s10_htile_0 {message_level} {error}
set_instance_parameter_value xcvr_native_s10_htile_0 {number_physical_bonding_clocks} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {osc_clk_divider} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_rx_dv_mode} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_tx_dv_mode} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {parallel_loopback_mode} {disable}
set_instance_parameter_value xcvr_native_s10_htile_0 {pcie_rate_match} {Bypass}
set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_direct_width} {8}
set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_reset_sequencing_mode} {not_bonded}
set_instance_parameter_value xcvr_native_s10_htile_0 {pll_select} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {plls} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {pma_mode} {basic}
set_instance_parameter_value xcvr_native_s10_htile_0 {protocol_mode} {basic_enh}
set_instance_parameter_value xcvr_native_s10_htile_0 {qsf_assignments_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_debug} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_rcfg_10}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_files_as_common_package} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_h_file_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_iface_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_jtag_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_mif_file_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_multi_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_cnt} {2}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data0} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data1} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data2} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data3} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data4} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data5} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data6} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data7} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_select} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_reduced_files_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_separate_avmm_busy} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_shared} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sv_file_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_txt_file_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_use_clk_reset_only} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {reduced_reset_sim_time} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout2_sel} {pcs_clkout}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout_sel} {pma_div_clkout}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_coreclkin_clock_network} {dedicated}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_ac_gain} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_eq_gain} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_align_del} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_control_del} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_mode} {Phase compensation}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pempty} {2}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pfull} {10}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_mode} {ctle_dfe}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_start_gui} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_analog_mode} {user_custom}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_div_clkout_divider} {33}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r4}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ppm_detect_threshold} {1000}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_vga_dc_gain} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_capability_reg_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_freq} {644.531250}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_receiver_detect_src} {iqclk}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_csr_soft_logic_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_data_rate} {10312.5}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_embedded_debug_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_calibration} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_eios_rx_protect} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_hip_cal_en} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_odi_soft_logic_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_pcs_bonding_master} {Auto}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_prbs_soft_logic_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_user_identifier} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_low_latency_bypass_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_pcs_pma_width} {10}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_8b10b_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_bitrev_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byte_deser_mode} {Disabled}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byterev_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_polinv_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_mode} {disabled}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_n} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_p} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_fast_sync_status_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_mode} {bitslip}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern} {0.0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern_len} {7}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_renumber} {3}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rgnumber} {3}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rknumber} {3}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rvnumber} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_disp_ctrl_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitrev_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitslip_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byte_ser_mode} {Disabled}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byterev_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_polinv_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {support_mode} {user_mode}
set_instance_parameter_value xcvr_native_s10_htile_0 {suppress_design_example_messages} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {tile_type_suffix} {}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout2_sel} {pcs_clkout}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout_sel} {pma_div_clkout}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_coreclkin_clock_network} {dedicated}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_mode} {Phase compensation}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pempty} {2}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pfull} {10}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pcs_bonding_clock_network} {dedicated}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_refclk} {644.53125}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_type} {ATX}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_analog_mode} {user_custom}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_clk_div} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_compensation_en} {enable}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_div_clkout_divider} {33}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_optimal_settings} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_output_swing_ctrl} {31}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_1st_post_tap} {negative}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_pre_tap_1t} {negative}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_1st_post_tap} {6}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_pre_tap_1t} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_slew_rate_ctrl} {5}
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_term_sel} {r_r1}
set_instance_parameter_value xcvr_native_s10_htile_0 {use_rx_clkout2} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {use_tx_clkout2} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {usr_rx_dv_mode} {enable}
set_instance_parameter_value xcvr_native_s10_htile_0 {usr_tx_dv_mode} {enable}
set_instance_parameter_value xcvr_native_s10_htile_0 {validation_rule_select} {}
set_instance_property xcvr_native_s10_htile_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property tx_analogreset EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset
set_interface_property rx_analogreset EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset
set_interface_property tx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset
set_interface_property rx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset
set_interface_property tx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset_stat
set_interface_property rx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset_stat
set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset_stat
set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset_stat
set_interface_property tx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.tx_cal_busy
set_interface_property rx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.rx_cal_busy
set_interface_property tx_serial_clk0 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk0
set_interface_property rx_cdr_refclk0 EXPORT_OF xcvr_native_s10_htile_0.rx_cdr_refclk0
set_interface_property tx_serial_data EXPORT_OF xcvr_native_s10_htile_0.tx_serial_data
set_interface_property rx_serial_data EXPORT_OF xcvr_native_s10_htile_0.rx_serial_data
set_interface_property rx_is_lockedtoref EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtoref
set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtodata
set_interface_property tx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.tx_coreclkin
set_interface_property rx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.rx_coreclkin
set_interface_property tx_clkout EXPORT_OF xcvr_native_s10_htile_0.tx_clkout
set_interface_property tx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.tx_clkout2
set_interface_property rx_clkout EXPORT_OF xcvr_native_s10_htile_0.rx_clkout
set_interface_property rx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.rx_clkout2
set_interface_property tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.tx_parallel_data
set_interface_property tx_control EXPORT_OF xcvr_native_s10_htile_0.tx_control
set_interface_property tx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.tx_enh_data_valid
set_interface_property unused_tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_tx_parallel_data
set_interface_property rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.rx_parallel_data
set_interface_property rx_control EXPORT_OF xcvr_native_s10_htile_0.rx_control
set_interface_property rx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.rx_enh_data_valid
set_interface_property unused_rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_rx_parallel_data
set_interface_property rx_bitslip EXPORT_OF xcvr_native_s10_htile_0.rx_bitslip
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="xcvr_native_s10_htile_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {eth_xcvr_gx.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {eth_xcvr_gx}
# save the system
sync_sysinfo_parameters
save_system eth_xcvr_gx
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_eth_xcvr_gx
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx_pll.tcl Normal file
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package require -exact qsys 21.3
# create the system "eth_xcvr_gx_pll"
proc do_create_eth_xcvr_gx_pll {} {
# create the system
create_system eth_xcvr_gx_pll
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance xcvr_fpll_s10_htile_0 altera_xcvr_fpll_s10_htile
set_instance_parameter_value xcvr_fpll_s10_htile_0 {base_device} {Unknown}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_analog_resets} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_bonding_clks} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_debug_ports_parameters} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_fb_comp_bonding} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_hfreq_clk} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_hip_cal_done_port} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_manual_configuration} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_hip_cal_done_port} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_pcie_clksw} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_reset} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pcie_hip_connectivity} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pld_fpll_cal_busy_port} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {generate_add_hdl_instance_example} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {generate_docs} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {mcgb_aux_clkin_cnt} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {mcgb_div} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {message_level} {error}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {outclk_en} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {pma_width} {64}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {powerdown_mode} {powerup}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_debug} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_fpll_s10}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_files_as_common_package} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_h_file_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_jtag_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_mif_file_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_multi_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_cnt} {2}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data0} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data1} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data2} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data3} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data4} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data5} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data6} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data7} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_select} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_reduced_files_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_separate_avmm_busy} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sv_file_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_txt_file_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {select_manual_config} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_altera_xcvr_fpll_s10_calibration_en} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_bw_sel} {medium}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_capability_reg_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_csr_soft_logic_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_dps} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_fractional} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_hclk_out} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_fref_clock_frequency} {100.0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_hip_cal_en} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_initial_phase_shift} {0.0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_initial_phase_shift_units} {degrees}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_c_counter} {4}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_k_counter} {1.0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_l_counter} {2}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_m_counter} {50}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_output_clock_frequency} {2500.0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_ref_clk_div} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_reference_clock_frequency} {100.0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_output_clock_frequency} {5156.25}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_power_mode} {1_1V}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_primary_use} {2}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_prot_mode} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_refclk_cnt} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_refclk_index} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_user_identifier} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x1_core_clock} {1}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x2_core_clock} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x4_core_clock} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {silicon_rev} {0}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {support_mode} {user_mode}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {test_mode} {false}
set_instance_parameter_value xcvr_fpll_s10_htile_0 {usr_enable_vco_bypass} {0}
set_instance_property xcvr_fpll_s10_htile_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property pll_refclk0 EXPORT_OF xcvr_fpll_s10_htile_0.pll_refclk0
set_interface_property tx_serial_clk EXPORT_OF xcvr_fpll_s10_htile_0.tx_serial_clk
set_interface_property pll_locked EXPORT_OF xcvr_fpll_s10_htile_0.pll_locked
set_interface_property pll_cal_busy EXPORT_OF xcvr_fpll_s10_htile_0.pll_cal_busy
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="xcvr_fpll_s10_htile_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {eth_xcvr_gx_pll.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {eth_xcvr_gx_pll}
# save the system
sync_sysinfo_parameters
save_system eth_xcvr_gx_pll
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_eth_xcvr_gx_pll
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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package require -exact qsys 21.3
# create the system "eth_xcvr_gxt_buf"
proc do_create_eth_xcvr_gxt_buf {} {
# create the system
create_system eth_xcvr_gxt_buf
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {atx_blw}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_bonding_clks} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_cascade_out} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_debug_ports_parameters} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_ext_lockdetect_ports} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_fb_comp_bonding} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hfreq_clk} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hip_cal_done_port} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_manual_configuration} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_pcie_clksw} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_reset} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_clk} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_hip_connectivity} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_atx_cal_busy_port} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pll_lock} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_vco_bypass} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {generate_add_hdl_instance_example} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_aux_clkin_cnt} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GXT clock output buffer}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_atx_pll_s10}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_files_as_common_package} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_h_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_jtag_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_mif_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_multi_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_cnt} {2}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data0} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data1} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data2} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data3} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data4} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data5} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data6} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data7} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_select} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_reduced_files_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_separate_avmm_busy} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sv_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_txt_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_cnt} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_index} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_altera_xcvr_atx_pll_s10_calibration_en} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_capability_reg_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_csr_soft_logic_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_fref_clock_frequency} {156.25}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_hip_cal_en} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_k_counter} {1.0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_counter} {4}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_predivider} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {12890.625}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {silicon_rev} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {support_mode} {user_mode}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {test_mode} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {usr_analog_voltage} {1_1V}
set_instance_property xcvr_atx_pll_s10_htile_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0
set_interface_property tx_serial_clk_gxt EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk_gxt
set_interface_property gxt_input_from_blw_atx EXPORT_OF xcvr_atx_pll_s10_htile_0.gxt_input_from_blw_atx
set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked
set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="xcvr_atx_pll_s10_htile_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {eth_xcvr_gxt_buf.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {eth_xcvr_gxt_buf}
# save the system
sync_sysinfo_parameters
save_system eth_xcvr_gxt_buf
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_eth_xcvr_gxt_buf
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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package require -exact qsys 21.3
# create the system "eth_xcvr_gxt_pll"
proc do_create_eth_xcvr_gxt_pll {} {
# create the system
create_system eth_xcvr_gxt_pll
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {atx_lcl}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_bonding_clks} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_cascade_out} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_debug_ports_parameters} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_ext_lockdetect_ports} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_fb_comp_bonding} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hfreq_clk} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hip_cal_done_port} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_manual_configuration} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_pcie_clksw} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_reset} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_clk} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_hip_connectivity} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_atx_cal_busy_port} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pll_lock} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_vco_bypass} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {generate_add_hdl_instance_example} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_aux_clkin_cnt} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GXT clock output buffer}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_atx_pll_s10}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_files_as_common_package} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_h_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_jtag_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_mif_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_multi_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_cnt} {2}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data0} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data1} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data2} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data3} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data4} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data5} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data6} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data7} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_select} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_reduced_files_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_separate_avmm_busy} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sv_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_txt_file_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_cnt} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_index} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_altera_xcvr_atx_pll_s10_calibration_en} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_capability_reg_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_csr_soft_logic_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_fref_clock_frequency} {156.25}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_hip_cal_en} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_k_counter} {1.0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_counter} {4}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_predivider} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {12890.625}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {silicon_rev} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {support_mode} {user_mode}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {test_mode} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {usr_analog_voltage} {1_1V}
set_instance_property xcvr_atx_pll_s10_htile_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0
set_interface_property tx_serial_clk_gxt EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk_gxt
set_interface_property gxt_output_to_abv_atx EXPORT_OF xcvr_atx_pll_s10_htile_0.gxt_output_to_abv_atx
set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked
set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="xcvr_atx_pll_s10_htile_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {eth_xcvr_gxt_pll.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {eth_xcvr_gxt_pll}
# save the system
sync_sysinfo_parameters
save_system eth_xcvr_gxt_pll
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_eth_xcvr_gxt_pll
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_reset.tcl Normal file
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package require -exact qsys 20.4
# create the system "eth_xcvr_reset"
proc do_create_eth_xcvr_reset {} {
# create the system
create_system eth_xcvr_reset
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance xcvr_reset_control_s10_0 altera_xcvr_reset_control_s10
set_instance_parameter_value xcvr_reset_control_s10_0 {CHANNELS} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {ENABLE_DIGITAL_SEQ} {0}
set_instance_parameter_value xcvr_reset_control_s10_0 {PLLS} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {REDUCED_SIM_TIME} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {RX_ENABLE} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {RX_MANUAL_RESET} {0}
set_instance_parameter_value xcvr_reset_control_s10_0 {RX_PER_CHANNEL} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {SYS_CLK_IN_MHZ} {300}
set_instance_parameter_value xcvr_reset_control_s10_0 {TILE_TYPE} {h_tile}
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_ENABLE} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_MANUAL_RESET} {0}
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PER_CHANNEL} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PLL_ENABLE} {0}
set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_LOCK_HYST} {0}
set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_POWERDOWN} {1000}
set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_ANALOGRESET} {40}
set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_DIGITALRESET} {5000}
set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_ANALOGRESET} {0}
set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_DIGITALRESET} {20}
set_instance_parameter_value xcvr_reset_control_s10_0 {gui_pll_cal_busy} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {gui_split_interfaces} {0}
set_instance_property xcvr_reset_control_s10_0 AUTO_EXPORT true
# add wirelevel expressions
# add the exports
set_interface_property clock EXPORT_OF xcvr_reset_control_s10_0.clock
set_interface_property reset EXPORT_OF xcvr_reset_control_s10_0.reset
set_interface_property tx_analogreset EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset
set_interface_property tx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset
set_interface_property tx_ready EXPORT_OF xcvr_reset_control_s10_0.tx_ready
set_interface_property pll_locked EXPORT_OF xcvr_reset_control_s10_0.pll_locked
set_interface_property pll_select EXPORT_OF xcvr_reset_control_s10_0.pll_select
set_interface_property tx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.tx_cal_busy
set_interface_property tx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset_stat
set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset_stat
set_interface_property pll_cal_busy EXPORT_OF xcvr_reset_control_s10_0.pll_cal_busy
set_interface_property rx_analogreset EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset
set_interface_property rx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset
set_interface_property rx_ready EXPORT_OF xcvr_reset_control_s10_0.rx_ready
set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_reset_control_s10_0.rx_is_lockedtodata
set_interface_property rx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.rx_cal_busy
set_interface_property rx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset_stat
set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset_stat
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="xcvr_reset_control_s10_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {eth_xcvr_reset.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {eth_xcvr_reset}
# save the system
sync_sysinfo_parameters
save_system eth_xcvr_reset
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_eth_xcvr_reset
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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fpga/mqnic/520N_MX/fpga_25g/ip/iopll_100mhz.tcl Normal file
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package require -exact qsys 21.3
# create the system "iopll_100mhz"
proc do_create_iopll_100mhz {} {
# create the system
create_system iopll_100mhz
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance iopll_0 altera_iopll
set_instance_parameter_value iopll_0 {gui_active_clk} {0}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src2} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src3} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src4} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src5} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src6} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src7} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src8} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_cal_code_hex_file} {iossm.hex}
set_instance_parameter_value iopll_0 {gui_cal_converge} {0}
set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean}
set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter10} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter11} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter12} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter13} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter14} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter15} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter16} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter17} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter2} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter3} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter4} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter5} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter6} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter7} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter8} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter9} {0}
set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0}
set_instance_parameter_value iopll_0 {gui_clk_bad} {0}
set_instance_parameter_value iopll_0 {gui_clock_name_global} {0}
set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0}
set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1}
set_instance_parameter_value iopll_0 {gui_clock_name_string10} {outclk10}
set_instance_parameter_value iopll_0 {gui_clock_name_string11} {outclk11}
set_instance_parameter_value iopll_0 {gui_clock_name_string12} {outclk12}
set_instance_parameter_value iopll_0 {gui_clock_name_string13} {outclk13}
set_instance_parameter_value iopll_0 {gui_clock_name_string14} {outclk14}
set_instance_parameter_value iopll_0 {gui_clock_name_string15} {outclk15}
set_instance_parameter_value iopll_0 {gui_clock_name_string16} {outclk16}
set_instance_parameter_value iopll_0 {gui_clock_name_string17} {outclk17}
set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2}
set_instance_parameter_value iopll_0 {gui_clock_name_string3} {outclk3}
set_instance_parameter_value iopll_0 {gui_clock_name_string4} {outclk4}
set_instance_parameter_value iopll_0 {gui_clock_name_string5} {outclk5}
set_instance_parameter_value iopll_0 {gui_clock_name_string6} {outclk6}
set_instance_parameter_value iopll_0 {gui_clock_name_string7} {outclk7}
set_instance_parameter_value iopll_0 {gui_clock_name_string8} {outclk8}
set_instance_parameter_value iopll_0 {gui_clock_name_string9} {outclk9}
set_instance_parameter_value iopll_0 {gui_clock_to_compensate} {0}
set_instance_parameter_value iopll_0 {gui_debug_mode} {0}
set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c10} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c11} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c12} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c13} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c14} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c15} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c16} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c17} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c3} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c4} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c5} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c6} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c7} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c8} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c9} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_n} {1}
set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0}
set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive}
set_instance_parameter_value iopll_0 {gui_dps_num} {1}
set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order}
set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle10} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle11} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle12} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle13} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle14} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle15} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle16} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle17} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle2} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle3} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle4} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle5} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle6} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle7} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle8} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle9} {50.0}
set_instance_parameter_value iopll_0 {gui_en_adv_params} {0}
set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_iossm_reconf} {0}
set_instance_parameter_value iopll_0 {gui_en_lvds_ports} {Disabled}
set_instance_parameter_value iopll_0 {gui_en_periphery_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_reconf} {0}
set_instance_parameter_value iopll_0 {gui_enable_cascade_in} {0}
set_instance_parameter_value iopll_0 {gui_enable_cascade_out} {0}
set_instance_parameter_value iopll_0 {gui_enable_mif_dps} {0}
set_instance_parameter_value iopll_0 {gui_enable_output_counter_cascading} {0}
set_instance_parameter_value iopll_0 {gui_enable_permit_cal} {0}
set_instance_parameter_value iopll_0 {gui_enable_upstream_out_clk} {0}
set_instance_parameter_value iopll_0 {gui_existing_mif_file_path} {~/pll.mif}
set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0}
set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0}
set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock}
set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0}
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0}
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1667.0}
set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0}
set_instance_parameter_value iopll_0 {gui_fractional_cout} {32}
set_instance_parameter_value iopll_0 {gui_include_iossm} {0}
set_instance_parameter_value iopll_0 {gui_location_type} {I/O Bank}
set_instance_parameter_value iopll_0 {gui_lock_setting} {Low Lock Time}
set_instance_parameter_value iopll_0 {gui_mif_config_name} {unnamed}
set_instance_parameter_value iopll_0 {gui_mif_gen_options} {Generate New MIF File}
set_instance_parameter_value iopll_0 {gui_multiply_factor} {6}
set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif}
set_instance_parameter_value iopll_0 {gui_number_of_clocks} {1}
set_instance_parameter_value iopll_0 {gui_operation_mode} {direct}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency12} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency13} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency14} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency15} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency16} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency17} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency3} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency4} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency5} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency6} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps12} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps13} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps14} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps15} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps16} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps17} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps3} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps4} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps5} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps6} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps7} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps8} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps9} {10000.0}
set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex}
set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift10} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift11} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift12} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift13} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift14} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift15} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift16} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift17} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift2} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift3} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift4} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift5} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift6} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift7} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift8} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift9} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg0} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg1} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg10} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg11} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg12} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg13} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg14} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg15} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg16} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg17} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg2} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg3} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg4} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg5} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg6} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg7} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg8} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg9} {0.0}
set_instance_parameter_value iopll_0 {gui_phout_division} {1}
set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {1}
set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Low}
set_instance_parameter_value iopll_0 {gui_pll_cal_done} {0}
set_instance_parameter_value iopll_0 {gui_pll_cascading_mode} {adjpllin}
set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1}
set_instance_parameter_value iopll_0 {gui_pll_freqcal_req_flag} {1}
set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL}
set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0}
set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src}
set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple}
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_band18}
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_band18}
set_instance_parameter_value iopll_0 {gui_prot_mode} {UNUSED}
set_instance_parameter_value iopll_0 {gui_ps_units0} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units1} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units10} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units11} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units12} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units13} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units14} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units15} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units16} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units17} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units2} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units3} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units4} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units5} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units6} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units7} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units8} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units9} {ps}
set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0}
set_instance_parameter_value iopll_0 {gui_refclk_might_change} {0}
set_instance_parameter_value iopll_0 {gui_refclk_switch} {0}
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {300.0}
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {3333.333}
set_instance_parameter_value iopll_0 {gui_simulation_type} {0}
set_instance_parameter_value iopll_0 {gui_skip_sdc_generation} {0}
set_instance_parameter_value iopll_0 {gui_switchover_delay} {0}
set_instance_parameter_value iopll_0 {gui_switchover_mode} {Automatic Switchover}
set_instance_parameter_value iopll_0 {gui_use_NDFB_modes} {0}
set_instance_parameter_value iopll_0 {gui_use_coreclk} {0}
set_instance_parameter_value iopll_0 {gui_use_locked} {1}
set_instance_parameter_value iopll_0 {gui_use_logical} {0}
set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1}
set_instance_parameter_value iopll_0 {gui_vco_frequency} {600.0}
set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0}
set_instance_parameter_value iopll_0 {system_info_device_iobank_rev} {}
set_instance_property iopll_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property reset EXPORT_OF iopll_0.reset
set_interface_property refclk EXPORT_OF iopll_0.refclk
set_interface_property locked EXPORT_OF iopll_0.locked
set_interface_property outclk0 EXPORT_OF iopll_0.outclk0
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="iopll_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {iopll_100mhz.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {iopll_100mhz}
# save the system
sync_sysinfo_parameters
save_system iopll_100mhz
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_iopll_100mhz
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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fpga/mqnic/520N_MX/fpga_25g/ip/pcie.tcl Normal file
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package require -exact qsys 21.3
# create the system "pcie"
proc do_create_pcie {} {
# create the system
create_system pcie
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {false}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance pcie_s10_hip_ast_0 altera_pcie_s10_hip_ast
set_instance_parameter_value pcie_s10_hip_ast_0 {anlg_voltage} {1_1V}
set_instance_parameter_value pcie_s10_hip_ast_0 {apps_type_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_clk_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_control_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_npor_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_pipe_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {ceb_extend_pcie_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {chosen_devkit_hwtcl} {Stratix 10 MX H-Tile Production FPGA Development Kit}
set_instance_parameter_value pcie_s10_hip_ast_0 {cvp_user_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {design_environment} {NATIVE}
set_instance_parameter_value pcie_s10_hip_ast_0 {device_ctrl_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {disable_256_to_512_adapter_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {eios_workaround_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_avst_reset_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_qii_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_sim_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_sim_rp_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_synth_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_synth_rp_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_tb_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_multi_func_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pcie_cv_fix} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pipe32_phyip_ser_driver_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pld_warm_rst_rdy_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_rx_buffer_limit_ports_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_sriov_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_test_out_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {hip_reconfig_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {hrc_rstctl_timer_g_delay_added_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {msi_info_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pcie_link_inspector_avmm_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pcie_link_inspector_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_auto_lane_flip_ctrl_en_hwtcl} {enable}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar0_address_width_hwtcl} {24}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar0_type_hwtcl} {64-bit prefetchable memory}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_class_code_hwtcl} {131072}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_eq_eieos_cnt_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_expansion_base_address_register_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_loopback_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msi_multiple_msg_cap_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_bir_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_offset_hwtcl} {12288.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_offset_hwtcl} {8192.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_hwtcl} {31}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_device_id_hwtcl} {4097}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_vendor_id_hwtcl} {4660}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ep_l1_accpt_latency_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ext_tag_supp_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_flr_cap_user_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_phy_slot_num_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_port_num_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_sel_deemphasis_hwtcl} {6dB}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_clk_config_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_power_limit_value_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_slot_imp_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_revision_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar0_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar0_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_device_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_subsys_dev_id_hwtcl} {1313}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_subsys_vendor_id_hwtcl} {6538}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_size_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_count_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar0_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar0_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_class_code_hwtcl} {16711680}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_expansion_base_address_register_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msi_multiple_msg_cap_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_bir_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_pba_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_pba_offset_hwtcl} {0.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_offset_hwtcl} {0.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_size_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_type0_device_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_type0_vendor_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_revision_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar0_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar0_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_device_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_subsys_dev_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_subsys_vendor_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_size_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_count_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar0_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar0_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_class_code_hwtcl} {16711680}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_expansion_base_address_register_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msi_multiple_msg_cap_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_bir_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_pba_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_pba_offset_hwtcl} {0.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_offset_hwtcl} {0.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_size_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_type0_device_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_type0_vendor_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_revision_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar0_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar0_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_device_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_subsys_dev_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_subsys_vendor_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_size_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_count_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar0_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar0_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_class_code_hwtcl} {16711680}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_expansion_base_address_register_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msi_multiple_msg_cap_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_bir_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_pba_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_pba_offset_hwtcl} {0.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_offset_hwtcl} {0.0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_size_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_type0_device_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_type0_vendor_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_revision_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar0_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar0_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar1_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar1_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar2_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar2_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar3_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar3_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar4_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar4_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar5_address_width_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar5_type_hwtcl} {Disabled}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_device_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_subsys_dev_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_subsys_vendor_id_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_size_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_count_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_st_dev_spec_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_st_int_mode_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {pll_refclk_freq_hwtcl} {100 MHz}
set_instance_parameter_value pcie_s10_hip_ast_0 {select_design_example_hwtcl} {PIO}
set_instance_parameter_value pcie_s10_hip_ast_0 {select_design_example_rtl_lang_hwtcl} {Verilog}
set_instance_parameter_value pcie_s10_hip_ast_0 {select_example_design_sim_BFM_hwtcl} {Intel FPGA BFM}
set_instance_parameter_value pcie_s10_hip_ast_0 {serial_sim_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {targeted_devkit_hwtcl} {NONE}
set_instance_parameter_value pcie_s10_hip_ast_0 {total_pf_count_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {use_ast_parity_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {use_pll_lock_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {use_rpbfm_pro} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_ep_native_hwtcl} {Native}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_maxpayload_size_hwtcl} {1024}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msi_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msix_enable_hwtcl} {1}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msi_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msix_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_msi_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_msix_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_ats_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_msi_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_msix_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_tph_cap_enable_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_rp_ep_mode_hwtcl} {Native Endpoint}
set_instance_parameter_value pcie_s10_hip_ast_0 {wrala_hwtcl} {Gen2x8, Interface - 256 bit, 125 MHz}
set_instance_parameter_value pcie_s10_hip_ast_0 {xcvr_adme_hwtcl} {0}
set_instance_parameter_value pcie_s10_hip_ast_0 {xcvr_reconfig_hwtcl} {0}
set_instance_property pcie_s10_hip_ast_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property refclk EXPORT_OF pcie_s10_hip_ast_0.refclk
set_interface_property coreclkout_hip EXPORT_OF pcie_s10_hip_ast_0.coreclkout_hip
set_interface_property npor EXPORT_OF pcie_s10_hip_ast_0.npor
set_interface_property hip_rst EXPORT_OF pcie_s10_hip_ast_0.hip_rst
set_interface_property clr_st EXPORT_OF pcie_s10_hip_ast_0.clr_st
set_interface_property ninit_done EXPORT_OF pcie_s10_hip_ast_0.ninit_done
set_interface_property rx_st EXPORT_OF pcie_s10_hip_ast_0.rx_st
set_interface_property tx_st EXPORT_OF pcie_s10_hip_ast_0.tx_st
set_interface_property rx_bar EXPORT_OF pcie_s10_hip_ast_0.rx_bar
set_interface_property tx_cred EXPORT_OF pcie_s10_hip_ast_0.tx_cred
set_interface_property int_msi EXPORT_OF pcie_s10_hip_ast_0.int_msi
set_interface_property hip_status EXPORT_OF pcie_s10_hip_ast_0.hip_status
set_interface_property config_tl EXPORT_OF pcie_s10_hip_ast_0.config_tl
set_interface_property hip_ctrl EXPORT_OF pcie_s10_hip_ast_0.hip_ctrl
set_interface_property currentspeed EXPORT_OF pcie_s10_hip_ast_0.currentspeed
set_interface_property hip_pipe EXPORT_OF pcie_s10_hip_ast_0.hip_pipe
set_interface_property hip_serial EXPORT_OF pcie_s10_hip_ast_0.hip_serial
set_interface_property power_mgnt EXPORT_OF pcie_s10_hip_ast_0.power_mgnt
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="pcie_s10_hip_ast_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {pcie.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {pcie}
# save the system
sync_sysinfo_parameters
save_system pcie
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_pcie
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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fpga/mqnic/520N_MX/fpga_25g/ip/ref_div.tcl Normal file
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package require -exact qsys 21.3
# create the system "ref_div"
proc do_create_ref_div {} {
# create the system
create_system ref_div
set_project_property DEVICE {1SM21CHU1F53E1VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance stratix10_clkctrl_0 stratix10_clkctrl
set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER} {1}
set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER_OUTPUTS} {3}
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE} {0}
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_REGISTER_TYPE} {1}
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_TYPE} {2}
set_instance_parameter_value stratix10_clkctrl_0 {GLITCH_FREE_SWITCHOVER} {0}
set_instance_parameter_value stratix10_clkctrl_0 {NUM_CLOCKS} {1}
set_instance_property stratix10_clkctrl_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property inclk EXPORT_OF stratix10_clkctrl_0.inclk
set_interface_property clock_div1x EXPORT_OF stratix10_clkctrl_0.clock_div1x
set_interface_property clock_div2x EXPORT_OF stratix10_clkctrl_0.clock_div2x
set_interface_property clock_div4x EXPORT_OF stratix10_clkctrl_0.clock_div4x
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="stratix10_clkctrl_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {ref_div.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {ref_div}
# save the system
sync_sysinfo_parameters
save_system ref_div
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_ref_div
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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package require -exact qsys 20.4
# create the system "reset_release"
proc do_create_reset_release {} {
# create the system
create_system reset_release
set_project_property DEVICE {1SM21CHU2F53E2VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate
set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface}
set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true
# add wirelevel expressions
# add the exports
set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="s10_user_rst_clkgate_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {reset_release.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {reset_release}
# save the system
sync_sysinfo_parameters
save_system reset_release
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_reset_release
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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/*
Copyright (c) 2013-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO
*/
module axis_fifo #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter OUTPUT_FIFO_ENABLE = 0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_WHEN_FULL = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire status_overflow,
output wire status_bad_frame,
output wire status_good_frame
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
// check configuration
initial begin
if (FRAME_FIFO && !LAST_ENABLE) begin
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
$finish;
end
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin
$error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
$finish;
end
end
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
// (* ramstyle = "no_rw_check" *)
// Workaround for Quartus MLAB RAM read enable bug
// https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html
(* ramstyle = "no_rw_check, m20k" *)
reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg mem_read_data_valid_reg = 1'b0;
(* shreg_extract = "no" *)
reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0];
reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0;
// full when first MSB different but rest same
wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
wire full_cur = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
// empty when pointers match exactly
wire empty = wr_ptr_reg == rd_ptr_reg;
// overflow within packet
wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
reg drop_frame_reg = 1'b0;
reg send_frame_reg = 1'b0;
reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
assign s_axis_tready = FRAME_FIFO ? (!full_cur || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : !full;
wire [WIDTH-1:0] s_axis;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
endgenerate
wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1];
wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1];
wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0];
wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
wire pipe_ready;
assign status_overflow = overflow_reg;
assign status_bad_frame = bad_frame_reg;
assign status_good_frame = good_frame_reg;
// Write logic
always @(posedge clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if (!FRAME_FIFO) begin
// normal FIFO mode
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
end else if ((full_cur && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_cur_reg <= wr_ptr_reg;
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// store it
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_cur_reg <= wr_ptr_cur_reg + 1;
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
// end of frame or send frame
send_frame_reg <= !s_axis_tlast;
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer
wr_ptr_cur_reg <= wr_ptr_reg;
bad_frame_reg <= 1'b1;
end else begin
// good packet or packet overflow, update write pointer
wr_ptr_reg <= wr_ptr_cur_reg + 1;
good_frame_reg <= s_axis_tlast;
end
end
end
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_reg <= wr_ptr_cur_reg;
end
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
drop_frame_reg <= 1'b0;
send_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// Read logic
integer j;
always @(posedge clk) begin
if (OUTPUT_FIFO_ENABLE || m_axis_tready) begin
// output ready; invalidate stage
m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
end
for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
if (OUTPUT_FIFO_ENABLE || m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin
// output ready or bubble in pipeline; transfer down pipeline
m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
end
end
if (OUTPUT_FIFO_ENABLE || m_axis_tready || ~m_axis_tvalid_pipe_reg) begin
// output ready or bubble in pipeline; read new data from FIFO
m_axis_tvalid_pipe_reg[0] <= 1'b0;
m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
if (!empty && pipe_ready) begin
// not empty, increment pointer
m_axis_tvalid_pipe_reg[0] <= 1'b1;
rd_ptr_reg <= rd_ptr_reg + 1;
end
end
if (rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
m_axis_tvalid_pipe_reg <= 0;
end
end
generate
if (!OUTPUT_FIFO_ENABLE) begin
assign pipe_ready = 1'b1;
assign m_axis_tvalid = m_axis_tvalid_pipe;
assign m_axis_tdata = m_axis_tdata_pipe;
assign m_axis_tkeep = m_axis_tkeep_pipe;
assign m_axis_tlast = m_axis_tlast_pipe;
assign m_axis_tid = m_axis_tid_pipe;
assign m_axis_tdest = m_axis_tdest_pipe;
assign m_axis_tuser = m_axis_tuser_pipe;
end else begin
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign pipe_ready = !out_fifo_half_full_reg;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
if (!out_fifo_full && m_axis_tvalid_pipe) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe;
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe;
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tvalid_reg <= 1'b1;
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
endgenerate
endmodule
`resetall

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/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver and PHY quad wrapper
*/
module eth_xcvr_phy_quad_wrapper #
(
parameter GXT = 0,
// PHY parameters
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 32,
parameter BITSLIP_LOW_CYCLES = 32,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Common
*/
input wire xcvr_ref_clk,
/*
* Serial data
*/
output wire [3:0] xcvr_tx_serial_data,
input wire [3:0] xcvr_rx_serial_data,
/*
* PHY connections
*/
output wire phy_1_tx_clk,
output wire phy_1_tx_rst,
input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc,
output wire phy_1_rx_clk,
output wire phy_1_rx_rst,
output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc,
output wire phy_1_tx_bad_block,
output wire [6:0] phy_1_rx_error_count,
output wire phy_1_rx_bad_block,
output wire phy_1_rx_sequence_error,
output wire phy_1_rx_block_lock,
output wire phy_1_rx_high_ber,
output wire phy_1_rx_status,
input wire phy_1_tx_prbs31_enable,
input wire phy_1_rx_prbs31_enable,
output wire phy_2_tx_clk,
output wire phy_2_tx_rst,
input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc,
output wire phy_2_rx_clk,
output wire phy_2_rx_rst,
output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc,
output wire phy_2_tx_bad_block,
output wire [6:0] phy_2_rx_error_count,
output wire phy_2_rx_bad_block,
output wire phy_2_rx_sequence_error,
output wire phy_2_rx_block_lock,
output wire phy_2_rx_high_ber,
output wire phy_2_rx_status,
input wire phy_2_tx_prbs31_enable,
input wire phy_2_rx_prbs31_enable,
output wire phy_3_tx_clk,
output wire phy_3_tx_rst,
input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc,
output wire phy_3_rx_clk,
output wire phy_3_rx_rst,
output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc,
output wire phy_3_tx_bad_block,
output wire [6:0] phy_3_rx_error_count,
output wire phy_3_rx_bad_block,
output wire phy_3_rx_sequence_error,
output wire phy_3_rx_block_lock,
output wire phy_3_rx_high_ber,
output wire phy_3_rx_status,
input wire phy_3_tx_prbs31_enable,
input wire phy_3_rx_prbs31_enable,
output wire phy_4_tx_clk,
output wire phy_4_tx_rst,
input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc,
output wire phy_4_rx_clk,
output wire phy_4_rx_rst,
output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc,
output wire phy_4_tx_bad_block,
output wire [6:0] phy_4_rx_error_count,
output wire phy_4_rx_bad_block,
output wire phy_4_rx_sequence_error,
output wire phy_4_rx_block_lock,
output wire phy_4_rx_high_ber,
output wire phy_4_rx_status,
input wire phy_4_tx_prbs31_enable,
input wire phy_4_rx_prbs31_enable
);
wire xcvr_gx_pll_locked;
wire xcvr_gx_pll_cal_busy;
wire xcvr_gxt_pll_locked;
wire xcvr_gxt_pll_cal_busy;
wire xcvr_tx_serial_gx_clk;
wire [1:0] xcvr_tx_serial_gxt_clk;
eth_xcvr_gx_pll eth_xcvr_gx_pll_inst (
.pll_refclk0 (xcvr_ref_clk),
.tx_serial_clk (xcvr_tx_serial_gx_clk),
.pll_locked (xcvr_gx_pll_locked),
.pll_cal_busy (xcvr_gx_pll_cal_busy)
);
generate
if (GXT) begin
wire atx_pll_cascade_clk;
eth_xcvr_gxt_pll eth_xcvr_gxt_pll_inst (
.pll_refclk0 (xcvr_ref_clk),
.tx_serial_clk_gxt (xcvr_tx_serial_gxt_clk[0]),
.gxt_output_to_abv_atx (atx_pll_cascade_clk),
.pll_locked (xcvr_gxt_pll_locked),
.pll_cal_busy (xcvr_gxt_pll_cal_busy)
);
eth_xcvr_gxt_buf eth_xcvr_gxt_buf_inst (
.pll_refclk0 (xcvr_ref_clk),
.tx_serial_clk_gxt (xcvr_tx_serial_gxt_clk[1]),
.gxt_input_from_blw_atx (atx_pll_cascade_clk),
.pll_locked (),
.pll_cal_busy ()
);
end else begin
assign xcvr_tx_serial_gxt_clk = 2'b00;
assign xcvr_gxt_pll_locked = 1'b1;
assign xcvr_gxt_pll_cal_busy = 1'b0;
end
endgenerate
eth_xcvr_phy_wrapper #(
.GXT(GXT),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_1 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Transceiver connections
.xcvr_gx_pll_locked(xcvr_gx_pll_locked),
.xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
.xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
.xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
.xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
.xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[0]),
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
.xcvr_tx_serial_data(xcvr_tx_serial_data[0]),
.xcvr_rx_serial_data(xcvr_rx_serial_data[0]),
// PHY connections
.phy_tx_clk(phy_1_tx_clk),
.phy_tx_rst(phy_1_tx_rst),
.phy_xgmii_txd(phy_1_xgmii_txd),
.phy_xgmii_txc(phy_1_xgmii_txc),
.phy_rx_clk(phy_1_rx_clk),
.phy_rx_rst(phy_1_rx_rst),
.phy_xgmii_rxd(phy_1_xgmii_rxd),
.phy_xgmii_rxc(phy_1_xgmii_rxc),
.phy_tx_bad_block(phy_1_tx_bad_block),
.phy_rx_error_count(phy_1_rx_error_count),
.phy_rx_bad_block(phy_1_rx_bad_block),
.phy_rx_sequence_error(phy_1_rx_sequence_error),
.phy_rx_block_lock(phy_1_rx_block_lock),
.phy_rx_high_ber(phy_1_rx_high_ber),
.phy_rx_status(phy_1_rx_status),
.phy_tx_prbs31_enable(phy_1_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_1_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
.GXT(GXT),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_2 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Transceiver connections
.xcvr_gx_pll_locked(xcvr_gx_pll_locked),
.xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
.xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
.xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
.xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
.xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[0]),
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
.xcvr_tx_serial_data(xcvr_tx_serial_data[1]),
.xcvr_rx_serial_data(xcvr_rx_serial_data[1]),
// PHY connections
.phy_tx_clk(phy_2_tx_clk),
.phy_tx_rst(phy_2_tx_rst),
.phy_xgmii_txd(phy_2_xgmii_txd),
.phy_xgmii_txc(phy_2_xgmii_txc),
.phy_rx_clk(phy_2_rx_clk),
.phy_rx_rst(phy_2_rx_rst),
.phy_xgmii_rxd(phy_2_xgmii_rxd),
.phy_xgmii_rxc(phy_2_xgmii_rxc),
.phy_tx_bad_block(phy_2_tx_bad_block),
.phy_rx_error_count(phy_2_rx_error_count),
.phy_rx_bad_block(phy_2_rx_bad_block),
.phy_rx_sequence_error(phy_2_rx_sequence_error),
.phy_rx_block_lock(phy_2_rx_block_lock),
.phy_rx_high_ber(phy_2_rx_high_ber),
.phy_rx_status(phy_2_rx_status),
.phy_tx_prbs31_enable(phy_2_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_2_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
.GXT(GXT),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_3 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Transceiver connections
.xcvr_gx_pll_locked(xcvr_gx_pll_locked),
.xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
.xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
.xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
.xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
.xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[1]),
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
.xcvr_tx_serial_data(xcvr_tx_serial_data[2]),
.xcvr_rx_serial_data(xcvr_rx_serial_data[2]),
// PHY connections
.phy_tx_clk(phy_3_tx_clk),
.phy_tx_rst(phy_3_tx_rst),
.phy_xgmii_txd(phy_3_xgmii_txd),
.phy_xgmii_txc(phy_3_xgmii_txc),
.phy_rx_clk(phy_3_rx_clk),
.phy_rx_rst(phy_3_rx_rst),
.phy_xgmii_rxd(phy_3_xgmii_rxd),
.phy_xgmii_rxc(phy_3_xgmii_rxc),
.phy_tx_bad_block(phy_3_tx_bad_block),
.phy_rx_error_count(phy_3_rx_error_count),
.phy_rx_bad_block(phy_3_rx_bad_block),
.phy_rx_sequence_error(phy_3_rx_sequence_error),
.phy_rx_block_lock(phy_3_rx_block_lock),
.phy_rx_high_ber(phy_3_rx_high_ber),
.phy_rx_status(phy_3_rx_status),
.phy_tx_prbs31_enable(phy_3_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_3_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
.GXT(GXT),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_4 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Transceiver connections
.xcvr_gx_pll_locked(xcvr_gx_pll_locked),
.xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
.xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
.xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
.xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
.xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[1]),
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
.xcvr_tx_serial_data(xcvr_tx_serial_data[3]),
.xcvr_rx_serial_data(xcvr_rx_serial_data[3]),
// PHY connections
.phy_tx_clk(phy_4_tx_clk),
.phy_tx_rst(phy_4_tx_rst),
.phy_xgmii_txd(phy_4_xgmii_txd),
.phy_xgmii_txc(phy_4_xgmii_txc),
.phy_rx_clk(phy_4_rx_clk),
.phy_rx_rst(phy_4_rx_rst),
.phy_xgmii_rxd(phy_4_xgmii_rxd),
.phy_xgmii_rxc(phy_4_xgmii_rxc),
.phy_tx_bad_block(phy_4_tx_bad_block),
.phy_rx_error_count(phy_4_rx_error_count),
.phy_rx_bad_block(phy_4_rx_bad_block),
.phy_rx_sequence_error(phy_4_rx_sequence_error),
.phy_rx_block_lock(phy_4_rx_block_lock),
.phy_rx_high_ber(phy_4_rx_high_ber),
.phy_rx_status(phy_4_rx_status),
.phy_tx_prbs31_enable(phy_4_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_4_rx_prbs31_enable)
);
endmodule
`resetall

330
fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_wrapper.v Normal file
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@ -0,0 +1,330 @@
/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver and PHY wrapper
*/
module eth_xcvr_phy_wrapper #
(
parameter GXT = 0,
// PHY parameters
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 32,
parameter BITSLIP_LOW_CYCLES = 32,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Transceiver connections
*/
input wire xcvr_gx_pll_locked,
input wire xcvr_gxt_pll_locked,
input wire xcvr_gx_pll_cal_busy,
input wire xcvr_gxt_pll_cal_busy,
input wire xcvr_tx_serial_gx_clk,
input wire xcvr_tx_serial_gxt_clk,
input wire xcvr_rx_cdr_refclk,
output wire xcvr_tx_serial_data,
input wire xcvr_rx_serial_data,
/*
* PHY connections
*/
output wire phy_tx_clk,
output wire phy_tx_rst,
input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
output wire phy_rx_clk,
output wire phy_rx_rst,
output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
output wire phy_tx_bad_block,
output wire [6:0] phy_rx_error_count,
output wire phy_rx_bad_block,
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
output wire phy_rx_status,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
);
wire xcvr_tx_analogreset;
wire xcvr_rx_analogreset;
wire xcvr_tx_digitalreset;
wire xcvr_rx_digitalreset;
wire xcvr_tx_analogreset_stat;
wire xcvr_rx_analogreset_stat;
wire xcvr_tx_digitalreset_stat;
wire xcvr_rx_digitalreset_stat;
wire xcvr_tx_cal_busy;
wire xcvr_rx_cal_busy;
wire xcvr_rx_is_lockedtoref;
wire xcvr_rx_is_lockedtodata;
wire xcvr_tx_ready;
wire xcvr_rx_ready;
wire xcvr_tx_clk;
wire xcvr_rx_clk;
assign phy_tx_clk = xcvr_tx_clk;
assign phy_rx_clk = xcvr_rx_clk;
wire [1:0] xcvr_tx_hdr;
wire [DATA_WIDTH-1:0] xcvr_tx_data;
wire [1:0] xcvr_rx_hdr;
wire [DATA_WIDTH-1:0] xcvr_rx_data;
wire [1:0] phy_tx_hdr;
wire [DATA_WIDTH-1:0] phy_tx_data;
wire [1:0] phy_rx_hdr;
wire [DATA_WIDTH-1:0] phy_rx_data;
assign {xcvr_tx_hdr, xcvr_tx_data} = {phy_tx_data, phy_tx_hdr};
assign {phy_rx_data, phy_rx_hdr} = {xcvr_rx_hdr, xcvr_rx_data};
wire xcvr_rx_bitslip;
wire phy_rx_reset_req;
wire phy_rx_reset_req_sync;
sync_reset #(
.N(4)
)
phy_rx_rst_req_reset_sync_inst (
.clk(xcvr_ctrl_clk),
.rst(phy_rx_reset_req),
.out(phy_rx_reset_req_sync)
);
eth_xcvr_reset eth_xcvr_reset_inst (
.clock (xcvr_ctrl_clk),
.reset (xcvr_ctrl_rst),
.tx_analogreset (xcvr_tx_analogreset),
.tx_digitalreset (xcvr_tx_digitalreset),
.tx_ready (xcvr_tx_ready),
.pll_locked (xcvr_gx_pll_locked && (GXT || xcvr_gxt_pll_locked)),
.pll_select (1'b0),
.tx_cal_busy (xcvr_tx_cal_busy),
.tx_analogreset_stat (xcvr_tx_analogreset_stat),
.tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
.pll_cal_busy (xcvr_gx_pll_cal_busy || (GXT && xcvr_gxt_pll_cal_busy)),
.rx_analogreset (xcvr_rx_analogreset),
.rx_digitalreset (xcvr_rx_digitalreset),
.rx_ready (xcvr_rx_ready),
.rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
.rx_cal_busy (xcvr_rx_cal_busy || phy_rx_reset_req_sync),
.rx_analogreset_stat (xcvr_rx_analogreset_stat),
.rx_digitalreset_stat (xcvr_rx_digitalreset_stat)
);
generate
if (GXT) begin
eth_xcvr_gxt eth_xcvr_inst (
.tx_analogreset (xcvr_tx_analogreset),
.rx_analogreset (xcvr_rx_analogreset),
.tx_digitalreset (xcvr_tx_digitalreset),
.rx_digitalreset (xcvr_rx_digitalreset),
.tx_analogreset_stat (xcvr_tx_analogreset_stat),
.rx_analogreset_stat (xcvr_rx_analogreset_stat),
.tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
.rx_digitalreset_stat (xcvr_rx_digitalreset_stat),
.tx_cal_busy (xcvr_tx_cal_busy),
.rx_cal_busy (xcvr_rx_cal_busy),
.tx_serial_clk0 (xcvr_tx_serial_gxt_clk),
.tx_serial_clk1 (xcvr_tx_serial_gx_clk),
.rx_cdr_refclk0 (xcvr_rx_cdr_refclk),
.tx_serial_data (xcvr_tx_serial_data),
.rx_serial_data (xcvr_rx_serial_data),
.rx_is_lockedtoref (xcvr_rx_is_lockedtoref),
.rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
.tx_coreclkin (xcvr_tx_clk),
.rx_coreclkin (xcvr_rx_clk),
.tx_clkout (xcvr_tx_clk),
.tx_clkout2 (),
.rx_clkout (xcvr_rx_clk),
.rx_clkout2 (),
.tx_parallel_data (xcvr_tx_data),
.tx_control (xcvr_tx_hdr),
.tx_enh_data_valid (1'b1),
.unused_tx_parallel_data (13'd0),
.rx_parallel_data (xcvr_rx_data),
.rx_control (xcvr_rx_hdr),
.rx_enh_data_valid (),
.unused_rx_parallel_data (),
.rx_bitslip (xcvr_rx_bitslip),
.reconfig_clk (xcvr_ctrl_clk),
.reconfig_reset (xcvr_ctrl_rst),
.reconfig_write (1'b0),
.reconfig_read (1'b0),
.reconfig_address (11'd0),
.reconfig_writedata (32'd0),
.reconfig_readdata (),
.reconfig_waitrequest ()
);
end else begin
eth_xcvr_gx eth_xcvr_inst (
.tx_analogreset (xcvr_tx_analogreset),
.rx_analogreset (xcvr_rx_analogreset),
.tx_digitalreset (xcvr_tx_digitalreset),
.rx_digitalreset (xcvr_rx_digitalreset),
.tx_analogreset_stat (xcvr_tx_analogreset_stat),
.rx_analogreset_stat (xcvr_rx_analogreset_stat),
.tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
.rx_digitalreset_stat (xcvr_rx_digitalreset_stat),
.tx_cal_busy (xcvr_tx_cal_busy),
.rx_cal_busy (xcvr_rx_cal_busy),
.tx_serial_clk0 (xcvr_tx_serial_gx_clk),
.rx_cdr_refclk0 (xcvr_rx_cdr_refclk),
.tx_serial_data (xcvr_tx_serial_data),
.rx_serial_data (xcvr_rx_serial_data),
.rx_is_lockedtoref (xcvr_rx_is_lockedtoref),
.rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
.tx_coreclkin (xcvr_tx_clk),
.rx_coreclkin (xcvr_rx_clk),
.tx_clkout (xcvr_tx_clk),
.tx_clkout2 (),
.rx_clkout (xcvr_rx_clk),
.rx_clkout2 (),
.tx_parallel_data (xcvr_tx_data),
.tx_control (xcvr_tx_hdr),
.tx_enh_data_valid (1'b1),
.unused_tx_parallel_data (13'd0),
.rx_parallel_data (xcvr_rx_data),
.rx_control (xcvr_rx_hdr),
.rx_enh_data_valid (),
.unused_rx_parallel_data (),
.rx_bitslip (xcvr_rx_bitslip)
);
end
endgenerate
wire phy_tx_rst_int;
reg phy_tx_rst_reg = 1'b0;
sync_reset #(
.N(4)
)
phy_tx_rst_reset_sync_inst (
.clk(phy_tx_clk),
.rst(~xcvr_tx_ready),
.out(phy_tx_rst_int)
);
always @(posedge phy_tx_clk) begin
phy_tx_rst_reg <= phy_tx_rst_int;
end
assign phy_tx_rst = phy_tx_rst_reg;
wire phy_rx_rst_int;
reg phy_rx_rst_reg = 1'b0;
sync_reset #(
.N(4)
)
phy_rx_rst_reset_sync_inst (
.clk(phy_rx_clk),
.rst(~xcvr_rx_ready),
.out(phy_rx_rst_int)
);
always @(posedge phy_rx_clk) begin
phy_rx_rst_reg <= phy_rx_rst_int;
end
assign phy_rx_rst = phy_rx_rst_reg;
eth_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(0),
.SCRAMBLER_DISABLE(0),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
phy_inst (
.tx_clk(phy_tx_clk),
.tx_rst(phy_tx_rst),
.rx_clk(phy_rx_clk),
.rx_rst(phy_rx_rst),
.xgmii_txd(phy_xgmii_txd),
.xgmii_txc(phy_xgmii_txc),
.xgmii_rxd(phy_xgmii_rxd),
.xgmii_rxc(phy_xgmii_rxc),
.serdes_tx_data(phy_tx_data),
.serdes_tx_hdr(phy_tx_hdr),
.serdes_rx_data(phy_rx_data),
.serdes_rx_hdr(phy_rx_hdr),
.serdes_rx_bitslip(xcvr_rx_bitslip),
.serdes_rx_reset_req(phy_rx_reset_req),
.tx_bad_block(phy_tx_bad_block),
.rx_error_count(phy_rx_error_count),
.rx_bad_block(phy_rx_bad_block),
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.rx_status(phy_rx_status),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
);
endmodule
`resetall

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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1 ns / 1 ps
`default_nettype none
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
`resetall

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# Copyright 2020-2023, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
TOPLEVEL_LANG = verilog
SIM ?= icarus
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = fpga_core
TOPLEVEL = $(DUT)
MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_s10.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fc_count.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_rx.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_tx.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters
# Structural configuration
export PARAM_IF_COUNT := 2
export PARAM_PORTS_PER_IF := 1
export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK := 0
# Clock configuration
export PARAM_CLK_PERIOD_NS_NUM := 4
export PARAM_CLK_PERIOD_NS_DENOM := 1
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 1
export PARAM_PTP_PEROUT_COUNT := 1
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
export PARAM_RX_DESC_TABLE_SIZE := 32
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH := 6
# Interface configuration
export PARAM_PTP_TS_ENABLE := 1
export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 32768
export PARAM_MAX_TX_SIZE := 9214
export PARAM_MAX_RX_SIZE := 9214
export PARAM_TX_RAM_SIZE := 32768
export PARAM_RX_RAM_SIZE := 32768
# Application block configuration
export PARAM_APP_ID := $(shell echo $$((0x00000000)) )
export PARAM_APP_ENABLE := 0
export PARAM_APP_CTRL_ENABLE := 1
export PARAM_APP_DMA_ENABLE := 1
export PARAM_APP_AXIS_DIRECT_ENABLE := 1
export PARAM_APP_AXIS_SYNC_ENABLE := 1
export PARAM_APP_AXIS_IF_ENABLE := 1
export PARAM_APP_STAT_ENABLE := 1
# DMA interface configuration
export PARAM_DMA_IMM_ENABLE := 0
export PARAM_DMA_IMM_WIDTH := 32
export PARAM_DMA_LEN_WIDTH := 16
export PARAM_DMA_TAG_WIDTH := 16
export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
export PARAM_RAM_PIPELINE := 2
# PCIe interface configuration
export PARAM_SEG_COUNT := 1
export PARAM_SEG_DATA_WIDTH := 256
export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32
export PARAM_AXIL_CTRL_ADDR_WIDTH := 24
# AXI lite interface configuration (application control)
export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH)
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24
# Ethernet interface configuration
export PARAM_AXIS_ETH_TX_PIPELINE := 0
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2
export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0
export PARAM_AXIS_ETH_RX_PIPELINE := 0
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2
# Statistics counter subsystem
export PARAM_STAT_ENABLE := 1
export PARAM_STAT_DMA_ENABLE := 1
export PARAM_STAT_PCIE_ENABLE := 1
export PARAM_STAT_INC_WIDTH := 24
export PARAM_STAT_ID_WIDTH := 12
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
COMPILE_ARGS += -s iverilog_dump
endif
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
echo 'end' >> $@
echo 'endmodule' >> $@
clean::
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst

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fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/mqnic.py Symbolic link
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../../../../../common/tb/mqnic.py

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"""
Copyright 2020-2023, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
"""
import logging
import os
import sys
import scapy.utils
from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, UDP
import cocotb_test.simulator
import cocotb
from cocotb.log import SimLog
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.eth import XgmiiSource, XgmiiSink
from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus
try:
import mqnic
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
import mqnic
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut, msix_count=32):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
pcie_link_width=8,
pld_clk_frequency=250e6,
l_tile=False,
pf_count=1,
max_payload_size=1024,
enable_extended_tag=True,
pf0_msi_enable=False,
pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=True,
pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals
# Clock and reset
# npor=dut.npor,
# pin_perst=dut.pin_perst,
# ninit_done=dut.ninit_done,
# pld_clk_inuse=dut.pld_clk_inuse,
# pld_core_ready=dut.pld_core_ready,
reset_status=dut.rst_250mhz,
# clr_st=dut.clr_st,
# refclk=dut.refclk,
coreclkout_hip=dut.clk_250mhz,
# RX interface
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
# TX interface
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
# TX flow control
tx_ph_cdts=dut.tx_ph_cdts,
tx_pd_cdts=dut.tx_pd_cdts,
tx_nph_cdts=dut.tx_nph_cdts,
tx_npd_cdts=dut.tx_npd_cdts,
tx_cplh_cdts=dut.tx_cplh_cdts,
tx_cpld_cdts=dut.tx_cpld_cdts,
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
tx_cdts_type=dut.tx_cdts_type,
tx_cdts_data_value=dut.tx_cdts_data_value,
# Hard IP status
# int_status=dut.int_status,
# int_status_common=dut.int_status_common,
# derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
# derr_rpl=dut.derr_rpl,
# derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
# derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
# rx_par_err=dut.rx_par_err,
# tx_par_err=dut.tx_par_err,
# ltssmstate=dut.ltssmstate,
# link_up=dut.link_up,
# lane_act=dut.lane_act,
# currentspeed=dut.currentspeed,
# Power management
# pm_linkst_in_l1=dut.pm_linkst_in_l1,
# pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
# pm_state=dut.pm_state,
# pm_dstate=dut.pm_dstate,
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
# apps_ready_entr_l23=dut.apps_ready_entr_l23,
# apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
# app_init_rst=dut.app_init_rst,
# app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface
# app_msi_req=dut.app_msi_req,
# app_msi_ack=dut.app_msi_ack,
# app_msi_tc=dut.app_msi_tc,
# app_msi_num=dut.app_msi_num,
# app_msi_func_num=dut.app_msi_func_num,
# app_int_sts=dut.app_int_sts,
# Error interface
# app_err_valid=dut.app_err_valid,
# app_err_hdr=dut.app_err_hdr,
# app_err_info=dut.app_err_info,
# app_err_func_num=dut.app_err_func_num,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# Configuration extension bus
# ceb_req=dut.ceb_req,
# ceb_ack=dut.ceb_ack,
# ceb_addr=dut.ceb_addr,
# ceb_din=dut.ceb_din,
# ceb_dout=dut.ceb_dout,
# ceb_wr=dut.ceb_wr,
# ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
# ceb_func_num=dut.ceb_func_num,
# ceb_vf_num=dut.ceb_vf_num,
# ceb_vf_active=dut.ceb_vf_active,
# Hard IP reconfiguration interface
# hip_reconfig_clk=dut.hip_reconfig_clk,
# hip_reconfig_address=dut.hip_reconfig_address,
# hip_reconfig_read=dut.hip_reconfig_read,
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
# hip_reconfig_write=dut.hip_reconfig_write,
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver()
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 2.56, units="ns").start())
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 2.56, units="ns").start())
self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 2.56, units="ns").start())
self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 2.56, units="ns").start())
self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 2.56, units="ns").start())
self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 2.56, units="ns").start())
self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 2.56, units="ns").start())
self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 2.56, units="ns").start())
self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 2.56, units="ns").start())
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 2.56, units="ns").start())
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 2.56, units="ns").start())
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 2.56, units="ns").start())
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 2.56, units="ns").start())
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 2.56, units="ns").start())
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_1, 2.56, units="ns").start())
self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_1, 2.56, units="ns").start())
self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_2, 2.56, units="ns").start())
self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_2, 2.56, units="ns").start())
self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_3, 2.56, units="ns").start())
self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_3, 2.56, units="ns").start())
self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_4, 2.56, units="ns").start())
self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 2.56, units="ns").start())
self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4)
cocotb.start_soon(Clock(dut.qsfp3_rx_clk_1, 2.56, units="ns").start())
self.qsfp3_1_source = XgmiiSource(dut.qsfp3_rxd_1, dut.qsfp3_rxc_1, dut.qsfp3_rx_clk_1, dut.qsfp3_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp3_tx_clk_1, 2.56, units="ns").start())
self.qsfp3_1_sink = XgmiiSink(dut.qsfp3_txd_1, dut.qsfp3_txc_1, dut.qsfp3_tx_clk_1, dut.qsfp3_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp3_rx_clk_2, 2.56, units="ns").start())
self.qsfp3_2_source = XgmiiSource(dut.qsfp3_rxd_2, dut.qsfp3_rxc_2, dut.qsfp3_rx_clk_2, dut.qsfp3_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp3_tx_clk_2, 2.56, units="ns").start())
self.qsfp3_2_sink = XgmiiSink(dut.qsfp3_txd_2, dut.qsfp3_txc_2, dut.qsfp3_tx_clk_2, dut.qsfp3_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp3_rx_clk_3, 2.56, units="ns").start())
self.qsfp3_3_source = XgmiiSource(dut.qsfp3_rxd_3, dut.qsfp3_rxc_3, dut.qsfp3_rx_clk_3, dut.qsfp3_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp3_tx_clk_3, 2.56, units="ns").start())
self.qsfp3_3_sink = XgmiiSink(dut.qsfp3_txd_3, dut.qsfp3_txc_3, dut.qsfp3_tx_clk_3, dut.qsfp3_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp3_rx_clk_4, 2.56, units="ns").start())
self.qsfp3_4_source = XgmiiSource(dut.qsfp3_rxd_4, dut.qsfp3_rxc_4, dut.qsfp3_rx_clk_4, dut.qsfp3_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp3_tx_clk_4, 2.56, units="ns").start())
self.qsfp3_4_sink = XgmiiSink(dut.qsfp3_txd_4, dut.qsfp3_txc_4, dut.qsfp3_tx_clk_4, dut.qsfp3_tx_rst_4)
dut.qsfp0_rx_status_1.setimmediatevalue(1)
dut.qsfp0_rx_status_2.setimmediatevalue(1)
dut.qsfp0_rx_status_3.setimmediatevalue(1)
dut.qsfp0_rx_status_4.setimmediatevalue(1)
dut.qsfp1_rx_status_1.setimmediatevalue(1)
dut.qsfp1_rx_status_2.setimmediatevalue(1)
dut.qsfp1_rx_status_3.setimmediatevalue(1)
dut.qsfp1_rx_status_4.setimmediatevalue(1)
dut.qsfp2_rx_status_1.setimmediatevalue(1)
dut.qsfp2_rx_status_2.setimmediatevalue(1)
dut.qsfp2_rx_status_3.setimmediatevalue(1)
dut.qsfp2_rx_status_4.setimmediatevalue(1)
dut.qsfp3_rx_status_1.setimmediatevalue(1)
dut.qsfp3_rx_status_2.setimmediatevalue(1)
dut.qsfp3_rx_status_3.setimmediatevalue(1)
dut.qsfp3_rx_status_4.setimmediatevalue(1)
dut.qsfp0_rx_error_count_1.setimmediatevalue(0)
dut.qsfp0_rx_error_count_2.setimmediatevalue(0)
dut.qsfp0_rx_error_count_3.setimmediatevalue(0)
dut.qsfp0_rx_error_count_4.setimmediatevalue(0)
dut.qsfp1_rx_error_count_1.setimmediatevalue(0)
dut.qsfp1_rx_error_count_2.setimmediatevalue(0)
dut.qsfp1_rx_error_count_3.setimmediatevalue(0)
dut.qsfp1_rx_error_count_4.setimmediatevalue(0)
dut.qsfp2_rx_error_count_1.setimmediatevalue(0)
dut.qsfp2_rx_error_count_2.setimmediatevalue(0)
dut.qsfp2_rx_error_count_3.setimmediatevalue(0)
dut.qsfp2_rx_error_count_4.setimmediatevalue(0)
dut.qsfp3_rx_error_count_1.setimmediatevalue(0)
dut.qsfp3_rx_error_count_2.setimmediatevalue(0)
dut.qsfp3_rx_error_count_3.setimmediatevalue(0)
dut.qsfp3_rx_error_count_4.setimmediatevalue(0)
dut.fpga_i2c_scl_i.setimmediatevalue(1)
dut.fpga_i2c_sda_i.setimmediatevalue(1)
dut.fpga_i2c_mux_gnt.setimmediatevalue(1)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_4.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_4.setimmediatevalue(0)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(1)
self.dut.qsfp0_tx_rst_2.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_3.setimmediatevalue(1)
self.dut.qsfp0_tx_rst_3.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_4.setimmediatevalue(1)
self.dut.qsfp0_tx_rst_4.setimmediatevalue(1)
self.dut.qsfp1_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp1_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp1_rx_rst_2.setimmediatevalue(1)
self.dut.qsfp1_tx_rst_2.setimmediatevalue(1)
self.dut.qsfp1_rx_rst_3.setimmediatevalue(1)
self.dut.qsfp1_tx_rst_3.setimmediatevalue(1)
self.dut.qsfp1_rx_rst_4.setimmediatevalue(1)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(1)
self.dut.qsfp2_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp2_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp2_rx_rst_2.setimmediatevalue(1)
self.dut.qsfp2_tx_rst_2.setimmediatevalue(1)
self.dut.qsfp2_rx_rst_3.setimmediatevalue(1)
self.dut.qsfp2_tx_rst_3.setimmediatevalue(1)
self.dut.qsfp2_rx_rst_4.setimmediatevalue(1)
self.dut.qsfp2_tx_rst_4.setimmediatevalue(1)
self.dut.qsfp3_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp3_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp3_rx_rst_2.setimmediatevalue(1)
self.dut.qsfp3_tx_rst_2.setimmediatevalue(1)
self.dut.qsfp3_rx_rst_3.setimmediatevalue(1)
self.dut.qsfp3_tx_rst_3.setimmediatevalue(1)
self.dut.qsfp3_rx_rst_4.setimmediatevalue(1)
self.dut.qsfp3_tx_rst_4.setimmediatevalue(1)
await FallingEdge(self.dut.rst_250mhz)
await Timer(100, 'ns')
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp2_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp2_tx_rst_4.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_2.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_2.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_3.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_3.setimmediatevalue(0)
self.dut.qsfp3_rx_rst_4.setimmediatevalue(0)
self.dut.qsfp3_tx_rst_4.setimmediatevalue(0)
await self.rc.enumerate()
async def _run_loopback(self):
while True:
await RisingEdge(self.dut.clk_250mhz)
if self.loopback_enable:
if not self.qsfp0_1_sink.empty():
await self.qsfp0_1_source.send(await self.qsfp0_1_sink.recv())
if not self.qsfp0_2_sink.empty():
await self.qsfp0_2_source.send(await self.qsfp0_2_sink.recv())
if not self.qsfp0_3_sink.empty():
await self.qsfp0_3_source.send(await self.qsfp0_3_sink.recv())
if not self.qsfp0_4_sink.empty():
await self.qsfp0_4_source.send(await self.qsfp0_4_sink.recv())
if not self.qsfp1_1_sink.empty():
await self.qsfp1_1_source.send(await self.qsfp1_1_sink.recv())
if not self.qsfp1_2_sink.empty():
await self.qsfp1_2_source.send(await self.qsfp1_2_sink.recv())
if not self.qsfp1_3_sink.empty():
await self.qsfp1_3_source.send(await self.qsfp1_3_sink.recv())
if not self.qsfp1_4_sink.empty():
await self.qsfp1_4_source.send(await self.qsfp1_4_sink.recv())
if not self.qsfp2_1_sink.empty():
await self.qsfp2_1_source.send(await self.qsfp2_1_sink.recv())
if not self.qsfp2_2_sink.empty():
await self.qsfp2_2_source.send(await self.qsfp2_2_sink.recv())
if not self.qsfp2_3_sink.empty():
await self.qsfp2_3_source.send(await self.qsfp2_3_sink.recv())
if not self.qsfp2_4_sink.empty():
await self.qsfp2_4_source.send(await self.qsfp2_4_sink.recv())
if not self.qsfp3_1_sink.empty():
await self.qsfp3_1_source.send(await self.qsfp3_1_sink.recv())
if not self.qsfp3_2_sink.empty():
await self.qsfp3_2_source.send(await self.qsfp3_2_sink.recv())
if not self.qsfp3_3_sink.empty():
await self.qsfp3_3_source.send(await self.qsfp3_3_sink.recv())
if not self.qsfp3_4_sink.empty():
await self.qsfp3_4_source.send(await self.qsfp3_4_sink.recv())
@cocotb.test()
async def run_test_nic(dut):
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init()
tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open()
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(len(tb.driver.interfaces[0].txq)):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
await tb.driver.hw_regs.read_dword(0)
tb.log.info("Init complete")
tb.log.info("Send and receive single packet")
data = bytearray([x % 256 for x in range(1024)])
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.qsfp0_1_sink.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfp0_1_source.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
# await tb.driver.interfaces[1].start_xmit(data, 0)
# pkt = await tb.qsfp1_1_sink.recv()
# tb.log.info("Packet: %s", pkt)
# await tb.qsfp1_1_source.send(pkt)
# pkt = await tb.driver.interfaces[1].recv()
# tb.log.info("Packet: %s", pkt)
# assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.log.info("RX and TX checksum tests")
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=2)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
pkt = await tb.qsfp0_1_sink.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfp0_1_source.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Multiple large packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_250mhz)
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
def test_fpga_core(request):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
verilog_sources = [
os.path.join(rtl_dir, f"{dut}.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie_s10.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
os.path.join(rtl_dir, "common", "rx_hash.v"),
os.path.join(rtl_dir, "common", "rx_checksum.v"),
os.path.join(rtl_dir, "common", "stats_counter.v"),
os.path.join(rtl_dir, "common", "stats_collect.v"),
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
os.path.join(rtl_dir, "common", "tdma_ber.v"),
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
os.path.join(axi_rtl_dir, "arbiter.v"),
os.path.join(axi_rtl_dir, "priority_encoder.v"),
os.path.join(axis_rtl_dir, "axis_adapter.v"),
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fc_count.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "irq_rate_limit.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
os.path.join(pcie_rtl_dir, "pcie_s10_if.v"),
os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"),
os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"),
os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
]
parameters = {}
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
parameters['PORT_MASK'] = 0
# Clock configuration
parameters['CLK_PERIOD_NS_NUM'] = 4
parameters['CLK_PERIOD_NS_DENOM'] = 1
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 32768
parameters['MAX_TX_SIZE'] = 9214
parameters['MAX_RX_SIZE'] = 9214
parameters['TX_RAM_SIZE'] = 32768
parameters['RX_RAM_SIZE'] = 32768
# Application block configuration
parameters['APP_ID'] = 0x00000000
parameters['APP_ENABLE'] = 0
parameters['APP_CTRL_ENABLE'] = 1
parameters['APP_DMA_ENABLE'] = 1
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
parameters['APP_AXIS_SYNC_ENABLE'] = 1
parameters['APP_AXIS_IF_ENABLE'] = 1
parameters['APP_STAT_ENABLE'] = 1
# DMA interface configuration
parameters['DMA_IMM_ENABLE'] = 0
parameters['DMA_IMM_WIDTH'] = 32
parameters['DMA_LEN_WIDTH'] = 16
parameters['DMA_TAG_WIDTH'] = 16
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
parameters['RAM_PIPELINE'] = 2
# PCIe interface configuration
parameters['SEG_COUNT'] = 1
parameters['SEG_DATA_WIDTH'] = 256
parameters['PF_COUNT'] = 1
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
# AXI lite interface configuration (application control)
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
# Ethernet interface configuration
parameters['AXIS_ETH_TX_PIPELINE'] = 0
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
parameters['AXIS_ETH_RX_PIPELINE'] = 0
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
# Statistics counter subsystem
parameters['STAT_ENABLE'] = 1
parameters['STAT_DMA_ENABLE'] = 1
parameters['STAT_PCIE_ENABLE'] = 1
parameters['STAT_INC_WIDTH'] = 24
parameters['STAT_ID_WIDTH'] = 12
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

67
modules/mqnic/mqnic_board.c
View File

@ -164,6 +164,31 @@ static int read_mac_from_eeprom_hex(struct mqnic_dev *mqnic,
return 0;
}
static int init_mac_list_from_eeprom(struct mqnic_dev *mqnic,
struct i2c_client *eeprom, int offset, int count)
{
int ret, k;
char mac[ETH_ALEN];
count = min(count, MQNIC_MAX_IF);
for (k = 0; k < count; k++) {
ret = read_mac_from_eeprom(mqnic, eeprom, offset + ETH_ALEN*k, mac);
if (ret < 0)
return ret;
if (!is_valid_ether_addr(mac)) {
dev_warn(mqnic->dev, "MAC is not valid");
return -1;
}
memcpy(mqnic->mac_list[k], mac, ETH_ALEN);
mqnic->mac_count = k+1;
}
return 0;
}
static int init_mac_list_from_eeprom_base(struct mqnic_dev *mqnic,
struct i2c_client *eeprom, int offset, int count)
{
@ -564,6 +589,48 @@ static int mqnic_generic_board_init(struct mqnic_dev *mqnic)
// I2C EEPROM
mqnic->eeprom_i2c_client = create_i2c_client(adapter, "24c16", 0x50);
break;
case MQNIC_BOARD_ID_520NMX:
// FPGA I2C
// TCA9548 0x72
// CH0: OC_2 J22
// CH1: OC_3 J23
// CH2: OC_0 J26
// CH3: OC_1 J27
// CH4: QSFP_0
// CH5: QSFP_1
// CH6: QSFP_2
// CH7: QSFP_3
// EEPROM 0x57
request_module("at24");
// I2C adapter
adapter = mqnic_i2c_adapter_create(mqnic, 0);
// TCA9548 I2C MUX
mux = create_i2c_client(adapter, "pca9548", 0x72);
// QSFP0
mqnic->mod_i2c_client[0] = create_i2c_client(get_i2c_mux_channel(mux, 4), "24c02", 0x50);
// QSFP1
mqnic->mod_i2c_client[1] = create_i2c_client(get_i2c_mux_channel(mux, 5), "24c02", 0x50);
// QSFP2
mqnic->mod_i2c_client[2] = create_i2c_client(get_i2c_mux_channel(mux, 6), "24c02", 0x50);
// QSFP3
mqnic->mod_i2c_client[3] = create_i2c_client(get_i2c_mux_channel(mux, 7), "24c02", 0x50);
mqnic->mod_i2c_client_count = 4;
// I2C EEPROM
mqnic->eeprom_i2c_client = create_i2c_client(adapter, "24c02", 0x57);
// read MACs from EEPROM
init_mac_list_from_eeprom(mqnic, mqnic->eeprom_i2c_client, 0x4B, 16);
break;
case MQNIC_BOARD_ID_XUPP3R:

1
modules/mqnic/mqnic_hw.h
View File

@ -73,6 +73,7 @@
#define MQNIC_BOARD_ID_DK_DEV_AGF014EA 0x1172b00e
#define MQNIC_BOARD_ID_DE10_AGILEX 0x1172b00a
#define MQNIC_BOARD_ID_XUPP3R 0x12ba9823
#define MQNIC_BOARD_ID_520NMX 0x198a0521
#define MQNIC_BOARD_ID_250SOC 0x198a250e
#define MQNIC_BOARD_ID_FB4CGG3_VU9P 0x1c2c9403
#define MQNIC_BOARD_ID_FB2CG_KU15P 0x1c2ca00e