From 2c8b1d0e29bc4a51a0f7c5ec26a54fbbef09ad82 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 12 Jun 2023 15:36:26 -0700 Subject: [PATCH] fpga/mqnic/520N_MX: Add 25G mqnic design for BittWare 520N-MX Signed-off-by: Alex Forencich --- fpga/mqnic/520N_MX/fpga_25g/README.md | 18 + fpga/mqnic/520N_MX/fpga_25g/app | 1 + .../520N_MX/fpga_25g/common/quartus_pro.mk | 188 ++ fpga/mqnic/520N_MX/fpga_25g/fpga.qsf | 1035 ++++++++++ fpga/mqnic/520N_MX/fpga_25g/fpga.sdc | 133 ++ fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile | 151 ++ fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl | 237 +++ fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile | 149 ++ .../520N_MX/fpga_25g/fpga_10g/config.tcl | 237 +++ .../mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx.tcl | 385 ++++ .../520N_MX/fpga_25g/ip/eth_xcvr_gx_pll.tcl | 143 ++ .../520N_MX/fpga_25g/ip/eth_xcvr_gxt.tcl | 389 ++++ .../520N_MX/fpga_25g/ip/eth_xcvr_gxt_buf.tcl | 144 ++ .../520N_MX/fpga_25g/ip/eth_xcvr_gxt_pll.tcl | 144 ++ .../520N_MX/fpga_25g/ip/eth_xcvr_reset.tcl | 87 + .../520N_MX/fpga_25g/ip/iopll_100mhz.tcl | 304 +++ fpga/mqnic/520N_MX/fpga_25g/ip/pcie.tcl | 350 ++++ fpga/mqnic/520N_MX/fpga_25g/ip/ref_div.tcl | 61 + .../520N_MX/fpga_25g/ip/reset_release.tcl | 50 + fpga/mqnic/520N_MX/fpga_25g/lib | 1 + fpga/mqnic/520N_MX/fpga_25g/rtl/axis_fifo.v | 408 ++++ fpga/mqnic/520N_MX/fpga_25g/rtl/common | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 386 ++++ .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 330 ++++ fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v | 1693 +++++++++++++++++ fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v | 1268 ++++++++++++ fpga/mqnic/520N_MX/fpga_25g/rtl/sync_signal.v | 62 + .../520N_MX/fpga_25g/tb/fpga_core/Makefile | 285 +++ .../520N_MX/fpga_25g/tb/fpga_core/mqnic.py | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 934 +++++++++ modules/mqnic/mqnic_board.c | 67 + modules/mqnic/mqnic_hw.h | 1 + 32 files changed, 9643 insertions(+) create mode 100644 fpga/mqnic/520N_MX/fpga_25g/README.md create mode 120000 fpga/mqnic/520N_MX/fpga_25g/app create mode 100644 fpga/mqnic/520N_MX/fpga_25g/common/quartus_pro.mk create mode 100644 fpga/mqnic/520N_MX/fpga_25g/fpga.qsf create mode 100644 fpga/mqnic/520N_MX/fpga_25g/fpga.sdc create mode 100644 fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile create mode 100644 fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile create mode 100644 fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx_pll.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_buf.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_pll.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_reset.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/iopll_100mhz.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/pcie.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/ref_div.tcl create mode 100644 fpga/mqnic/520N_MX/fpga_25g/ip/reset_release.tcl create mode 120000 fpga/mqnic/520N_MX/fpga_25g/lib create mode 100644 fpga/mqnic/520N_MX/fpga_25g/rtl/axis_fifo.v create mode 120000 fpga/mqnic/520N_MX/fpga_25g/rtl/common create mode 100644 fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v create mode 100644 fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_wrapper.v create mode 100644 fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v create mode 100644 fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v create mode 100644 fpga/mqnic/520N_MX/fpga_25g/rtl/sync_signal.v create mode 100644 fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile create mode 120000 fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/mqnic.py create mode 100644 fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py diff --git a/fpga/mqnic/520N_MX/fpga_25g/README.md b/fpga/mqnic/520N_MX/fpga_25g/README.md new file mode 100644 index 000000000..37ebbd4ce --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/README.md @@ -0,0 +1,18 @@ +# Corundum mqnic for 520N-MX + +## Introduction + +This design targets the BittWare 520N-MX FPGA development board. + +* FPGA: 1SM21CHU2F53E2VG +* PHY: Transceiver in 10G BASE-R native mode + +## How to build + +Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH. + +Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. + +## How to test + +Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization. diff --git a/fpga/mqnic/520N_MX/fpga_25g/app b/fpga/mqnic/520N_MX/fpga_25g/app new file mode 120000 index 000000000..4d46690fb --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/app @@ -0,0 +1 @@ +../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/520N_MX/fpga_25g/common/quartus_pro.mk b/fpga/mqnic/520N_MX/fpga_25g/common/quartus_pro.mk new file mode 100644 index 000000000..f7e9cea62 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/common/quartus_pro.mk @@ -0,0 +1,188 @@ +################################################################### +# +# Makefile for Intel Quartus Prime Pro +# +# Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX) +# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG) +# SYN_FILES - space-separated list of source files +# IP_FILES - space-separated list of IP files +# IP_TCL_FILES - space-separated list of TCL files for qsys-script +# QSF_FILES - space-separated list of settings files +# SDC_FILES - space-separated list of timing constraint files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = "Stratix 10 DX" +# FPGA_DEVICE = 1SD280PT2F55E1VG +# SYN_FILES = rtl/fpga.v +# QSF_FILES = fpga.qsf +# SDC_FILES = fpga.sdc +# include ../common/quartus_pro.mk +# +################################################################### + +# phony targets +.PHONY: clean fpga + +# output files to hang on to +.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt +.SECONDARY: + +# any project specific settings +CONFIG ?= config.mk +-include ../$(CONFIG) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES)) +IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES))) + +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES))) +IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES))) + +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef QSF_FILES + QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + QSF_FILES_REL = ../$(FPGA_TOP).qsf +endif + +SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and database +################################################################### + +all: fpga + +fpga: $(FPGA_TOP).sof + +quartus: $(FPGA_TOP).qpf + quartus $(FPGA_TOP).qpf + +tmpclean:: + -rm -rf defines.v + -rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp + -rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit + -rm -rf create_project.tcl update_config.tcl update_ip_*.tcl + +clean:: tmpclean + -rm -rf *.sof *.pof *.jdi *.jic *.map + +distclean:: clean + -rm -rf rev + +syn: smart.log output_files/$(PROJECT).syn.rpt +fit: smart.log output_files/$(PROJECT).fit.rpt +asm: smart.log output_files/$(PROJECT).asm.rpt +sta: smart.log output_files/$(PROJECT).sta.rpt +smart: smart.log + +################################################################### +# Executable Configuration +################################################################### + +IP_ARGS = --run_default_mode_op +SYN_ARGS = --read_settings_files=on --write_settings_files=off +FIT_ARGS = --read_settings_files=on --write_settings_files=off +ASM_ARGS = --read_settings_files=on --write_settings_files=off +STA_ARGS = + +################################################################### +# Target implementations +################################################################### + +STAMP = echo done > + +define COPY_IP_RULE +$(patsubst %, ip/%, $(notdir $(1))): $(1) + @mkdir -p ip + @cp -pv $(1) ip/ +endef +$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l)))) + +define TCL_IP_GEN_RULE +$(patsubst %.tcl,%.ip,$(1)): $(1) + cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf} + cd ip && qsys-script --script=$(notdir $(1)) +endef +$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l)))) + +%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) + quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP) + +%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL) + quartus_syn $(SYN_ARGS) $(FPGA_TOP) + +%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL) + quartus_fit $(FIT_ARGS) $(FPGA_TOP) + +%.sta.rpt: sta.chg %.fit.rpt + quartus_sta $(STA_ARGS) $(FPGA_TOP) + +%.asm.rpt: asm.chg %.sta.rpt + quartus_asm $(ASM_ARGS) $(FPGA_TOP) + mkdir -p rev + EXT=sof; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do let COUNT=COUNT+1; done; \ + cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_rev$$COUNT.$$EXT"; + +%.sof: smart.log %.asm.rpt + + +smart.log: $(ASSIGNMENT_FILES) + quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log + +################################################################### +# Project initialization +################################################################### + +create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) + rm -f update_config.tcl + echo "project_new $(FPGA_TOP) -overwrite" > $@ + echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@ + echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@ + for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \ + case $${x##*.} in \ + v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\ + vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\ + qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\ + ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\ + *) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\ + esac; \ + done + for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done + for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) + echo "project_open $(FPGA_TOP)" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done + +$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl + for x in $?; do quartus_sh -t "$$x"; done + touch -c $(ASSIGNMENT_FILES) + +syn.chg: + $(STAMP) syn.chg +fit.chg: + $(STAMP) fit.chg +sta.chg: + $(STAMP) sta.chg +asm.chg: + $(STAMP) asm.chg diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga.qsf b/fpga/mqnic/520N_MX/fpga_25g/fpga.qsf new file mode 100644 index 000000000..1b006d508 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga.qsf @@ -0,0 +1,1035 @@ +# I/O constraints for the BittWare 520N-MX FPGA development board +# part: 1SM21CHU2F53E2VG + +set_global_assignment -name USE_CONF_DONE SDM_IO16 +set_global_assignment -name USE_INIT_DONE SDM_IO0 + +set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 +set_global_assignment -name USE_PWRMGT_ALERT SDM_IO12 +set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 01 +set_global_assignment -name VID_OPERATION_MODE "PMBUS SLAVE" + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X16" +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V +set_global_assignment -name USE_CHECKSUM_AS_USERCODE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name ENABLE_ED_CRC_CHECK ON +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name MINIMUM_SEU_INTERVAL 0 + +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON + +set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on + +# Clock and reset +set_location_assignment PIN_BB20 -to "config_clk" + +set_location_assignment PIN_BE17 -to "usr_refclk0" +set_location_assignment PIN_BD17 -to "usr_refclk0(n)" + +set_location_assignment PIN_A24 -to "usr_refclk1" +set_location_assignment PIN_B23 -to "usr_refclk1(n)" + +set_location_assignment PIN_AW31 -to "mem0_refclk" +set_location_assignment PIN_AY31 -to "mem0_refclk(n)" + +set_location_assignment PIN_A42 -to "mem1_refclk" +set_location_assignment PIN_B41 -to "mem1_refclk(n)" + +set_location_assignment PIN_AU31 -to "esram_0_refclk" +set_location_assignment PIN_AU32 -to "esram_0_refclk(n)" + +set_location_assignment PIN_V31 -to "esram_1_refclk" +set_location_assignment PIN_U31 -to "esram_1_refclk(n)" + +set_location_assignment PIN_AR26 -to "hbm_bottom_refclk" +set_location_assignment PIN_AP26 -to "hbm_bottom_refclk(n)" + +set_location_assignment PIN_P27 -to "hbm_top_refclk" +set_location_assignment PIN_R27 -to "hbm_top_refclk(n)" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "config_clk" + +set_instance_assignment -name IO_STANDARD LVDS -to "usr_refclk0" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "usr_refclk0" + +set_instance_assignment -name IO_STANDARD LVDS -to "usr_refclk1" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "usr_refclk1" + +set_instance_assignment -name IO_STANDARD LVDS -to "esram_0_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "esram_0_refclk" + +set_instance_assignment -name IO_STANDARD LVDS -to "esram_1_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "esram_1_refclk" + +set_instance_assignment -name IO_STANDARD LVDS -to "hbm_bottom_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "hbm_bottom_refclk" + +set_instance_assignment -name IO_STANDARD LVDS -to "hbm_top_refclk" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "hbm_top_refclk" + +# LEDs +set_location_assignment PIN_AA39 -to "led_user_grn[0]" +set_location_assignment PIN_AL38 -to "led_user_grn[1]" + +set_location_assignment PIN_AA38 -to "led_user_red[0]" +set_location_assignment PIN_AL39 -to "led_user_red[1]" + +set_location_assignment PIN_AH39 -to "led_qsfp[0]" +set_location_assignment PIN_AJ39 -to "led_qsfp[1]" +set_location_assignment PIN_AK39 -to "led_qsfp[2]" +set_location_assignment PIN_AM38 -to "led_qsfp[3]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "led_user_red[*]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "led_user_grn[*]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "led_qsfp[*]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "led_user_red[*]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "led_user_grn[*]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "led_qsfp[*]" + +# UART +set_location_assignment PIN_BD12 -to "uart_tx" +set_location_assignment PIN_BE12 -to "uart_rx" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "uart_tx" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "uart_rx" + +# I2C +set_location_assignment PIN_BJ17 -to "fpga_i2c_sda" +set_location_assignment PIN_BJ18 -to "fpga_i2c_scl" +set_location_assignment PIN_BK17 -to "fpga_i2c_req_l" +set_location_assignment PIN_BK16 -to "fpga_i2c_mux_gnt" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_sda" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_scl" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_req_l" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_i2c_mux_gnt" + +# BMC SPI +set_location_assignment PIN_BK15 -to "bmc_spi_mosi" +set_location_assignment PIN_BF18 -to "bmc_spi_nss" +set_location_assignment PIN_BF19 -to "bmc_spi_sclk" +set_location_assignment PIN_BL15 -to "bmc_spi_miso" + +set_location_assignment PIN_BH20 -to "bmc_irq" + +set_location_assignment PIN_BH19 -to "fpga_gpio_1" +set_location_assignment PIN_BG20 -to "fpga_rst_n" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_mosi" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_nss" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_sclk" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_spi_miso" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "bmc_irq" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_gpio_1" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "fpga_rst_n" + +# PCIe banks 1K 1L 1M +set_location_assignment PIN_AE51 -to "pcie_tx[0]" ;# GXBL1K_TX_CH0P +set_location_assignment PIN_AE50 -to "pcie_tx[0](n)" ;# GXBL1K_TX_CH0N +set_location_assignment PIN_AC47 -to "pcie_rx[0]" ;# GXBL1K_RX_CH0P +set_location_assignment PIN_AC46 -to "pcie_rx[0](n)" ;# GXBL1K_RX_CH0N +set_location_assignment PIN_AD49 -to "pcie_tx[1]" ;# GXBL1K_TX_CH1P +set_location_assignment PIN_AD48 -to "pcie_tx[1](n)" ;# GXBL1K_TX_CH1N +set_location_assignment PIN_AD45 -to "pcie_rx[1]" ;# GXBL1K_RX_CH1P +set_location_assignment PIN_AD44 -to "pcie_rx[1](n)" ;# GXBL1K_RX_CH1N +set_location_assignment PIN_AC51 -to "pcie_tx[2]" ;# GXBL1K_TX_CH2P +set_location_assignment PIN_AC50 -to "pcie_tx[2](n)" ;# GXBL1K_TX_CH2N +set_location_assignment PIN_AA47 -to "pcie_rx[2]" ;# GXBL1K_RX_CH2P +set_location_assignment PIN_AA46 -to "pcie_rx[2](n)" ;# GXBL1K_RX_CH2N +set_location_assignment PIN_AB49 -to "pcie_tx[3]" ;# GXBL1K_TX_CH3P +set_location_assignment PIN_AB48 -to "pcie_tx[3](n)" ;# GXBL1K_TX_CH3N +set_location_assignment PIN_AB45 -to "pcie_rx[3]" ;# GXBL1K_RX_CH3P +set_location_assignment PIN_AB44 -to "pcie_rx[3](n)" ;# GXBL1K_RX_CH3N +set_location_assignment PIN_AA51 -to "pcie_tx[4]" ;# GXBL1K_TX_CH4P +set_location_assignment PIN_AA50 -to "pcie_tx[4](n)" ;# GXBL1K_TX_CH4N +set_location_assignment PIN_W47 -to "pcie_rx[4]" ;# GXBL1K_RX_CH4P +set_location_assignment PIN_W46 -to "pcie_rx[4](n)" ;# GXBL1K_RX_CH4N +set_location_assignment PIN_Y49 -to "pcie_tx[5]" ;# GXBL1K_TX_CH5P +set_location_assignment PIN_Y48 -to "pcie_tx[5](n)" ;# GXBL1K_TX_CH5N +set_location_assignment PIN_Y45 -to "pcie_rx[5]" ;# GXBL1K_RX_CH5P +set_location_assignment PIN_Y44 -to "pcie_rx[5](n)" ;# GXBL1K_RX_CH5N +set_location_assignment PIN_W51 -to "pcie_tx[6]" ;# GXBL1L_TX_CH0P +set_location_assignment PIN_W50 -to "pcie_tx[6](n)" ;# GXBL1L_TX_CH0N +set_location_assignment PIN_U47 -to "pcie_rx[6]" ;# GXBL1L_RX_CH0P +set_location_assignment PIN_U46 -to "pcie_rx[6](n)" ;# GXBL1L_RX_CH0N +set_location_assignment PIN_V49 -to "pcie_tx[7]" ;# GXBL1L_TX_CH1P +set_location_assignment PIN_V48 -to "pcie_tx[7](n)" ;# GXBL1L_TX_CH1N +set_location_assignment PIN_V45 -to "pcie_rx[7]" ;# GXBL1L_RX_CH1P +set_location_assignment PIN_V44 -to "pcie_rx[7](n)" ;# GXBL1L_RX_CH1N +set_location_assignment PIN_U51 -to "pcie_tx[8]" ;# GXBL1L_TX_CH2P +set_location_assignment PIN_U50 -to "pcie_tx[8](n)" ;# GXBL1L_TX_CH2N +set_location_assignment PIN_R47 -to "pcie_rx[8]" ;# GXBL1L_RX_CH2P +set_location_assignment PIN_R46 -to "pcie_rx[8](n)" ;# GXBL1L_RX_CH2N +set_location_assignment PIN_T49 -to "pcie_tx[9]" ;# GXBL1L_TX_CH3P +set_location_assignment PIN_T48 -to "pcie_tx[9](n)" ;# GXBL1L_TX_CH3N +set_location_assignment PIN_T45 -to "pcie_rx[9]" ;# GXBL1L_RX_CH3P +set_location_assignment PIN_T44 -to "pcie_rx[9](n)" ;# GXBL1L_RX_CH3N +set_location_assignment PIN_R51 -to "pcie_tx[10]" ;# GXBL1L_TX_CH4P +set_location_assignment PIN_R50 -to "pcie_tx[10](n)" ;# GXBL1L_TX_CH4N +set_location_assignment PIN_N47 -to "pcie_rx[10]" ;# GXBL1L_RX_CH4P +set_location_assignment PIN_N46 -to "pcie_rx[10](n)" ;# GXBL1L_RX_CH4N +set_location_assignment PIN_P49 -to "pcie_tx[11]" ;# GXBL1L_TX_CH5P +set_location_assignment PIN_P48 -to "pcie_tx[11](n)" ;# GXBL1L_TX_CH5N +set_location_assignment PIN_P45 -to "pcie_rx[11]" ;# GXBL1L_RX_CH5P +set_location_assignment PIN_P44 -to "pcie_rx[11](n)" ;# GXBL1L_RX_CH5N +set_location_assignment PIN_N51 -to "pcie_tx[12]" ;# GXBL1M_TX_CH0P +set_location_assignment PIN_N50 -to "pcie_tx[12](n)" ;# GXBL1M_TX_CH0N +set_location_assignment PIN_L47 -to "pcie_rx[12]" ;# GXBL1M_RX_CH0P +set_location_assignment PIN_L46 -to "pcie_rx[12](n)" ;# GXBL1M_RX_CH0N +set_location_assignment PIN_M49 -to "pcie_tx[13]" ;# GXBL1M_TX_CH1P +set_location_assignment PIN_M48 -to "pcie_tx[13](n)" ;# GXBL1M_TX_CH1N +set_location_assignment PIN_M45 -to "pcie_rx[13]" ;# GXBL1M_RX_CH1P +set_location_assignment PIN_M44 -to "pcie_rx[13](n)" ;# GXBL1M_RX_CH1N +set_location_assignment PIN_L51 -to "pcie_tx[14]" ;# GXBL1M_TX_CH2P +set_location_assignment PIN_L50 -to "pcie_tx[14](n)" ;# GXBL1M_TX_CH2N +set_location_assignment PIN_J47 -to "pcie_rx[14]" ;# GXBL1M_RX_CH2P +set_location_assignment PIN_J46 -to "pcie_rx[14](n)" ;# GXBL1M_RX_CH2N +set_location_assignment PIN_K49 -to "pcie_tx[15]" ;# GXBL1M_TX_CH3P +set_location_assignment PIN_K48 -to "pcie_tx[15](n)" ;# GXBL1M_TX_CH3N +set_location_assignment PIN_K45 -to "pcie_rx[15]" ;# GXBL1M_RX_CH3P +set_location_assignment PIN_K44 -to "pcie_rx[15](n)" ;# GXBL1M_RX_CH3N + +set_location_assignment PIN_AC43 -to "pcie_refclk" ;# REFCLK_GXBL1K_CHTP +set_location_assignment PIN_AC42 -to "pcie_refclk(n)" ;# REFCLK_GXBL1K_CHTN + +set_location_assignment PIN_Y39 -to "pcie_perstn" + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_rx[*]" + +set_instance_assignment -name IO_STANDARD "HCSL" -to "pcie_refclk" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "pcie_perstn" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "pcie_perstn" + +# QSFP + +# QSFP0 (bank 1D) +set_location_assignment PIN_BD49 -to "qsfp0_tx[0]" ;# GXBL1D_TX_CH0P +set_location_assignment PIN_BD48 -to "qsfp0_tx[0](n)" ;# GXBL1D_TX_CH0N +set_location_assignment PIN_BB45 -to "qsfp0_rx[0]" ;# GXBL1D_RX_CH0P +set_location_assignment PIN_BB44 -to "qsfp0_rx[0](n)" ;# GXBL1D_RX_CH0N +set_location_assignment PIN_BC51 -to "qsfp0_tx[1]" ;# GXBL1D_TX_CH1P +set_location_assignment PIN_BC50 -to "qsfp0_tx[1](n)" ;# GXBL1D_TX_CH1N +set_location_assignment PIN_BC47 -to "qsfp0_rx[1]" ;# GXBL1D_RX_CH1P +set_location_assignment PIN_BC46 -to "qsfp0_rx[1](n)" ;# GXBL1D_RX_CH1N +set_location_assignment PIN_BA51 -to "qsfp0_tx[2]" ;# GXBL1D_TX_CH3P +set_location_assignment PIN_BA50 -to "qsfp0_tx[2](n)" ;# GXBL1D_TX_CH3N +set_location_assignment PIN_AY45 -to "qsfp0_rx[2]" ;# GXBL1D_RX_CH3P +set_location_assignment PIN_AY44 -to "qsfp0_rx[2](n)" ;# GXBL1D_RX_CH3N +set_location_assignment PIN_AY49 -to "qsfp0_tx[3]" ;# GXBL1D_TX_CH4P +set_location_assignment PIN_AY48 -to "qsfp0_tx[3](n)" ;# GXBL1D_TX_CH4N +set_location_assignment PIN_AW47 -to "qsfp0_rx[3]" ;# GXBL1D_RX_CH4P +set_location_assignment PIN_AW46 -to "qsfp0_rx[3](n)" ;# GXBL1D_RX_CH4N +set_location_assignment PIN_AU43 -to "qsfp0_refclk" ;# REFCLK_GXBL1D_CHBP +set_location_assignment PIN_AU42 -to "qsfp0_refclk(n)" ;# REFCLK_GXBL1D_CHBN +set_location_assignment PIN_AR43 -to "qsfp0_rcvrd_refclk" ;# REFCLK_GXBL1D_CHTP +set_location_assignment PIN_AR42 -to "qsfp0_rcvrd_refclk(n)" ;# REFCLK_GXBL1D_CHTN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp0_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp0_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp0_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp0_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp0_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp0_rcvrd_refclk" + +# QSFP1 (bank 1E) +set_location_assignment PIN_AV49 -to "qsfp1_tx[0]" ;# GXBL1E_TX_CH0P +set_location_assignment PIN_AV48 -to "qsfp1_tx[0](n)" ;# GXBL1E_TX_CH0N +set_location_assignment PIN_AU47 -to "qsfp1_rx[0]" ;# GXBL1E_RX_CH0P +set_location_assignment PIN_AU46 -to "qsfp1_rx[0](n)" ;# GXBL1E_RX_CH0N +set_location_assignment PIN_AU51 -to "qsfp1_tx[1]" ;# GXBL1E_TX_CH1P +set_location_assignment PIN_AU50 -to "qsfp1_tx[1](n)" ;# GXBL1E_TX_CH1N +set_location_assignment PIN_AT45 -to "qsfp1_rx[1]" ;# GXBL1E_RX_CH1P +set_location_assignment PIN_AT44 -to "qsfp1_rx[1](n)" ;# GXBL1E_RX_CH1N +set_location_assignment PIN_AR51 -to "qsfp1_tx[2]" ;# GXBL1E_TX_CH3P +set_location_assignment PIN_AR50 -to "qsfp1_tx[2](n)" ;# GXBL1E_TX_CH3N +set_location_assignment PIN_AP45 -to "qsfp1_rx[2]" ;# GXBL1E_RX_CH3P +set_location_assignment PIN_AP44 -to "qsfp1_rx[2](n)" ;# GXBL1E_RX_CH3N +set_location_assignment PIN_AM49 -to "qsfp1_tx[3]" ;# GXBL1E_TX_CH4P +set_location_assignment PIN_AM48 -to "qsfp1_tx[3](n)" ;# GXBL1E_TX_CH4N +set_location_assignment PIN_AL47 -to "qsfp1_rx[3]" ;# GXBL1E_RX_CH4P +set_location_assignment PIN_AL46 -to "qsfp1_rx[3](n)" ;# GXBL1E_RX_CH4N +set_location_assignment PIN_AN43 -to "qsfp1_refclk" ;# REFCLK_GXBL1E_CHBP +set_location_assignment PIN_AN42 -to "qsfp1_refclk(n)" ;# REFCLK_GXBL1E_CHBN +set_location_assignment PIN_AL43 -to "qsfp1_rcvrd_refclk" ;# REFCLK_GXBL1E_CHTP +set_location_assignment PIN_AL42 -to "qsfp1_rcvrd_refclk(n)" ;# REFCLK_GXBL1E_CHTN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp1_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp1_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp1_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp1_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp1_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp1_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp1_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp1_rcvrd_refclk" + +# QSFP2 (bank 1F, hard 100G MAC) +set_location_assignment PIN_AN51 -to "qsfp2_tx[0]" ;# GXBL1F_TX_CH0P +set_location_assignment PIN_AN50 -to "qsfp2_tx[0](n)" ;# GXBL1F_TX_CH0N +set_location_assignment PIN_AM45 -to "qsfp2_rx[0]" ;# GXBL1F_RX_CH0P +set_location_assignment PIN_AM44 -to "qsfp2_rx[0](n)" ;# GXBL1F_RX_CH0N +set_location_assignment PIN_AL51 -to "qsfp2_tx[1]" ;# GXBL1F_TX_CH1P +set_location_assignment PIN_AL50 -to "qsfp2_tx[1](n)" ;# GXBL1F_TX_CH1N +set_location_assignment PIN_AK45 -to "qsfp2_rx[1]" ;# GXBL1F_RX_CH1P +set_location_assignment PIN_AK44 -to "qsfp2_rx[1](n)" ;# GXBL1F_RX_CH1N +set_location_assignment PIN_AJ51 -to "qsfp2_tx[2]" ;# GXBL1F_TX_CH3P +set_location_assignment PIN_AJ50 -to "qsfp2_tx[2](n)" ;# GXBL1F_TX_CH3N +set_location_assignment PIN_AH45 -to "qsfp2_rx[2]" ;# GXBL1F_RX_CH3P +set_location_assignment PIN_AH44 -to "qsfp2_rx[2](n)" ;# GXBL1F_RX_CH3N +set_location_assignment PIN_AG51 -to "qsfp2_tx[3]" ;# GXBL1F_TX_CH4P +set_location_assignment PIN_AG50 -to "qsfp2_tx[3](n)" ;# GXBL1F_TX_CH4N +set_location_assignment PIN_AF45 -to "qsfp2_rx[3]" ;# GXBL1F_RX_CH4P +set_location_assignment PIN_AF44 -to "qsfp2_rx[3](n)" ;# GXBL1F_RX_CH4N +set_location_assignment PIN_AJ43 -to "qsfp2_refclk" ;# REFCLK_GXBL1F_CHBP +set_location_assignment PIN_AJ42 -to "qsfp2_refclk(n)" ;# REFCLK_GXBL1F_CHBN +set_location_assignment PIN_AG43 -to "qsfp2_rcvrd_refclk" ;# REFCLK_GXBL1F_CHTP +set_location_assignment PIN_AG42 -to "qsfp2_rcvrd_refclk(n)" ;# REFCLK_GXBL1F_CHTN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp2_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp2_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp2_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp2_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp2_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp2_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp2_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp2_rcvrd_refclk" + +# QSFP3 (bank 1N, hard 100G MAC) +set_location_assignment PIN_J51 -to "qsfp3_tx[0]" ;# GXBL1N_TX_CH0P +set_location_assignment PIN_J50 -to "qsfp3_tx[0](n)" ;# GXBL1N_TX_CH0N +set_location_assignment PIN_H45 -to "qsfp3_rx[0]" ;# GXBL1N_RX_CH0P +set_location_assignment PIN_H44 -to "qsfp3_rx[0](n)" ;# GXBL1N_RX_CH0N +set_location_assignment PIN_G51 -to "qsfp3_tx[1]" ;# GXBL1N_TX_CH1P +set_location_assignment PIN_G50 -to "qsfp3_tx[1](n)" ;# GXBL1N_TX_CH1N +set_location_assignment PIN_F45 -to "qsfp3_rx[1]" ;# GXBL1N_RX_CH1P +set_location_assignment PIN_F44 -to "qsfp3_rx[1](n)" ;# GXBL1N_RX_CH1N +set_location_assignment PIN_E51 -to "qsfp3_tx[2]" ;# GXBL1N_TX_CH3P +set_location_assignment PIN_D51 -to "qsfp3_tx[2](n)" ;# GXBL1N_TX_CH3N +set_location_assignment PIN_D45 -to "qsfp3_rx[2]" ;# GXBL1N_RX_CH3P +set_location_assignment PIN_D44 -to "qsfp3_rx[2](n)" ;# GXBL1N_RX_CH3N +set_location_assignment PIN_C50 -to "qsfp3_tx[3]" ;# GXBL1N_TX_CH4P +set_location_assignment PIN_B50 -to "qsfp3_tx[3](n)" ;# GXBL1N_TX_CH4N +set_location_assignment PIN_B44 -to "qsfp3_rx[3]" ;# GXBL1N_RX_CH4P +set_location_assignment PIN_A44 -to "qsfp3_rx[3](n)" ;# GXBL1N_RX_CH4N +set_location_assignment PIN_N43 -to "qsfp3_refclk" ;# REFCLK_GXBL1N_CHBP +set_location_assignment PIN_N42 -to "qsfp3_refclk(n)" ;# REFCLK_GXBL1N_CHBN +set_location_assignment PIN_L43 -to "qsfp3_rcvrd_refclk" ;# REFCLK_GXBL1N_CHTP +set_location_assignment PIN_L42 -to "qsfp3_rcvrd_refclk(n)" ;# REFCLK_GXBL1N_CHTN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp3_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp3_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp3_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp3_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp3_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp3_refclk" +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp3_rcvrd_refclk" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "qsfp3_rcvrd_refclk" + +set_location_assignment PIN_H19 -to "qsfp_irq_n[0]" +set_location_assignment PIN_H18 -to "qsfp_irq_n[1]" +set_location_assignment PIN_A22 -to "qsfp_irq_n[2]" +set_location_assignment PIN_C23 -to "qsfp_irq_n[3]" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_irq_n[*]" + +# OCuLink + +# OCuLink 0 (J26, PCIe, banks 4C, 4D) +set_location_assignment PIN_BL5 -to "oc0_tx[0]" ;# GXBR4C_TX_CH0P +set_location_assignment PIN_BL6 -to "oc0_tx[0](n)" ;# GXBR4C_TX_CH0N +set_location_assignment PIN_BH7 -to "oc0_rx[0]" ;# GXBR4C_RX_CH0P +set_location_assignment PIN_BH8 -to "oc0_rx[0](n)" ;# GXBR4C_RX_CH0N +set_location_assignment PIN_BK3 -to "oc0_tx[1]" ;# GXBR4C_TX_CH1P +set_location_assignment PIN_BK4 -to "oc0_tx[1](n)" ;# GXBR4C_TX_CH1N +set_location_assignment PIN_BJ5 -to "oc0_rx[1]" ;# GXBR4C_RX_CH1P +set_location_assignment PIN_BJ6 -to "oc0_rx[1](n)" ;# GXBR4C_RX_CH1N +set_location_assignment PIN_BH3 -to "oc0_tx[2]" ;# GXBR4C_TX_CH2P +set_location_assignment PIN_BH4 -to "oc0_tx[2](n)" ;# GXBR4C_TX_CH2N +set_location_assignment PIN_BG5 -to "oc0_rx[2]" ;# GXBR4C_RX_CH2P +set_location_assignment PIN_BG6 -to "oc0_rx[2](n)" ;# GXBR4C_RX_CH2N +set_location_assignment PIN_BG1 -to "oc0_tx[3]" ;# GXBR4C_TX_CH3P +set_location_assignment PIN_BG2 -to "oc0_tx[3](n)" ;# GXBR4C_TX_CH3N +set_location_assignment PIN_BF7 -to "oc0_rx[3]" ;# GXBR4C_RX_CH3P +set_location_assignment PIN_BF8 -to "oc0_rx[3](n)" ;# GXBR4C_RX_CH3N +set_location_assignment PIN_BF3 -to "oc0_tx[4]" ;# GXBR4C_TX_CH4P +set_location_assignment PIN_BF4 -to "oc0_tx[4](n)" ;# GXBR4C_TX_CH4N +set_location_assignment PIN_BE5 -to "oc0_rx[4]" ;# GXBR4C_RX_CH4P +set_location_assignment PIN_BE6 -to "oc0_rx[4](n)" ;# GXBR4C_RX_CH4N +set_location_assignment PIN_BE1 -to "oc0_tx[5]" ;# GXBR4C_TX_CH5P +set_location_assignment PIN_BE2 -to "oc0_tx[5](n)" ;# GXBR4C_TX_CH5N +set_location_assignment PIN_BD7 -to "oc0_rx[5]" ;# GXBR4C_RX_CH5P +set_location_assignment PIN_BD8 -to "oc0_rx[5](n)" ;# GXBR4C_RX_CH5N +set_location_assignment PIN_BD3 -to "oc0_tx[6]" ;# GXBR4D_TX_CH0P +set_location_assignment PIN_BD4 -to "oc0_tx[6](n)" ;# GXBR4D_TX_CH0N +set_location_assignment PIN_BB7 -to "oc0_rx[6]" ;# GXBR4D_RX_CH0P +set_location_assignment PIN_BB8 -to "oc0_rx[6](n)" ;# GXBR4D_RX_CH0N +set_location_assignment PIN_BC1 -to "oc0_tx[7]" ;# GXBR4D_TX_CH1P +set_location_assignment PIN_BC2 -to "oc0_tx[7](n)" ;# GXBR4D_TX_CH1N +set_location_assignment PIN_BC5 -to "oc0_rx[7]" ;# GXBR4D_RX_CH1P +set_location_assignment PIN_BC6 -to "oc0_rx[7](n)" ;# GXBR4D_RX_CH1N +set_location_assignment PIN_AW9 -to "oc0_refclk_1" ;# REFCLK_GXBR4C_CHTP +set_location_assignment PIN_AW10 -to "oc0_refclk_1(n)" ;# REFCLK_GXBR4C_CHTN +set_location_assignment PIN_BA9 -to "oc0_refclk_2" ;# REFCLK_GXBR4C_CHBP +set_location_assignment PIN_BA10 -to "oc0_refclk_2(n)" ;# REFCLK_GXBR4C_CHBN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc0_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc0_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc0_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc0_rx[*]" + +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc0_refclk_1" +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc0_refclk_2" + +set_location_assignment PIN_BL10 -to "oc0_gpio[0]" +set_location_assignment PIN_BH10 -to "oc0_gpio[1]" +set_location_assignment PIN_BG10 -to "oc0_gpio[2]" +set_location_assignment PIN_BF10 -to "oc0_gpio[3]" +set_location_assignment PIN_AT15 -to "oc0_gpio[4]" +set_location_assignment PIN_AR15 -to "oc0_gpio[5]" +set_location_assignment PIN_AV15 -to "oc0_gpio[6]" +set_location_assignment PIN_AU15 -to "oc0_gpio[7]" +set_location_assignment PIN_AW14 -to "oc0_gpio[8]" +set_location_assignment PIN_AV14 -to "oc0_gpio[9]" +set_location_assignment PIN_AY14 -to "oc0_gpio[10]" +set_location_assignment PIN_BA14 -to "oc0_gpio[11]" +set_location_assignment PIN_BB15 -to "oc0_gpio[12]" +set_location_assignment PIN_BA15 -to "oc0_gpio[13]" +set_location_assignment PIN_BC14 -to "oc0_gpio[14]" +set_location_assignment PIN_BC15 -to "oc0_gpio[15]" + +set_location_assignment PIN_BE10 -to "oc0_gpio_dir[0]" +set_location_assignment PIN_BD10 -to "oc0_gpio_dir[1]" +set_location_assignment PIN_BC10 -to "oc0_gpio_dir[2]" +set_location_assignment PIN_AP39 -to "oc0_gpio_dir[3]" +set_location_assignment PIN_BF14 -to "oc0_gpio_dir[4]" +set_location_assignment PIN_BF13 -to "oc0_gpio_dir[5]" +set_location_assignment PIN_BH13 -to "oc0_gpio_dir[6]" +set_location_assignment PIN_BG13 -to "oc0_gpio_dir[7]" +set_location_assignment PIN_BJ13 -to "oc0_gpio_dir[8]" +set_location_assignment PIN_BJ12 -to "oc0_gpio_dir[9]" +set_location_assignment PIN_BJ14 -to "oc0_gpio_dir[10]" +set_location_assignment PIN_BK14 -to "oc0_gpio_dir[11]" +set_location_assignment PIN_BL14 -to "oc0_gpio_dir[12]" +set_location_assignment PIN_BL13 -to "oc0_gpio_dir[13]" +set_location_assignment PIN_AU17 -to "oc0_gpio_dir[14]" +set_location_assignment PIN_AU16 -to "oc0_gpio_dir[15]" + +set_location_assignment PIN_AW17 -to "oc0_buff_en_n[0]" +set_location_assignment PIN_AY17 -to "oc0_buff_en_n[1]" +set_location_assignment PIN_AW16 -to "oc0_buff_en_n[2]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio[15]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc0_gpio_dir[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc0_gpio_dir[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_gpio_dir[15]" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc0_buff_en_n[*]" + +# OCuLink 1 (J27, PCIe, banks 4K, 4L) +set_location_assignment PIN_AF3 -to "oc1_tx[0]" ;# GXBR4K_TX_CH0P +set_location_assignment PIN_AF4 -to "oc1_tx[0](n)" ;# GXBR4K_TX_CH0N +set_location_assignment PIN_AE5 -to "oc1_rx[0]" ;# GXBR4K_RX_CH0P +set_location_assignment PIN_AE6 -to "oc1_rx[0](n)" ;# GXBR4K_RX_CH0N +set_location_assignment PIN_AE1 -to "oc1_tx[1]" ;# GXBR4K_TX_CH1P +set_location_assignment PIN_AE2 -to "oc1_tx[1](n)" ;# GXBR4K_TX_CH1N +set_location_assignment PIN_AD7 -to "oc1_rx[1]" ;# GXBR4K_RX_CH1P +set_location_assignment PIN_AD8 -to "oc1_rx[1](n)" ;# GXBR4K_RX_CH1N +set_location_assignment PIN_AD3 -to "oc1_tx[2]" ;# GXBR4K_TX_CH2P +set_location_assignment PIN_AD4 -to "oc1_tx[2](n)" ;# GXBR4K_TX_CH2N +set_location_assignment PIN_AC5 -to "oc1_rx[2]" ;# GXBR4K_RX_CH2P +set_location_assignment PIN_AC6 -to "oc1_rx[2](n)" ;# GXBR4K_RX_CH2N +set_location_assignment PIN_AC1 -to "oc1_tx[3]" ;# GXBR4K_TX_CH3P +set_location_assignment PIN_AC2 -to "oc1_tx[3](n)" ;# GXBR4K_TX_CH3N +set_location_assignment PIN_AB7 -to "oc1_rx[3]" ;# GXBR4K_RX_CH3P +set_location_assignment PIN_AB8 -to "oc1_rx[3](n)" ;# GXBR4K_RX_CH3N +set_location_assignment PIN_AB3 -to "oc1_tx[4]" ;# GXBR4K_TX_CH4P +set_location_assignment PIN_AB4 -to "oc1_tx[4](n)" ;# GXBR4K_TX_CH4N +set_location_assignment PIN_AA5 -to "oc1_rx[4]" ;# GXBR4K_RX_CH4P +set_location_assignment PIN_AA6 -to "oc1_rx[4](n)" ;# GXBR4K_RX_CH4N +set_location_assignment PIN_AA1 -to "oc1_tx[5]" ;# GXBR4K_TX_CH5P +set_location_assignment PIN_AA2 -to "oc1_tx[5](n)" ;# GXBR4K_TX_CH5N +set_location_assignment PIN_Y7 -to "oc1_rx[5]" ;# GXBR4K_RX_CH5P +set_location_assignment PIN_Y8 -to "oc1_rx[5](n)" ;# GXBR4K_RX_CH5N +set_location_assignment PIN_Y3 -to "oc1_tx[6]" ;# GXBR4L_TX_CH0P +set_location_assignment PIN_Y4 -to "oc1_tx[6](n)" ;# GXBR4L_TX_CH0N +set_location_assignment PIN_W5 -to "oc1_rx[6]" ;# GXBR4L_RX_CH0P +set_location_assignment PIN_W6 -to "oc1_rx[6](n)" ;# GXBR4L_RX_CH0N +set_location_assignment PIN_W1 -to "oc1_tx[7]" ;# GXBR4L_TX_CH1P +set_location_assignment PIN_W2 -to "oc1_tx[7](n)" ;# GXBR4L_TX_CH1N +set_location_assignment PIN_V7 -to "oc1_rx[7]" ;# GXBR4L_RX_CH1P +set_location_assignment PIN_V8 -to "oc1_rx[7](n)" ;# GXBR4L_RX_CH1N +set_location_assignment PIN_AC9 -to "oc1_refclk_1" ;# REFCLK_GXBR4K_CHTP +set_location_assignment PIN_AC10 -to "oc1_refclk_1(n)" ;# REFCLK_GXBR4K_CHTN +set_location_assignment PIN_AE9 -to "oc1_refclk_2" ;# REFCLK_GXBR4K_CHBP +set_location_assignment PIN_AE10 -to "oc1_refclk_2(n)" ;# REFCLK_GXBR4K_CHBN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc1_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc1_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc1_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc1_rx[*]" + +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc1_refclk_1" +set_instance_assignment -name IO_STANDARD "HCSL" -to "oc1_refclk_2" + +set_location_assignment PIN_AG13 -to "oc1_gpio[0]" +set_location_assignment PIN_AL13 -to "oc1_gpio[1]" +set_location_assignment PIN_AM13 -to "oc1_gpio[2]" +set_location_assignment PIN_AN13 -to "oc1_gpio[3]" +set_location_assignment PIN_C16 -to "oc1_gpio[4]" +set_location_assignment PIN_D16 -to "oc1_gpio[5]" +set_location_assignment PIN_B15 -to "oc1_gpio[6]" +set_location_assignment PIN_B16 -to "oc1_gpio[7]" +set_location_assignment PIN_C14 -to "oc1_gpio[8]" +set_location_assignment PIN_C15 -to "oc1_gpio[9]" +set_location_assignment PIN_A14 -to "oc1_gpio[10]" +set_location_assignment PIN_A15 -to "oc1_gpio[11]" +set_location_assignment PIN_E15 -to "oc1_gpio[12]" +set_location_assignment PIN_F15 -to "oc1_gpio[13]" +set_location_assignment PIN_H15 -to "oc1_gpio[14]" +set_location_assignment PIN_G15 -to "oc1_gpio[15]" + +set_location_assignment PIN_AH13 -to "oc1_gpio_dir[0]" +set_location_assignment PIN_AP13 -to "oc1_gpio_dir[1]" +set_location_assignment PIN_AF13 -to "oc1_gpio_dir[2]" +set_location_assignment PIN_AC38 -to "oc1_gpio_dir[3]" +set_location_assignment PIN_J16 -to "oc1_gpio_dir[4]" +set_location_assignment PIN_K16 -to "oc1_gpio_dir[5]" +set_location_assignment PIN_L15 -to "oc1_gpio_dir[6]" +set_location_assignment PIN_K15 -to "oc1_gpio_dir[7]" +set_location_assignment PIN_M15 -to "oc1_gpio_dir[8]" +set_location_assignment PIN_N15 -to "oc1_gpio_dir[9]" +set_location_assignment PIN_M16 -to "oc1_gpio_dir[10]" +set_location_assignment PIN_N16 -to "oc1_gpio_dir[11]" +set_location_assignment PIN_P16 -to "oc1_gpio_dir[12]" +set_location_assignment PIN_R16 -to "oc1_gpio_dir[13]" +set_location_assignment PIN_A13 -to "oc1_gpio_dir[14]" +set_location_assignment PIN_A12 -to "oc1_gpio_dir[15]" + +set_location_assignment PIN_B13 -to "oc1_buff_en_n[0]" +set_location_assignment PIN_C13 -to "oc1_buff_en_n[1]" +set_location_assignment PIN_B12 -to "oc1_buff_en_n[2]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio[15]" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[0]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[1]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[2]" +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc1_gpio_dir[3]" + +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[0]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[1]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[2]" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc1_gpio_dir[3]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[4]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[5]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[6]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[7]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[8]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[9]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[10]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[11]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[12]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[13]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[14]" +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_gpio_dir[15]" + +set_instance_assignment -name IO_STANDARD "1.8 V" -to "oc1_buff_en_n[*]" + +# OCuLink 2 (J22, 25G, banks 4M, 4N) +set_location_assignment PIN_P3 -to "oc2_tx[0]" ;# GXBR4M_TX_CH0P +set_location_assignment PIN_P4 -to "oc2_tx[0](n)" ;# GXBR4M_TX_CH0N +set_location_assignment PIN_N5 -to "oc2_rx[0]" ;# GXBR4M_RX_CH0P +set_location_assignment PIN_N6 -to "oc2_rx[0](n)" ;# GXBR4M_RX_CH0N +set_location_assignment PIN_N1 -to "oc2_tx[1]" ;# GXBR4M_TX_CH1P +set_location_assignment PIN_N2 -to "oc2_tx[1](n)" ;# GXBR4M_TX_CH1N +set_location_assignment PIN_M7 -to "oc2_rx[1]" ;# GXBR4M_RX_CH1P +set_location_assignment PIN_M8 -to "oc2_rx[1](n)" ;# GXBR4M_RX_CH1N +set_location_assignment PIN_L1 -to "oc2_tx[2]" ;# GXBR4M_TX_CH3P +set_location_assignment PIN_L2 -to "oc2_tx[2](n)" ;# GXBR4M_TX_CH3N +set_location_assignment PIN_K7 -to "oc2_rx[2]" ;# GXBR4M_RX_CH3P +set_location_assignment PIN_K8 -to "oc2_rx[2](n)" ;# GXBR4M_RX_CH3N +set_location_assignment PIN_K3 -to "oc2_tx[3]" ;# GXBR4M_TX_CH3P +set_location_assignment PIN_K4 -to "oc2_tx[3](n)" ;# GXBR4M_TX_CH3N +set_location_assignment PIN_J5 -to "oc2_rx[3]" ;# GXBR4M_RX_CH3P +set_location_assignment PIN_J6 -to "oc2_rx[3](n)" ;# GXBR4M_RX_CH3N +set_location_assignment PIN_H3 -to "oc2_tx[4]" ;# GXBR4N_TX_CH0P +set_location_assignment PIN_H4 -to "oc2_tx[4](n)" ;# GXBR4N_TX_CH0N +set_location_assignment PIN_G5 -to "oc2_rx[4]" ;# GXBR4N_RX_CH0P +set_location_assignment PIN_G6 -to "oc2_rx[4](n)" ;# GXBR4N_RX_CH0N +set_location_assignment PIN_G1 -to "oc2_tx[5]" ;# GXBR4N_TX_CH1P +set_location_assignment PIN_G2 -to "oc2_tx[5](n)" ;# GXBR4N_TX_CH1N +set_location_assignment PIN_F7 -to "oc2_rx[5]" ;# GXBR4N_RX_CH1P +set_location_assignment PIN_F8 -to "oc2_rx[5](n)" ;# GXBR4N_RX_CH1N +set_location_assignment PIN_E1 -to "oc2_tx[6]" ;# GXBR4N_TX_CH3P +set_location_assignment PIN_E2 -to "oc2_tx[6](n)" ;# GXBR4N_TX_CH3N +set_location_assignment PIN_D7 -to "oc2_rx[6]" ;# GXBR4N_RX_CH3P +set_location_assignment PIN_D8 -to "oc2_rx[6](n)" ;# GXBR4N_RX_CH3N +set_location_assignment PIN_D3 -to "oc2_tx[7]" ;# GXBR4N_TX_CH4P +set_location_assignment PIN_D4 -to "oc2_tx[7](n)" ;# GXBR4N_TX_CH4N +set_location_assignment PIN_C5 -to "oc2_rx[7]" ;# GXBR4N_RX_CH4P +set_location_assignment PIN_C6 -to "oc2_rx[7](n)" ;# GXBR4N_RX_CH4N +set_location_assignment PIN_R9 -to "oc2_refclk_1" ;# REFCLK_GXBR4M_CHTP +set_location_assignment PIN_R10 -to "oc2_refclk_1(n)" ;# REFCLK_GXBR4M_CHTN +set_location_assignment PIN_L9 -to "oc2_refclk_2" ;# REFCLK_GXBR4N_CHTP +set_location_assignment PIN_L10 -to "oc2_refclk_2(n)" ;# REFCLK_GXBR4N_CHTN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc2_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc2_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc2_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc2_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "oc2_refclk_1" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc2_refclk_1" +set_instance_assignment -name IO_STANDARD LVDS -to "oc2_refclk_2" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc2_refclk_2" + +set_location_assignment PIN_AJ13 -to "oc2_perst_n" +set_location_assignment PIN_AC39 -to "oc2_buff_in_sel" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc2_perst_n" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc2_perst_n" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc2_buff_in_sel" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc2_buff_in_sel" + +# OCuLink 3 (J23, 25G, banks 4E, 4F) +set_location_assignment PIN_AV3 -to "oc3_tx[0]" ;# GXBR4E_TX_CH0P +set_location_assignment PIN_AV4 -to "oc3_tx[0](n)" ;# GXBR4E_TX_CH0N +set_location_assignment PIN_AU5 -to "oc3_rx[0]" ;# GXBR4E_RX_CH0P +set_location_assignment PIN_AU6 -to "oc3_rx[0](n)" ;# GXBR4E_RX_CH0N +set_location_assignment PIN_AU1 -to "oc3_tx[1]" ;# GXBR4C_TX_CH1P +set_location_assignment PIN_AU2 -to "oc3_tx[1](n)" ;# GXBR4C_TX_CH1N +set_location_assignment PIN_AT7 -to "oc3_rx[1]" ;# GXBR4C_RX_CH1P +set_location_assignment PIN_AT8 -to "oc3_rx[1](n)" ;# GXBR4C_RX_CH1N +set_location_assignment PIN_AR1 -to "oc3_tx[2]" ;# GXBR4C_TX_CH3P +set_location_assignment PIN_AR2 -to "oc3_tx[2](n)" ;# GXBR4C_TX_CH3N +set_location_assignment PIN_AP7 -to "oc3_rx[2]" ;# GXBR4C_RX_CH3P +set_location_assignment PIN_AP8 -to "oc3_rx[2](n)" ;# GXBR4C_RX_CH3N +set_location_assignment PIN_AP3 -to "oc3_tx[3]" ;# GXBR4C_TX_CH4P +set_location_assignment PIN_AP4 -to "oc3_tx[3](n)" ;# GXBR4C_TX_CH4N +set_location_assignment PIN_AN5 -to "oc3_rx[3]" ;# GXBR4C_RX_CH4P +set_location_assignment PIN_AN6 -to "oc3_rx[3](n)" ;# GXBR4C_RX_CH4N +set_location_assignment PIN_AM3 -to "oc3_tx[4]" ;# GXBR4D_TX_CH0P +set_location_assignment PIN_AM4 -to "oc3_tx[4](n)" ;# GXBR4D_TX_CH0N +set_location_assignment PIN_AL5 -to "oc3_rx[4]" ;# GXBR4D_RX_CH0P +set_location_assignment PIN_AL6 -to "oc3_rx[4](n)" ;# GXBR4D_RX_CH0N +set_location_assignment PIN_AL1 -to "oc3_tx[5]" ;# GXBR4D_TX_CH1P +set_location_assignment PIN_AL2 -to "oc3_tx[5](n)" ;# GXBR4D_TX_CH1N +set_location_assignment PIN_AK7 -to "oc3_rx[5]" ;# GXBR4D_RX_CH1P +set_location_assignment PIN_AK8 -to "oc3_rx[5](n)" ;# GXBR4D_RX_CH1N +set_location_assignment PIN_AJ1 -to "oc3_tx[6]" ;# GXBR4D_TX_CH3P +set_location_assignment PIN_AJ2 -to "oc3_tx[6](n)" ;# GXBR4D_TX_CH3N +set_location_assignment PIN_AH7 -to "oc3_rx[6]" ;# GXBR4D_RX_CH3P +set_location_assignment PIN_AH8 -to "oc3_rx[6](n)" ;# GXBR4D_RX_CH3N +set_location_assignment PIN_AH3 -to "oc3_tx[7]" ;# GXBR4D_TX_CH4P +set_location_assignment PIN_AH4 -to "oc3_tx[7](n)" ;# GXBR4D_TX_CH4N +set_location_assignment PIN_AG5 -to "oc3_rx[7]" ;# GXBR4D_RX_CH4P +set_location_assignment PIN_AG6 -to "oc3_rx[7](n)" ;# GXBR4D_RX_CH4N +set_location_assignment PIN_AL9 -to "oc3_refclk_1" ;# REFCLK_GXBR4E_CHTP +set_location_assignment PIN_AL10 -to "oc3_refclk_1(n)" ;# REFCLK_GXBR4E_CHTN +set_location_assignment PIN_AG9 -to "oc3_refclk_2" ;# REFCLK_GXBR4F_CHTP +set_location_assignment PIN_AG10 -to "oc3_refclk_2(n)" ;# REFCLK_GXBR4F_CHTN + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc3_tx[*]" +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "oc3_rx[*]" + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc3_tx[*]" +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "oc3_rx[*]" + +set_instance_assignment -name IO_STANDARD LVDS -to "oc3_refclk_1" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc3_refclk_1" +set_instance_assignment -name IO_STANDARD LVDS -to "oc3_refclk_2" +set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to "oc3_refclk_2" + +set_location_assignment PIN_BK10 -to "oc3_perst_n" +set_location_assignment PIN_AN39 -to "oc3_buff_in_sel" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc3_perst_n" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc3_perst_n" + +set_instance_assignment -name USE_AS_3V_GPIO ON -to "oc3_buff_in_sel" +set_instance_assignment -name IO_STANDARD "2.5 V" -to "oc3_buff_in_sel" + +# DDR4 module 0 +set_location_assignment PIN_BA33 -to "mem0_rzq" + +set_location_assignment PIN_BC31 -to "mem0_alert_n" +set_location_assignment PIN_AW33 -to "mem0_reset_n" +set_location_assignment PIN_BH35 -to "mem0_par" + +set_location_assignment PIN_BL34 -to "mem0_a[0]" +set_location_assignment PIN_BK34 -to "mem0_a[1]" +set_location_assignment PIN_BJ34 -to "mem0_a[2]" +set_location_assignment PIN_BH34 -to "mem0_a[3]" +set_location_assignment PIN_BH33 -to "mem0_a[4]" +set_location_assignment PIN_BJ33 -to "mem0_a[5]" +set_location_assignment PIN_BK35 -to "mem0_a[6]" +set_location_assignment PIN_BL35 -to "mem0_a[7]" +set_location_assignment PIN_BD33 -to "mem0_a[8]" +set_location_assignment PIN_BC33 -to "mem0_a[9]" +set_location_assignment PIN_BG33 -to "mem0_a[10]" +set_location_assignment PIN_BF33 -to "mem0_a[11]" +set_location_assignment PIN_BB33 -to "mem0_a[12]" +set_location_assignment PIN_BB32 -to "mem0_a[13]" +set_location_assignment PIN_BA32 -to "mem0_a[14]" +set_location_assignment PIN_AW32 -to "mem0_a[15]" +set_location_assignment PIN_AY32 -to "mem0_a[16]" +set_location_assignment PIN_BD32 -to "mem0_bg[0]" +set_location_assignment PIN_AV33 -to "mem0_bg[1]" +set_location_assignment PIN_AV34 -to "mem0_act_n" +set_location_assignment PIN_BA34 -to "mem0_odt[0]" +set_location_assignment PIN_AY34 -to "mem0_odt[1]" +set_location_assignment PIN_BF34 -to "mem0_ck_p[0]" +set_location_assignment PIN_BE34 -to "mem0_ck_n[0]" +set_location_assignment PIN_AW34 -to "mem0_cs_n[0]" +set_location_assignment PIN_BG35 -to "mem0_cs_n[1]" +set_location_assignment PIN_BD34 -to "mem0_cke[0]" +set_location_assignment PIN_BC34 -to "mem0_cke[1]" +set_location_assignment PIN_BF32 -to "mem0_ba[0]" +set_location_assignment PIN_BE32 -to "mem0_ba[1]" + +set_location_assignment PIN_BF23 -to "mem0_dqs_p[0]" +set_location_assignment PIN_BG23 -to "mem0_dqs_n[0]" +set_location_assignment PIN_BJ22 -to "mem0_dqs_p[1]" +set_location_assignment PIN_BK22 -to "mem0_dqs_n[1]" +set_location_assignment PIN_BC26 -to "mem0_dqs_p[2]" +set_location_assignment PIN_BD26 -to "mem0_dqs_n[2]" +set_location_assignment PIN_BG25 -to "mem0_dqs_p[3]" +set_location_assignment PIN_BF25 -to "mem0_dqs_n[3]" +set_location_assignment PIN_BK26 -to "mem0_dqs_p[4]" +set_location_assignment PIN_BK25 -to "mem0_dqs_n[4]" +set_location_assignment PIN_BK24 -to "mem0_dqs_p[5]" +set_location_assignment PIN_BJ24 -to "mem0_dqs_n[5]" +set_location_assignment PIN_BJ28 -to "mem0_dqs_p[6]" +set_location_assignment PIN_BH28 -to "mem0_dqs_n[6]" +set_location_assignment PIN_BK27 -to "mem0_dqs_p[7]" +set_location_assignment PIN_BJ27 -to "mem0_dqs_n[7]" +set_location_assignment PIN_BF29 -to "mem0_dqs_p[8]" +set_location_assignment PIN_BE29 -to "mem0_dqs_n[8]" +set_location_assignment PIN_BA28 -to "mem0_dqs_p[9]" +set_location_assignment PIN_BA29 -to "mem0_dqs_n[9]" +set_location_assignment PIN_BB30 -to "mem0_dqs_p[10]" +set_location_assignment PIN_BC30 -to "mem0_dqs_n[10]" +set_location_assignment PIN_BH30 -to "mem0_dqs_p[11]" +set_location_assignment PIN_BG30 -to "mem0_dqs_n[11]" +set_location_assignment PIN_BK39 -to "mem0_dqs_p[12]" +set_location_assignment PIN_BL39 -to "mem0_dqs_n[12]" +set_location_assignment PIN_BG40 -to "mem0_dqs_p[13]" +set_location_assignment PIN_BH40 -to "mem0_dqs_n[13]" +set_location_assignment PIN_BH38 -to "mem0_dqs_p[14]" +set_location_assignment PIN_BJ38 -to "mem0_dqs_n[14]" +set_location_assignment PIN_BC38 -to "mem0_dqs_p[15]" +set_location_assignment PIN_BD38 -to "mem0_dqs_n[15]" +set_location_assignment PIN_BA37 -to "mem0_dqs_p[16]" +set_location_assignment PIN_BB37 -to "mem0_dqs_n[16]" +set_location_assignment PIN_BG37 -to "mem0_dqs_p[17]" +set_location_assignment PIN_BF37 -to "mem0_dqs_n[17]" + +set_location_assignment PIN_BE24 -to "mem0_dq[0]" +set_location_assignment PIN_BF24 -to "mem0_dq[1]" +set_location_assignment PIN_BH24 -to "mem0_dq[2]" +set_location_assignment PIN_BH25 -to "mem0_dq[3]" +set_location_assignment PIN_BL23 -to "mem0_dq[4]" +set_location_assignment PIN_BL22 -to "mem0_dq[5]" +set_location_assignment PIN_BJ23 -to "mem0_dq[6]" +set_location_assignment PIN_BH23 -to "mem0_dq[7]" +set_location_assignment PIN_AW28 -to "mem0_dq[8]" +set_location_assignment PIN_AW27 -to "mem0_dq[9]" +set_location_assignment PIN_AY27 -to "mem0_dq[10]" +set_location_assignment PIN_BA27 -to "mem0_dq[11]" +set_location_assignment PIN_BE26 -to "mem0_dq[12]" +set_location_assignment PIN_BE25 -to "mem0_dq[13]" +set_location_assignment PIN_BB26 -to "mem0_dq[14]" +set_location_assignment PIN_BB27 -to "mem0_dq[15]" +set_location_assignment PIN_BE27 -to "mem0_dq[16]" +set_location_assignment PIN_BF27 -to "mem0_dq[17]" +set_location_assignment PIN_BG26 -to "mem0_dq[18]" +set_location_assignment PIN_BG27 -to "mem0_dq[19]" +set_location_assignment PIN_BL25 -to "mem0_dq[20]" +set_location_assignment PIN_BL24 -to "mem0_dq[21]" +set_location_assignment PIN_BJ26 -to "mem0_dq[22]" +set_location_assignment PIN_BH26 -to "mem0_dq[23]" +set_location_assignment PIN_BC28 -to "mem0_dq[24]" +set_location_assignment PIN_BB28 -to "mem0_dq[25]" +set_location_assignment PIN_BD28 -to "mem0_dq[26]" +set_location_assignment PIN_BD27 -to "mem0_dq[27]" +set_location_assignment PIN_BL28 -to "mem0_dq[28]" +set_location_assignment PIN_BL27 -to "mem0_dq[29]" +set_location_assignment PIN_BG28 -to "mem0_dq[30]" +set_location_assignment PIN_BF28 -to "mem0_dq[31]" +set_location_assignment PIN_BK30 -to "mem0_dq[32]" +set_location_assignment PIN_BL30 -to "mem0_dq[33]" +set_location_assignment PIN_BK29 -to "mem0_dq[34]" +set_location_assignment PIN_BL29 -to "mem0_dq[35]" +set_location_assignment PIN_BD29 -to "mem0_dq[36]" +set_location_assignment PIN_BC29 -to "mem0_dq[37]" +set_location_assignment PIN_BJ29 -to "mem0_dq[38]" +set_location_assignment PIN_BH29 -to "mem0_dq[39]" +set_location_assignment PIN_AV30 -to "mem0_dq[40]" +set_location_assignment PIN_AV29 -to "mem0_dq[41]" +set_location_assignment PIN_AW29 -to "mem0_dq[42]" +set_location_assignment PIN_AY29 -to "mem0_dq[43]" +set_location_assignment PIN_BF30 -to "mem0_dq[44]" +set_location_assignment PIN_BE30 -to "mem0_dq[45]" +set_location_assignment PIN_AY30 -to "mem0_dq[46]" +set_location_assignment PIN_BA30 -to "mem0_dq[47]" +set_location_assignment PIN_BJ39 -to "mem0_dq[48]" +set_location_assignment PIN_BH39 -to "mem0_dq[49]" +set_location_assignment PIN_BF39 -to "mem0_dq[50]" +set_location_assignment PIN_BE39 -to "mem0_dq[51]" +set_location_assignment PIN_BE40 -to "mem0_dq[52]" +set_location_assignment PIN_BF40 -to "mem0_dq[53]" +set_location_assignment PIN_BK40 -to "mem0_dq[54]" +set_location_assignment PIN_BL40 -to "mem0_dq[55]" +set_location_assignment PIN_BL37 -to "mem0_dq[56]" +set_location_assignment PIN_BL38 -to "mem0_dq[57]" +set_location_assignment PIN_BJ37 -to "mem0_dq[58]" +set_location_assignment PIN_BK37 -to "mem0_dq[59]" +set_location_assignment PIN_BC39 -to "mem0_dq[60]" +set_location_assignment PIN_BD39 -to "mem0_dq[61]" +set_location_assignment PIN_BF38 -to "mem0_dq[62]" +set_location_assignment PIN_BG38 -to "mem0_dq[63]" +set_location_assignment PIN_BC36 -to "mem0_dq[64]" +set_location_assignment PIN_BB36 -to "mem0_dq[65]" +set_location_assignment PIN_AY36 -to "mem0_dq[66]" +set_location_assignment PIN_AW36 -to "mem0_dq[67]" +set_location_assignment PIN_BD37 -to "mem0_dq[68]" +set_location_assignment PIN_BE37 -to "mem0_dq[69]" +set_location_assignment PIN_AW37 -to "mem0_dq[70]" +set_location_assignment PIN_AY37 -to "mem0_dq[71]" + +# DDR4 module 1 +set_location_assignment PIN_A40 -to "mem1_rzq" + +set_location_assignment PIN_P36 -to "mem1_alert_n" +set_location_assignment PIN_F35 -to "mem1_reset_n" +set_location_assignment PIN_A39 -to "mem1_par" + +set_location_assignment PIN_H34 -to "mem1_a[0]" +set_location_assignment PIN_J34 -to "mem1_a[1]" +set_location_assignment PIN_G35 -to "mem1_a[2]" +set_location_assignment PIN_H35 -to "mem1_a[3]" +set_location_assignment PIN_L35 -to "mem1_a[4]" +set_location_assignment PIN_K35 -to "mem1_a[5]" +set_location_assignment PIN_L34 -to "mem1_a[6]" +set_location_assignment PIN_K34 -to "mem1_a[7]" +set_location_assignment PIN_N34 -to "mem1_a[8]" +set_location_assignment PIN_P34 -to "mem1_a[9]" +set_location_assignment PIN_M35 -to "mem1_a[10]" +set_location_assignment PIN_N35 -to "mem1_a[11]" +set_location_assignment PIN_B40 -to "mem1_a[12]" +set_location_assignment PIN_C39 -to "mem1_a[13]" +set_location_assignment PIN_D39 -to "mem1_a[14]" +set_location_assignment PIN_D38 -to "mem1_a[15]" +set_location_assignment PIN_C38 -to "mem1_a[16]" +set_location_assignment PIN_G37 -to "mem1_bg[0]" +set_location_assignment PIN_F34 -to "mem1_bg[1]" +set_location_assignment PIN_E35 -to "mem1_act_n" +set_location_assignment PIN_C36 -to "mem1_odt[0]" +set_location_assignment PIN_D36 -to "mem1_odt[1]" +set_location_assignment PIN_B37 -to "mem1_ck_p[0]" +set_location_assignment PIN_B38 -to "mem1_ck_n[0]" +set_location_assignment PIN_E36 -to "mem1_cs_n[0]" +set_location_assignment PIN_A38 -to "mem1_cs_n[1]" +set_location_assignment PIN_B36 -to "mem1_cke[0]" +set_location_assignment PIN_A37 -to "mem1_cke[1]" +set_location_assignment PIN_D37 -to "mem1_ba[0]" +set_location_assignment PIN_F37 -to "mem1_ba[1]" + +set_location_assignment PIN_K29 -to "mem1_dqs_p[0]" +set_location_assignment PIN_L29 -to "mem1_dqs_n[0]" +set_location_assignment PIN_R30 -to "mem1_dqs_p[1]" +set_location_assignment PIN_R29 -to "mem1_dqs_n[1]" +set_location_assignment PIN_E29 -to "mem1_dqs_p[2]" +set_location_assignment PIN_F29 -to "mem1_dqs_n[2]" +set_location_assignment PIN_G30 -to "mem1_dqs_p[3]" +set_location_assignment PIN_H30 -to "mem1_dqs_n[3]" +set_location_assignment PIN_M31 -to "mem1_dqs_p[4]" +set_location_assignment PIN_N31 -to "mem1_dqs_n[4]" +set_location_assignment PIN_P32 -to "mem1_dqs_p[5]" +set_location_assignment PIN_R32 -to "mem1_dqs_n[5]" +set_location_assignment PIN_G33 -to "mem1_dqs_p[6]" +set_location_assignment PIN_F33 -to "mem1_dqs_n[6]" +set_location_assignment PIN_K32 -to "mem1_dqs_p[7]" +set_location_assignment PIN_J32 -to "mem1_dqs_n[7]" +set_location_assignment PIN_D32 -to "mem1_dqs_p[8]" +set_location_assignment PIN_E32 -to "mem1_dqs_n[8]" +set_location_assignment PIN_G31 -to "mem1_dqs_p[9]" +set_location_assignment PIN_H31 -to "mem1_dqs_n[9]" +set_location_assignment PIN_B31 -to "mem1_dqs_p[10]" +set_location_assignment PIN_A32 -to "mem1_dqs_n[10]" +set_location_assignment PIN_A35 -to "mem1_dqs_p[11]" +set_location_assignment PIN_B35 -to "mem1_dqs_n[11]" +set_location_assignment PIN_E41 -to "mem1_dqs_p[12]" +set_location_assignment PIN_E40 -to "mem1_dqs_n[12]" +set_location_assignment PIN_C42 -to "mem1_dqs_p[13]" +set_location_assignment PIN_B42 -to "mem1_dqs_n[13]" +set_location_assignment PIN_H38 -to "mem1_dqs_p[14]" +set_location_assignment PIN_J38 -to "mem1_dqs_n[14]" +set_location_assignment PIN_H39 -to "mem1_dqs_p[15]" +set_location_assignment PIN_G38 -to "mem1_dqs_n[15]" +set_location_assignment PIN_E42 -to "mem1_dqs_p[16]" +set_location_assignment PIN_F42 -to "mem1_dqs_n[16]" +set_location_assignment PIN_L38 -to "mem1_dqs_p[17]" +set_location_assignment PIN_L39 -to "mem1_dqs_n[17]" + +set_location_assignment PIN_H29 -to "mem1_dq[0]" +set_location_assignment PIN_J29 -to "mem1_dq[1]" +set_location_assignment PIN_M30 -to "mem1_dq[2]" +set_location_assignment PIN_N30 -to "mem1_dq[3]" +set_location_assignment PIN_N29 -to "mem1_dq[4]" +set_location_assignment PIN_P29 -to "mem1_dq[5]" +set_location_assignment PIN_K30 -to "mem1_dq[6]" +set_location_assignment PIN_L30 -to "mem1_dq[7]" +set_location_assignment PIN_A28 -to "mem1_dq[8]" +set_location_assignment PIN_A29 -to "mem1_dq[9]" +set_location_assignment PIN_C28 -to "mem1_dq[10]" +set_location_assignment PIN_B28 -to "mem1_dq[11]" +set_location_assignment PIN_E30 -to "mem1_dq[12]" +set_location_assignment PIN_F30 -to "mem1_dq[13]" +set_location_assignment PIN_C29 -to "mem1_dq[14]" +set_location_assignment PIN_D29 -to "mem1_dq[15]" +set_location_assignment PIN_N33 -to "mem1_dq[16]" +set_location_assignment PIN_P33 -to "mem1_dq[17]" +set_location_assignment PIN_L33 -to "mem1_dq[18]" +set_location_assignment PIN_M33 -to "mem1_dq[19]" +set_location_assignment PIN_P31 -to "mem1_dq[20]" +set_location_assignment PIN_R31 -to "mem1_dq[21]" +set_location_assignment PIN_T33 -to "mem1_dq[22]" +set_location_assignment PIN_T32 -to "mem1_dq[23]" +set_location_assignment PIN_C34 -to "mem1_dq[24]" +set_location_assignment PIN_C35 -to "mem1_dq[25]" +set_location_assignment PIN_D34 -to "mem1_dq[26]" +set_location_assignment PIN_E34 -to "mem1_dq[27]" +set_location_assignment PIN_M32 -to "mem1_dq[28]" +set_location_assignment PIN_L32 -to "mem1_dq[29]" +set_location_assignment PIN_H33 -to "mem1_dq[30]" +set_location_assignment PIN_J33 -to "mem1_dq[31]" +set_location_assignment PIN_J31 -to "mem1_dq[32]" +set_location_assignment PIN_K31 -to "mem1_dq[33]" +set_location_assignment PIN_B33 -to "mem1_dq[34]" +set_location_assignment PIN_B32 -to "mem1_dq[35]" +set_location_assignment PIN_F32 -to "mem1_dq[36]" +set_location_assignment PIN_G32 -to "mem1_dq[37]" +set_location_assignment PIN_D33 -to "mem1_dq[38]" +set_location_assignment PIN_C33 -to "mem1_dq[39]" +set_location_assignment PIN_B30 -to "mem1_dq[40]" +set_location_assignment PIN_A30 -to "mem1_dq[41]" +set_location_assignment PIN_C30 -to "mem1_dq[42]" +set_location_assignment PIN_C31 -to "mem1_dq[43]" +set_location_assignment PIN_A33 -to "mem1_dq[44]" +set_location_assignment PIN_A34 -to "mem1_dq[45]" +set_location_assignment PIN_D31 -to "mem1_dq[46]" +set_location_assignment PIN_E31 -to "mem1_dq[47]" +set_location_assignment PIN_E39 -to "mem1_dq[48]" +set_location_assignment PIN_F40 -to "mem1_dq[49]" +set_location_assignment PIN_F38 -to "mem1_dq[50]" +set_location_assignment PIN_F39 -to "mem1_dq[51]" +set_location_assignment PIN_C41 -to "mem1_dq[52]" +set_location_assignment PIN_C40 -to "mem1_dq[53]" +set_location_assignment PIN_D42 -to "mem1_dq[54]" +set_location_assignment PIN_D41 -to "mem1_dq[55]" +set_location_assignment PIN_R37 -to "mem1_dq[56]" +set_location_assignment PIN_P37 -to "mem1_dq[57]" +set_location_assignment PIN_P38 -to "mem1_dq[58]" +set_location_assignment PIN_N38 -to "mem1_dq[59]" +set_location_assignment PIN_J37 -to "mem1_dq[60]" +set_location_assignment PIN_K37 -to "mem1_dq[61]" +set_location_assignment PIN_L37 -to "mem1_dq[62]" +set_location_assignment PIN_M37 -to "mem1_dq[63]" +set_location_assignment PIN_H41 -to "mem1_dq[64]" +set_location_assignment PIN_G41 -to "mem1_dq[65]" +set_location_assignment PIN_G42 -to "mem1_dq[66]" +set_location_assignment PIN_H42 -to "mem1_dq[67]" +set_location_assignment PIN_K39 -to "mem1_dq[68]" +set_location_assignment PIN_J39 -to "mem1_dq[69]" +set_location_assignment PIN_H40 -to "mem1_dq[70]" +set_location_assignment PIN_G40 -to "mem1_dq[71]" diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga.sdc b/fpga/mqnic/520N_MX/fpga_25g/fpga.sdc new file mode 100644 index 000000000..14b84cc80 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga.sdc @@ -0,0 +1,133 @@ +# Timing constraints for BittWare 520N-MX + +set_time_format -unit ns -decimal_places 3 + +# Clock constraints +create_clock -name {config_clk} -period 20.000 [ get_ports {config_clk} ] +create_clock -name {usr_refclk0} -period 3.333 [ get_ports {usr_refclk0} ] +create_clock -name {usr_refclk1} -period 3.333 [ get_ports {usr_refclk1} ] + +create_clock -name {mem0_refclk} -period 3.333 [ get_ports {mem0_refclk} ] +create_clock -name {mem1_refclk} -period 3.333 [ get_ports {mem1_refclk} ] + +create_clock -name {esram_0_refclk} -period 5.000 [ get_ports {esram_0_refclk} ] +create_clock -name {esram_1_refclk} -period 5.000 [ get_ports {esram_1_refclk} ] + +create_clock -name {hbm_top_refclk} -period 5.000 [ get_ports {hbm_top_refclk} ] +create_clock -name {hbm_bottom_refclk} -period 5.000 [ get_ports {hbm_bottom_refclk} ] + +create_clock -name {pcie_refclk} -period 10.000 [ get_ports {pcie_refclk} ] + +create_clock -name {qsfp0_refclk} -period 1.551 [ get_ports {qsfp0_refclk} ] +create_clock -name {qsfp1_refclk} -period 1.551 [ get_ports {qsfp1_refclk} ] +create_clock -name {qsfp2_refclk} -period 1.551 [ get_ports {qsfp2_refclk} ] +create_clock -name {qsfp3_refclk} -period 1.551 [ get_ports {qsfp3_refclk} ] + +derive_clock_uncertainty + +set_clock_groups -asynchronous -group [ get_clocks {config_clk} ] +set_clock_groups -asynchronous -group [ get_clocks {usr_refclk0} ] +set_clock_groups -asynchronous -group [ get_clocks {usr_refclk1} ] + +set_clock_groups -asynchronous -group [ get_clocks {mem0_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {mem1_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {esram_0_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {esram_1_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {hbm_top_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {hbm_bottom_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {pcie_refclk} ] + +set_clock_groups -asynchronous -group [ get_clocks {qsfp0_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp1_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp2_refclk} ] +set_clock_groups -asynchronous -group [ get_clocks {qsfp3_refclk} ] + +# JTAG constraints +create_clock -name {altera_reserved_tck} -period 62.500 {altera_reserved_tck} + +set_clock_groups -asynchronous -group {altera_reserved_tck} + +# IO constraints +set_false_path -to "led_user_red[*]" +set_false_path -to "led_user_grn[*]" +set_false_path -to "led_qsfp[*]" + +set_false_path -to "uart_rx" +set_false_path -from "uart_tx" + +set_false_path -to "fpga_i2c_sda" +set_false_path -from "fpga_i2c_sda" +set_false_path -to "fpga_i2c_scl" +set_false_path -from "fpga_i2c_scl" +set_false_path -to "fpga_i2c_req_l" +set_false_path -from "fpga_i2c_mux_gnt" + +set_false_path -from "fpga_gpio_1" +set_false_path -from "fpga_rst_n" + +set_false_path -from "pcie_perstn" + +set_false_path -from "qsfp_irq_n[*]" + +set_false_path -to "oc0_gpio[*]" +set_false_path -from "oc0_gpio[*]" +set_false_path -to "oc0_gpio_dir[*]" +set_false_path -to "oc0_buff_en_n[*]" + +set_false_path -to "oc1_gpio[*]" +set_false_path -from "oc1_gpio[*]" +set_false_path -to "oc1_gpio_dir[*]" +set_false_path -to "oc1_buff_en_n[*]" + +set_false_path -from "oc2_perst_n" +set_false_path -to "oc2_buff_in_sel" + +set_false_path -from "oc3_perst_n" +set_false_path -to "oc3_buff_in_sel" + + +source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc +source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc +source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc + +# 100 MHz clock +set_clock_groups -asynchronous -group [ get_clocks "iopll_100mhz_inst|iopll_0_outclk0" ] + +# clocking infrastructure +constrain_sync_reset_inst "sync_reset_100mhz_inst" +constrain_sync_reset_inst "ptp_rst_reset_sync_inst" + +# PTP ref clock +set_clock_groups -asynchronous -group [ get_clocks "ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div4" ] + +# PHYs +proc constrain_phy { inst } { + puts "Inserting timing constraints for PHY $inst" + + set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|tx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|rx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile0|tx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile0|rx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile1|tx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile1|rx_clkout|ch0" ] + + constrain_sync_reset_inst "$inst|phy_tx_rst_reset_sync_inst" + constrain_sync_reset_inst "$inst|phy_rx_rst_reset_sync_inst" +} + +proc constrain_phy_quad { inst } { + puts "Inserting timing constraints for PHY quad $inst" + + constrain_phy "${inst}|eth_xcvr_phy_1" + constrain_phy "${inst}|eth_xcvr_phy_2" + constrain_phy "${inst}|eth_xcvr_phy_3" + constrain_phy "${inst}|eth_xcvr_phy_4" +} + +constrain_phy_quad "qsfp0_eth_xcvr_phy_quad" +constrain_phy_quad "qsfp1_eth_xcvr_phy_quad" +constrain_phy_quad "qsfp2_eth_xcvr_phy_quad" +constrain_phy_quad "qsfp3_eth_xcvr_phy_quad" diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile new file mode 100644 index 000000000..3214c3d45 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile @@ -0,0 +1,151 @@ + +# FPGA settings +FPGA_TOP = fpga +FPGA_FAMILY = "Stratix 10 MX" +FPGA_DEVICE = 1SM21CHU2F53E2VG + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v +SYN_FILES += rtl/common/mqnic_core_pcie_s10.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +# Workaround for Quartus MLAB RAM read enable bug +# https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html +SYN_FILES += rtl/axis_fifo.v +# SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v +SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_s10_if.v +SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v +SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v +SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# IP files +IP_TCL_FILES += ip/reset_release.tcl +IP_TCL_FILES += ip/iopll_100mhz.tcl +IP_TCL_FILES += ip/pcie.tcl +IP_TCL_FILES += ip/eth_xcvr_gxt.tcl +IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl +IP_TCL_FILES += ip/eth_xcvr_gxt_pll.tcl +IP_TCL_FILES += ip/eth_xcvr_gxt_buf.tcl +IP_TCL_FILES += ip/eth_xcvr_reset.tcl +IP_TCL_FILES += ip/ref_div.tcl + +# QSF files +QSF_FILES = fpga.qsf + +# SDC files +SDC_FILES = fpga.sdc + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/quartus_pro.mk + +program: fpga + quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl b/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..c6598d300 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl @@ -0,0 +1,237 @@ +# Copyright 2023, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x432AC0DD] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x198A] +set board_device_id [expr 0x0521] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Structural configuration +dict set params IF_COUNT "2" +dict set params PORTS_PER_IF "1" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "8" +dict set params CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "1" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] +dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] +dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params TX_QUEUE_INDEX_WIDTH "8" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] +dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] +dict set params EVENT_QUEUE_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "1" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# Application block configuration +dict set params APP_ID "32'h00000000" +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# Interrupt configuration +dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "24" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "1" +dict set params AXIS_ETH_TX_PIPELINE "0" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" +dict set params AXIS_ETH_TX_TS_PIPELINE "0" +dict set params AXIS_ETH_RX_PIPELINE "0" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" +dict set params ETH_XCVR_GXT "1" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# PCIe IP core settings +set pcie pcie_s10_hip_ast_0 +set pcie_ip pcie +set fp [open "update_ip_${pcie_ip}.tcl" "w"] + +puts $fp "package require qsys" +puts $fp "load_system ip/${pcie_ip}.ip" + +# PCIe IDs +puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {$pcie_class_code}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {$pcie_revision_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}" + +# PCIe IP core configuration +puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}" + +# configure BAR settings +proc configure_bar {fp pcie pf bar aperture} { + if {$aperture > 0} { + puts "PF${pf} BAR${bar}: aperture ${aperture} bits" + + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}" + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}" + + return + } + puts "PF${pf} BAR${bar}: disabled" + + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}" + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}" +} + +# Control BAR (BAR 0) +configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +puts $fp "sync_sysinfo_parameters" +puts $fp "save_system" +close $fp + +# apply parameters to PCIe IP core +exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl" + +# apply parameters to top-level +dict for {name value} $params { + set_parameter -name $name $value +} diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..cca104cca --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,149 @@ + +# FPGA settings +FPGA_TOP = fpga +FPGA_FAMILY = "Stratix 10 MX" +FPGA_DEVICE = 1SM21CHU2F53E2VG + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v +SYN_FILES += rtl/common/mqnic_core_pcie_s10.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +# Workaround for Quartus MLAB RAM read enable bug +# https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html +SYN_FILES += rtl/axis_fifo.v +# SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v +SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_s10_if.v +SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v +SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v +SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# IP files +IP_TCL_FILES += ip/reset_release.tcl +IP_TCL_FILES += ip/iopll_100mhz.tcl +IP_TCL_FILES += ip/pcie.tcl +IP_TCL_FILES += ip/eth_xcvr_gx.tcl +IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl +IP_TCL_FILES += ip/eth_xcvr_reset.tcl +IP_TCL_FILES += ip/ref_div.tcl + +# QSF files +QSF_FILES = fpga.qsf + +# SDC files +SDC_FILES = fpga.sdc + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/quartus_pro.mk + +program: fpga + quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..70bd5906a --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,237 @@ +# Copyright 2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x432AC0DD] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x198A] +set board_device_id [expr 0x0521] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Structural configuration +dict set params IF_COUNT "2" +dict set params PORTS_PER_IF "1" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "8" +dict set params CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "1" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] +dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] +dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params TX_QUEUE_INDEX_WIDTH "8" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] +dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] +dict set params EVENT_QUEUE_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "1" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# Application block configuration +dict set params APP_ID "32'h00000000" +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# Interrupt configuration +dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "24" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "0" +dict set params AXIS_ETH_TX_PIPELINE "0" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" +dict set params AXIS_ETH_TX_TS_PIPELINE "0" +dict set params AXIS_ETH_RX_PIPELINE "0" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" +dict set params ETH_XCVR_GXT "0" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# PCIe IP core settings +set pcie pcie_s10_hip_ast_0 +set pcie_ip pcie +set fp [open "update_ip_${pcie_ip}.tcl" "w"] + +puts $fp "package require qsys" +puts $fp "load_system ip/${pcie_ip}.ip" + +# PCIe IDs +puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {$pcie_class_code}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {$pcie_revision_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}" +puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}" + +# PCIe IP core configuration +puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}" + +# configure BAR settings +proc configure_bar {fp pcie pf bar aperture} { + if {$aperture > 0} { + puts "PF${pf} BAR${bar}: aperture ${aperture} bits" + + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}" + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}" + + return + } + puts "PF${pf} BAR${bar}: disabled" + + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}" + puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}" +} + +# Control BAR (BAR 0) +configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +puts $fp "sync_sysinfo_parameters" +puts $fp "save_system" +close $fp + +# apply parameters to PCIe IP core +exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl" + +# apply parameters to top-level +dict for {name value} $params { + set_parameter -name $name $value +} diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx.tcl new file mode 100644 index 000000000..18f45fcc6 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx.tcl @@ -0,0 +1,385 @@ +package require -exact qsys 21.3 + +# create the system "eth_xcvr_gx" +proc do_create_eth_xcvr_gx {} { + # create the system + create_system eth_xcvr_gx + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_native_s10_htile_0 altera_xcvr_native_s10_htile + set_instance_parameter_value xcvr_native_s10_htile_0 {adapter_ehip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_link} {lr} + set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_voltage} {1_1V} + set_instance_parameter_value xcvr_native_s10_htile_0 {avmm_ehip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {base_device} {Unknown} + set_instance_parameter_value xcvr_native_s10_htile_0 {bonded_mode} {not_bonded} + set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_cnt} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_select} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {channel_type} {GX} + set_instance_parameter_value xcvr_native_s10_htile_0 {channels} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout2_sel} {clock_delay_measurement_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout_sel} {clock_delay_measurement_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {design_environment} {NATIVE} + set_instance_parameter_value xcvr_native_s10_htile_0 {design_example_filename} {dexample} + set_instance_parameter_value xcvr_native_s10_htile_0 {disable_digital_reset_sequencer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {disable_reset_sequencer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {duplex_mode} {duplex} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t1} {60} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t2} {150} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t3} {1000} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_advanced_user_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_background_cal_gui} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_channel_powerdown} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_de_hardware_debug} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_debug_ports} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_direct_reset_control} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_double_rate_transfer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_early_spd_chng} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ehip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_fast_sim} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hard_reset} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_insert_eios_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_mac_total_control} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_manual_bonding_settings} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_clock_delay_measurement} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_tx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_latency_measurement} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_data_valid} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_bitslip} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_blk_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_clr_errblk_count} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_crc32_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber_clr_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_align_clr} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_insert} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_latency_adj_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pempty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pfull} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_rd_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtodata} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtoref} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_clkslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_iqtxrx_clkout} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_qpipulldn} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_polinv} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_seriallpbken} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitrev_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslipboundarysel} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_byterev_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_signaldetect} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_a1a2size} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_patternalign} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_dll_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_bitslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_burst_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_latency_adj_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pempty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pfull} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_elecidle} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_iqtxrx_clkout} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipulldn} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipullup} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_rxfound} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_txdetectrx} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_polinv} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_std_bitslipboundarysel} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_adaptation} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_hclk} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_rx_elecidle} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_sw} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_manual_cdr_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_prbs} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_async_transfer} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rcfg_tx_digitalreset_release_ctrl} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rx_fast_pipeln_reg} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_simple_interface} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_split_interface} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_transparent_pcs} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_coreclkin2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_fast_pipeln_reg} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_workaround_rules} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_advanced_user_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_low_latency_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pcs_pma_width} {64} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pld_pcs_width} {66} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_64b66b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_bitslip_enable} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_blksync_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_crcchk_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_descram_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_dispchk_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_mfrm_length} {2048} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_type} {10G} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_64b66b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_bitslip_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcerr_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_dispgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_burst_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_mfrm_length} {2048} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_len} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_randomdispbit_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_sh_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {generate_add_hdl_instance_example} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {generate_docs} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_channels} {x1} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_prot_mode} {gen1} + set_instance_parameter_value xcvr_native_s10_htile_0 {loopback_tx_clk_sel} {internal_clk} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {message_level} {error} + set_instance_parameter_value xcvr_native_s10_htile_0 {number_physical_bonding_clocks} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {osc_clk_divider} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_rx_dv_mode} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_tx_dv_mode} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {parallel_loopback_mode} {disable} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcie_rate_match} {Bypass} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_direct_width} {8} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_reset_sequencing_mode} {not_bonded} + set_instance_parameter_value xcvr_native_s10_htile_0 {pll_select} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {plls} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {pma_mode} {basic} + set_instance_parameter_value xcvr_native_s10_htile_0 {protocol_mode} {basic_enh} + set_instance_parameter_value xcvr_native_s10_htile_0 {qsf_assignments_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_debug} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable_avmm_busy_port} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_rcfg_10} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_files_as_common_package} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_h_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_iface_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_jtag_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_mif_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_multi_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_cnt} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data0} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data1} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data2} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data3} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data4} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data5} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data6} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data7} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_select} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_reduced_files_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data0} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data1} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data2} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data3} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data4} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data5} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data6} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data7} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_separate_avmm_busy} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_shared} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sv_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_txt_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_use_clk_reset_only} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {reduced_reset_sim_time} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout2_sel} {pcs_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout_sel} {pma_div_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_coreclkin_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_ac_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_eq_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_align_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_control_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_mode} {Phase compensation} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pempty} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pfull} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_mode} {ctle_dfe} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_start_gui} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_analog_mode} {user_custom} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_div_clkout_divider} {33} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r4} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ppm_detect_threshold} {1000} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_vga_dc_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_capability_reg_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_freq} {644.531250} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_receiver_detect_src} {iqclk} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_csr_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_data_rate} {10312.5} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_embedded_debug_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_calibration} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_eios_rx_protect} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_hip_cal_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_odi_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_pcs_bonding_master} {Auto} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_prbs_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_rcfg_emb_strm_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_user_identifier} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_low_latency_bypass_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_pcs_pma_width} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_8b10b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_bitrev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byte_deser_mode} {Disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byterev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_mode} {disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_n} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_p} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_fast_sync_status_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_mode} {bitslip} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern} {0.0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern_len} {7} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_renumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rgnumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rknumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rvnumber} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_disp_ctrl_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitrev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitslip_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byte_ser_mode} {Disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byterev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {support_mode} {user_mode} + set_instance_parameter_value xcvr_native_s10_htile_0 {suppress_design_example_messages} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tile_type_suffix} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout2_sel} {pcs_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout_sel} {pma_div_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_coreclkin_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_mode} {Phase compensation} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pempty} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pfull} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pcs_bonding_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_refclk} {644.53125} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_type} {ATX} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_analog_mode} {user_custom} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_clk_div} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_compensation_en} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_div_clkout_divider} {33} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_optimal_settings} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_output_swing_ctrl} {31} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_1st_post_tap} {negative} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_pre_tap_1t} {negative} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_1st_post_tap} {6} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_pre_tap_1t} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_slew_rate_ctrl} {5} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_term_sel} {r_r1} + set_instance_parameter_value xcvr_native_s10_htile_0 {use_rx_clkout2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {use_tx_clkout2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {usr_rx_dv_mode} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {usr_tx_dv_mode} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {validation_rule_select} {} + set_instance_property xcvr_native_s10_htile_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property tx_analogreset EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset + set_interface_property rx_analogreset EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset + set_interface_property tx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset + set_interface_property rx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset + set_interface_property tx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset_stat + set_interface_property rx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset_stat + set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset_stat + set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset_stat + set_interface_property tx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.tx_cal_busy + set_interface_property rx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.rx_cal_busy + set_interface_property tx_serial_clk0 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk0 + set_interface_property rx_cdr_refclk0 EXPORT_OF xcvr_native_s10_htile_0.rx_cdr_refclk0 + set_interface_property tx_serial_data EXPORT_OF xcvr_native_s10_htile_0.tx_serial_data + set_interface_property rx_serial_data EXPORT_OF xcvr_native_s10_htile_0.rx_serial_data + set_interface_property rx_is_lockedtoref EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtoref + set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtodata + set_interface_property tx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.tx_coreclkin + set_interface_property rx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.rx_coreclkin + set_interface_property tx_clkout EXPORT_OF xcvr_native_s10_htile_0.tx_clkout + set_interface_property tx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.tx_clkout2 + set_interface_property rx_clkout EXPORT_OF xcvr_native_s10_htile_0.rx_clkout + set_interface_property rx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.rx_clkout2 + set_interface_property tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.tx_parallel_data + set_interface_property tx_control EXPORT_OF xcvr_native_s10_htile_0.tx_control + set_interface_property tx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.tx_enh_data_valid + set_interface_property unused_tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_tx_parallel_data + set_interface_property rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.rx_parallel_data + set_interface_property rx_control EXPORT_OF xcvr_native_s10_htile_0.rx_control + set_interface_property rx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.rx_enh_data_valid + set_interface_property unused_rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_rx_parallel_data + set_interface_property rx_bitslip EXPORT_OF xcvr_native_s10_htile_0.rx_bitslip + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_gx.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_gx} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_gx +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_gx + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx_pll.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx_pll.tcl new file mode 100644 index 000000000..1fd68b0d9 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gx_pll.tcl @@ -0,0 +1,143 @@ +package require -exact qsys 21.3 + +# create the system "eth_xcvr_gx_pll" +proc do_create_eth_xcvr_gx_pll {} { + # create the system + create_system eth_xcvr_gx_pll + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_fpll_s10_htile_0 altera_xcvr_fpll_s10_htile + set_instance_parameter_value xcvr_fpll_s10_htile_0 {base_device} {Unknown} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_analog_resets} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_bonding_clks} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_debug_ports_parameters} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_fb_comp_bonding} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_hfreq_clk} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_hip_cal_done_port} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_manual_configuration} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_hip_cal_done_port} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_pcie_clksw} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_reset} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pcie_hip_connectivity} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pld_fpll_cal_busy_port} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {generate_add_hdl_instance_example} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {generate_docs} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {mcgb_aux_clkin_cnt} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {mcgb_div} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {message_level} {error} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {outclk_en} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {pma_width} {64} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {powerdown_mode} {powerup} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_debug} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_fpll_s10} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_files_as_common_package} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_h_file_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_jtag_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_mif_file_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_multi_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_cnt} {2} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data0} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data1} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data2} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data3} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data4} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data5} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data6} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data7} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_select} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_reduced_files_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_separate_avmm_busy} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sv_file_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_txt_file_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {select_manual_config} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_altera_xcvr_fpll_s10_calibration_en} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_bw_sel} {medium} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_capability_reg_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_csr_soft_logic_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_dps} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_fractional} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_hclk_out} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_fref_clock_frequency} {100.0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_hip_cal_en} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_initial_phase_shift} {0.0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_initial_phase_shift_units} {degrees} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_c_counter} {4} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_k_counter} {1.0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_l_counter} {2} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_m_counter} {50} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_output_clock_frequency} {2500.0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_ref_clk_div} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_reference_clock_frequency} {100.0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_output_clock_frequency} {5156.25} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_power_mode} {1_1V} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_primary_use} {2} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_prot_mode} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_rcfg_emb_strm_enable} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_refclk_cnt} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_refclk_index} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_user_identifier} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x1_core_clock} {1} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x2_core_clock} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x4_core_clock} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {silicon_rev} {0} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {support_mode} {user_mode} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {test_mode} {false} + set_instance_parameter_value xcvr_fpll_s10_htile_0 {usr_enable_vco_bypass} {0} + set_instance_property xcvr_fpll_s10_htile_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property pll_refclk0 EXPORT_OF xcvr_fpll_s10_htile_0.pll_refclk0 + set_interface_property tx_serial_clk EXPORT_OF xcvr_fpll_s10_htile_0.tx_serial_clk + set_interface_property pll_locked EXPORT_OF xcvr_fpll_s10_htile_0.pll_locked + set_interface_property pll_cal_busy EXPORT_OF xcvr_fpll_s10_htile_0.pll_cal_busy + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_gx_pll.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_gx_pll} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_gx_pll +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_gx_pll + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt.tcl new file mode 100644 index 000000000..6fda444b8 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt.tcl @@ -0,0 +1,389 @@ +package require -exact qsys 21.3 + +# create the system "eth_xcvr_gxt" +proc do_create_eth_xcvr_gxt {} { + # create the system + create_system eth_xcvr_gxt + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_native_s10_htile_0 altera_xcvr_native_s10_htile + set_instance_parameter_value xcvr_native_s10_htile_0 {adapter_ehip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_link} {lr} + set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_voltage} {1_1V} + set_instance_parameter_value xcvr_native_s10_htile_0 {avmm_ehip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {base_device} {Unknown} + set_instance_parameter_value xcvr_native_s10_htile_0 {bonded_mode} {not_bonded} + set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_cnt} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_select} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {channel_type} {GXT} + set_instance_parameter_value xcvr_native_s10_htile_0 {channels} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout2_sel} {clock_delay_measurement_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout_sel} {clock_delay_measurement_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {design_environment} {NATIVE} + set_instance_parameter_value xcvr_native_s10_htile_0 {design_example_filename} {dexample} + set_instance_parameter_value xcvr_native_s10_htile_0 {disable_digital_reset_sequencer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {disable_reset_sequencer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {duplex_mode} {duplex} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t1} {60} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t2} {150} + set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t3} {1000} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_advanced_user_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_background_cal_gui} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_channel_powerdown} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_de_hardware_debug} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_debug_ports} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_direct_reset_control} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_double_rate_transfer} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_early_spd_chng} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ehip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_fast_sim} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hard_reset} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_insert_eios_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_mac_total_control} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_manual_bonding_settings} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_clock_delay_measurement} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_tx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_latency_measurement} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_data_valid} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_bitslip} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_blk_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_clr_errblk_count} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_crc32_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber_clr_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_align_clr} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_insert} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_latency_adj_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pempty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pfull} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_rd_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtodata} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtoref} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_clkslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_iqtxrx_clkout} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_qpipulldn} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_polinv} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_seriallpbken} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitrev_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslipboundarysel} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_byterev_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_signaldetect} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_a1a2size} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_patternalign} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout_hioint} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_dll_lock} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_bitslip} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_burst_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_diag_status} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_latency_adj_ena} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pempty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pfull} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_empty} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_full} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_elecidle} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_iqtxrx_clkout} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipulldn} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipullup} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_rxfound} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_txdetectrx} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_polinv} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_std_bitslipboundarysel} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_adaptation} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_hclk} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_rx_elecidle} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_sw} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_manual_cdr_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_prbs} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_async_transfer} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rcfg_tx_digitalreset_release_ctrl} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rx_fast_pipeln_reg} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_simple_interface} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_split_interface} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_transparent_pcs} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_coreclkin2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_fast_pipeln_reg} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enable_workaround_rules} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_advanced_user_mode} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_low_latency_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pcs_pma_width} {64} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pld_pcs_width} {66} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_64b66b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_bitslip_enable} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_blksync_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_crcchk_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_descram_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_dispchk_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_mfrm_length} {2048} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_type} {10G} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_64b66b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_bitslip_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcerr_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_dispgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_burst_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_mfrm_length} {2048} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_len} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_randomdispbit_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.0} + set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_sh_err} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {generate_add_hdl_instance_example} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {generate_docs} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_channels} {x1} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_mode} {disable_hip} + set_instance_parameter_value xcvr_native_s10_htile_0 {hip_prot_mode} {gen1} + set_instance_parameter_value xcvr_native_s10_htile_0 {loopback_tx_clk_sel} {internal_clk} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_comp_cnt} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_mode} {individual} + set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_indv} {indv_en} + set_instance_parameter_value xcvr_native_s10_htile_0 {message_level} {error} + set_instance_parameter_value xcvr_native_s10_htile_0 {number_physical_bonding_clocks} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {osc_clk_divider} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_rx_dv_mode} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_tx_dv_mode} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {parallel_loopback_mode} {disable} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcie_rate_match} {Bypass} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_direct_width} {8} + set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_reset_sequencing_mode} {not_bonded} + set_instance_parameter_value xcvr_native_s10_htile_0 {pll_select} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {plls} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {pma_mode} {basic} + set_instance_parameter_value xcvr_native_s10_htile_0 {protocol_mode} {basic_enh} + set_instance_parameter_value xcvr_native_s10_htile_0 {qsf_assignments_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_debug} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable_avmm_busy_port} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_rcfg_10} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_files_as_common_package} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_h_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_iface_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_jtag_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_mif_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_multi_enable} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_cnt} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data0} {rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 0 set_user_identifier 0 set_csr_soft_logic_enable 1 support_mode user_mode channel_type GXT protocol_mode basic_enh pma_mode basic duplex_mode duplex channels 1 set_data_rate 25781.25 rcfg_iface_enable 0 enable_simple_interface 1 enable_split_interface 0 set_enable_calibration 1 enable_double_rate_transfer 0 enable_background_cal_gui 1 enable_direct_reset_control 0 disable_reset_sequencer 0 disable_digital_reset_sequencer 0 bonded_mode not_bonded set_pcs_bonding_master Auto pcs_reset_sequencing_mode not_bonded manual_pcs_bonding_mode individual manual_pcs_bonding_comp_cnt 0 manual_tx_hssi_aib_bonding_mode individual manual_tx_hssi_aib_bonding_comp_cnt 0 manual_tx_core_aib_bonding_mode individual manual_tx_core_aib_bonding_comp_cnt 0 manual_rx_hssi_aib_bonding_mode individual manual_rx_hssi_aib_bonding_comp_cnt 0 manual_rx_core_aib_bonding_mode individual manual_rx_core_aib_bonding_comp_cnt 0 manual_tx_hssi_aib_indv indv_en manual_tx_core_aib_indv indv_en manual_rx_hssi_aib_indv indv_en manual_rx_core_aib_indv indv_en tx_pma_clk_div 1 plls 2 pll_select 0 enable_port_tx_pma_iqtxrx_clkout 0 enable_port_tx_pma_elecidle 0 number_physical_bonding_clocks 1 enable_qpi_mode 0 enable_qpi_async_transfer 1 enable_port_tx_pma_qpipullup 0 enable_port_tx_pma_qpipulldn 0 enable_port_tx_pma_rxfound 0 enable_port_rx_pma_qpipulldn 0 enable_port_tx_pma_txdetectrx 0 cdr_refclk_cnt 1 cdr_refclk_select 0 set_cdr_refclk_freq 644.531250 rx_ppm_detect_threshold 1000 enable_port_rx_pma_iqtxrx_clkout 0 enable_port_rx_pma_clkslip 0 enable_port_rx_is_lockedtodata 1 enable_port_rx_is_lockedtoref 1 enable_ports_rx_manual_cdr_mode 0 enable_ports_rx_prbs 0 enable_port_rx_seriallpbken 0 std_pcs_pma_width 10 std_low_latency_bypass_enable 0 enable_hip 0 enable_hard_reset 0 set_hip_cal_en 0 hip_mode disable_hip hip_prot_mode gen1 hip_channels x1 enable_ehip 0 avmm_ehip_mode disable_hip adapter_ehip_mode disable_hip std_tx_byte_ser_mode Disabled std_rx_byte_deser_mode Disabled std_tx_8b10b_enable 0 std_tx_8b10b_disp_ctrl_enable 0 std_rx_8b10b_enable 0 std_rx_rmfifo_mode disabled std_rx_rmfifo_pattern_n 0 std_rx_rmfifo_pattern_p 0 enable_port_rx_std_rmfifo_full 0 enable_port_rx_std_rmfifo_empty 0 pcie_rate_match Bypass std_tx_bitslip_enable 0 enable_port_tx_std_bitslipboundarysel 0 std_rx_word_aligner_mode bitslip std_rx_word_aligner_pattern_len 7 std_rx_word_aligner_pattern 0 std_rx_word_aligner_rknumber 3 std_rx_word_aligner_renumber 3 std_rx_word_aligner_rgnumber 3 std_rx_word_aligner_fast_sync_status_enable 0 enable_port_rx_std_wa_patternalign 0 enable_port_rx_std_wa_a1a2size 0 enable_port_rx_std_bitslipboundarysel 0 enable_port_rx_std_bitslip 0 std_tx_bitrev_enable 0 std_tx_byterev_enable 0 std_tx_polinv_enable 0 enable_port_tx_polinv 0 std_rx_bitrev_enable 0 enable_port_rx_std_bitrev_ena 0 std_rx_byterev_enable 0 enable_port_rx_std_byterev_ena 0 std_rx_polinv_enable 0 enable_port_rx_polinv 0 enable_port_rx_std_signaldetect 0 enable_ports_pipe_sw 0 enable_ports_pipe_rx_elecidle 0 enable_ports_pipe_hclk 0 enh_pcs_pma_width 64 enh_pld_pcs_width 66 enh_low_latency_enable 0 enh_advanced_user_mode 0 enh_tx_frmgen_enable 0 enh_tx_frmgen_mfrm_length 2048 enh_tx_frmgen_burst_enable 0 enable_port_tx_enh_frame 0 enable_port_tx_enh_frame_diag_status 0 enable_port_tx_enh_frame_burst_en 0 enh_rx_frmsync_enable 0 enh_rx_frmsync_mfrm_length 2048 enable_port_rx_enh_frame 0 enable_port_rx_enh_frame_lock 0 enable_port_rx_enh_frame_diag_status 0 enh_tx_crcgen_enable 0 enh_tx_crcerr_enable 0 enh_rx_crcchk_enable 0 enable_port_rx_enh_crc32_err 0 enable_port_rx_enh_highber 0 enable_port_rx_enh_highber_clr_cnt 0 enable_port_rx_enh_clr_errblk_count 0 enh_tx_64b66b_enable 0 enh_rx_64b66b_enable 0 enh_tx_sh_err 0 enh_tx_scram_enable 0 enh_tx_scram_seed 2 enh_rx_descram_enable 0 enh_tx_dispgen_enable 0 enh_rx_dispchk_enable 0 enh_tx_randomdispbit_enable 0 enh_rx_blksync_enable 0 enable_port_rx_enh_blk_lock 0 enh_tx_bitslip_enable 0 enh_tx_polinv_enable 0 enh_rx_bitslip_enable 1 enh_rx_polinv_enable 0 enable_port_tx_enh_bitslip 0 enable_port_rx_enh_bitslip 1 enh_rx_krfec_err_mark_enable 0 enh_rx_krfec_err_mark_type 10G enh_tx_krfec_burst_err_enable 0 enh_tx_krfec_burst_err_len 1 enable_port_krfec_tx_enh_frame 0 enable_port_krfec_rx_enh_frame 0 enable_port_krfec_rx_enh_frame_diag_status 0 pcs_direct_width 8 enable_tx_fast_pipeln_reg 0 enable_rx_fast_pipeln_reg 0 parallel_loopback_mode disable loopback_tx_clk_sel internal_clk enable_debug_ports 0 tx_fifo_mode {Phase compensation} tx_fifo_pfull 10 tx_fifo_pempty 2 enable_port_tx_fifo_full 0 enable_port_tx_fifo_empty 0 enable_port_tx_fifo_pfull 0 enable_port_tx_fifo_pempty 0 enable_port_tx_pcs_fifo_full 0 enable_port_tx_pcs_fifo_empty 0 enable_port_tx_dll_lock 0 rx_fifo_mode {Phase compensation} rx_fifo_pfull 10 rx_fifo_pempty 2 rx_fifo_align_del 0 rx_fifo_control_del 0 enable_port_rx_data_valid 0 enable_port_rx_fifo_full 0 enable_port_rx_fifo_empty 0 enable_port_rx_fifo_pfull 0 enable_port_rx_fifo_pempty 0 enable_port_rx_fifo_del 0 enable_port_rx_fifo_insert 0 enable_port_rx_fifo_rd_en 0 enable_port_rx_fifo_align_clr 0 enable_port_rx_pcs_fifo_full 0 enable_port_rx_pcs_fifo_empty 0 tx_clkout_sel pma_div_clkout enable_port_tx_clkout2 1 tx_clkout2_sel pcs_clkout enable_port_tx_clkout_hioint 0 enable_port_tx_clkout2_hioint 0 tx_pma_div_clkout_divider 33 tx_coreclkin_clock_network dedicated tx_pcs_bonding_clock_network dedicated rx_clkout_sel pma_div_clkout enable_port_rx_clkout2 1 rx_clkout2_sel pcs_clkout enable_port_rx_clkout_hioint 0 enable_port_rx_clkout2_hioint 0 rx_pma_div_clkout_divider 33 rx_coreclkin_clock_network dedicated osc_clk_divider 1 enable_port_tx_fifo_latency_adj_ena 0 enable_port_rx_fifo_latency_adj_ena 0 enable_port_latency_measurement 0 enable_port_clock_delay_measurement 0 delay_measurement_clkout_sel clock_delay_measurement_clkout delay_measurement_clkout2_sel clock_delay_measurement_clkout ovrd_tx_dv_mode 1 usr_tx_dv_mode enable ovrd_rx_dv_mode 1 usr_rx_dv_mode enable set_prbs_soft_logic_enable 0 enable_rcfg_tx_digitalreset_release_ctrl 0 anlg_voltage 1_1V anlg_link lr enable_ports_adaptation 0 tx_pma_analog_mode user_custom rx_pma_analog_mode user_custom tx_pma_optimal_settings 0 tx_pma_output_swing_ctrl 31 tx_pma_pre_emp_sign_pre_tap_1t negative tx_pma_pre_emp_switching_ctrl_pre_tap_1t 0 tx_pma_pre_emp_sign_1st_post_tap negative tx_pma_pre_emp_switching_ctrl_1st_post_tap 6 tx_pma_slew_rate_ctrl 5 tx_pma_term_sel r_r1 tx_pma_compensation_en enable rx_pma_adapt_mode ctle_dfe rx_pma_term_sel r_r4 rx_ctle_ac_gain 0 rx_ctle_eq_gain 0 rx_vga_dc_gain 0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data1} {rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 0 set_user_identifier 0 set_csr_soft_logic_enable 1 support_mode user_mode channel_type GX protocol_mode basic_enh pma_mode basic duplex_mode duplex channels 1 set_data_rate 10312.5 rcfg_iface_enable 0 enable_simple_interface 1 enable_split_interface 0 set_enable_calibration 1 enable_double_rate_transfer 0 enable_background_cal_gui 1 enable_direct_reset_control 0 disable_reset_sequencer 0 disable_digital_reset_sequencer 0 bonded_mode not_bonded set_pcs_bonding_master Auto pcs_reset_sequencing_mode not_bonded manual_pcs_bonding_mode individual manual_pcs_bonding_comp_cnt 0 manual_tx_hssi_aib_bonding_mode individual manual_tx_hssi_aib_bonding_comp_cnt 0 manual_tx_core_aib_bonding_mode individual manual_tx_core_aib_bonding_comp_cnt 0 manual_rx_hssi_aib_bonding_mode individual manual_rx_hssi_aib_bonding_comp_cnt 0 manual_rx_core_aib_bonding_mode individual manual_rx_core_aib_bonding_comp_cnt 0 manual_tx_hssi_aib_indv indv_en manual_tx_core_aib_indv indv_en manual_rx_hssi_aib_indv indv_en manual_rx_core_aib_indv indv_en tx_pma_clk_div 1 plls 2 pll_select 1 enable_port_tx_pma_iqtxrx_clkout 0 enable_port_tx_pma_elecidle 0 number_physical_bonding_clocks 1 enable_qpi_mode 0 enable_qpi_async_transfer 1 enable_port_tx_pma_qpipullup 0 enable_port_tx_pma_qpipulldn 0 enable_port_tx_pma_rxfound 0 enable_port_rx_pma_qpipulldn 0 enable_port_tx_pma_txdetectrx 0 cdr_refclk_cnt 1 cdr_refclk_select 0 set_cdr_refclk_freq 644.531250 rx_ppm_detect_threshold 1000 enable_port_rx_pma_iqtxrx_clkout 0 enable_port_rx_pma_clkslip 0 enable_port_rx_is_lockedtodata 1 enable_port_rx_is_lockedtoref 1 enable_ports_rx_manual_cdr_mode 0 enable_ports_rx_prbs 0 enable_port_rx_seriallpbken 0 std_pcs_pma_width 10 std_low_latency_bypass_enable 0 enable_hip 0 enable_hard_reset 0 set_hip_cal_en 0 hip_mode disable_hip hip_prot_mode gen1 hip_channels x1 enable_ehip 0 avmm_ehip_mode disable_hip adapter_ehip_mode disable_hip std_tx_byte_ser_mode Disabled std_rx_byte_deser_mode Disabled std_tx_8b10b_enable 0 std_tx_8b10b_disp_ctrl_enable 0 std_rx_8b10b_enable 0 std_rx_rmfifo_mode disabled std_rx_rmfifo_pattern_n 0 std_rx_rmfifo_pattern_p 0 enable_port_rx_std_rmfifo_full 0 enable_port_rx_std_rmfifo_empty 0 pcie_rate_match Bypass std_tx_bitslip_enable 0 enable_port_tx_std_bitslipboundarysel 0 std_rx_word_aligner_mode bitslip std_rx_word_aligner_pattern_len 7 std_rx_word_aligner_pattern 0 std_rx_word_aligner_rknumber 3 std_rx_word_aligner_renumber 3 std_rx_word_aligner_rgnumber 3 std_rx_word_aligner_fast_sync_status_enable 0 enable_port_rx_std_wa_patternalign 0 enable_port_rx_std_wa_a1a2size 0 enable_port_rx_std_bitslipboundarysel 0 enable_port_rx_std_bitslip 0 std_tx_bitrev_enable 0 std_tx_byterev_enable 0 std_tx_polinv_enable 0 enable_port_tx_polinv 0 std_rx_bitrev_enable 0 enable_port_rx_std_bitrev_ena 0 std_rx_byterev_enable 0 enable_port_rx_std_byterev_ena 0 std_rx_polinv_enable 0 enable_port_rx_polinv 0 enable_port_rx_std_signaldetect 0 enable_ports_pipe_sw 0 enable_ports_pipe_rx_elecidle 0 enable_ports_pipe_hclk 0 enh_pcs_pma_width 64 enh_pld_pcs_width 66 enh_low_latency_enable 0 enh_advanced_user_mode 0 enh_tx_frmgen_enable 0 enh_tx_frmgen_mfrm_length 2048 enh_tx_frmgen_burst_enable 0 enable_port_tx_enh_frame 0 enable_port_tx_enh_frame_diag_status 0 enable_port_tx_enh_frame_burst_en 0 enh_rx_frmsync_enable 0 enh_rx_frmsync_mfrm_length 2048 enable_port_rx_enh_frame 0 enable_port_rx_enh_frame_lock 0 enable_port_rx_enh_frame_diag_status 0 enh_tx_crcgen_enable 0 enh_tx_crcerr_enable 0 enh_rx_crcchk_enable 0 enable_port_rx_enh_crc32_err 0 enable_port_rx_enh_highber 0 enable_port_rx_enh_highber_clr_cnt 0 enable_port_rx_enh_clr_errblk_count 0 enh_tx_64b66b_enable 0 enh_rx_64b66b_enable 0 enh_tx_sh_err 0 enh_tx_scram_enable 0 enh_tx_scram_seed 2 enh_rx_descram_enable 0 enh_tx_dispgen_enable 0 enh_rx_dispchk_enable 0 enh_tx_randomdispbit_enable 0 enh_rx_blksync_enable 0 enable_port_rx_enh_blk_lock 0 enh_tx_bitslip_enable 0 enh_tx_polinv_enable 0 enh_rx_bitslip_enable 1 enh_rx_polinv_enable 0 enable_port_tx_enh_bitslip 0 enable_port_rx_enh_bitslip 1 enh_rx_krfec_err_mark_enable 0 enh_rx_krfec_err_mark_type 10G enh_tx_krfec_burst_err_enable 0 enh_tx_krfec_burst_err_len 1 enable_port_krfec_tx_enh_frame 0 enable_port_krfec_rx_enh_frame 0 enable_port_krfec_rx_enh_frame_diag_status 0 pcs_direct_width 8 enable_tx_fast_pipeln_reg 0 enable_rx_fast_pipeln_reg 0 parallel_loopback_mode disable loopback_tx_clk_sel internal_clk enable_debug_ports 0 tx_fifo_mode {Phase compensation} tx_fifo_pfull 10 tx_fifo_pempty 2 enable_port_tx_fifo_full 0 enable_port_tx_fifo_empty 0 enable_port_tx_fifo_pfull 0 enable_port_tx_fifo_pempty 0 enable_port_tx_pcs_fifo_full 0 enable_port_tx_pcs_fifo_empty 0 enable_port_tx_dll_lock 0 rx_fifo_mode {Phase compensation} rx_fifo_pfull 10 rx_fifo_pempty 2 rx_fifo_align_del 0 rx_fifo_control_del 0 enable_port_rx_data_valid 0 enable_port_rx_fifo_full 0 enable_port_rx_fifo_empty 0 enable_port_rx_fifo_pfull 0 enable_port_rx_fifo_pempty 0 enable_port_rx_fifo_del 0 enable_port_rx_fifo_insert 0 enable_port_rx_fifo_rd_en 0 enable_port_rx_fifo_align_clr 0 enable_port_rx_pcs_fifo_full 0 enable_port_rx_pcs_fifo_empty 0 tx_clkout_sel pma_div_clkout enable_port_tx_clkout2 1 tx_clkout2_sel pcs_clkout enable_port_tx_clkout_hioint 0 enable_port_tx_clkout2_hioint 0 tx_pma_div_clkout_divider 33 tx_coreclkin_clock_network dedicated tx_pcs_bonding_clock_network dedicated rx_clkout_sel pma_div_clkout enable_port_rx_clkout2 1 rx_clkout2_sel pcs_clkout enable_port_rx_clkout_hioint 0 enable_port_rx_clkout2_hioint 0 rx_pma_div_clkout_divider 33 rx_coreclkin_clock_network dedicated osc_clk_divider 1 enable_port_tx_fifo_latency_adj_ena 0 enable_port_rx_fifo_latency_adj_ena 0 enable_port_latency_measurement 0 enable_port_clock_delay_measurement 0 delay_measurement_clkout_sel clock_delay_measurement_clkout delay_measurement_clkout2_sel clock_delay_measurement_clkout ovrd_tx_dv_mode 1 usr_tx_dv_mode enable ovrd_rx_dv_mode 1 usr_rx_dv_mode enable set_prbs_soft_logic_enable 0 enable_rcfg_tx_digitalreset_release_ctrl 0 anlg_voltage 1_1V anlg_link lr enable_ports_adaptation 0 tx_pma_analog_mode user_custom rx_pma_analog_mode user_custom tx_pma_optimal_settings 0 tx_pma_output_swing_ctrl 31 tx_pma_pre_emp_sign_pre_tap_1t negative tx_pma_pre_emp_switching_ctrl_pre_tap_1t 0 tx_pma_pre_emp_sign_1st_post_tap negative tx_pma_pre_emp_switching_ctrl_1st_post_tap 6 tx_pma_slew_rate_ctrl 5 tx_pma_term_sel r_r1 tx_pma_compensation_en enable rx_pma_adapt_mode ctle_dfe rx_pma_term_sel r_r4 rx_ctle_ac_gain 0 rx_ctle_eq_gain 0 rx_vga_dc_gain 0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data2} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data3} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data4} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data5} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data6} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data7} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_select} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_reduced_files_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data0} {enable_multi_profile 1 dbg_embedded_debug_enable 1 dbg_capability_reg_enable 0 dbg_user_identifier 0 dbg_stat_soft_logic_enable 1 dbg_ctrl_soft_logic_enable 1 l_tx_transfer_clk_hz 805664062 l_rx_transfer_clk_hz 805664062 enable_background_cal 1 l_tx_fifo_transfer_mode x2 l_rx_fifo_transfer_mode x2 l_num_tx_digitalreset 1 l_num_rx_digitalreset 1 l_enable_channel_bonding 0 l_enable_pma_bonding 0 l_enable_pcs_bonding 0 l_tx_hssi_aib_indv indv_en l_tx_core_aib_indv indv_en l_rx_hssi_aib_indv indv_en l_rx_core_aib_indv indv_en display_std_tx_pld_adapt_width 10 display_std_rx_pld_adapt_width 10 datapath_select Enhanced} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data1} {enable_multi_profile 1 dbg_embedded_debug_enable 1 dbg_capability_reg_enable 0 dbg_user_identifier 0 dbg_stat_soft_logic_enable 1 dbg_ctrl_soft_logic_enable 1 l_tx_transfer_clk_hz 322265624 l_rx_transfer_clk_hz 322265624 enable_background_cal 1 l_tx_fifo_transfer_mode x2 l_rx_fifo_transfer_mode x2 l_num_tx_digitalreset 1 l_num_rx_digitalreset 1 l_enable_channel_bonding 0 l_enable_pma_bonding 0 l_enable_pcs_bonding 0 l_tx_hssi_aib_indv indv_en l_tx_core_aib_indv indv_en l_rx_hssi_aib_indv indv_en l_rx_core_aib_indv indv_en display_std_tx_pld_adapt_width 10 display_std_rx_pld_adapt_width 10 datapath_select Enhanced} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data2} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data3} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data4} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data5} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data6} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data7} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_separate_avmm_busy} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_shared} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sv_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_txt_file_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_use_clk_reset_only} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {reduced_reset_sim_time} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout2_sel} {pcs_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout_sel} {pma_div_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_coreclkin_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_ac_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_eq_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_align_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_control_del} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_mode} {Phase compensation} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pempty} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pfull} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_mode} {ctle_dfe} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_start_gui} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_analog_mode} {user_custom} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_div_clkout_divider} {33} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r4} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ppm_detect_threshold} {1000} + set_instance_parameter_value xcvr_native_s10_htile_0 {rx_vga_dc_gain} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_capability_reg_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_freq} {644.531250} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_receiver_detect_src} {iqclk} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_csr_soft_logic_enable} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_data_rate} {25781.25} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_embedded_debug_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_calibration} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_eios_rx_protect} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_hip_cal_en} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_odi_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_pcs_bonding_master} {Auto} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_prbs_soft_logic_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_rcfg_emb_strm_enable} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {set_user_identifier} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_low_latency_bypass_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_pcs_pma_width} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_8b10b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_bitrev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byte_deser_mode} {Disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byterev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_mode} {disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_n} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_p} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_fast_sync_status_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_mode} {bitslip} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern} {0.0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern_len} {7} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_renumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rgnumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rknumber} {3} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rvnumber} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_disp_ctrl_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitrev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitslip_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byte_ser_mode} {Disabled} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byterev_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_polinv_enable} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {support_mode} {user_mode} + set_instance_parameter_value xcvr_native_s10_htile_0 {suppress_design_example_messages} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tile_type_suffix} {} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout2_sel} {pcs_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout_sel} {pma_div_clkout} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_coreclkin_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_mode} {Phase compensation} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pempty} {2} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pfull} {10} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pcs_bonding_clock_network} {dedicated} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_refclk} {644.53125} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_type} {ATX} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_analog_mode} {user_custom} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_clk_div} {1} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_compensation_en} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_div_clkout_divider} {33} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_optimal_settings} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_output_swing_ctrl} {31} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_1st_post_tap} {negative} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_pre_tap_1t} {negative} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_1st_post_tap} {6} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_pre_tap_1t} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_slew_rate_ctrl} {5} + set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_term_sel} {r_r1} + set_instance_parameter_value xcvr_native_s10_htile_0 {use_rx_clkout2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {use_tx_clkout2} {0} + set_instance_parameter_value xcvr_native_s10_htile_0 {usr_rx_dv_mode} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {usr_tx_dv_mode} {enable} + set_instance_parameter_value xcvr_native_s10_htile_0 {validation_rule_select} {} + set_instance_property xcvr_native_s10_htile_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property tx_analogreset EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset + set_interface_property rx_analogreset EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset + set_interface_property tx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset + set_interface_property rx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset + set_interface_property tx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset_stat + set_interface_property rx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset_stat + set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset_stat + set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset_stat + set_interface_property tx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.tx_cal_busy + set_interface_property rx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.rx_cal_busy + set_interface_property tx_serial_clk0 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk0 + set_interface_property tx_serial_clk1 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk1 + set_interface_property rx_cdr_refclk0 EXPORT_OF xcvr_native_s10_htile_0.rx_cdr_refclk0 + set_interface_property tx_serial_data EXPORT_OF xcvr_native_s10_htile_0.tx_serial_data + set_interface_property rx_serial_data EXPORT_OF xcvr_native_s10_htile_0.rx_serial_data + set_interface_property rx_is_lockedtoref EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtoref + set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtodata + set_interface_property tx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.tx_coreclkin + set_interface_property rx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.rx_coreclkin + set_interface_property tx_clkout EXPORT_OF xcvr_native_s10_htile_0.tx_clkout + set_interface_property tx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.tx_clkout2 + set_interface_property rx_clkout EXPORT_OF xcvr_native_s10_htile_0.rx_clkout + set_interface_property rx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.rx_clkout2 + set_interface_property tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.tx_parallel_data + set_interface_property tx_control EXPORT_OF xcvr_native_s10_htile_0.tx_control + set_interface_property tx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.tx_enh_data_valid + set_interface_property unused_tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_tx_parallel_data + set_interface_property rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.rx_parallel_data + set_interface_property rx_control EXPORT_OF xcvr_native_s10_htile_0.rx_control + set_interface_property rx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.rx_enh_data_valid + set_interface_property unused_rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_rx_parallel_data + set_interface_property rx_bitslip EXPORT_OF xcvr_native_s10_htile_0.rx_bitslip + set_interface_property reconfig_clk EXPORT_OF xcvr_native_s10_htile_0.reconfig_clk + set_interface_property reconfig_reset EXPORT_OF xcvr_native_s10_htile_0.reconfig_reset + set_interface_property reconfig_avmm EXPORT_OF xcvr_native_s10_htile_0.reconfig_avmm + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_gxt.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_gxt} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_gxt +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_gxt + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_buf.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_buf.tcl new file mode 100644 index 000000000..deae1b8fc --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_buf.tcl @@ -0,0 +1,144 @@ +package require -exact qsys 21.3 + +# create the system "eth_xcvr_gxt_buf" +proc do_create_eth_xcvr_gxt_buf {} { + # create the system + create_system eth_xcvr_gxt_buf + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {atx_blw} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_bonding_clks} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_cascade_out} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_debug_ports_parameters} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_ext_lockdetect_ports} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_fb_comp_bonding} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hfreq_clk} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hip_cal_done_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_manual_configuration} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_pcie_clksw} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_reset} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_clk} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_hip_connectivity} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_atx_cal_busy_port} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pll_lock} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_vco_bypass} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {generate_add_hdl_instance_example} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_aux_clkin_cnt} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GXT clock output buffer} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_atx_pll_s10} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_files_as_common_package} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_h_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_jtag_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_mif_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_multi_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_cnt} {2} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data0} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data1} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data2} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data3} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data4} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data5} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data6} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data7} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_select} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_reduced_files_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_separate_avmm_busy} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sv_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_txt_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_cnt} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_index} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_altera_xcvr_atx_pll_s10_calibration_en} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_capability_reg_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_csr_soft_logic_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_fref_clock_frequency} {156.25} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_hip_cal_en} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_k_counter} {1.0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_counter} {4} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_predivider} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {12890.625} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {silicon_rev} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {support_mode} {user_mode} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {test_mode} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {usr_analog_voltage} {1_1V} + set_instance_property xcvr_atx_pll_s10_htile_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0 + set_interface_property tx_serial_clk_gxt EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk_gxt + set_interface_property gxt_input_from_blw_atx EXPORT_OF xcvr_atx_pll_s10_htile_0.gxt_input_from_blw_atx + set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked + set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_gxt_buf.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_gxt_buf} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_gxt_buf +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_gxt_buf + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_pll.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_pll.tcl new file mode 100644 index 000000000..364beb9fc --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_gxt_pll.tcl @@ -0,0 +1,144 @@ +package require -exact qsys 21.3 + +# create the system "eth_xcvr_gxt_pll" +proc do_create_eth_xcvr_gxt_pll {} { + # create the system + create_system eth_xcvr_gxt_pll + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {atx_lcl} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_bonding_clks} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_cascade_out} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_debug_ports_parameters} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_ext_lockdetect_ports} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_fb_comp_bonding} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hfreq_clk} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hip_cal_done_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_manual_configuration} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_pcie_clksw} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_reset} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_clk} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_hip_connectivity} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_atx_cal_busy_port} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pll_lock} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_vco_bypass} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {generate_add_hdl_instance_example} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_aux_clkin_cnt} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GXT clock output buffer} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_atx_pll_s10} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_files_as_common_package} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_h_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_jtag_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_mif_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_multi_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_cnt} {2} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data0} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data1} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data2} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data3} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data4} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data5} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data6} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data7} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_select} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_reduced_files_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_separate_avmm_busy} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sv_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_txt_file_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_cnt} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_index} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_altera_xcvr_atx_pll_s10_calibration_en} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_capability_reg_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_csr_soft_logic_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_fref_clock_frequency} {156.25} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_hip_cal_en} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_k_counter} {1.0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_counter} {4} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_predivider} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {12890.625} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {silicon_rev} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {support_mode} {user_mode} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {test_mode} {0} + set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {usr_analog_voltage} {1_1V} + set_instance_property xcvr_atx_pll_s10_htile_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0 + set_interface_property tx_serial_clk_gxt EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk_gxt + set_interface_property gxt_output_to_abv_atx EXPORT_OF xcvr_atx_pll_s10_htile_0.gxt_output_to_abv_atx + set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked + set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_gxt_pll.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_gxt_pll} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_gxt_pll +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_gxt_pll + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_reset.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_reset.tcl new file mode 100644 index 000000000..35f1f585a --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/eth_xcvr_reset.tcl @@ -0,0 +1,87 @@ +package require -exact qsys 20.4 + +# create the system "eth_xcvr_reset" +proc do_create_eth_xcvr_reset {} { + # create the system + create_system eth_xcvr_reset + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance xcvr_reset_control_s10_0 altera_xcvr_reset_control_s10 + set_instance_parameter_value xcvr_reset_control_s10_0 {CHANNELS} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {ENABLE_DIGITAL_SEQ} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {PLLS} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {REDUCED_SIM_TIME} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {RX_ENABLE} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {RX_MANUAL_RESET} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {RX_PER_CHANNEL} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {SYS_CLK_IN_MHZ} {300} + set_instance_parameter_value xcvr_reset_control_s10_0 {TILE_TYPE} {h_tile} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_ENABLE} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_MANUAL_RESET} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PER_CHANNEL} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PLL_ENABLE} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_LOCK_HYST} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_ANALOGRESET} {40} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_DIGITALRESET} {5000} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_ANALOGRESET} {0} + set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_DIGITALRESET} {20} + set_instance_parameter_value xcvr_reset_control_s10_0 {gui_pll_cal_busy} {1} + set_instance_parameter_value xcvr_reset_control_s10_0 {gui_split_interfaces} {0} + set_instance_property xcvr_reset_control_s10_0 AUTO_EXPORT true + + # add wirelevel expressions + + # add the exports + set_interface_property clock EXPORT_OF xcvr_reset_control_s10_0.clock + set_interface_property reset EXPORT_OF xcvr_reset_control_s10_0.reset + set_interface_property tx_analogreset EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset + set_interface_property tx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset + set_interface_property tx_ready EXPORT_OF xcvr_reset_control_s10_0.tx_ready + set_interface_property pll_locked EXPORT_OF xcvr_reset_control_s10_0.pll_locked + set_interface_property pll_select EXPORT_OF xcvr_reset_control_s10_0.pll_select + set_interface_property tx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.tx_cal_busy + set_interface_property tx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset_stat + set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset_stat + set_interface_property pll_cal_busy EXPORT_OF xcvr_reset_control_s10_0.pll_cal_busy + set_interface_property rx_analogreset EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset + set_interface_property rx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset + set_interface_property rx_ready EXPORT_OF xcvr_reset_control_s10_0.rx_ready + set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_reset_control_s10_0.rx_is_lockedtodata + set_interface_property rx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.rx_cal_busy + set_interface_property rx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset_stat + set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset_stat + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {eth_xcvr_reset.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {eth_xcvr_reset} + + # save the system + sync_sysinfo_parameters + save_system eth_xcvr_reset +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_eth_xcvr_reset + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/iopll_100mhz.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/iopll_100mhz.tcl new file mode 100644 index 000000000..b6fa46341 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/iopll_100mhz.tcl @@ -0,0 +1,304 @@ +package require -exact qsys 21.3 + +# create the system "iopll_100mhz" +proc do_create_iopll_100mhz {} { + # create the system + create_system iopll_100mhz + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance iopll_0 altera_iopll + set_instance_parameter_value iopll_0 {gui_active_clk} {0} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src2} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src3} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src4} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src5} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src6} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src7} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src8} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_cal_code_hex_file} {iossm.hex} + set_instance_parameter_value iopll_0 {gui_cal_converge} {0} + set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean} + set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter10} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter11} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter12} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter13} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter14} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter15} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter16} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter17} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter2} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter3} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter4} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter5} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter6} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter7} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter8} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter9} {0} + set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0} + set_instance_parameter_value iopll_0 {gui_clk_bad} {0} + set_instance_parameter_value iopll_0 {gui_clock_name_global} {0} + set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0} + set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1} + set_instance_parameter_value iopll_0 {gui_clock_name_string10} {outclk10} + set_instance_parameter_value iopll_0 {gui_clock_name_string11} {outclk11} + set_instance_parameter_value iopll_0 {gui_clock_name_string12} {outclk12} + set_instance_parameter_value iopll_0 {gui_clock_name_string13} {outclk13} + set_instance_parameter_value iopll_0 {gui_clock_name_string14} {outclk14} + set_instance_parameter_value iopll_0 {gui_clock_name_string15} {outclk15} + set_instance_parameter_value iopll_0 {gui_clock_name_string16} {outclk16} + set_instance_parameter_value iopll_0 {gui_clock_name_string17} {outclk17} + set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2} + set_instance_parameter_value iopll_0 {gui_clock_name_string3} {outclk3} + set_instance_parameter_value iopll_0 {gui_clock_name_string4} {outclk4} + set_instance_parameter_value iopll_0 {gui_clock_name_string5} {outclk5} + set_instance_parameter_value iopll_0 {gui_clock_name_string6} {outclk6} + set_instance_parameter_value iopll_0 {gui_clock_name_string7} {outclk7} + set_instance_parameter_value iopll_0 {gui_clock_name_string8} {outclk8} + set_instance_parameter_value iopll_0 {gui_clock_name_string9} {outclk9} + set_instance_parameter_value iopll_0 {gui_clock_to_compensate} {0} + set_instance_parameter_value iopll_0 {gui_debug_mode} {0} + set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c10} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c11} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c12} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c13} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c14} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c15} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c16} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c17} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c3} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c4} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c5} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c6} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c7} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c8} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c9} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_n} {1} + set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0} + set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive} + set_instance_parameter_value iopll_0 {gui_dps_num} {1} + set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order} + set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle10} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle11} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle12} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle13} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle14} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle15} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle16} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle17} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle2} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle3} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle4} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle5} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle6} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle7} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle8} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle9} {50.0} + set_instance_parameter_value iopll_0 {gui_en_adv_params} {0} + set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_iossm_reconf} {0} + set_instance_parameter_value iopll_0 {gui_en_lvds_ports} {Disabled} + set_instance_parameter_value iopll_0 {gui_en_periphery_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_reconf} {0} + set_instance_parameter_value iopll_0 {gui_enable_cascade_in} {0} + set_instance_parameter_value iopll_0 {gui_enable_cascade_out} {0} + set_instance_parameter_value iopll_0 {gui_enable_mif_dps} {0} + set_instance_parameter_value iopll_0 {gui_enable_output_counter_cascading} {0} + set_instance_parameter_value iopll_0 {gui_enable_permit_cal} {0} + set_instance_parameter_value iopll_0 {gui_enable_upstream_out_clk} {0} + set_instance_parameter_value iopll_0 {gui_existing_mif_file_path} {~/pll.mif} + set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0} + set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0} + set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock} + set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0} + set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0} + set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1667.0} + set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0} + set_instance_parameter_value iopll_0 {gui_fractional_cout} {32} + set_instance_parameter_value iopll_0 {gui_include_iossm} {0} + set_instance_parameter_value iopll_0 {gui_location_type} {I/O Bank} + set_instance_parameter_value iopll_0 {gui_lock_setting} {Low Lock Time} + set_instance_parameter_value iopll_0 {gui_mif_config_name} {unnamed} + set_instance_parameter_value iopll_0 {gui_mif_gen_options} {Generate New MIF File} + set_instance_parameter_value iopll_0 {gui_multiply_factor} {6} + set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif} + set_instance_parameter_value iopll_0 {gui_number_of_clocks} {1} + set_instance_parameter_value iopll_0 {gui_operation_mode} {direct} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency12} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency13} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency14} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency15} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency16} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency17} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency3} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency4} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency5} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency6} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps12} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps13} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps14} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps15} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps16} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps17} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps3} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps4} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps5} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps6} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps7} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps8} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps9} {10000.0} + set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex} + set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift10} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift11} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift12} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift13} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift14} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift15} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift16} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift17} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift2} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift3} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift4} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift5} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift6} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift7} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift8} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift9} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg0} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg1} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg10} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg11} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg12} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg13} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg14} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg15} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg16} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg17} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg2} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg3} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg4} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg5} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg6} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg7} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg8} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg9} {0.0} + set_instance_parameter_value iopll_0 {gui_phout_division} {1} + set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {1} + set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Low} + set_instance_parameter_value iopll_0 {gui_pll_cal_done} {0} + set_instance_parameter_value iopll_0 {gui_pll_cascading_mode} {adjpllin} + set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1} + set_instance_parameter_value iopll_0 {gui_pll_freqcal_req_flag} {1} + set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL} + set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0} + set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src} + set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_band18} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_band18} + set_instance_parameter_value iopll_0 {gui_prot_mode} {UNUSED} + set_instance_parameter_value iopll_0 {gui_ps_units0} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units1} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units10} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units11} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units12} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units13} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units14} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units15} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units16} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units17} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units2} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units3} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units4} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units5} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units6} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units7} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units8} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units9} {ps} + set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0} + set_instance_parameter_value iopll_0 {gui_refclk_might_change} {0} + set_instance_parameter_value iopll_0 {gui_refclk_switch} {0} + set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {300.0} + set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {3333.333} + set_instance_parameter_value iopll_0 {gui_simulation_type} {0} + set_instance_parameter_value iopll_0 {gui_skip_sdc_generation} {0} + set_instance_parameter_value iopll_0 {gui_switchover_delay} {0} + set_instance_parameter_value iopll_0 {gui_switchover_mode} {Automatic Switchover} + set_instance_parameter_value iopll_0 {gui_use_NDFB_modes} {0} + set_instance_parameter_value iopll_0 {gui_use_coreclk} {0} + set_instance_parameter_value iopll_0 {gui_use_locked} {1} + set_instance_parameter_value iopll_0 {gui_use_logical} {0} + set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1} + set_instance_parameter_value iopll_0 {gui_vco_frequency} {600.0} + set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0} + set_instance_parameter_value iopll_0 {system_info_device_iobank_rev} {} + set_instance_property iopll_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property reset EXPORT_OF iopll_0.reset + set_interface_property refclk EXPORT_OF iopll_0.refclk + set_interface_property locked EXPORT_OF iopll_0.locked + set_interface_property outclk0 EXPORT_OF iopll_0.outclk0 + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {iopll_100mhz.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {iopll_100mhz} + + # save the system + sync_sysinfo_parameters + save_system iopll_100mhz +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_iopll_100mhz + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/pcie.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/pcie.tcl new file mode 100644 index 000000000..02bb4faad --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/pcie.tcl @@ -0,0 +1,350 @@ +package require -exact qsys 21.3 + +# create the system "pcie" +proc do_create_pcie {} { + # create the system + create_system pcie + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance pcie_s10_hip_ast_0 altera_pcie_s10_hip_ast + set_instance_parameter_value pcie_s10_hip_ast_0 {anlg_voltage} {1_1V} + set_instance_parameter_value pcie_s10_hip_ast_0 {apps_type_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_clk_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_control_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_npor_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_pipe_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {ceb_extend_pcie_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {chosen_devkit_hwtcl} {Stratix 10 MX H-Tile Production FPGA Development Kit} + set_instance_parameter_value pcie_s10_hip_ast_0 {cvp_user_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {design_environment} {NATIVE} + set_instance_parameter_value pcie_s10_hip_ast_0 {device_ctrl_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {disable_256_to_512_adapter_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {eios_workaround_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_avst_reset_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_qii_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_sim_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_sim_rp_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_synth_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_synth_rp_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_tb_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_multi_func_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pcie_cv_fix} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pipe32_phyip_ser_driver_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pld_warm_rst_rdy_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_rx_buffer_limit_ports_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_sriov_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {enable_test_out_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {hip_reconfig_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {hrc_rstctl_timer_g_delay_added_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {msi_info_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pcie_link_inspector_avmm_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pcie_link_inspector_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_auto_lane_flip_ctrl_en_hwtcl} {enable} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar0_address_width_hwtcl} {24} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar0_type_hwtcl} {64-bit prefetchable memory} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_class_code_hwtcl} {131072} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_eq_eieos_cnt_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_expansion_base_address_register_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_loopback_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msi_multiple_msg_cap_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_bir_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_offset_hwtcl} {12288.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_offset_hwtcl} {8192.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_hwtcl} {31} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_device_id_hwtcl} {4097} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_vendor_id_hwtcl} {4660} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ext_tag_supp_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_flr_cap_user_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_phy_slot_num_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_port_num_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_sel_deemphasis_hwtcl} {6dB} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_clk_config_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_slot_imp_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_revision_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar0_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar0_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_device_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_subsys_dev_id_hwtcl} {1313} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_subsys_vendor_id_hwtcl} {6538} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_size_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_count_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar0_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar0_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_class_code_hwtcl} {16711680} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_expansion_base_address_register_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msi_multiple_msg_cap_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_bir_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_pba_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_pba_offset_hwtcl} {0.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_offset_hwtcl} {0.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_size_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_type0_device_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_type0_vendor_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_revision_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar0_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar0_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_device_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_subsys_dev_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_subsys_vendor_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_size_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_count_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar0_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar0_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_class_code_hwtcl} {16711680} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_expansion_base_address_register_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msi_multiple_msg_cap_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_bir_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_pba_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_pba_offset_hwtcl} {0.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_offset_hwtcl} {0.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_size_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_type0_device_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_type0_vendor_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_revision_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar0_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar0_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_device_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_subsys_dev_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_subsys_vendor_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_size_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_count_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar0_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar0_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_class_code_hwtcl} {16711680} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_expansion_base_address_register_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msi_multiple_msg_cap_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_bir_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_pba_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_pba_offset_hwtcl} {0.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_offset_hwtcl} {0.0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_size_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_type0_device_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_type0_vendor_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_revision_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar0_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar0_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar1_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar1_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar2_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar2_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar3_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar3_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar4_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar4_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar5_address_width_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar5_type_hwtcl} {Disabled} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_device_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_subsys_dev_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_subsys_vendor_id_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_size_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_count_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_st_dev_spec_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_st_int_mode_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {pll_refclk_freq_hwtcl} {100 MHz} + set_instance_parameter_value pcie_s10_hip_ast_0 {select_design_example_hwtcl} {PIO} + set_instance_parameter_value pcie_s10_hip_ast_0 {select_design_example_rtl_lang_hwtcl} {Verilog} + set_instance_parameter_value pcie_s10_hip_ast_0 {select_example_design_sim_BFM_hwtcl} {Intel FPGA BFM} + set_instance_parameter_value pcie_s10_hip_ast_0 {serial_sim_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {targeted_devkit_hwtcl} {NONE} + set_instance_parameter_value pcie_s10_hip_ast_0 {total_pf_count_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {use_ast_parity_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {use_pll_lock_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {use_rpbfm_pro} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_ep_native_hwtcl} {Native} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_maxpayload_size_hwtcl} {1024} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msi_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msix_enable_hwtcl} {1} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msi_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msix_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_msi_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_msix_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_ats_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_msi_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_msix_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_tph_cap_enable_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_rp_ep_mode_hwtcl} {Native Endpoint} + set_instance_parameter_value pcie_s10_hip_ast_0 {wrala_hwtcl} {Gen2x8, Interface - 256 bit, 125 MHz} + set_instance_parameter_value pcie_s10_hip_ast_0 {xcvr_adme_hwtcl} {0} + set_instance_parameter_value pcie_s10_hip_ast_0 {xcvr_reconfig_hwtcl} {0} + set_instance_property pcie_s10_hip_ast_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property refclk EXPORT_OF pcie_s10_hip_ast_0.refclk + set_interface_property coreclkout_hip EXPORT_OF pcie_s10_hip_ast_0.coreclkout_hip + set_interface_property npor EXPORT_OF pcie_s10_hip_ast_0.npor + set_interface_property hip_rst EXPORT_OF pcie_s10_hip_ast_0.hip_rst + set_interface_property clr_st EXPORT_OF pcie_s10_hip_ast_0.clr_st + set_interface_property ninit_done EXPORT_OF pcie_s10_hip_ast_0.ninit_done + set_interface_property rx_st EXPORT_OF pcie_s10_hip_ast_0.rx_st + set_interface_property tx_st EXPORT_OF pcie_s10_hip_ast_0.tx_st + set_interface_property rx_bar EXPORT_OF pcie_s10_hip_ast_0.rx_bar + set_interface_property tx_cred EXPORT_OF pcie_s10_hip_ast_0.tx_cred + set_interface_property int_msi EXPORT_OF pcie_s10_hip_ast_0.int_msi + set_interface_property hip_status EXPORT_OF pcie_s10_hip_ast_0.hip_status + set_interface_property config_tl EXPORT_OF pcie_s10_hip_ast_0.config_tl + set_interface_property hip_ctrl EXPORT_OF pcie_s10_hip_ast_0.hip_ctrl + set_interface_property currentspeed EXPORT_OF pcie_s10_hip_ast_0.currentspeed + set_interface_property hip_pipe EXPORT_OF pcie_s10_hip_ast_0.hip_pipe + set_interface_property hip_serial EXPORT_OF pcie_s10_hip_ast_0.hip_serial + set_interface_property power_mgnt EXPORT_OF pcie_s10_hip_ast_0.power_mgnt + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {pcie.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {pcie} + + # save the system + sync_sysinfo_parameters + save_system pcie +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_pcie + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/ref_div.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/ref_div.tcl new file mode 100644 index 000000000..e971958e6 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/ref_div.tcl @@ -0,0 +1,61 @@ +package require -exact qsys 21.3 + +# create the system "ref_div" +proc do_create_ref_div {} { + # create the system + create_system ref_div + set_project_property DEVICE {1SM21CHU1F53E1VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance stratix10_clkctrl_0 stratix10_clkctrl + set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER} {1} + set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER_OUTPUTS} {3} + set_instance_parameter_value stratix10_clkctrl_0 {ENABLE} {0} + set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_REGISTER_TYPE} {1} + set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_TYPE} {2} + set_instance_parameter_value stratix10_clkctrl_0 {GLITCH_FREE_SWITCHOVER} {0} + set_instance_parameter_value stratix10_clkctrl_0 {NUM_CLOCKS} {1} + set_instance_property stratix10_clkctrl_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property inclk EXPORT_OF stratix10_clkctrl_0.inclk + set_interface_property clock_div1x EXPORT_OF stratix10_clkctrl_0.clock_div1x + set_interface_property clock_div2x EXPORT_OF stratix10_clkctrl_0.clock_div2x + set_interface_property clock_div4x EXPORT_OF stratix10_clkctrl_0.clock_div4x + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {ref_div.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {ref_div} + + # save the system + sync_sysinfo_parameters + save_system ref_div +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_ref_div + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/ip/reset_release.tcl b/fpga/mqnic/520N_MX/fpga_25g/ip/reset_release.tcl new file mode 100644 index 000000000..b79c1ae73 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/ip/reset_release.tcl @@ -0,0 +1,50 @@ +package require -exact qsys 20.4 + +# create the system "reset_release" +proc do_create_reset_release {} { + # create the system + create_system reset_release + set_project_property DEVICE {1SM21CHU2F53E2VG} + set_project_property DEVICE_FAMILY {Stratix 10} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate + set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} + set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true + + # add wirelevel expressions + + # add the exports + set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {reset_release.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {reset_release} + + # save the system + sync_sysinfo_parameters + save_system reset_release +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_reset_release + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/520N_MX/fpga_25g/lib b/fpga/mqnic/520N_MX/fpga_25g/lib new file mode 120000 index 000000000..9512b3d5e --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/lib @@ -0,0 +1 @@ +../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/axis_fifo.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/axis_fifo.v new file mode 100644 index 000000000..3ea0ecf04 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/axis_fifo.v @@ -0,0 +1,408 @@ +/* + +Copyright (c) 2013-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream FIFO + */ +module axis_fifo # +( + // FIFO depth in words + // KEEP_WIDTH words per cycle if KEEP_ENABLE set + // Rounded up to nearest power of 2 cycles + parameter DEPTH = 4096, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + // If disabled, tkeep assumed to be 1'b1 + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), + // Propagate tlast signal + parameter LAST_ENABLE = 1, + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // number of RAM pipeline registers + parameter RAM_PIPELINE = 1, + // use output FIFO + // When set, the RAM read enable and pipeline clock enables are removed + parameter OUTPUT_FIFO_ENABLE = 0, + // Frame FIFO mode - operate on frames instead of cycles + // When set, m_axis_tvalid will not be deasserted within a frame + // Requires LAST_ENABLE set + parameter FRAME_FIFO = 0, + // tuser value for bad frame marker + parameter USER_BAD_FRAME_VALUE = 1'b1, + // tuser mask for bad frame marker + parameter USER_BAD_FRAME_MASK = 1'b1, + // Drop frames larger than FIFO + // Requires FRAME_FIFO set + parameter DROP_OVERSIZE_FRAME = FRAME_FIFO, + // Drop frames marked bad + // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set + parameter DROP_BAD_FRAME = 0, + // Drop incoming frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set + parameter DROP_WHEN_FULL = 0 +) +( + input wire clk, + input wire rst, + + /* + * AXI input + */ + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI output + */ + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser, + + /* + * Status + */ + output wire status_overflow, + output wire status_bad_frame, + output wire status_good_frame +); + +parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH); + +parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7); + +// check configuration +initial begin + if (FRAME_FIFO && !LAST_ENABLE) begin + $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); + $finish; + end + + if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin + $error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin + $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); + $finish; + end + + if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin + $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin + $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); + $finish; + end +end + +localparam KEEP_OFFSET = DATA_WIDTH; +localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0); +localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0); +localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0); +localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); +localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); + +reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}; + +// (* ramstyle = "no_rw_check" *) +// Workaround for Quartus MLAB RAM read enable bug +// https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html +(* ramstyle = "no_rw_check, m20k" *) +reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; +reg mem_read_data_valid_reg = 1'b0; + +(* shreg_extract = "no" *) +reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0]; +reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0; + +// full when first MSB different but rest same +wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); +wire full_cur = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); +// empty when pointers match exactly +wire empty = wr_ptr_reg == rd_ptr_reg; +// overflow within packet +wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); + +reg drop_frame_reg = 1'b0; +reg send_frame_reg = 1'b0; +reg overflow_reg = 1'b0; +reg bad_frame_reg = 1'b0; +reg good_frame_reg = 1'b0; + +assign s_axis_tready = FRAME_FIFO ? (!full_cur || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : !full; + +wire [WIDTH-1:0] s_axis; + +generate + assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; + if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; + if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast; + if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; + if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; + if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; +endgenerate + +wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1]; + +wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1]; + +wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0]; +wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; +wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1; +wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}}; +wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; +wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; + +wire pipe_ready; + +assign status_overflow = overflow_reg; +assign status_bad_frame = bad_frame_reg; +assign status_good_frame = good_frame_reg; + +// Write logic +always @(posedge clk) begin + overflow_reg <= 1'b0; + bad_frame_reg <= 1'b0; + good_frame_reg <= 1'b0; + + if (s_axis_tready && s_axis_tvalid) begin + // transfer in + if (!FRAME_FIFO) begin + // normal FIFO mode + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_reg <= wr_ptr_reg + 1; + end else if ((full_cur && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin + // full, packet overflow, or currently dropping frame + // drop frame + drop_frame_reg <= 1'b1; + if (s_axis_tlast) begin + // end of frame, reset write pointer + wr_ptr_cur_reg <= wr_ptr_reg; + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else begin + // store it + mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_cur_reg <= wr_ptr_cur_reg + 1; + if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin + // end of frame or send frame + send_frame_reg <= !s_axis_tlast; + if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin + // bad packet, reset write pointer + wr_ptr_cur_reg <= wr_ptr_reg; + bad_frame_reg <= 1'b1; + end else begin + // good packet or packet overflow, update write pointer + wr_ptr_reg <= wr_ptr_cur_reg + 1; + good_frame_reg <= s_axis_tlast; + end + end + end + end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin + // data valid with packet overflow + // update write pointer + send_frame_reg <= 1'b1; + wr_ptr_reg <= wr_ptr_cur_reg; + end + + if (rst) begin + wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}}; + + drop_frame_reg <= 1'b0; + send_frame_reg <= 1'b0; + overflow_reg <= 1'b0; + bad_frame_reg <= 1'b0; + good_frame_reg <= 1'b0; + end +end + +// Read logic +integer j; + +always @(posedge clk) begin + if (OUTPUT_FIFO_ENABLE || m_axis_tready) begin + // output ready; invalidate stage + m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; + end + + for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin + if (OUTPUT_FIFO_ENABLE || m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin + // output ready or bubble in pipeline; transfer down pipeline + m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1]; + m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1]; + m_axis_tvalid_pipe_reg[j-1] <= 1'b0; + end + end + + if (OUTPUT_FIFO_ENABLE || m_axis_tready || ~m_axis_tvalid_pipe_reg) begin + // output ready or bubble in pipeline; read new data from FIFO + m_axis_tvalid_pipe_reg[0] <= 1'b0; + m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]]; + if (!empty && pipe_ready) begin + // not empty, increment pointer + m_axis_tvalid_pipe_reg[0] <= 1'b1; + rd_ptr_reg <= rd_ptr_reg + 1; + end + end + + if (rst) begin + rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + m_axis_tvalid_pipe_reg <= 0; + end +end + +generate + +if (!OUTPUT_FIFO_ENABLE) begin + + assign pipe_ready = 1'b1; + + assign m_axis_tvalid = m_axis_tvalid_pipe; + + assign m_axis_tdata = m_axis_tdata_pipe; + assign m_axis_tkeep = m_axis_tkeep_pipe; + assign m_axis_tlast = m_axis_tlast_pipe; + assign m_axis_tid = m_axis_tid_pipe; + assign m_axis_tdest = m_axis_tdest_pipe; + assign m_axis_tuser = m_axis_tuser_pipe; + +end else begin + + // output datapath logic + reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; + reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; + reg m_axis_tvalid_reg = 1'b0; + reg m_axis_tlast_reg = 1'b0; + reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; + reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; + reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + + reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0; + reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0; + reg out_fifo_half_full_reg = 1'b0; + + wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}}); + wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; + + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; + + assign pipe_ready = !out_fifo_half_full_reg; + + assign m_axis_tdata = m_axis_tdata_reg; + assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; + assign m_axis_tvalid = m_axis_tvalid_reg; + assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; + assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; + assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; + assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + + always @(posedge clk) begin + m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready; + + out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1); + + if (!out_fifo_full && m_axis_tvalid_pipe) begin + out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe; + out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe; + out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe; + out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe; + out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe; + out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe; + out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1; + end + + if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin + m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; + m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; + m_axis_tvalid_reg <= 1'b1; + m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; + m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; + m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; + m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; + out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1; + end + + if (rst) begin + out_fifo_wr_ptr_reg <= 0; + out_fifo_rd_ptr_reg <= 0; + m_axis_tvalid_reg <= 1'b0; + end + end + +end + +endgenerate + +endmodule + +`resetall diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/common b/fpga/mqnic/520N_MX/fpga_25g/rtl/common new file mode 120000 index 000000000..449c9409c --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/common @@ -0,0 +1 @@ +../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..3c04cac10 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,386 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter GXT = 0, + + // PHY parameters + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 32, + parameter BITSLIP_LOW_CYCLES = 32, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + input wire xcvr_ref_clk, + + /* + * Serial data + */ + output wire [3:0] xcvr_tx_serial_data, + input wire [3:0] xcvr_rx_serial_data, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_tx_prbs31_enable, + input wire phy_1_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_tx_prbs31_enable, + input wire phy_2_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_tx_prbs31_enable, + input wire phy_3_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_tx_prbs31_enable, + input wire phy_4_rx_prbs31_enable +); + +wire xcvr_gx_pll_locked; +wire xcvr_gx_pll_cal_busy; +wire xcvr_gxt_pll_locked; +wire xcvr_gxt_pll_cal_busy; + +wire xcvr_tx_serial_gx_clk; +wire [1:0] xcvr_tx_serial_gxt_clk; + +eth_xcvr_gx_pll eth_xcvr_gx_pll_inst ( + .pll_refclk0 (xcvr_ref_clk), + .tx_serial_clk (xcvr_tx_serial_gx_clk), + .pll_locked (xcvr_gx_pll_locked), + .pll_cal_busy (xcvr_gx_pll_cal_busy) +); + +generate + +if (GXT) begin + + wire atx_pll_cascade_clk; + + eth_xcvr_gxt_pll eth_xcvr_gxt_pll_inst ( + .pll_refclk0 (xcvr_ref_clk), + .tx_serial_clk_gxt (xcvr_tx_serial_gxt_clk[0]), + .gxt_output_to_abv_atx (atx_pll_cascade_clk), + .pll_locked (xcvr_gxt_pll_locked), + .pll_cal_busy (xcvr_gxt_pll_cal_busy) + ); + + eth_xcvr_gxt_buf eth_xcvr_gxt_buf_inst ( + .pll_refclk0 (xcvr_ref_clk), + .tx_serial_clk_gxt (xcvr_tx_serial_gxt_clk[1]), + .gxt_input_from_blw_atx (atx_pll_cascade_clk), + .pll_locked (), + .pll_cal_busy () + ); + +end else begin + + assign xcvr_tx_serial_gxt_clk = 2'b00; + assign xcvr_gxt_pll_locked = 1'b1; + assign xcvr_gxt_pll_cal_busy = 1'b0; + +end + +endgenerate + +eth_xcvr_phy_wrapper #( + .GXT(GXT), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Transceiver connections + .xcvr_gx_pll_locked(xcvr_gx_pll_locked), + .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked), + .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy), + .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy), + .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk), + .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[0]), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[0]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_tx_prbs31_enable(phy_1_tx_prbs31_enable), + .phy_rx_prbs31_enable(phy_1_rx_prbs31_enable) +); + +eth_xcvr_phy_wrapper #( + .GXT(GXT), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Transceiver connections + .xcvr_gx_pll_locked(xcvr_gx_pll_locked), + .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked), + .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy), + .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy), + .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk), + .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[0]), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[1]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_tx_prbs31_enable(phy_2_tx_prbs31_enable), + .phy_rx_prbs31_enable(phy_2_rx_prbs31_enable) +); + +eth_xcvr_phy_wrapper #( + .GXT(GXT), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Transceiver connections + .xcvr_gx_pll_locked(xcvr_gx_pll_locked), + .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked), + .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy), + .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy), + .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk), + .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[1]), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[2]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_tx_prbs31_enable(phy_3_tx_prbs31_enable), + .phy_rx_prbs31_enable(phy_3_rx_prbs31_enable) +); + +eth_xcvr_phy_wrapper #( + .GXT(GXT), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Transceiver connections + .xcvr_gx_pll_locked(xcvr_gx_pll_locked), + .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked), + .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy), + .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy), + .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk), + .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[1]), + .xcvr_rx_cdr_refclk(xcvr_ref_clk), + .xcvr_tx_serial_data(xcvr_tx_serial_data[3]), + .xcvr_rx_serial_data(xcvr_rx_serial_data[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_tx_prbs31_enable(phy_4_tx_prbs31_enable), + .phy_rx_prbs31_enable(phy_4_rx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_wrapper.v new file mode 100644 index 000000000..675acd98b --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -0,0 +1,330 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY wrapper + */ +module eth_xcvr_phy_wrapper # +( + parameter GXT = 0, + + // PHY parameters + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 32, + parameter BITSLIP_LOW_CYCLES = 32, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Transceiver connections + */ + input wire xcvr_gx_pll_locked, + input wire xcvr_gxt_pll_locked, + input wire xcvr_gx_pll_cal_busy, + input wire xcvr_gxt_pll_cal_busy, + input wire xcvr_tx_serial_gx_clk, + input wire xcvr_tx_serial_gxt_clk, + input wire xcvr_rx_cdr_refclk, + output wire xcvr_tx_serial_data, + input wire xcvr_rx_serial_data, + + /* + * PHY connections + */ + output wire phy_tx_clk, + output wire phy_tx_rst, + input wire [DATA_WIDTH-1:0] phy_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_xgmii_txc, + output wire phy_rx_clk, + output wire phy_rx_rst, + output wire [DATA_WIDTH-1:0] phy_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc, + output wire phy_tx_bad_block, + output wire [6:0] phy_rx_error_count, + output wire phy_rx_bad_block, + output wire phy_rx_sequence_error, + output wire phy_rx_block_lock, + output wire phy_rx_high_ber, + output wire phy_rx_status, + input wire phy_tx_prbs31_enable, + input wire phy_rx_prbs31_enable +); + +wire xcvr_tx_analogreset; +wire xcvr_rx_analogreset; +wire xcvr_tx_digitalreset; +wire xcvr_rx_digitalreset; +wire xcvr_tx_analogreset_stat; +wire xcvr_rx_analogreset_stat; +wire xcvr_tx_digitalreset_stat; +wire xcvr_rx_digitalreset_stat; +wire xcvr_tx_cal_busy; +wire xcvr_rx_cal_busy; +wire xcvr_rx_is_lockedtoref; +wire xcvr_rx_is_lockedtodata; +wire xcvr_tx_ready; +wire xcvr_rx_ready; + +wire xcvr_tx_clk; +wire xcvr_rx_clk; + +assign phy_tx_clk = xcvr_tx_clk; +assign phy_rx_clk = xcvr_rx_clk; + +wire [1:0] xcvr_tx_hdr; +wire [DATA_WIDTH-1:0] xcvr_tx_data; +wire [1:0] xcvr_rx_hdr; +wire [DATA_WIDTH-1:0] xcvr_rx_data; + +wire [1:0] phy_tx_hdr; +wire [DATA_WIDTH-1:0] phy_tx_data; +wire [1:0] phy_rx_hdr; +wire [DATA_WIDTH-1:0] phy_rx_data; + +assign {xcvr_tx_hdr, xcvr_tx_data} = {phy_tx_data, phy_tx_hdr}; +assign {phy_rx_data, phy_rx_hdr} = {xcvr_rx_hdr, xcvr_rx_data}; + +wire xcvr_rx_bitslip; + +wire phy_rx_reset_req; +wire phy_rx_reset_req_sync; + +sync_reset #( + .N(4) +) +phy_rx_rst_req_reset_sync_inst ( + .clk(xcvr_ctrl_clk), + .rst(phy_rx_reset_req), + .out(phy_rx_reset_req_sync) +); + +eth_xcvr_reset eth_xcvr_reset_inst ( + .clock (xcvr_ctrl_clk), + .reset (xcvr_ctrl_rst), + .tx_analogreset (xcvr_tx_analogreset), + .tx_digitalreset (xcvr_tx_digitalreset), + .tx_ready (xcvr_tx_ready), + .pll_locked (xcvr_gx_pll_locked && (GXT || xcvr_gxt_pll_locked)), + .pll_select (1'b0), + .tx_cal_busy (xcvr_tx_cal_busy), + .tx_analogreset_stat (xcvr_tx_analogreset_stat), + .tx_digitalreset_stat (xcvr_tx_digitalreset_stat), + .pll_cal_busy (xcvr_gx_pll_cal_busy || (GXT && xcvr_gxt_pll_cal_busy)), + .rx_analogreset (xcvr_rx_analogreset), + .rx_digitalreset (xcvr_rx_digitalreset), + .rx_ready (xcvr_rx_ready), + .rx_is_lockedtodata (xcvr_rx_is_lockedtodata), + .rx_cal_busy (xcvr_rx_cal_busy || phy_rx_reset_req_sync), + .rx_analogreset_stat (xcvr_rx_analogreset_stat), + .rx_digitalreset_stat (xcvr_rx_digitalreset_stat) +); + +generate + +if (GXT) begin + + eth_xcvr_gxt eth_xcvr_inst ( + .tx_analogreset (xcvr_tx_analogreset), + .rx_analogreset (xcvr_rx_analogreset), + .tx_digitalreset (xcvr_tx_digitalreset), + .rx_digitalreset (xcvr_rx_digitalreset), + .tx_analogreset_stat (xcvr_tx_analogreset_stat), + .rx_analogreset_stat (xcvr_rx_analogreset_stat), + .tx_digitalreset_stat (xcvr_tx_digitalreset_stat), + .rx_digitalreset_stat (xcvr_rx_digitalreset_stat), + .tx_cal_busy (xcvr_tx_cal_busy), + .rx_cal_busy (xcvr_rx_cal_busy), + .tx_serial_clk0 (xcvr_tx_serial_gxt_clk), + .tx_serial_clk1 (xcvr_tx_serial_gx_clk), + .rx_cdr_refclk0 (xcvr_rx_cdr_refclk), + .tx_serial_data (xcvr_tx_serial_data), + .rx_serial_data (xcvr_rx_serial_data), + .rx_is_lockedtoref (xcvr_rx_is_lockedtoref), + .rx_is_lockedtodata (xcvr_rx_is_lockedtodata), + .tx_coreclkin (xcvr_tx_clk), + .rx_coreclkin (xcvr_rx_clk), + .tx_clkout (xcvr_tx_clk), + .tx_clkout2 (), + .rx_clkout (xcvr_rx_clk), + .rx_clkout2 (), + .tx_parallel_data (xcvr_tx_data), + .tx_control (xcvr_tx_hdr), + .tx_enh_data_valid (1'b1), + .unused_tx_parallel_data (13'd0), + .rx_parallel_data (xcvr_rx_data), + .rx_control (xcvr_rx_hdr), + .rx_enh_data_valid (), + .unused_rx_parallel_data (), + .rx_bitslip (xcvr_rx_bitslip), + .reconfig_clk (xcvr_ctrl_clk), + .reconfig_reset (xcvr_ctrl_rst), + .reconfig_write (1'b0), + .reconfig_read (1'b0), + .reconfig_address (11'd0), + .reconfig_writedata (32'd0), + .reconfig_readdata (), + .reconfig_waitrequest () + ); + +end else begin + + eth_xcvr_gx eth_xcvr_inst ( + .tx_analogreset (xcvr_tx_analogreset), + .rx_analogreset (xcvr_rx_analogreset), + .tx_digitalreset (xcvr_tx_digitalreset), + .rx_digitalreset (xcvr_rx_digitalreset), + .tx_analogreset_stat (xcvr_tx_analogreset_stat), + .rx_analogreset_stat (xcvr_rx_analogreset_stat), + .tx_digitalreset_stat (xcvr_tx_digitalreset_stat), + .rx_digitalreset_stat (xcvr_rx_digitalreset_stat), + .tx_cal_busy (xcvr_tx_cal_busy), + .rx_cal_busy (xcvr_rx_cal_busy), + .tx_serial_clk0 (xcvr_tx_serial_gx_clk), + .rx_cdr_refclk0 (xcvr_rx_cdr_refclk), + .tx_serial_data (xcvr_tx_serial_data), + .rx_serial_data (xcvr_rx_serial_data), + .rx_is_lockedtoref (xcvr_rx_is_lockedtoref), + .rx_is_lockedtodata (xcvr_rx_is_lockedtodata), + .tx_coreclkin (xcvr_tx_clk), + .rx_coreclkin (xcvr_rx_clk), + .tx_clkout (xcvr_tx_clk), + .tx_clkout2 (), + .rx_clkout (xcvr_rx_clk), + .rx_clkout2 (), + .tx_parallel_data (xcvr_tx_data), + .tx_control (xcvr_tx_hdr), + .tx_enh_data_valid (1'b1), + .unused_tx_parallel_data (13'd0), + .rx_parallel_data (xcvr_rx_data), + .rx_control (xcvr_rx_hdr), + .rx_enh_data_valid (), + .unused_rx_parallel_data (), + .rx_bitslip (xcvr_rx_bitslip) + ); + +end + +endgenerate + +wire phy_tx_rst_int; +reg phy_tx_rst_reg = 1'b0; + +sync_reset #( + .N(4) +) +phy_tx_rst_reset_sync_inst ( + .clk(phy_tx_clk), + .rst(~xcvr_tx_ready), + .out(phy_tx_rst_int) +); + +always @(posedge phy_tx_clk) begin + phy_tx_rst_reg <= phy_tx_rst_int; +end + +assign phy_tx_rst = phy_tx_rst_reg; + +wire phy_rx_rst_int; +reg phy_rx_rst_reg = 1'b0; + +sync_reset #( + .N(4) +) +phy_rx_rst_reset_sync_inst ( + .clk(phy_rx_clk), + .rst(~xcvr_rx_ready), + .out(phy_rx_rst_int) +); + +always @(posedge phy_rx_clk) begin + phy_rx_rst_reg <= phy_rx_rst_int; +end + +assign phy_rx_rst = phy_rx_rst_reg; + +eth_phy_10g #( + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .BIT_REVERSE(0), + .SCRAMBLER_DISABLE(0), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +phy_inst ( + .tx_clk(phy_tx_clk), + .tx_rst(phy_tx_rst), + .rx_clk(phy_rx_clk), + .rx_rst(phy_rx_rst), + .xgmii_txd(phy_xgmii_txd), + .xgmii_txc(phy_xgmii_txc), + .xgmii_rxd(phy_xgmii_rxd), + .xgmii_rxc(phy_xgmii_rxc), + .serdes_tx_data(phy_tx_data), + .serdes_tx_hdr(phy_tx_hdr), + .serdes_rx_data(phy_rx_data), + .serdes_rx_hdr(phy_rx_hdr), + .serdes_rx_bitslip(xcvr_rx_bitslip), + .serdes_rx_reset_req(phy_rx_reset_req), + .tx_bad_block(phy_tx_bad_block), + .rx_error_count(phy_rx_error_count), + .rx_bad_block(phy_rx_bad_block), + .rx_sequence_error(phy_rx_sequence_error), + .rx_block_lock(phy_rx_block_lock), + .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), + .tx_prbs31_enable(phy_tx_prbs31_enable), + .rx_prbs31_enable(phy_rx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v new file mode 100644 index 000000000..192ff619a --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v @@ -0,0 +1,1693 @@ +/* + +Copyright 2023, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // FW and board IDs + parameter FPGA_ID = 32'h432AC0DD, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h198A_0521, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd1563227611, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, + parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, + parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 10, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, + parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter EVENT_QUEUE_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, + parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter SEG_COUNT = 1, + parameter SEG_DATA_WIDTH = 256, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, + parameter AXIS_ETH_TX_PIPELINE = 0, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, + parameter AXIS_ETH_TX_TS_PIPELINE = 0, + parameter AXIS_ETH_RX_PIPELINE = 0, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, + parameter ETH_XCVR_GXT = 1, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 300 MHz + */ + input wire usr_refclk0, + + /* + * GPIO + */ + output wire [1:0] led_user_grn, + output wire [1:0] led_user_red, + output wire [3:0] led_qsfp, + + /* + * I2C + */ + inout wire fpga_i2c_sda, + inout wire fpga_i2c_scl, + output wire fpga_i2c_req_l, + input wire fpga_i2c_mux_gnt, + + /* + * PCIe: gen 3 x16 + */ + output wire [15:0] pcie_tx, + input wire [15:0] pcie_rx, + input wire pcie_refclk, + input wire pcie_perstn, + + /* + * Ethernet: QSFP28 + */ + output wire [3:0] qsfp0_tx, + input wire [3:0] qsfp0_rx, + input wire qsfp0_refclk, + + output wire [3:0] qsfp1_tx, + input wire [3:0] qsfp1_rx, + input wire qsfp1_refclk, + + output wire [3:0] qsfp2_tx, + input wire [3:0] qsfp2_rx, + input wire qsfp2_refclk, + + output wire [3:0] qsfp3_tx, + input wire [3:0] qsfp3_rx, + input wire qsfp3_refclk, + + input wire [3:0] qsfp_irq_n +); + +// PTP configuration +parameter PTP_CLK_PERIOD_NS_NUM = 1024; +parameter PTP_CLK_PERIOD_NS_DENOM = 165; +parameter PTP_TS_WIDTH = 96; +parameter PTP_USE_SAMPLE_CLOCK = 1; +parameter IF_PTP_PERIOD_NS = 6'h6; +parameter IF_PTP_PERIOD_FNS = 16'h6666; + +// Interface configuration +parameter TX_TAG_WIDTH = 16; + +// PCIe interface configuration +parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32); +parameter TX_SEQ_NUM_WIDTH = 6; +parameter PCIE_TAG_COUNT = 256; + +// Ethernet interface configuration +parameter XGMII_DATA_WIDTH = 64; +parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; +parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); +parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; +parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; + +// Clock and reset +wire ninit_done; + +reset_release reset_release_inst ( + .ninit_done (ninit_done) +); + +wire clk_100mhz; +wire rst_100mhz; +wire iopll_100mhz_locked; + +iopll_100mhz iopll_100mhz_inst ( + .rst (ninit_done), + .refclk (usr_refclk0), + .locked (iopll_100mhz_locked), + .outclk_0 (clk_100mhz) +); + +sync_reset #( + .N(20) +) +sync_reset_100mhz_inst ( + .clk(clk_100mhz), + .rst(!iopll_100mhz_locked), + .out(rst_100mhz) +); + +// GPIO +wire fpga_i2c_scl_i; +wire fpga_i2c_scl_o; +wire fpga_i2c_scl_t; +wire fpga_i2c_sda_i; +wire fpga_i2c_sda_o; +wire fpga_i2c_sda_t; +wire fpga_i2c_req_l_int; +wire fpga_i2c_mux_gnt_int; + +reg fpga_i2c_scl_o_reg; +reg fpga_i2c_scl_t_reg; +reg fpga_i2c_sda_o_reg; +reg fpga_i2c_sda_t_reg; +reg fpga_i2c_req_l_reg; + +always @(posedge pcie_clk) begin + fpga_i2c_scl_o_reg <= fpga_i2c_scl_o; + fpga_i2c_scl_t_reg <= fpga_i2c_scl_t; + fpga_i2c_sda_o_reg <= fpga_i2c_sda_o; + fpga_i2c_sda_t_reg <= fpga_i2c_sda_t; + fpga_i2c_req_l_reg <= fpga_i2c_req_l_int; +end + +sync_signal #( + .WIDTH(3), + .N(2) +) +sync_signal_inst ( + .clk(pcie_clk), + .in({fpga_i2c_scl, fpga_i2c_sda, fpga_i2c_mux_gnt}), + .out({fpga_i2c_scl_i, fpga_i2c_sda_i, fpga_i2c_mux_gnt_int}) +); + +assign fpga_i2c_scl = fpga_i2c_scl_t_reg ? 1'bz : fpga_i2c_scl_o_reg; +assign fpga_i2c_sda = fpga_i2c_sda_t_reg ? 1'bz : fpga_i2c_sda_o_reg; +assign fpga_i2c_req_l = fpga_i2c_req_l_reg; + +// PCIe +wire coreclkout_hip; +wire reset_status; + +wire pcie_clk = coreclkout_hip; +wire pcie_rst = reset_status; + +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data; +wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty; +wire [SEG_COUNT-1:0] rx_st_sop; +wire [SEG_COUNT-1:0] rx_st_eop; +wire [SEG_COUNT-1:0] rx_st_valid; +wire rx_st_ready; +wire [SEG_COUNT-1:0] rx_st_vf_active = 0; +wire [SEG_COUNT*3-1:0] rx_st_func_num = 0; +wire [SEG_COUNT*11-1:0] rx_st_vf_num = 0; +wire [SEG_COUNT*3-1:0] rx_st_bar_range; + +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data; +wire [SEG_COUNT-1:0] tx_st_sop; +wire [SEG_COUNT-1:0] tx_st_eop; +wire [SEG_COUNT-1:0] tx_st_valid; +wire tx_st_ready; +wire [SEG_COUNT-1:0] tx_st_err; + +wire [7:0] tx_ph_cdts; +wire [11:0] tx_pd_cdts; +wire [7:0] tx_nph_cdts; +wire [11:0] tx_npd_cdts; +wire [7:0] tx_cplh_cdts; +wire [11:0] tx_cpld_cdts; +wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed; +wire [SEG_COUNT-1:0] tx_data_cdts_consumed; +wire [SEG_COUNT*2-1:0] tx_cdts_type; +wire [SEG_COUNT*1-1:0] tx_cdts_data_value; + +wire [31:0] tl_cfg_ctl; +wire [4:0] tl_cfg_add; +wire [1:0] tl_cfg_func; + +pcie pcie_hip_inst ( + .refclk (pcie_refclk), + .coreclkout_hip (coreclkout_hip), + .npor (!rst_100mhz), + .pin_perst (pcie_perstn), + .reset_status (reset_status), + .serdes_pll_locked (), + .pld_core_ready (1'b1), + .pld_clk_inuse (), + .testin_zero (), + .clr_st (), + .ninit_done (ninit_done), + .rx_st_ready (rx_st_ready), + .rx_st_sop (rx_st_sop), + .rx_st_eop (rx_st_eop), + .rx_st_data (rx_st_data), + .rx_st_valid (rx_st_valid), + .rx_st_empty (rx_st_empty), + .tx_st_sop (tx_st_sop), + .tx_st_eop (tx_st_eop), + .tx_st_data (tx_st_data), + .tx_st_valid (tx_st_valid), + .tx_st_err (tx_st_err), + .tx_st_ready (tx_st_ready), + .rx_st_bar_range (rx_st_bar_range), + .tx_cdts_type (tx_cdts_type), + .tx_data_cdts_consumed (tx_data_cdts_consumed), + .tx_hdr_cdts_consumed (tx_hdr_cdts_consumed), + .tx_cdts_data_value (tx_cdts_data_value), + .tx_cpld_cdts (tx_cpld_cdts), + .tx_pd_cdts (tx_pd_cdts), + .tx_npd_cdts (tx_npd_cdts), + .tx_cplh_cdts (tx_cplh_cdts), + .tx_ph_cdts (tx_ph_cdts), + .tx_nph_cdts (tx_nph_cdts), + .app_msi_req (1'b0), + .app_msi_ack (), + .app_msi_tc (3'd0), + .app_msi_num (5'd0), + .app_int_sts (4'd0), + .app_msi_func_num (2'd0), + .int_status (), + .int_status_common (), + .derr_cor_ext_rpl (), + .derr_rpl (), + .derr_cor_ext_rcv (), + .derr_uncor_ext_rcv (), + .rx_par_err (), + .tx_par_err (), + .ltssmstate (), + .link_up (), + .lane_act (), + .tl_cfg_func (tl_cfg_func), + .tl_cfg_add (tl_cfg_add), + .tl_cfg_ctl (tl_cfg_ctl), + .app_err_valid (0), + .app_err_hdr (0), + .app_err_info (0), + .app_err_func_num (0), + .test_in (0), + .simu_mode_pipe (0), + .currentspeed (), + .sim_pipe_pclk_in (1'b0), + .sim_pipe_rate (), + .sim_ltssmstate (), + .txdata0 (), + .txdata1 (), + .txdata2 (), + .txdata3 (), + .txdata4 (), + .txdata5 (), + .txdata6 (), + .txdata7 (), + .txdatak0 (), + .txdatak1 (), + .txdatak2 (), + .txdatak3 (), + .txdatak4 (), + .txdatak5 (), + .txdatak6 (), + .txdatak7 (), + .txcompl0 (), + .txcompl1 (), + .txcompl2 (), + .txcompl3 (), + .txcompl4 (), + .txcompl5 (), + .txcompl6 (), + .txcompl7 (), + .txelecidle0 (), + .txelecidle1 (), + .txelecidle2 (), + .txelecidle3 (), + .txelecidle4 (), + .txelecidle5 (), + .txelecidle6 (), + .txelecidle7 (), + .txdetectrx0 (), + .txdetectrx1 (), + .txdetectrx2 (), + .txdetectrx3 (), + .txdetectrx4 (), + .txdetectrx5 (), + .txdetectrx6 (), + .txdetectrx7 (), + .powerdown0 (), + .powerdown1 (), + .powerdown2 (), + .powerdown3 (), + .powerdown4 (), + .powerdown5 (), + .powerdown6 (), + .powerdown7 (), + .txmargin0 (), + .txmargin1 (), + .txmargin2 (), + .txmargin3 (), + .txmargin4 (), + .txmargin5 (), + .txmargin6 (), + .txmargin7 (), + .txdeemph0 (), + .txdeemph1 (), + .txdeemph2 (), + .txdeemph3 (), + .txdeemph4 (), + .txdeemph5 (), + .txdeemph6 (), + .txdeemph7 (), + .txswing0 (), + .txswing1 (), + .txswing2 (), + .txswing3 (), + .txswing4 (), + .txswing5 (), + .txswing6 (), + .txswing7 (), + .txsynchd0 (), + .txsynchd1 (), + .txsynchd2 (), + .txsynchd3 (), + .txsynchd4 (), + .txsynchd5 (), + .txsynchd6 (), + .txsynchd7 (), + .txblkst0 (), + .txblkst1 (), + .txblkst2 (), + .txblkst3 (), + .txblkst4 (), + .txblkst5 (), + .txblkst6 (), + .txblkst7 (), + .txdataskip0 (), + .txdataskip1 (), + .txdataskip2 (), + .txdataskip3 (), + .txdataskip4 (), + .txdataskip5 (), + .txdataskip6 (), + .txdataskip7 (), + .rate0 (), + .rate1 (), + .rate2 (), + .rate3 (), + .rate4 (), + .rate5 (), + .rate6 (), + .rate7 (), + .rxpolarity0 (), + .rxpolarity1 (), + .rxpolarity2 (), + .rxpolarity3 (), + .rxpolarity4 (), + .rxpolarity5 (), + .rxpolarity6 (), + .rxpolarity7 (), + .currentrxpreset0 (), + .currentrxpreset1 (), + .currentrxpreset2 (), + .currentrxpreset3 (), + .currentrxpreset4 (), + .currentrxpreset5 (), + .currentrxpreset6 (), + .currentrxpreset7 (), + .currentcoeff0 (), + .currentcoeff1 (), + .currentcoeff2 (), + .currentcoeff3 (), + .currentcoeff4 (), + .currentcoeff5 (), + .currentcoeff6 (), + .currentcoeff7 (), + .rxeqeval0 (), + .rxeqeval1 (), + .rxeqeval2 (), + .rxeqeval3 (), + .rxeqeval4 (), + .rxeqeval5 (), + .rxeqeval6 (), + .rxeqeval7 (), + .rxeqinprogress0 (), + .rxeqinprogress1 (), + .rxeqinprogress2 (), + .rxeqinprogress3 (), + .rxeqinprogress4 (), + .rxeqinprogress5 (), + .rxeqinprogress6 (), + .rxeqinprogress7 (), + .invalidreq0 (), + .invalidreq1 (), + .invalidreq2 (), + .invalidreq3 (), + .invalidreq4 (), + .invalidreq5 (), + .invalidreq6 (), + .invalidreq7 (), + .rxdata0 (32'd0), + .rxdata1 (32'd0), + .rxdata2 (32'd0), + .rxdata3 (32'd0), + .rxdata4 (32'd0), + .rxdata5 (32'd0), + .rxdata6 (32'd0), + .rxdata7 (32'd0), + .rxdatak0 (4'd0), + .rxdatak1 (4'd0), + .rxdatak2 (4'd0), + .rxdatak3 (4'd0), + .rxdatak4 (4'd0), + .rxdatak5 (4'd0), + .rxdatak6 (4'd0), + .rxdatak7 (4'd0), + .phystatus0 (1'b0), + .phystatus1 (1'b0), + .phystatus2 (1'b0), + .phystatus3 (1'b0), + .phystatus4 (1'b0), + .phystatus5 (1'b0), + .phystatus6 (1'b0), + .phystatus7 (1'b0), + .rxvalid0 (1'b0), + .rxvalid1 (1'b0), + .rxvalid2 (1'b0), + .rxvalid3 (1'b0), + .rxvalid4 (1'b0), + .rxvalid5 (1'b0), + .rxvalid6 (1'b0), + .rxvalid7 (1'b0), + .rxstatus0 (3'd0), + .rxstatus1 (3'd0), + .rxstatus2 (3'd0), + .rxstatus3 (3'd0), + .rxstatus4 (3'd0), + .rxstatus5 (3'd0), + .rxstatus6 (3'd0), + .rxstatus7 (3'd0), + .rxelecidle0 (1'b0), + .rxelecidle1 (1'b0), + .rxelecidle2 (1'b0), + .rxelecidle3 (1'b0), + .rxelecidle4 (1'b0), + .rxelecidle5 (1'b0), + .rxelecidle6 (1'b0), + .rxelecidle7 (1'b0), + .rxsynchd0 (2'd0), + .rxsynchd1 (2'd0), + .rxsynchd2 (2'd0), + .rxsynchd3 (2'd0), + .rxsynchd4 (2'd0), + .rxsynchd5 (2'd0), + .rxsynchd6 (2'd0), + .rxsynchd7 (2'd0), + .rxblkst0 (1'b0), + .rxblkst1 (1'b0), + .rxblkst2 (1'b0), + .rxblkst3 (1'b0), + .rxblkst4 (1'b0), + .rxblkst5 (1'b0), + .rxblkst6 (1'b0), + .rxblkst7 (1'b0), + .rxdataskip0 (1'b0), + .rxdataskip1 (1'b0), + .rxdataskip2 (1'b0), + .rxdataskip3 (1'b0), + .rxdataskip4 (1'b0), + .rxdataskip5 (1'b0), + .rxdataskip6 (1'b0), + .rxdataskip7 (1'b0), + .dirfeedback0 (6'd0), + .dirfeedback1 (6'd0), + .dirfeedback2 (6'd0), + .dirfeedback3 (6'd0), + .dirfeedback4 (6'd0), + .dirfeedback5 (6'd0), + .dirfeedback6 (6'd0), + .dirfeedback7 (6'd0), + .sim_pipe_mask_tx_pll_lock (1'b0), + .rx_in0 (pcie_rx[0]), + .rx_in1 (pcie_rx[1]), + .rx_in2 (pcie_rx[2]), + .rx_in3 (pcie_rx[3]), + .rx_in4 (pcie_rx[4]), + .rx_in5 (pcie_rx[5]), + .rx_in6 (pcie_rx[6]), + .rx_in7 (pcie_rx[7]), + .tx_out0 (pcie_tx[0]), + .tx_out1 (pcie_tx[1]), + .tx_out2 (pcie_tx[2]), + .tx_out3 (pcie_tx[3]), + .tx_out4 (pcie_tx[4]), + .tx_out5 (pcie_tx[5]), + .tx_out6 (pcie_tx[6]), + .tx_out7 (pcie_tx[7]), + .pm_linkst_in_l1 (), + .pm_linkst_in_l0s (), + .pm_state (), + .pm_dstate (), + .apps_pm_xmt_pme (0), + .apps_ready_entr_l23 (0), + .apps_pm_xmt_turnoff (0), + .app_init_rst (0), + .app_xfer_pending (0) +); + +// XGMII 10G PHY + +// QSFP0 +wire qsfp0_tx_clk_1_int; +wire qsfp0_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int; +wire qsfp0_tx_prbs31_enable_1_int; +wire qsfp0_rx_clk_1_int; +wire qsfp0_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int; +wire qsfp0_rx_prbs31_enable_1_int; +wire [6:0] qsfp0_rx_error_count_1_int; +wire qsfp0_tx_clk_2_int; +wire qsfp0_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int; +wire qsfp0_tx_prbs31_enable_2_int; +wire qsfp0_rx_clk_2_int; +wire qsfp0_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int; +wire qsfp0_rx_prbs31_enable_2_int; +wire [6:0] qsfp0_rx_error_count_2_int; +wire qsfp0_tx_clk_3_int; +wire qsfp0_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int; +wire qsfp0_tx_prbs31_enable_3_int; +wire qsfp0_rx_clk_3_int; +wire qsfp0_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int; +wire qsfp0_rx_prbs31_enable_3_int; +wire [6:0] qsfp0_rx_error_count_3_int; +wire qsfp0_tx_clk_4_int; +wire qsfp0_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int; +wire qsfp0_tx_prbs31_enable_4_int; +wire qsfp0_rx_clk_4_int; +wire qsfp0_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int; +wire qsfp0_rx_prbs31_enable_4_int; +wire [6:0] qsfp0_rx_error_count_4_int; + +wire qsfp0_rx_block_lock_1; +wire qsfp0_rx_status_1; +wire qsfp0_rx_block_lock_2; +wire qsfp0_rx_status_2; +wire qsfp0_rx_block_lock_3; +wire qsfp0_rx_status_3; +wire qsfp0_rx_block_lock_4; +wire qsfp0_rx_status_4; + +eth_xcvr_phy_quad_wrapper #( + .GXT(ETH_XCVR_GXT), + .DATA_WIDTH(XGMII_DATA_WIDTH), + .CTRL_WIDTH(XGMII_CTRL_WIDTH), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp0_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_100mhz), + .xcvr_ctrl_rst(rst_100mhz), + .xcvr_ref_clk(qsfp0_refclk), + .xcvr_tx_serial_data(qsfp0_tx), + .xcvr_rx_serial_data(qsfp0_rx), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp0_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp0_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp0_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp0_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp0_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp0_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp0_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp0_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int) +); + +// QSFP1 +wire qsfp1_tx_clk_1_int; +wire qsfp1_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int; +wire qsfp1_tx_prbs31_enable_1_int; +wire qsfp1_rx_clk_1_int; +wire qsfp1_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int; +wire qsfp1_rx_prbs31_enable_1_int; +wire [6:0] qsfp1_rx_error_count_1_int; +wire qsfp1_tx_clk_2_int; +wire qsfp1_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int; +wire qsfp1_tx_prbs31_enable_2_int; +wire qsfp1_rx_clk_2_int; +wire qsfp1_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int; +wire qsfp1_rx_prbs31_enable_2_int; +wire [6:0] qsfp1_rx_error_count_2_int; +wire qsfp1_tx_clk_3_int; +wire qsfp1_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int; +wire qsfp1_tx_prbs31_enable_3_int; +wire qsfp1_rx_clk_3_int; +wire qsfp1_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int; +wire qsfp1_rx_prbs31_enable_3_int; +wire [6:0] qsfp1_rx_error_count_3_int; +wire qsfp1_tx_clk_4_int; +wire qsfp1_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int; +wire qsfp1_tx_prbs31_enable_4_int; +wire qsfp1_rx_clk_4_int; +wire qsfp1_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int; +wire qsfp1_rx_prbs31_enable_4_int; +wire [6:0] qsfp1_rx_error_count_4_int; + +wire qsfp1_rx_block_lock_1; +wire qsfp1_rx_status_1; +wire qsfp1_rx_block_lock_2; +wire qsfp1_rx_status_2; +wire qsfp1_rx_block_lock_3; +wire qsfp1_rx_status_3; +wire qsfp1_rx_block_lock_4; +wire qsfp1_rx_status_4; + +eth_xcvr_phy_quad_wrapper #( + .GXT(ETH_XCVR_GXT), + .DATA_WIDTH(XGMII_DATA_WIDTH), + .CTRL_WIDTH(XGMII_CTRL_WIDTH), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp1_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_100mhz), + .xcvr_ctrl_rst(rst_100mhz), + .xcvr_ref_clk(qsfp1_refclk), + .xcvr_tx_serial_data(qsfp1_tx), + .xcvr_rx_serial_data(qsfp1_rx), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp1_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp1_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp1_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp1_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp1_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp1_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp1_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp1_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int) +); + +// QSFP2 +wire qsfp2_tx_clk_1_int; +wire qsfp2_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1_int; +wire qsfp2_tx_prbs31_enable_1_int; +wire qsfp2_rx_clk_1_int; +wire qsfp2_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1_int; +wire qsfp2_rx_prbs31_enable_1_int; +wire [6:0] qsfp2_rx_error_count_1_int; +wire qsfp2_tx_clk_2_int; +wire qsfp2_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2_int; +wire qsfp2_tx_prbs31_enable_2_int; +wire qsfp2_rx_clk_2_int; +wire qsfp2_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2_int; +wire qsfp2_rx_prbs31_enable_2_int; +wire [6:0] qsfp2_rx_error_count_2_int; +wire qsfp2_tx_clk_3_int; +wire qsfp2_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3_int; +wire qsfp2_tx_prbs31_enable_3_int; +wire qsfp2_rx_clk_3_int; +wire qsfp2_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3_int; +wire qsfp2_rx_prbs31_enable_3_int; +wire [6:0] qsfp2_rx_error_count_3_int; +wire qsfp2_tx_clk_4_int; +wire qsfp2_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4_int; +wire qsfp2_tx_prbs31_enable_4_int; +wire qsfp2_rx_clk_4_int; +wire qsfp2_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4_int; +wire qsfp2_rx_prbs31_enable_4_int; +wire [6:0] qsfp2_rx_error_count_4_int; + +wire qsfp2_rx_block_lock_1; +wire qsfp2_rx_status_1; +wire qsfp2_rx_block_lock_2; +wire qsfp2_rx_status_2; +wire qsfp2_rx_block_lock_3; +wire qsfp2_rx_status_3; +wire qsfp2_rx_block_lock_4; +wire qsfp2_rx_status_4; + +eth_xcvr_phy_quad_wrapper #( + .GXT(ETH_XCVR_GXT), + .DATA_WIDTH(XGMII_DATA_WIDTH), + .CTRL_WIDTH(XGMII_CTRL_WIDTH), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp2_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_100mhz), + .xcvr_ctrl_rst(rst_100mhz), + .xcvr_ref_clk(qsfp2_refclk), + .xcvr_tx_serial_data(qsfp2_tx), + .xcvr_rx_serial_data(qsfp2_rx), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp2_tx_clk_1_int), + .phy_1_tx_rst(qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp2_txd_1_int), + .phy_1_xgmii_txc(qsfp2_txc_1_int), + .phy_1_rx_clk(qsfp2_rx_clk_1_int), + .phy_1_rx_rst(qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp2_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp2_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp2_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp2_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp2_tx_clk_2_int), + .phy_2_tx_rst(qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp2_txd_2_int), + .phy_2_xgmii_txc(qsfp2_txc_2_int), + .phy_2_rx_clk(qsfp2_rx_clk_2_int), + .phy_2_rx_rst(qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp2_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp2_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp2_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp2_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp2_tx_clk_3_int), + .phy_3_tx_rst(qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp2_txd_3_int), + .phy_3_xgmii_txc(qsfp2_txc_3_int), + .phy_3_rx_clk(qsfp2_rx_clk_3_int), + .phy_3_rx_rst(qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp2_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp2_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp2_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp2_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp2_tx_clk_4_int), + .phy_4_tx_rst(qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp2_txd_4_int), + .phy_4_xgmii_txc(qsfp2_txc_4_int), + .phy_4_rx_clk(qsfp2_rx_clk_4_int), + .phy_4_rx_rst(qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp2_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp2_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp2_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp2_rx_prbs31_enable_4_int) +); + +// QSFP3 +wire qsfp3_tx_clk_1_int; +wire qsfp3_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1_int; +wire qsfp3_tx_prbs31_enable_1_int; +wire qsfp3_rx_clk_1_int; +wire qsfp3_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1_int; +wire qsfp3_rx_prbs31_enable_1_int; +wire [6:0] qsfp3_rx_error_count_1_int; +wire qsfp3_tx_clk_2_int; +wire qsfp3_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2_int; +wire qsfp3_tx_prbs31_enable_2_int; +wire qsfp3_rx_clk_2_int; +wire qsfp3_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2_int; +wire qsfp3_rx_prbs31_enable_2_int; +wire [6:0] qsfp3_rx_error_count_2_int; +wire qsfp3_tx_clk_3_int; +wire qsfp3_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3_int; +wire qsfp3_tx_prbs31_enable_3_int; +wire qsfp3_rx_clk_3_int; +wire qsfp3_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3_int; +wire qsfp3_rx_prbs31_enable_3_int; +wire [6:0] qsfp3_rx_error_count_3_int; +wire qsfp3_tx_clk_4_int; +wire qsfp3_tx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4_int; +wire qsfp3_tx_prbs31_enable_4_int; +wire qsfp3_rx_clk_4_int; +wire qsfp3_rx_rst_4_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4_int; +wire qsfp3_rx_prbs31_enable_4_int; +wire [6:0] qsfp3_rx_error_count_4_int; + +wire qsfp3_rx_block_lock_1; +wire qsfp3_rx_status_1; +wire qsfp3_rx_block_lock_2; +wire qsfp3_rx_status_2; +wire qsfp3_rx_block_lock_3; +wire qsfp3_rx_status_3; +wire qsfp3_rx_block_lock_4; +wire qsfp3_rx_status_4; + +eth_xcvr_phy_quad_wrapper #( + .GXT(ETH_XCVR_GXT), + .DATA_WIDTH(XGMII_DATA_WIDTH), + .CTRL_WIDTH(XGMII_CTRL_WIDTH), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp3_eth_xcvr_phy_quad ( + .xcvr_ctrl_clk(clk_100mhz), + .xcvr_ctrl_rst(rst_100mhz), + .xcvr_ref_clk(qsfp3_refclk), + .xcvr_tx_serial_data(qsfp3_tx), + .xcvr_rx_serial_data(qsfp3_rx), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp3_tx_clk_1_int), + .phy_1_tx_rst(qsfp3_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp3_txd_1_int), + .phy_1_xgmii_txc(qsfp3_txc_1_int), + .phy_1_rx_clk(qsfp3_rx_clk_1_int), + .phy_1_rx_rst(qsfp3_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp3_rxd_1_int), + .phy_1_xgmii_rxc(qsfp3_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp3_rx_error_count_1_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp3_rx_block_lock_1), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp3_rx_status_1), + .phy_1_tx_prbs31_enable(qsfp3_tx_prbs31_enable_1_int), + .phy_1_rx_prbs31_enable(qsfp3_rx_prbs31_enable_1_int), + + .phy_2_tx_clk(qsfp3_tx_clk_2_int), + .phy_2_tx_rst(qsfp3_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp3_txd_2_int), + .phy_2_xgmii_txc(qsfp3_txc_2_int), + .phy_2_rx_clk(qsfp3_rx_clk_2_int), + .phy_2_rx_rst(qsfp3_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp3_rxd_2_int), + .phy_2_xgmii_rxc(qsfp3_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp3_rx_error_count_2_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp3_rx_block_lock_2), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp3_rx_status_2), + .phy_2_tx_prbs31_enable(qsfp3_tx_prbs31_enable_2_int), + .phy_2_rx_prbs31_enable(qsfp3_rx_prbs31_enable_2_int), + + .phy_3_tx_clk(qsfp3_tx_clk_3_int), + .phy_3_tx_rst(qsfp3_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp3_txd_3_int), + .phy_3_xgmii_txc(qsfp3_txc_3_int), + .phy_3_rx_clk(qsfp3_rx_clk_3_int), + .phy_3_rx_rst(qsfp3_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp3_rxd_3_int), + .phy_3_xgmii_rxc(qsfp3_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp3_rx_error_count_3_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp3_rx_block_lock_3), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp3_rx_status_3), + .phy_3_tx_prbs31_enable(qsfp3_tx_prbs31_enable_3_int), + .phy_3_rx_prbs31_enable(qsfp3_rx_prbs31_enable_3_int), + + .phy_4_tx_clk(qsfp3_tx_clk_4_int), + .phy_4_tx_rst(qsfp3_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp3_txd_4_int), + .phy_4_xgmii_txc(qsfp3_txc_4_int), + .phy_4_rx_clk(qsfp3_rx_clk_4_int), + .phy_4_rx_rst(qsfp3_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp3_rxd_4_int), + .phy_4_xgmii_rxc(qsfp3_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp3_rx_error_count_4_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp3_rx_block_lock_4), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp3_rx_status_4), + .phy_4_tx_prbs31_enable(qsfp3_tx_prbs31_enable_4_int), + .phy_4_rx_prbs31_enable(qsfp3_rx_prbs31_enable_4_int) +); + +wire ptp_clk; +wire ptp_rst; +wire ptp_sample_clk; + +assign ptp_sample_clk = clk_100mhz; + +ref_div ref_div_inst ( + .inclk(qsfp0_refclk), + .clock_div1x(), + .clock_div2x(), + .clock_div4x(ptp_clk) +); + +sync_reset #( + .N(4) +) +ptp_rst_reset_sync_inst ( + .clk(ptp_clk), + .rst(rst_100mhz), + .out(ptp_rst) +); + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + .IF_PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .IF_PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), + .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), + .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), + .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH), + .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(pcie_clk), + .rst_250mhz(pcie_rst), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + .led_user_grn(led_user_grn), + .led_user_red(led_user_red), + .led_qsfp(led_qsfp), + + /* + * I2C + */ + .fpga_i2c_sda_i(fpga_i2c_sda_i), + .fpga_i2c_sda_o(fpga_i2c_sda_o), + .fpga_i2c_sda_t(fpga_i2c_sda_t), + .fpga_i2c_scl_i(fpga_i2c_scl_i), + .fpga_i2c_scl_o(fpga_i2c_scl_o), + .fpga_i2c_scl_t(fpga_i2c_scl_t), + .fpga_i2c_req_l(fpga_i2c_req_l_int), + .fpga_i2c_mux_gnt(fpga_i2c_mux_gnt_int), + + /* + * H-Tile interface + */ + .rx_st_data(rx_st_data), + .rx_st_empty(rx_st_empty), + .rx_st_sop(rx_st_sop), + .rx_st_eop(rx_st_eop), + .rx_st_valid(rx_st_valid), + .rx_st_ready(rx_st_ready), + .rx_st_vf_active(rx_st_vf_active), + .rx_st_func_num(rx_st_func_num), + .rx_st_vf_num(rx_st_vf_num), + .rx_st_bar_range(rx_st_bar_range), + + .tx_st_data(tx_st_data), + .tx_st_sop(tx_st_sop), + .tx_st_eop(tx_st_eop), + .tx_st_valid(tx_st_valid), + .tx_st_ready(tx_st_ready), + .tx_st_err(tx_st_err), + + .tx_ph_cdts(tx_ph_cdts), + .tx_pd_cdts(tx_pd_cdts), + .tx_nph_cdts(tx_nph_cdts), + .tx_npd_cdts(tx_npd_cdts), + .tx_cplh_cdts(tx_cplh_cdts), + .tx_cpld_cdts(tx_cpld_cdts), + .tx_hdr_cdts_consumed(tx_hdr_cdts_consumed), + .tx_data_cdts_consumed(tx_data_cdts_consumed), + .tx_cdts_type(tx_cdts_type), + .tx_cdts_data_value(tx_cdts_data_value), + + .tl_cfg_ctl(tl_cfg_ctl), + .tl_cfg_add(tl_cfg_add), + .tl_cfg_func(tl_cfg_func), + + /* + * Ethernet: QSFP28 + */ + .qsfp0_tx_clk_1(qsfp0_tx_clk_1_int), + .qsfp0_tx_rst_1(qsfp0_tx_rst_1_int), + .qsfp0_txd_1(qsfp0_txd_1_int), + .qsfp0_txc_1(qsfp0_txc_1_int), + .qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int), + .qsfp0_rx_clk_1(qsfp0_rx_clk_1_int), + .qsfp0_rx_rst_1(qsfp0_rx_rst_1_int), + .qsfp0_rxd_1(qsfp0_rxd_1_int), + .qsfp0_rxc_1(qsfp0_rxc_1_int), + .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int), + .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int), + .qsfp0_rx_status_1(qsfp0_rx_status_1), + .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int), + .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int), + .qsfp0_txd_2(qsfp0_txd_2_int), + .qsfp0_txc_2(qsfp0_txc_2_int), + .qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int), + .qsfp0_rx_clk_2(qsfp0_rx_clk_2_int), + .qsfp0_rx_rst_2(qsfp0_rx_rst_2_int), + .qsfp0_rxd_2(qsfp0_rxd_2_int), + .qsfp0_rxc_2(qsfp0_rxc_2_int), + .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int), + .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int), + .qsfp0_rx_status_2(qsfp0_rx_status_2), + .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int), + .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int), + .qsfp0_txd_3(qsfp0_txd_3_int), + .qsfp0_txc_3(qsfp0_txc_3_int), + .qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int), + .qsfp0_rx_clk_3(qsfp0_rx_clk_3_int), + .qsfp0_rx_rst_3(qsfp0_rx_rst_3_int), + .qsfp0_rxd_3(qsfp0_rxd_3_int), + .qsfp0_rxc_3(qsfp0_rxc_3_int), + .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int), + .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int), + .qsfp0_rx_status_3(qsfp0_rx_status_3), + .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int), + .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int), + .qsfp0_txd_4(qsfp0_txd_4_int), + .qsfp0_txc_4(qsfp0_txc_4_int), + .qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int), + .qsfp0_rx_clk_4(qsfp0_rx_clk_4_int), + .qsfp0_rx_rst_4(qsfp0_rx_rst_4_int), + .qsfp0_rxd_4(qsfp0_rxd_4_int), + .qsfp0_rxc_4(qsfp0_rxc_4_int), + .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int), + .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int), + .qsfp0_rx_status_4(qsfp0_rx_status_4), + + .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), + .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), + .qsfp1_txd_1(qsfp1_txd_1_int), + .qsfp1_txc_1(qsfp1_txc_1_int), + .qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int), + .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), + .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), + .qsfp1_rxd_1(qsfp1_rxd_1_int), + .qsfp1_rxc_1(qsfp1_rxc_1_int), + .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int), + .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int), + .qsfp1_rx_status_1(qsfp1_rx_status_1), + .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), + .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), + .qsfp1_txd_2(qsfp1_txd_2_int), + .qsfp1_txc_2(qsfp1_txc_2_int), + .qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int), + .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), + .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), + .qsfp1_rxd_2(qsfp1_rxd_2_int), + .qsfp1_rxc_2(qsfp1_rxc_2_int), + .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int), + .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int), + .qsfp1_rx_status_2(qsfp1_rx_status_2), + .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), + .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), + .qsfp1_txd_3(qsfp1_txd_3_int), + .qsfp1_txc_3(qsfp1_txc_3_int), + .qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int), + .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), + .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), + .qsfp1_rxd_3(qsfp1_rxd_3_int), + .qsfp1_rxc_3(qsfp1_rxc_3_int), + .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int), + .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int), + .qsfp1_rx_status_3(qsfp1_rx_status_3), + .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), + .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), + .qsfp1_txd_4(qsfp1_txd_4_int), + .qsfp1_txc_4(qsfp1_txc_4_int), + .qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int), + .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), + .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), + .qsfp1_rxd_4(qsfp1_rxd_4_int), + .qsfp1_rxc_4(qsfp1_rxc_4_int), + .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int), + .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int), + .qsfp1_rx_status_4(qsfp1_rx_status_4), + + .qsfp2_tx_clk_1(qsfp2_tx_clk_1_int), + .qsfp2_tx_rst_1(qsfp2_tx_rst_1_int), + .qsfp2_txd_1(qsfp2_txd_1_int), + .qsfp2_txc_1(qsfp2_txc_1_int), + .qsfp2_tx_prbs31_enable_1(qsfp2_tx_prbs31_enable_1_int), + .qsfp2_rx_clk_1(qsfp2_rx_clk_1_int), + .qsfp2_rx_rst_1(qsfp2_rx_rst_1_int), + .qsfp2_rxd_1(qsfp2_rxd_1_int), + .qsfp2_rxc_1(qsfp2_rxc_1_int), + .qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int), + .qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int), + .qsfp2_rx_status_1(qsfp2_rx_status_1), + .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int), + .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int), + .qsfp2_txd_2(qsfp2_txd_2_int), + .qsfp2_txc_2(qsfp2_txc_2_int), + .qsfp2_tx_prbs31_enable_2(qsfp2_tx_prbs31_enable_2_int), + .qsfp2_rx_clk_2(qsfp2_rx_clk_2_int), + .qsfp2_rx_rst_2(qsfp2_rx_rst_2_int), + .qsfp2_rxd_2(qsfp2_rxd_2_int), + .qsfp2_rxc_2(qsfp2_rxc_2_int), + .qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int), + .qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int), + .qsfp2_rx_status_2(qsfp2_rx_status_2), + .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int), + .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int), + .qsfp2_txd_3(qsfp2_txd_3_int), + .qsfp2_txc_3(qsfp2_txc_3_int), + .qsfp2_tx_prbs31_enable_3(qsfp2_tx_prbs31_enable_3_int), + .qsfp2_rx_clk_3(qsfp2_rx_clk_3_int), + .qsfp2_rx_rst_3(qsfp2_rx_rst_3_int), + .qsfp2_rxd_3(qsfp2_rxd_3_int), + .qsfp2_rxc_3(qsfp2_rxc_3_int), + .qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int), + .qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int), + .qsfp2_rx_status_3(qsfp2_rx_status_3), + .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int), + .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int), + .qsfp2_txd_4(qsfp2_txd_4_int), + .qsfp2_txc_4(qsfp2_txc_4_int), + .qsfp2_tx_prbs31_enable_4(qsfp2_tx_prbs31_enable_4_int), + .qsfp2_rx_clk_4(qsfp2_rx_clk_4_int), + .qsfp2_rx_rst_4(qsfp2_rx_rst_4_int), + .qsfp2_rxd_4(qsfp2_rxd_4_int), + .qsfp2_rxc_4(qsfp2_rxc_4_int), + .qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int), + .qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int), + .qsfp2_rx_status_4(qsfp2_rx_status_4), + + .qsfp3_tx_clk_1(qsfp3_tx_clk_1_int), + .qsfp3_tx_rst_1(qsfp3_tx_rst_1_int), + .qsfp3_txd_1(qsfp3_txd_1_int), + .qsfp3_txc_1(qsfp3_txc_1_int), + .qsfp3_tx_prbs31_enable_1(qsfp3_tx_prbs31_enable_1_int), + .qsfp3_rx_clk_1(qsfp3_rx_clk_1_int), + .qsfp3_rx_rst_1(qsfp3_rx_rst_1_int), + .qsfp3_rxd_1(qsfp3_rxd_1_int), + .qsfp3_rxc_1(qsfp3_rxc_1_int), + .qsfp3_rx_prbs31_enable_1(qsfp3_rx_prbs31_enable_1_int), + .qsfp3_rx_error_count_1(qsfp3_rx_error_count_1_int), + .qsfp3_rx_status_1(qsfp3_rx_status_1), + .qsfp3_tx_clk_2(qsfp3_tx_clk_2_int), + .qsfp3_tx_rst_2(qsfp3_tx_rst_2_int), + .qsfp3_txd_2(qsfp3_txd_2_int), + .qsfp3_txc_2(qsfp3_txc_2_int), + .qsfp3_tx_prbs31_enable_2(qsfp3_tx_prbs31_enable_2_int), + .qsfp3_rx_clk_2(qsfp3_rx_clk_2_int), + .qsfp3_rx_rst_2(qsfp3_rx_rst_2_int), + .qsfp3_rxd_2(qsfp3_rxd_2_int), + .qsfp3_rxc_2(qsfp3_rxc_2_int), + .qsfp3_rx_prbs31_enable_2(qsfp3_rx_prbs31_enable_2_int), + .qsfp3_rx_error_count_2(qsfp3_rx_error_count_2_int), + .qsfp3_rx_status_2(qsfp3_rx_status_2), + .qsfp3_tx_clk_3(qsfp3_tx_clk_3_int), + .qsfp3_tx_rst_3(qsfp3_tx_rst_3_int), + .qsfp3_txd_3(qsfp3_txd_3_int), + .qsfp3_txc_3(qsfp3_txc_3_int), + .qsfp3_tx_prbs31_enable_3(qsfp3_tx_prbs31_enable_3_int), + .qsfp3_rx_clk_3(qsfp3_rx_clk_3_int), + .qsfp3_rx_rst_3(qsfp3_rx_rst_3_int), + .qsfp3_rxd_3(qsfp3_rxd_3_int), + .qsfp3_rxc_3(qsfp3_rxc_3_int), + .qsfp3_rx_prbs31_enable_3(qsfp3_rx_prbs31_enable_3_int), + .qsfp3_rx_error_count_3(qsfp3_rx_error_count_3_int), + .qsfp3_rx_status_3(qsfp3_rx_status_3), + .qsfp3_tx_clk_4(qsfp3_tx_clk_4_int), + .qsfp3_tx_rst_4(qsfp3_tx_rst_4_int), + .qsfp3_txd_4(qsfp3_txd_4_int), + .qsfp3_txc_4(qsfp3_txc_4_int), + .qsfp3_tx_prbs31_enable_4(qsfp3_tx_prbs31_enable_4_int), + .qsfp3_rx_clk_4(qsfp3_rx_clk_4_int), + .qsfp3_rx_rst_4(qsfp3_rx_rst_4_int), + .qsfp3_rxd_4(qsfp3_rxd_4_int), + .qsfp3_rxc_4(qsfp3_rxc_4_int), + .qsfp3_rx_prbs31_enable_4(qsfp3_rx_prbs31_enable_4_int), + .qsfp3_rx_error_count_4(qsfp3_rx_error_count_4_int), + .qsfp3_rx_status_4(qsfp3_rx_status_4) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v new file mode 100644 index 000000000..8d79363d4 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v @@ -0,0 +1,1268 @@ +/* + +Copyright 2023, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // FW and board IDs + parameter FPGA_ID = 32'h432AC0DD, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h198A_0521, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd1563227611, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 32, + parameter PTP_CLK_PERIOD_NS_DENOM = 5, + parameter PTP_TS_WIDTH = 96, + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_USE_SAMPLE_CLOCK = 1, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + parameter IF_PTP_PERIOD_NS = 6'h6, + parameter IF_PTP_PERIOD_FNS = 16'h6666, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, + parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, + parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, + parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter EVENT_QUEUE_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, + parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_TAG_WIDTH = 16, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter SEG_COUNT = 1, + parameter SEG_DATA_WIDTH = 256, + parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32), + parameter TX_SEQ_NUM_WIDTH = 6, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + parameter PCIE_TAG_COUNT = 256, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter XGMII_DATA_WIDTH = 64, + parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, + parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, + parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, + parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, + parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + parameter AXIS_ETH_TX_PIPELINE = 0, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, + parameter AXIS_ETH_TX_TS_PIPELINE = 0, + parameter AXIS_ETH_RX_PIPELINE = 0, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 250 MHz + * Synchronous reset + */ + input wire clk_250mhz, + input wire rst_250mhz, + + /* + * PTP clock + */ + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + + /* + * GPIO + */ + output wire [1:0] led_user_grn, + output wire [1:0] led_user_red, + output wire [3:0] led_qsfp, + + /* + * I2C + */ + input wire fpga_i2c_sda_i, + output wire fpga_i2c_sda_o, + output wire fpga_i2c_sda_t, + input wire fpga_i2c_scl_i, + output wire fpga_i2c_scl_o, + output wire fpga_i2c_scl_t, + output wire fpga_i2c_req_l, + input wire fpga_i2c_mux_gnt, + + /* + * H-Tile interface + */ + input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data, + input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty, + input wire [SEG_COUNT-1:0] rx_st_sop, + input wire [SEG_COUNT-1:0] rx_st_eop, + input wire [SEG_COUNT-1:0] rx_st_valid, + output wire rx_st_ready, + input wire [SEG_COUNT-1:0] rx_st_vf_active, + input wire [SEG_COUNT*2-1:0] rx_st_func_num, + input wire [SEG_COUNT*11-1:0] rx_st_vf_num, + input wire [SEG_COUNT*3-1:0] rx_st_bar_range, + + output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data, + output wire [SEG_COUNT-1:0] tx_st_sop, + output wire [SEG_COUNT-1:0] tx_st_eop, + output wire [SEG_COUNT-1:0] tx_st_valid, + input wire tx_st_ready, + output wire [SEG_COUNT-1:0] tx_st_err, + + input wire [7:0] tx_ph_cdts, + input wire [11:0] tx_pd_cdts, + input wire [7:0] tx_nph_cdts, + input wire [11:0] tx_npd_cdts, + input wire [7:0] tx_cplh_cdts, + input wire [11:0] tx_cpld_cdts, + input wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed, + input wire [SEG_COUNT-1:0] tx_data_cdts_consumed, + input wire [SEG_COUNT*2-1:0] tx_cdts_type, + input wire [SEG_COUNT*1-1:0] tx_cdts_data_value, + + input wire [31:0] tl_cfg_ctl, + input wire [4:0] tl_cfg_add, + input wire [1:0] tl_cfg_func, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp0_tx_clk_1, + input wire qsfp0_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1, + output wire qsfp0_tx_prbs31_enable_1, + input wire qsfp0_rx_clk_1, + input wire qsfp0_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1, + output wire qsfp0_rx_prbs31_enable_1, + input wire [6:0] qsfp0_rx_error_count_1, + input wire qsfp0_rx_status_1, + input wire qsfp0_tx_clk_2, + input wire qsfp0_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2, + output wire qsfp0_tx_prbs31_enable_2, + input wire qsfp0_rx_clk_2, + input wire qsfp0_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2, + output wire qsfp0_rx_prbs31_enable_2, + input wire [6:0] qsfp0_rx_error_count_2, + input wire qsfp0_rx_status_2, + input wire qsfp0_tx_clk_3, + input wire qsfp0_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3, + output wire qsfp0_tx_prbs31_enable_3, + input wire qsfp0_rx_clk_3, + input wire qsfp0_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3, + output wire qsfp0_rx_prbs31_enable_3, + input wire [6:0] qsfp0_rx_error_count_3, + input wire qsfp0_rx_status_3, + input wire qsfp0_tx_clk_4, + input wire qsfp0_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4, + output wire qsfp0_tx_prbs31_enable_4, + input wire qsfp0_rx_clk_4, + input wire qsfp0_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4, + output wire qsfp0_rx_prbs31_enable_4, + input wire [6:0] qsfp0_rx_error_count_4, + input wire qsfp0_rx_status_4, + + input wire qsfp1_tx_clk_1, + input wire qsfp1_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1, + output wire qsfp1_tx_prbs31_enable_1, + input wire qsfp1_rx_clk_1, + input wire qsfp1_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1, + output wire qsfp1_rx_prbs31_enable_1, + input wire [6:0] qsfp1_rx_error_count_1, + input wire qsfp1_rx_status_1, + input wire qsfp1_tx_clk_2, + input wire qsfp1_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2, + output wire qsfp1_tx_prbs31_enable_2, + input wire qsfp1_rx_clk_2, + input wire qsfp1_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2, + output wire qsfp1_rx_prbs31_enable_2, + input wire [6:0] qsfp1_rx_error_count_2, + input wire qsfp1_rx_status_2, + input wire qsfp1_tx_clk_3, + input wire qsfp1_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3, + output wire qsfp1_tx_prbs31_enable_3, + input wire qsfp1_rx_clk_3, + input wire qsfp1_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3, + output wire qsfp1_rx_prbs31_enable_3, + input wire [6:0] qsfp1_rx_error_count_3, + input wire qsfp1_rx_status_3, + input wire qsfp1_tx_clk_4, + input wire qsfp1_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4, + output wire qsfp1_tx_prbs31_enable_4, + input wire qsfp1_rx_clk_4, + input wire qsfp1_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4, + output wire qsfp1_rx_prbs31_enable_4, + input wire [6:0] qsfp1_rx_error_count_4, + input wire qsfp1_rx_status_4, + + input wire qsfp2_tx_clk_1, + input wire qsfp2_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1, + output wire qsfp2_tx_prbs31_enable_1, + input wire qsfp2_rx_clk_1, + input wire qsfp2_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1, + output wire qsfp2_rx_prbs31_enable_1, + input wire [6:0] qsfp2_rx_error_count_1, + input wire qsfp2_rx_status_1, + input wire qsfp2_tx_clk_2, + input wire qsfp2_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2, + output wire qsfp2_tx_prbs31_enable_2, + input wire qsfp2_rx_clk_2, + input wire qsfp2_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2, + output wire qsfp2_rx_prbs31_enable_2, + input wire [6:0] qsfp2_rx_error_count_2, + input wire qsfp2_rx_status_2, + input wire qsfp2_tx_clk_3, + input wire qsfp2_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3, + output wire qsfp2_tx_prbs31_enable_3, + input wire qsfp2_rx_clk_3, + input wire qsfp2_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3, + output wire qsfp2_rx_prbs31_enable_3, + input wire [6:0] qsfp2_rx_error_count_3, + input wire qsfp2_rx_status_3, + input wire qsfp2_tx_clk_4, + input wire qsfp2_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4, + output wire qsfp2_tx_prbs31_enable_4, + input wire qsfp2_rx_clk_4, + input wire qsfp2_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4, + output wire qsfp2_rx_prbs31_enable_4, + input wire [6:0] qsfp2_rx_error_count_4, + input wire qsfp2_rx_status_4, + + input wire qsfp3_tx_clk_1, + input wire qsfp3_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1, + output wire qsfp3_tx_prbs31_enable_1, + input wire qsfp3_rx_clk_1, + input wire qsfp3_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1, + output wire qsfp3_rx_prbs31_enable_1, + input wire [6:0] qsfp3_rx_error_count_1, + input wire qsfp3_rx_status_1, + input wire qsfp3_tx_clk_2, + input wire qsfp3_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2, + output wire qsfp3_tx_prbs31_enable_2, + input wire qsfp3_rx_clk_2, + input wire qsfp3_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2, + output wire qsfp3_rx_prbs31_enable_2, + input wire [6:0] qsfp3_rx_error_count_2, + input wire qsfp3_rx_status_2, + input wire qsfp3_tx_clk_3, + input wire qsfp3_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3, + output wire qsfp3_tx_prbs31_enable_3, + input wire qsfp3_rx_clk_3, + input wire qsfp3_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3, + output wire qsfp3_rx_prbs31_enable_3, + input wire [6:0] qsfp3_rx_error_count_3, + input wire qsfp3_rx_status_3, + input wire qsfp3_tx_clk_4, + input wire qsfp3_tx_rst_4, + output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4, + output wire qsfp3_tx_prbs31_enable_4, + input wire qsfp3_rx_clk_4, + input wire qsfp3_rx_rst_4, + input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4, + output wire qsfp3_rx_prbs31_enable_4, + input wire [6:0] qsfp3_rx_error_count_4, + input wire qsfp3_rx_status_4 +); + +parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; + +parameter F_COUNT = PF_COUNT+VF_COUNT; + +parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); +parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); +parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); + +localparam RB_BASE_ADDR = 16'h1000; +localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; + +initial begin + if (PORT_COUNT > 8) begin + $error("Error: Max port count exceeded (instance %m)"); + $finish; + end +end + +// AXI lite connections +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; +wire [2:0] axil_csr_awprot; +wire axil_csr_awvalid; +wire axil_csr_awready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; +wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; +wire axil_csr_wvalid; +wire axil_csr_wready; +wire [1:0] axil_csr_bresp; +wire axil_csr_bvalid; +wire axil_csr_bready; +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; +wire [2:0] axil_csr_arprot; +wire axil_csr_arvalid; +wire axil_csr_arready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; +wire [1:0] axil_csr_rresp; +wire axil_csr_rvalid; +wire axil_csr_rready; + +// PTP +wire [PTP_TS_WIDTH-1:0] ptp_ts_96; +wire ptp_ts_step; +wire ptp_pps; +wire ptp_pps_str; +wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; +wire ptp_sync_ts_step; +wire ptp_sync_pps; + +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; + +// control registers +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; +wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; +wire ctrl_reg_wr_en; +wire ctrl_reg_wr_wait; +wire ctrl_reg_wr_ack; +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; +wire ctrl_reg_rd_en; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; +wire ctrl_reg_rd_wait; +wire ctrl_reg_rd_ack; + +reg ctrl_reg_wr_ack_reg = 1'b0; +reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; +reg ctrl_reg_rd_ack_reg = 1'b0; + +reg fpga_i2c_scl_o_reg = 1'b1; +reg fpga_i2c_sda_o_reg = 1'b1; + +assign ctrl_reg_wr_wait = 1'b0; +assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg; +assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg; +assign ctrl_reg_rd_wait = 1'b0; +assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg; + +assign fpga_i2c_scl_o = fpga_i2c_scl_o_reg; +assign fpga_i2c_scl_t = fpga_i2c_scl_o_reg; +assign fpga_i2c_sda_o = fpga_i2c_sda_o_reg; +assign fpga_i2c_sda_t = fpga_i2c_sda_o_reg; +assign fpga_i2c_req_l = 1'b0; + +always @(posedge clk_250mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; + ctrl_reg_rd_ack_reg <= 1'b0; + + if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin + // write operation + ctrl_reg_wr_ack_reg <= 1'b0; + case ({ctrl_reg_wr_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h0C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + fpga_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + fpga_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + default: ctrl_reg_wr_ack_reg <= 1'b0; + endcase + end + + if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin + // read operation + ctrl_reg_rd_ack_reg <= 1'b1; + case ({ctrl_reg_rd_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h08: ctrl_reg_rd_data_reg <= 0; // I2C ctrl: Next header + RBB+8'h0C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= fpga_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= fpga_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= fpga_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= fpga_i2c_sda_o_reg; + end + default: ctrl_reg_rd_ack_reg <= 1'b0; + endcase + end + + if (rst_250mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_ack_reg <= 1'b0; + + fpga_i2c_scl_o_reg <= 1'b1; + fpga_i2c_sda_o_reg <= 1'b1; + end +end + +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(16), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(16)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp3_tx_prbs31_enable_4, qsfp3_tx_prbs31_enable_3, qsfp3_tx_prbs31_enable_2, qsfp3_tx_prbs31_enable_1, qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp3_rx_prbs31_enable_4, qsfp3_rx_prbs31_enable_3, qsfp3_rx_prbs31_enable_2, qsfp3_rx_prbs31_enable_1, qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + assign qsfp2_tx_prbs31_enable_1 = 1'b0; + assign qsfp2_rx_prbs31_enable_1 = 1'b0; + assign qsfp2_tx_prbs31_enable_2 = 1'b0; + assign qsfp2_rx_prbs31_enable_2 = 1'b0; + assign qsfp2_tx_prbs31_enable_3 = 1'b0; + assign qsfp2_rx_prbs31_enable_3 = 1'b0; + assign qsfp2_tx_prbs31_enable_4 = 1'b0; + assign qsfp2_rx_prbs31_enable_4 = 1'b0; + assign qsfp3_tx_prbs31_enable_1 = 1'b0; + assign qsfp3_rx_prbs31_enable_1 = 1'b0; + assign qsfp3_tx_prbs31_enable_2 = 1'b0; + assign qsfp3_rx_prbs31_enable_2 = 1'b0; + assign qsfp3_tx_prbs31_enable_3 = 1'b0; + assign qsfp3_rx_prbs31_enable_3 = 1'b0; + assign qsfp3_tx_prbs31_enable_4 = 1'b0; + assign qsfp3_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate + +assign led_user_grn[0] = 1'b1; +assign led_user_grn[1] = !ptp_pps_str; + +assign led_user_red[0] = 1'b1; +assign led_user_red[1] = 1'b1; + +assign led_qsfp[0] = 1'b1; +assign led_qsfp[1] = 1'b1; +assign led_qsfp[2] = 1'b1; +assign led_qsfp[3] = 1'b1; + +wire [PORT_COUNT-1:0] eth_tx_clk; +wire [PORT_COUNT-1:0] eth_tx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_tx_tready; +wire [PORT_COUNT-1:0] axis_eth_tx_tlast; +wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; +wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; + +wire [PORT_COUNT-1:0] eth_tx_status; + +wire [PORT_COUNT-1:0] eth_rx_clk; +wire [PORT_COUNT-1:0] eth_rx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_rx_tready; +wire [PORT_COUNT-1:0] axis_eth_rx_tlast; +wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; + +wire [PORT_COUNT-1:0] eth_rx_status; + +wire [PORT_COUNT-1:0] port_xgmii_tx_clk; +wire [PORT_COUNT-1:0] port_xgmii_tx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; + +wire [PORT_COUNT-1:0] port_xgmii_rx_clk; +wire [PORT_COUNT-1:0] port_xgmii_rx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; + +mqnic_port_map_phy_xgmii #( + .PHY_COUNT(16), + .PORT_MASK(PORT_MASK), + .PORT_GROUP_SIZE(4), + + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) +) +mqnic_port_map_phy_xgmii_inst ( + // towards PHY + .phy_xgmii_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_xgmii_tx_rst({qsfp3_tx_rst_4, qsfp3_tx_rst_3, qsfp3_tx_rst_2, qsfp3_tx_rst_1, qsfp2_tx_rst_4, qsfp2_tx_rst_3, qsfp2_tx_rst_2, qsfp2_tx_rst_1, qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}), + .phy_xgmii_txd({qsfp3_txd_4, qsfp3_txd_3, qsfp3_txd_2, qsfp3_txd_1, qsfp2_txd_4, qsfp2_txd_3, qsfp2_txd_2, qsfp2_txd_1, qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}), + .phy_xgmii_txc({qsfp3_txc_4, qsfp3_txc_3, qsfp3_txc_2, qsfp3_txc_1, qsfp2_txc_4, qsfp2_txc_3, qsfp2_txc_2, qsfp2_txc_1, qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}), + .phy_tx_status(16'hffff), + + .phy_xgmii_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_xgmii_rx_rst({qsfp3_rx_rst_4, qsfp3_rx_rst_3, qsfp3_rx_rst_2, qsfp3_rx_rst_1, qsfp2_rx_rst_4, qsfp2_rx_rst_3, qsfp2_rx_rst_2, qsfp2_rx_rst_1, qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}), + .phy_xgmii_rxd({qsfp3_rxd_4, qsfp3_rxd_3, qsfp3_rxd_2, qsfp3_rxd_1, qsfp2_rxd_4, qsfp2_rxd_3, qsfp2_rxd_2, qsfp2_rxd_1, qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}), + .phy_xgmii_rxc({qsfp3_rxc_4, qsfp3_rxc_3, qsfp3_rxc_2, qsfp3_rxc_1, qsfp2_rxc_4, qsfp2_rxc_3, qsfp2_rxc_2, qsfp2_rxc_1, qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}), + .phy_rx_status({qsfp3_rx_status_4, qsfp3_rx_status_3, qsfp3_rx_status_2, qsfp3_rx_status_1, qsfp2_rx_status_4, qsfp2_rx_status_3, qsfp2_rx_status_2, qsfp2_rx_status_1, qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}), + + // towards MAC + .port_xgmii_tx_clk(port_xgmii_tx_clk), + .port_xgmii_tx_rst(port_xgmii_tx_rst), + .port_xgmii_txd(port_xgmii_txd), + .port_xgmii_txc(port_xgmii_txc), + .port_tx_status(eth_tx_status), + + .port_xgmii_rx_clk(port_xgmii_rx_clk), + .port_xgmii_rx_rst(port_xgmii_rx_rst), + .port_xgmii_rxd(port_xgmii_rxd), + .port_xgmii_rxc(port_xgmii_rxc), + .port_rx_status(eth_rx_status) +); + +generate + genvar n; + + for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac + + assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; + assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; + assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; + assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; + + eth_mac_10g #( + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), + .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + eth_mac_inst ( + .tx_clk(port_xgmii_tx_clk[n]), + .tx_rst(port_xgmii_tx_rst[n]), + .rx_clk(port_xgmii_rx_clk[n]), + .rx_rst(port_xgmii_rx_rst[n]), + + .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), + .tx_axis_tready(axis_eth_tx_tready[n +: 1]), + .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), + .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), + + .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), + .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), + .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), + + .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + + .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), + + .tx_error_underflow(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + + .ifg_delay(8'd12) + ); + + end + +endgenerate + +mqnic_core_pcie_s10 #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_SEPARATE_TX_CLOCK(0), + .PTP_SEPARATE_RX_CLOCK(0), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), + .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), + .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), + .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + .APP_GPIO_IN_WIDTH(32), + .APP_GPIO_OUT_WIDTH(32), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH), + .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), + .TX_SEQ_NUM_ENABLE(1), + .L_TILE(0), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .F_COUNT(F_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), + .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .AXIL_CSR_PASSTHROUGH_ENABLE(0), + .RB_NEXT_PTR(RB_BASE_ADDR), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_RX_USE_READY(0), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * H-Tile/L-Tile RX AVST interface + */ + .rx_st_data(rx_st_data), + .rx_st_empty(rx_st_empty), + .rx_st_sop(rx_st_sop), + .rx_st_eop(rx_st_eop), + .rx_st_valid(rx_st_valid), + .rx_st_ready(rx_st_ready), + .rx_st_vf_active(rx_st_vf_active), + .rx_st_func_num(rx_st_func_num), + .rx_st_vf_num(rx_st_vf_num), + .rx_st_bar_range(rx_st_bar_range), + + /* + * H-Tile/L-Tile TX AVST interface + */ + .tx_st_data(tx_st_data), + .tx_st_sop(tx_st_sop), + .tx_st_eop(tx_st_eop), + .tx_st_valid(tx_st_valid), + .tx_st_ready(tx_st_ready), + .tx_st_err(tx_st_err), + + /* + * H-Tile/L-Tile TX flow control + */ + .tx_ph_cdts(tx_ph_cdts), + .tx_pd_cdts(tx_pd_cdts), + .tx_nph_cdts(tx_nph_cdts), + .tx_npd_cdts(tx_npd_cdts), + .tx_cplh_cdts(tx_cplh_cdts), + .tx_cpld_cdts(tx_cpld_cdts), + .tx_hdr_cdts_consumed(tx_hdr_cdts_consumed), + .tx_data_cdts_consumed(tx_data_cdts_consumed), + .tx_cdts_type(tx_cdts_type), + .tx_cdts_data_value(tx_cdts_data_value), + + /* + * H-Tile/L-Tile configuration interface + */ + .tl_cfg_ctl(tl_cfg_ctl), + .tl_cfg_add(tl_cfg_add), + .tl_cfg_func(tl_cfg_func), + + /* + * AXI-Lite master interface (passthrough for NIC control and status) + */ + .m_axil_csr_awaddr(axil_csr_awaddr), + .m_axil_csr_awprot(axil_csr_awprot), + .m_axil_csr_awvalid(axil_csr_awvalid), + .m_axil_csr_awready(axil_csr_awready), + .m_axil_csr_wdata(axil_csr_wdata), + .m_axil_csr_wstrb(axil_csr_wstrb), + .m_axil_csr_wvalid(axil_csr_wvalid), + .m_axil_csr_wready(axil_csr_wready), + .m_axil_csr_bresp(axil_csr_bresp), + .m_axil_csr_bvalid(axil_csr_bvalid), + .m_axil_csr_bready(axil_csr_bready), + .m_axil_csr_araddr(axil_csr_araddr), + .m_axil_csr_arprot(axil_csr_arprot), + .m_axil_csr_arvalid(axil_csr_arvalid), + .m_axil_csr_arready(axil_csr_arready), + .m_axil_csr_rdata(axil_csr_rdata), + .m_axil_csr_rresp(axil_csr_rresp), + .m_axil_csr_rvalid(axil_csr_rvalid), + .m_axil_csr_rready(axil_csr_rready), + + /* + * Control register interface + */ + .ctrl_reg_wr_addr(ctrl_reg_wr_addr), + .ctrl_reg_wr_data(ctrl_reg_wr_data), + .ctrl_reg_wr_strb(ctrl_reg_wr_strb), + .ctrl_reg_wr_en(ctrl_reg_wr_en), + .ctrl_reg_wr_wait(ctrl_reg_wr_wait), + .ctrl_reg_wr_ack(ctrl_reg_wr_ack), + .ctrl_reg_rd_addr(ctrl_reg_rd_addr), + .ctrl_reg_rd_en(ctrl_reg_rd_en), + .ctrl_reg_rd_data(ctrl_reg_rd_data), + .ctrl_reg_rd_wait(ctrl_reg_rd_wait), + .ctrl_reg_rd_ack(ctrl_reg_rd_ack), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + .ptp_sync_pps(ptp_sync_pps), + .ptp_sync_ts_96(ptp_sync_ts_96), + .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_perout_locked(ptp_perout_locked), + .ptp_perout_error(ptp_perout_error), + .ptp_perout_pulse(ptp_perout_pulse), + + /* + * Ethernet + */ + .eth_tx_clk(eth_tx_clk), + .eth_tx_rst(eth_tx_rst), + + .eth_tx_ptp_clk(0), + .eth_tx_ptp_rst(0), + .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), + .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + + .m_axis_eth_tx_tdata(axis_eth_tx_tdata), + .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), + .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), + .m_axis_eth_tx_tready(axis_eth_tx_tready), + .m_axis_eth_tx_tlast(axis_eth_tx_tlast), + .m_axis_eth_tx_tuser(axis_eth_tx_tuser), + + .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), + .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), + .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), + .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), + + .eth_tx_status(eth_tx_status), + + .eth_rx_clk(eth_rx_clk), + .eth_rx_rst(eth_rx_rst), + + .eth_rx_ptp_clk(0), + .eth_rx_ptp_rst(0), + .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), + .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + + .s_axis_eth_rx_tdata(axis_eth_rx_tdata), + .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), + .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), + .s_axis_eth_rx_tready(axis_eth_rx_tready), + .s_axis_eth_rx_tlast(axis_eth_rx_tlast), + .s_axis_eth_rx_tuser(axis_eth_rx_tuser), + + .eth_rx_status(eth_rx_status), + + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + + /* + * Statistics input + */ + .s_axis_stat_tdata(0), + .s_axis_stat_tid(0), + .s_axis_stat_tvalid(1'b0), + .s_axis_stat_tready(), + + /* + * GPIO + */ + .app_gpio_in(0), + .app_gpio_out(), + + /* + * JTAG + */ + .app_jtag_tdi(1'b0), + .app_jtag_tdo(), + .app_jtag_tms(1'b0), + .app_jtag_tck(1'b0) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/sync_signal.v new file mode 100644 index 000000000..74b855fa1 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/sync_signal.v @@ -0,0 +1,62 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule + +`resetall diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile new file mode 100644 index 000000000..789eea280 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile @@ -0,0 +1,285 @@ +# Copyright 2020-2023, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_s10.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v +VERILOG_SOURCES += ../../rtl/common/cpl_write.v +VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v +VERILOG_SOURCES += ../../rtl/common/desc_fetch.v +VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/event_mux.v +VERILOG_SOURCES += ../../rtl/common/queue_manager.v +VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v +VERILOG_SOURCES += ../../rtl/common/tx_engine.v +VERILOG_SOURCES += ../../rtl/common/rx_engine.v +VERILOG_SOURCES += ../../rtl/common/tx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rx_hash.v +VERILOG_SOURCES += ../../rtl/common/rx_checksum.v +VERILOG_SOURCES += ../../rtl/common/stats_counter.v +VERILOG_SOURCES += ../../rtl/common/stats_collect.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v +VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fc_count.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_rx.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_tx.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_cfg.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v + +# module parameters + +# Structural configuration +export PARAM_IF_COUNT := 2 +export PARAM_PORTS_PER_IF := 1 +export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) +export PARAM_PORT_MASK := 0 + +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM := 4 +export PARAM_CLK_PERIOD_NS_DENOM := 1 + +# PTP configuration +export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 +export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 +export PARAM_PTP_CLOCK_PIPELINE := 0 +export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 +export PARAM_PTP_USE_SAMPLE_CLOCK := 1 +export PARAM_PTP_PORT_CDC_PIPELINE := 0 +export PARAM_PTP_PEROUT_ENABLE := 1 +export PARAM_PTP_PEROUT_COUNT := 1 + +# Queue manager configuration +export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) +export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) +export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_TX_QUEUE_INDEX_WIDTH := 13 +export PARAM_RX_QUEUE_INDEX_WIDTH := 8 +export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) +export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) +export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) + +# TX and RX engine configuration +export PARAM_TX_DESC_TABLE_SIZE := 32 +export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") + +# Scheduler configuration +export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) +export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_TDMA_INDEX_WIDTH := 6 + +# Interface configuration +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_TX_CPL_FIFO_DEPTH := 32 +export PARAM_TX_CHECKSUM_ENABLE := 1 +export PARAM_RX_HASH_ENABLE := 1 +export PARAM_RX_CHECKSUM_ENABLE := 1 +export PARAM_TX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_MAX_TX_SIZE := 9214 +export PARAM_MAX_RX_SIZE := 9214 +export PARAM_TX_RAM_SIZE := 32768 +export PARAM_RX_RAM_SIZE := 32768 + +# Application block configuration +export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) +export PARAM_APP_ENABLE := 0 +export PARAM_APP_CTRL_ENABLE := 1 +export PARAM_APP_DMA_ENABLE := 1 +export PARAM_APP_AXIS_DIRECT_ENABLE := 1 +export PARAM_APP_AXIS_SYNC_ENABLE := 1 +export PARAM_APP_AXIS_IF_ENABLE := 1 +export PARAM_APP_STAT_ENABLE := 1 + +# DMA interface configuration +export PARAM_DMA_IMM_ENABLE := 0 +export PARAM_DMA_IMM_WIDTH := 32 +export PARAM_DMA_LEN_WIDTH := 16 +export PARAM_DMA_TAG_WIDTH := 16 +export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") +export PARAM_RAM_PIPELINE := 2 + +# PCIe interface configuration +export PARAM_SEG_COUNT := 1 +export PARAM_SEG_DATA_WIDTH := 256 +export PARAM_PF_COUNT := 1 +export PARAM_VF_COUNT := 0 + +# Interrupt configuration +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_WIDTH := 32 +export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 + +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 + +# Ethernet interface configuration +export PARAM_AXIS_ETH_TX_PIPELINE := 0 +export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2 +export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0 +export PARAM_AXIS_ETH_RX_PIPELINE := 0 +export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2 + +# Statistics counter subsystem +export PARAM_STAT_ENABLE := 1 +export PARAM_STAT_DMA_ENABLE := 1 +export PARAM_STAT_PCIE_ENABLE := 1 +export PARAM_STAT_INC_WIDTH := 24 +export PARAM_STAT_ID_WIDTH := 12 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/mqnic.py new file mode 120000 index 000000000..dfa8522e7 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/mqnic.py @@ -0,0 +1 @@ +../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..30a732304 --- /dev/null +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,934 @@ +""" + +Copyright 2020-2023, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +""" + +import logging +import os +import sys + +import scapy.utils +from scapy.layers.l2 import Ether +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer + +from cocotbext.eth import XgmiiSource, XgmiiSink +from cocotbext.pcie.core import RootComplex +from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus + +try: + import mqnic +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + import mqnic + finally: + del sys.path[0] + + +class TB(object): + def __init__(self, dut, msix_count=32): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # PCIe + self.rc = RootComplex() + + self.rc.max_payload_size = 0x1 # 256 bytes + self.rc.max_read_request_size = 0x2 # 512 bytes + + self.dev = S10PcieDevice( + # configuration options + pcie_generation=3, + pcie_link_width=8, + pld_clk_frequency=250e6, + l_tile=False, + pf_count=1, + max_payload_size=1024, + enable_extended_tag=True, + + pf0_msi_enable=False, + pf0_msi_count=32, + pf1_msi_enable=False, + pf1_msi_count=1, + pf2_msi_enable=False, + pf2_msi_count=1, + pf3_msi_enable=False, + pf3_msi_count=1, + pf0_msix_enable=True, + pf0_msix_table_size=msix_count-1, + pf0_msix_table_bir=0, + pf0_msix_table_offset=0x00010000, + pf0_msix_pba_bir=0, + pf0_msix_pba_offset=0x00018000, + pf1_msix_enable=False, + pf1_msix_table_size=0, + pf1_msix_table_bir=0, + pf1_msix_table_offset=0x00000000, + pf1_msix_pba_bir=0, + pf1_msix_pba_offset=0x00000000, + pf2_msix_enable=False, + pf2_msix_table_size=0, + pf2_msix_table_bir=0, + pf2_msix_table_offset=0x00000000, + pf2_msix_pba_bir=0, + pf2_msix_pba_offset=0x00000000, + pf3_msix_enable=False, + pf3_msix_table_size=0, + pf3_msix_table_bir=0, + pf3_msix_table_offset=0x00000000, + pf3_msix_pba_bir=0, + pf3_msix_pba_offset=0x00000000, + + # signals + # Clock and reset + # npor=dut.npor, + # pin_perst=dut.pin_perst, + # ninit_done=dut.ninit_done, + # pld_clk_inuse=dut.pld_clk_inuse, + # pld_core_ready=dut.pld_core_ready, + reset_status=dut.rst_250mhz, + # clr_st=dut.clr_st, + # refclk=dut.refclk, + coreclkout_hip=dut.clk_250mhz, + + # RX interface + rx_bus=S10RxBus.from_prefix(dut, "rx_st"), + + # TX interface + tx_bus=S10TxBus.from_prefix(dut, "tx_st"), + + # TX flow control + tx_ph_cdts=dut.tx_ph_cdts, + tx_pd_cdts=dut.tx_pd_cdts, + tx_nph_cdts=dut.tx_nph_cdts, + tx_npd_cdts=dut.tx_npd_cdts, + tx_cplh_cdts=dut.tx_cplh_cdts, + tx_cpld_cdts=dut.tx_cpld_cdts, + tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed, + tx_data_cdts_consumed=dut.tx_data_cdts_consumed, + tx_cdts_type=dut.tx_cdts_type, + tx_cdts_data_value=dut.tx_cdts_data_value, + + # Hard IP status + # int_status=dut.int_status, + # int_status_common=dut.int_status_common, + # derr_cor_ext_rpl=dut.derr_cor_ext_rpl, + # derr_rpl=dut.derr_rpl, + # derr_cor_ext_rcv=dut.derr_cor_ext_rcv, + # derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv, + # rx_par_err=dut.rx_par_err, + # tx_par_err=dut.tx_par_err, + # ltssmstate=dut.ltssmstate, + # link_up=dut.link_up, + # lane_act=dut.lane_act, + # currentspeed=dut.currentspeed, + + # Power management + # pm_linkst_in_l1=dut.pm_linkst_in_l1, + # pm_linkst_in_l0s=dut.pm_linkst_in_l0s, + # pm_state=dut.pm_state, + # pm_dstate=dut.pm_dstate, + # apps_pm_xmt_pme=dut.apps_pm_xmt_pme, + # apps_ready_entr_l23=dut.apps_ready_entr_l23, + # apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff, + # app_init_rst=dut.app_init_rst, + # app_xfer_pending=dut.app_xfer_pending, + + # Interrupt interface + # app_msi_req=dut.app_msi_req, + # app_msi_ack=dut.app_msi_ack, + # app_msi_tc=dut.app_msi_tc, + # app_msi_num=dut.app_msi_num, + # app_msi_func_num=dut.app_msi_func_num, + # app_int_sts=dut.app_int_sts, + + # Error interface + # app_err_valid=dut.app_err_valid, + # app_err_hdr=dut.app_err_hdr, + # app_err_info=dut.app_err_info, + # app_err_func_num=dut.app_err_func_num, + + # Configuration output + tl_cfg_func=dut.tl_cfg_func, + tl_cfg_add=dut.tl_cfg_add, + tl_cfg_ctl=dut.tl_cfg_ctl, + + # Configuration extension bus + # ceb_req=dut.ceb_req, + # ceb_ack=dut.ceb_ack, + # ceb_addr=dut.ceb_addr, + # ceb_din=dut.ceb_din, + # ceb_dout=dut.ceb_dout, + # ceb_wr=dut.ceb_wr, + # ceb_cdm_convert_data=dut.ceb_cdm_convert_data, + # ceb_func_num=dut.ceb_func_num, + # ceb_vf_num=dut.ceb_vf_num, + # ceb_vf_active=dut.ceb_vf_active, + + # Hard IP reconfiguration interface + # hip_reconfig_clk=dut.hip_reconfig_clk, + # hip_reconfig_address=dut.hip_reconfig_address, + # hip_reconfig_read=dut.hip_reconfig_read, + # hip_reconfig_readdata=dut.hip_reconfig_readdata, + # hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid, + # hip_reconfig_write=dut.hip_reconfig_write, + # hip_reconfig_writedata=dut.hip_reconfig_writedata, + # hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest, + ) + + # self.dev.log.setLevel(logging.DEBUG) + + self.rc.make_port().connect(self.dev) + + self.driver = mqnic.Driver() + + self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + + cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) + dut.ptp_rst.setimmediatevalue(0) + cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) + + # Ethernet + cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 2.56, units="ns").start()) + self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 2.56, units="ns").start()) + self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 2.56, units="ns").start()) + self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 2.56, units="ns").start()) + self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 2.56, units="ns").start()) + self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 2.56, units="ns").start()) + self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 2.56, units="ns").start()) + self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 2.56, units="ns").start()) + self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 2.56, units="ns").start()) + self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 2.56, units="ns").start()) + self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 2.56, units="ns").start()) + self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 2.56, units="ns").start()) + self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 2.56, units="ns").start()) + self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 2.56, units="ns").start()) + self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 2.56, units="ns").start()) + self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start()) + self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp2_rx_clk_1, 2.56, units="ns").start()) + self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp2_tx_clk_1, 2.56, units="ns").start()) + self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp2_rx_clk_2, 2.56, units="ns").start()) + self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp2_tx_clk_2, 2.56, units="ns").start()) + self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp2_rx_clk_3, 2.56, units="ns").start()) + self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp2_tx_clk_3, 2.56, units="ns").start()) + self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp2_rx_clk_4, 2.56, units="ns").start()) + self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 2.56, units="ns").start()) + self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4) + + cocotb.start_soon(Clock(dut.qsfp3_rx_clk_1, 2.56, units="ns").start()) + self.qsfp3_1_source = XgmiiSource(dut.qsfp3_rxd_1, dut.qsfp3_rxc_1, dut.qsfp3_rx_clk_1, dut.qsfp3_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp3_tx_clk_1, 2.56, units="ns").start()) + self.qsfp3_1_sink = XgmiiSink(dut.qsfp3_txd_1, dut.qsfp3_txc_1, dut.qsfp3_tx_clk_1, dut.qsfp3_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp3_rx_clk_2, 2.56, units="ns").start()) + self.qsfp3_2_source = XgmiiSource(dut.qsfp3_rxd_2, dut.qsfp3_rxc_2, dut.qsfp3_rx_clk_2, dut.qsfp3_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp3_tx_clk_2, 2.56, units="ns").start()) + self.qsfp3_2_sink = XgmiiSink(dut.qsfp3_txd_2, dut.qsfp3_txc_2, dut.qsfp3_tx_clk_2, dut.qsfp3_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp3_rx_clk_3, 2.56, units="ns").start()) + self.qsfp3_3_source = XgmiiSource(dut.qsfp3_rxd_3, dut.qsfp3_rxc_3, dut.qsfp3_rx_clk_3, dut.qsfp3_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp3_tx_clk_3, 2.56, units="ns").start()) + self.qsfp3_3_sink = XgmiiSink(dut.qsfp3_txd_3, dut.qsfp3_txc_3, dut.qsfp3_tx_clk_3, dut.qsfp3_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp3_rx_clk_4, 2.56, units="ns").start()) + self.qsfp3_4_source = XgmiiSource(dut.qsfp3_rxd_4, dut.qsfp3_rxc_4, dut.qsfp3_rx_clk_4, dut.qsfp3_rx_rst_4) + cocotb.start_soon(Clock(dut.qsfp3_tx_clk_4, 2.56, units="ns").start()) + self.qsfp3_4_sink = XgmiiSink(dut.qsfp3_txd_4, dut.qsfp3_txc_4, dut.qsfp3_tx_clk_4, dut.qsfp3_tx_rst_4) + + dut.qsfp0_rx_status_1.setimmediatevalue(1) + dut.qsfp0_rx_status_2.setimmediatevalue(1) + dut.qsfp0_rx_status_3.setimmediatevalue(1) + dut.qsfp0_rx_status_4.setimmediatevalue(1) + + dut.qsfp1_rx_status_1.setimmediatevalue(1) + dut.qsfp1_rx_status_2.setimmediatevalue(1) + dut.qsfp1_rx_status_3.setimmediatevalue(1) + dut.qsfp1_rx_status_4.setimmediatevalue(1) + + dut.qsfp2_rx_status_1.setimmediatevalue(1) + dut.qsfp2_rx_status_2.setimmediatevalue(1) + dut.qsfp2_rx_status_3.setimmediatevalue(1) + dut.qsfp2_rx_status_4.setimmediatevalue(1) + + dut.qsfp3_rx_status_1.setimmediatevalue(1) + dut.qsfp3_rx_status_2.setimmediatevalue(1) + dut.qsfp3_rx_status_3.setimmediatevalue(1) + dut.qsfp3_rx_status_4.setimmediatevalue(1) + + dut.qsfp0_rx_error_count_1.setimmediatevalue(0) + dut.qsfp0_rx_error_count_2.setimmediatevalue(0) + dut.qsfp0_rx_error_count_3.setimmediatevalue(0) + dut.qsfp0_rx_error_count_4.setimmediatevalue(0) + + dut.qsfp1_rx_error_count_1.setimmediatevalue(0) + dut.qsfp1_rx_error_count_2.setimmediatevalue(0) + dut.qsfp1_rx_error_count_3.setimmediatevalue(0) + dut.qsfp1_rx_error_count_4.setimmediatevalue(0) + + dut.qsfp2_rx_error_count_1.setimmediatevalue(0) + dut.qsfp2_rx_error_count_2.setimmediatevalue(0) + dut.qsfp2_rx_error_count_3.setimmediatevalue(0) + dut.qsfp2_rx_error_count_4.setimmediatevalue(0) + + dut.qsfp3_rx_error_count_1.setimmediatevalue(0) + dut.qsfp3_rx_error_count_2.setimmediatevalue(0) + dut.qsfp3_rx_error_count_3.setimmediatevalue(0) + dut.qsfp3_rx_error_count_4.setimmediatevalue(0) + + dut.fpga_i2c_scl_i.setimmediatevalue(1) + dut.fpga_i2c_sda_i.setimmediatevalue(1) + dut.fpga_i2c_mux_gnt.setimmediatevalue(1) + + self.loopback_enable = False + cocotb.start_soon(self._run_loopback()) + + async def init(self): + + self.dut.ptp_rst.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_4.setimmediatevalue(0) + + await RisingEdge(self.dut.clk_250mhz) + await RisingEdge(self.dut.clk_250mhz) + + self.dut.ptp_rst.setimmediatevalue(1) + self.dut.qsfp0_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp0_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp0_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp0_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp0_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp0_tx_rst_3.setimmediatevalue(1) + self.dut.qsfp0_rx_rst_4.setimmediatevalue(1) + self.dut.qsfp0_tx_rst_4.setimmediatevalue(1) + self.dut.qsfp1_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp1_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp1_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp1_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp1_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp1_tx_rst_3.setimmediatevalue(1) + self.dut.qsfp1_rx_rst_4.setimmediatevalue(1) + self.dut.qsfp1_tx_rst_4.setimmediatevalue(1) + self.dut.qsfp2_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp2_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp2_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp2_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp2_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp2_tx_rst_3.setimmediatevalue(1) + self.dut.qsfp2_rx_rst_4.setimmediatevalue(1) + self.dut.qsfp2_tx_rst_4.setimmediatevalue(1) + self.dut.qsfp3_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp3_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp3_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp3_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp3_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp3_tx_rst_3.setimmediatevalue(1) + self.dut.qsfp3_rx_rst_4.setimmediatevalue(1) + self.dut.qsfp3_tx_rst_4.setimmediatevalue(1) + + await FallingEdge(self.dut.rst_250mhz) + await Timer(100, 'ns') + + await RisingEdge(self.dut.clk_250mhz) + await RisingEdge(self.dut.clk_250mhz) + + self.dut.ptp_rst.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp3_rx_rst_4.setimmediatevalue(0) + self.dut.qsfp3_tx_rst_4.setimmediatevalue(0) + + await self.rc.enumerate() + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.clk_250mhz) + + if self.loopback_enable: + if not self.qsfp0_1_sink.empty(): + await self.qsfp0_1_source.send(await self.qsfp0_1_sink.recv()) + if not self.qsfp0_2_sink.empty(): + await self.qsfp0_2_source.send(await self.qsfp0_2_sink.recv()) + if not self.qsfp0_3_sink.empty(): + await self.qsfp0_3_source.send(await self.qsfp0_3_sink.recv()) + if not self.qsfp0_4_sink.empty(): + await self.qsfp0_4_source.send(await self.qsfp0_4_sink.recv()) + if not self.qsfp1_1_sink.empty(): + await self.qsfp1_1_source.send(await self.qsfp1_1_sink.recv()) + if not self.qsfp1_2_sink.empty(): + await self.qsfp1_2_source.send(await self.qsfp1_2_sink.recv()) + if not self.qsfp1_3_sink.empty(): + await self.qsfp1_3_source.send(await self.qsfp1_3_sink.recv()) + if not self.qsfp1_4_sink.empty(): + await self.qsfp1_4_source.send(await self.qsfp1_4_sink.recv()) + if not self.qsfp2_1_sink.empty(): + await self.qsfp2_1_source.send(await self.qsfp2_1_sink.recv()) + if not self.qsfp2_2_sink.empty(): + await self.qsfp2_2_source.send(await self.qsfp2_2_sink.recv()) + if not self.qsfp2_3_sink.empty(): + await self.qsfp2_3_source.send(await self.qsfp2_3_sink.recv()) + if not self.qsfp2_4_sink.empty(): + await self.qsfp2_4_source.send(await self.qsfp2_4_sink.recv()) + if not self.qsfp3_1_sink.empty(): + await self.qsfp3_1_source.send(await self.qsfp3_1_sink.recv()) + if not self.qsfp3_2_sink.empty(): + await self.qsfp3_2_source.send(await self.qsfp3_2_sink.recv()) + if not self.qsfp3_3_sink.empty(): + await self.qsfp3_3_source.send(await self.qsfp3_3_sink.recv()) + if not self.qsfp3_4_sink.empty(): + await self.qsfp3_4_source.send(await self.qsfp3_4_sink.recv()) + + +@cocotb.test() +async def run_test_nic(dut): + + tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) + + await tb.init() + + tb.log.info("Init driver") + await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) + await tb.driver.interfaces[0].open() + # await tb.driver.interfaces[1].open() + + # enable queues + tb.log.info("Enable queues") + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) + for k in range(len(tb.driver.interfaces[0].txq)): + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) + + # wait for all writes to complete + await tb.driver.hw_regs.read_dword(0) + tb.log.info("Init complete") + + tb.log.info("Send and receive single packet") + + data = bytearray([x % 256 for x in range(1024)]) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.qsfp0_1_sink.recv() + tb.log.info("Packet: %s", pkt) + + await tb.qsfp0_1_source.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + # await tb.driver.interfaces[1].start_xmit(data, 0) + + # pkt = await tb.qsfp1_1_sink.recv() + # tb.log.info("Packet: %s", pkt) + + # await tb.qsfp1_1_source.send(pkt) + + # pkt = await tb.driver.interfaces[1].recv() + + # tb.log.info("Packet: %s", pkt) + # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.log.info("RX and TX checksum tests") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=2) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + pkt = await tb.qsfp0_1_sink.recv() + tb.log.info("Packet: %s", pkt) + + await tb.qsfp0_1_source.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert Ether(pkt.data).build() == test_pkt.build() + + tb.log.info("Queue mapping offset test") + + data = bytearray([x % 256 for x in range(1024)]) + + tb.loopback_enable = True + + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert pkt.queue == k + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) + + tb.log.info("Queue mapping RSS mask test") + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + + tb.loopback_enable = True + + queues = set() + + for k in range(64): + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=k+0) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + for k in range(64): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + queues.add(pkt.queue) + + assert len(queues) == 4 + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + await RisingEdge(dut.clk_250mhz) + await RisingEdge(dut.clk_250mhz) + + +# cocotb-test + +tests_dir = os.path.dirname(__file__) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) +axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) +pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(rtl_dir, "common", "mqnic_core_pcie_s10.v"), + os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_interface.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), + os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), + os.path.join(rtl_dir, "common", "cpl_write.v"), + os.path.join(rtl_dir, "common", "cpl_op_mux.v"), + os.path.join(rtl_dir, "common", "desc_fetch.v"), + os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "event_mux.v"), + os.path.join(rtl_dir, "common", "queue_manager.v"), + os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), + os.path.join(rtl_dir, "common", "tx_engine.v"), + os.path.join(rtl_dir, "common", "rx_engine.v"), + os.path.join(rtl_dir, "common", "tx_checksum.v"), + os.path.join(rtl_dir, "common", "rx_hash.v"), + os.path.join(rtl_dir, "common", "rx_checksum.v"), + os.path.join(rtl_dir, "common", "stats_counter.v"), + os.path.join(rtl_dir, "common", "stats_collect.v"), + os.path.join(rtl_dir, "common", "stats_pcie_if.v"), + os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), + os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), + os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), + os.path.join(rtl_dir, "common", "tdma_scheduler.v"), + os.path.join(rtl_dir, "common", "tdma_ber.v"), + os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "ptp_clock.v"), + os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_perout.v"), + os.path.join(axi_rtl_dir, "axil_interconnect.v"), + os.path.join(axi_rtl_dir, "axil_crossbar.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), + os.path.join(axi_rtl_dir, "axil_reg_if.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), + os.path.join(axi_rtl_dir, "axil_register_rd.v"), + os.path.join(axi_rtl_dir, "axil_register_wr.v"), + os.path.join(axi_rtl_dir, "arbiter.v"), + os.path.join(axi_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_adapter.v"), + os.path.join(axis_rtl_dir, "axis_arb_mux.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), + os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fc_count.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), + os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_psdpram.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_s10_if.v"), + os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"), + os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"), + os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"), + os.path.join(pcie_rtl_dir, "pulse_merge.v"), + ] + + parameters = {} + + # Structural configuration + parameters['IF_COUNT'] = 2 + parameters['PORTS_PER_IF'] = 1 + parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] + parameters['PORT_MASK'] = 0 + + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + + # PTP configuration + parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 + parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 + parameters['PTP_CLOCK_PIPELINE'] = 0 + parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 + parameters['PTP_USE_SAMPLE_CLOCK'] = 1 + parameters['PTP_PORT_CDC_PIPELINE'] = 0 + parameters['PTP_PEROUT_ENABLE'] = 1 + parameters['PTP_PEROUT_COUNT'] = 1 + + # Queue manager configuration + parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] + parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] + parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['TX_QUEUE_INDEX_WIDTH'] = 13 + parameters['RX_QUEUE_INDEX_WIDTH'] = 8 + parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] + parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] + parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + + # TX and RX engine configuration + parameters['TX_DESC_TABLE_SIZE'] = 32 + parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) + + # Scheduler configuration + parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] + parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['TDMA_INDEX_WIDTH'] = 6 + + # Interface configuration + parameters['PTP_TS_ENABLE'] = 1 + parameters['TX_CPL_FIFO_DEPTH'] = 32 + parameters['TX_CHECKSUM_ENABLE'] = 1 + parameters['RX_HASH_ENABLE'] = 1 + parameters['RX_CHECKSUM_ENABLE'] = 1 + parameters['TX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 32768 + parameters['MAX_TX_SIZE'] = 9214 + parameters['MAX_RX_SIZE'] = 9214 + parameters['TX_RAM_SIZE'] = 32768 + parameters['RX_RAM_SIZE'] = 32768 + + # Application block configuration + parameters['APP_ID'] = 0x00000000 + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + + # DMA interface configuration + parameters['DMA_IMM_ENABLE'] = 0 + parameters['DMA_IMM_WIDTH'] = 32 + parameters['DMA_LEN_WIDTH'] = 16 + parameters['DMA_TAG_WIDTH'] = 16 + parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() + parameters['RAM_PIPELINE'] = 2 + + # PCIe interface configuration + parameters['SEG_COUNT'] = 1 + parameters['SEG_DATA_WIDTH'] = 256 + parameters['PF_COUNT'] = 1 + parameters['VF_COUNT'] = 0 + + # Interrupt configuration + parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_WIDTH'] = 32 + parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 + + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + + # Ethernet interface configuration + parameters['AXIS_ETH_TX_PIPELINE'] = 0 + parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 + parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 + + # Statistics counter subsystem + parameters['STAT_ENABLE'] = 1 + parameters['STAT_DMA_ENABLE'] = 1 + parameters['STAT_PCIE_ENABLE'] = 1 + parameters['STAT_INC_WIDTH'] = 24 + parameters['STAT_ID_WIDTH'] = 12 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/modules/mqnic/mqnic_board.c b/modules/mqnic/mqnic_board.c index e8339a409..5b111b473 100644 --- a/modules/mqnic/mqnic_board.c +++ b/modules/mqnic/mqnic_board.c @@ -164,6 +164,31 @@ static int read_mac_from_eeprom_hex(struct mqnic_dev *mqnic, return 0; } +static int init_mac_list_from_eeprom(struct mqnic_dev *mqnic, + struct i2c_client *eeprom, int offset, int count) +{ + int ret, k; + char mac[ETH_ALEN]; + + count = min(count, MQNIC_MAX_IF); + + for (k = 0; k < count; k++) { + ret = read_mac_from_eeprom(mqnic, eeprom, offset + ETH_ALEN*k, mac); + if (ret < 0) + return ret; + + if (!is_valid_ether_addr(mac)) { + dev_warn(mqnic->dev, "MAC is not valid"); + return -1; + } + + memcpy(mqnic->mac_list[k], mac, ETH_ALEN); + mqnic->mac_count = k+1; + } + + return 0; +} + static int init_mac_list_from_eeprom_base(struct mqnic_dev *mqnic, struct i2c_client *eeprom, int offset, int count) { @@ -564,6 +589,48 @@ static int mqnic_generic_board_init(struct mqnic_dev *mqnic) // I2C EEPROM mqnic->eeprom_i2c_client = create_i2c_client(adapter, "24c16", 0x50); + break; + case MQNIC_BOARD_ID_520NMX: + // FPGA I2C + // TCA9548 0x72 + // CH0: OC_2 J22 + // CH1: OC_3 J23 + // CH2: OC_0 J26 + // CH3: OC_1 J27 + // CH4: QSFP_0 + // CH5: QSFP_1 + // CH6: QSFP_2 + // CH7: QSFP_3 + // EEPROM 0x57 + + request_module("at24"); + + // I2C adapter + adapter = mqnic_i2c_adapter_create(mqnic, 0); + + // TCA9548 I2C MUX + mux = create_i2c_client(adapter, "pca9548", 0x72); + + // QSFP0 + mqnic->mod_i2c_client[0] = create_i2c_client(get_i2c_mux_channel(mux, 4), "24c02", 0x50); + + // QSFP1 + mqnic->mod_i2c_client[1] = create_i2c_client(get_i2c_mux_channel(mux, 5), "24c02", 0x50); + + // QSFP2 + mqnic->mod_i2c_client[2] = create_i2c_client(get_i2c_mux_channel(mux, 6), "24c02", 0x50); + + // QSFP3 + mqnic->mod_i2c_client[3] = create_i2c_client(get_i2c_mux_channel(mux, 7), "24c02", 0x50); + + mqnic->mod_i2c_client_count = 4; + + // I2C EEPROM + mqnic->eeprom_i2c_client = create_i2c_client(adapter, "24c02", 0x57); + + // read MACs from EEPROM + init_mac_list_from_eeprom(mqnic, mqnic->eeprom_i2c_client, 0x4B, 16); + break; case MQNIC_BOARD_ID_XUPP3R: diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index d9e0a2fe1..c41b6e9e3 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -73,6 +73,7 @@ #define MQNIC_BOARD_ID_DK_DEV_AGF014EA 0x1172b00e #define MQNIC_BOARD_ID_DE10_AGILEX 0x1172b00a #define MQNIC_BOARD_ID_XUPP3R 0x12ba9823 +#define MQNIC_BOARD_ID_520NMX 0x198a0521 #define MQNIC_BOARD_ID_250SOC 0x198a250e #define MQNIC_BOARD_ID_FB4CGG3_VU9P 0x1c2c9403 #define MQNIC_BOARD_ID_FB2CG_KU15P 0x1c2ca00e