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Update DRP info

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This commit is contained in:
Alex Forencich 2022-03-02 23:12:02 -08:00
parent a54b673d54
commit 2cc3dbd5cc
2 changed files with 4 additions and 4 deletions
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4
fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v
View File

@ -768,7 +768,7 @@ bmc_spi_inst (
rb_drp #(
.DRP_ADDR_WIDTH(24),
.DRP_DATA_WIDTH(16),
.DRP_INFO({8'd0, 8'd0, 8'd0, 8'd4}),
.DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}),
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
@ -810,7 +810,7 @@ qsfp_0_rb_drp_inst (
rb_drp #(
.DRP_ADDR_WIDTH(24),
.DRP_DATA_WIDTH(16),
.DRP_INFO({8'd0, 8'd0, 8'd0, 8'd4}),
.DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}),
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),

4
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -768,7 +768,7 @@ bmc_spi_inst (
rb_drp #(
.DRP_ADDR_WIDTH(24),
.DRP_DATA_WIDTH(16),
.DRP_INFO({8'd0, 8'd0, 8'd0, 8'd4}),
.DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}),
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
@ -810,7 +810,7 @@ qsfp_0_rb_drp_inst (
rb_drp #(
.DRP_ADDR_WIDTH(24),
.DRP_DATA_WIDTH(16),
.DRP_INFO({8'd0, 8'd0, 8'd0, 8'd4}),
.DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}),
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),