diff --git a/rtl/dma_if_axi.v b/rtl/dma_if_axi.v index 582635ca1..4465485af 100644 --- a/rtl/dma_if_axi.v +++ b/rtl/dma_if_axi.v @@ -177,6 +177,12 @@ module dma_if_axi # input wire read_enable, input wire write_enable, + /* + * Status + */ + output wire status_rd_busy, + output wire status_wr_busy, + /* * Statistics */ @@ -285,6 +291,11 @@ dma_if_axi_rd_inst ( */ .enable(read_enable), + /* + * Status + */ + .status_busy(status_rd_busy), + /* * Statistics */ @@ -386,6 +397,11 @@ dma_if_axi_wr_inst ( */ .enable(write_enable), + /* + * Status + */ + .status_busy(status_wr_busy), + /* * Statistics */ diff --git a/rtl/dma_if_axi_rd.v b/rtl/dma_if_axi_rd.v index bdeb4b73d..b80e52328 100644 --- a/rtl/dma_if_axi_rd.v +++ b/rtl/dma_if_axi_rd.v @@ -122,6 +122,11 @@ module dma_if_axi_rd # */ input wire enable, + /* + * Status + */ + output wire status_busy, + /* * Statistics */ @@ -291,6 +296,10 @@ reg status_fifo_rd_finish_reg = 1'b0, status_fifo_rd_finish_next; reg [3:0] status_fifo_rd_error_reg = 4'd0, status_fifo_rd_error_next; reg status_fifo_rd_valid_reg = 1'b0, status_fifo_rd_valid_next; +reg [OP_TAG_WIDTH+1-1:0] active_op_count_reg = 0; +reg inc_active_op; +reg dec_active_op; + reg [AXI_DATA_WIDTH-1:0] m_axi_rdata_int_reg = {AXI_DATA_WIDTH{1'b0}}, m_axi_rdata_int_next; reg m_axi_rvalid_int_reg = 1'b0, m_axi_rvalid_int_next; @@ -306,6 +315,8 @@ reg [TAG_WIDTH-1:0] m_axis_read_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_ reg [3:0] m_axis_read_desc_status_error_reg = 4'd0, m_axis_read_desc_status_error_next; reg m_axis_read_desc_status_valid_reg = 1'b0, m_axis_read_desc_status_valid_next; +reg status_busy_reg = 1'b0; + reg [OP_TAG_WIDTH-1:0] stat_rd_op_start_tag_reg = 0, stat_rd_op_start_tag_next; reg [LEN_WIDTH-1:0] stat_rd_op_start_len_reg = 0, stat_rd_op_start_len_next; reg stat_rd_op_start_valid_reg = 1'b0, stat_rd_op_start_valid_next; @@ -349,6 +360,8 @@ assign m_axis_read_desc_status_tag = m_axis_read_desc_status_tag_reg; assign m_axis_read_desc_status_error = m_axis_read_desc_status_error_reg; assign m_axis_read_desc_status_valid = m_axis_read_desc_status_valid_reg; +assign status_busy = status_busy_reg; + assign stat_rd_op_start_tag = stat_rd_op_start_tag_reg; assign stat_rd_op_start_len = stat_rd_op_start_len_reg; assign stat_rd_op_start_valid = stat_rd_op_start_valid_reg; @@ -467,6 +480,8 @@ always @* begin op_table_start_last = 0; op_table_start_en = 1'b0; + inc_active_op = 1'b0; + // segmentation and request generation case (req_state_reg) REQ_STATE_IDLE: begin @@ -532,6 +547,7 @@ always @* begin op_table_start_cycle_count = (req_tr_count_next + (req_axi_addr_reg & OFFSET_MASK) - 1) >> AXI_BURST_SIZE; op_table_start_last = req_op_count_reg == req_tr_count_next; op_table_start_en = 1'b1; + inc_active_op = 1'b1; stat_rd_req_start_tag_next = op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]; stat_rd_req_start_len_next = req_zero_len_reg ? 0 : req_tr_count_reg; @@ -836,6 +852,7 @@ always @* begin // commit operations in-order op_table_finish_en = 1'b0; + dec_active_op = 1'b0; if (m_axis_read_desc_status_valid_reg) begin m_axis_read_desc_status_error_next = DMA_ERROR_NONE; @@ -852,6 +869,7 @@ always @* begin if (op_table_active[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_write_complete[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_finish_ptr_reg != op_table_start_ptr_reg) begin op_table_finish_en = 1'b1; + dec_active_op = 1'b1; if (op_table_error_a[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] != op_table_error_b[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin m_axis_read_desc_status_error_next = op_table_error_code[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]; @@ -910,6 +928,8 @@ always @(posedge clk) begin m_axis_read_desc_status_error_reg <= m_axis_read_desc_status_error_next; m_axis_read_desc_status_valid_reg <= m_axis_read_desc_status_valid_next; + status_busy_reg <= active_op_count_reg != 0; + stat_rd_op_start_tag_reg <= stat_rd_op_start_tag_next; stat_rd_op_start_len_reg <= stat_rd_op_start_len_next; stat_rd_op_start_valid_reg <= stat_rd_op_start_valid_next; @@ -947,6 +967,8 @@ always @(posedge clk) begin status_fifo_half_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**(STATUS_FIFO_ADDR_WIDTH-1); + active_op_count_reg <= active_op_count_reg + inc_active_op - dec_active_op; + if (op_table_start_en) begin op_table_start_ptr_reg <= op_table_start_ptr_reg + 1; op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b1; @@ -995,6 +1017,8 @@ always @(posedge clk) begin m_axis_read_desc_status_error_reg = 4'd0; m_axis_read_desc_status_valid_reg <= 1'b0; + status_busy_reg <= 1'b0; + stat_rd_op_start_tag_reg <= 0; stat_rd_op_start_valid_reg <= 1'b0; stat_rd_op_finish_tag_reg <= 0; @@ -1009,6 +1033,8 @@ always @(posedge clk) begin status_fifo_we_reg <= 1'b0; status_fifo_rd_valid_reg <= 1'b0; + active_op_count_reg <= 0; + op_table_start_ptr_reg <= 0; op_table_read_complete_ptr_reg <= 0; op_table_finish_ptr_reg <= 0; diff --git a/rtl/dma_if_axi_wr.v b/rtl/dma_if_axi_wr.v index f50cc2ea5..35e5c786a 100644 --- a/rtl/dma_if_axi_wr.v +++ b/rtl/dma_if_axi_wr.v @@ -131,6 +131,11 @@ module dma_if_axi_wr # */ input wire enable, + /* + * Status + */ + output wire status_busy, + /* * Statistics */ @@ -323,6 +328,10 @@ reg [RAM_SEG_COUNT-1:0] mask_fifo_wr_mask; wire mask_fifo_empty = mask_fifo_wr_ptr_reg == mask_fifo_rd_ptr_reg; wire mask_fifo_full = mask_fifo_wr_ptr_reg == (mask_fifo_rd_ptr_reg ^ (1 << MASK_FIFO_ADDR_WIDTH)); +reg [OP_TAG_WIDTH+1-1:0] active_op_count_reg = 0; +reg inc_active_op; +reg dec_active_op; + reg [AXI_ID_WIDTH-1:0] m_axi_awid_reg = {AXI_ID_WIDTH{1'b0}}, m_axi_awid_next; reg [AXI_ADDR_WIDTH-1:0] m_axi_awaddr_reg = {AXI_ADDR_WIDTH{1'b0}}, m_axi_awaddr_next; reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next; @@ -340,6 +349,8 @@ reg [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr_reg = 0, ram_rd_cmd_a reg [RAM_SEG_COUNT-1:0] ram_rd_cmd_valid_reg = 0, ram_rd_cmd_valid_next; reg [RAM_SEG_COUNT-1:0] ram_rd_resp_ready_cmb; +reg status_busy_reg = 1'b0; + reg [OP_TAG_WIDTH-1:0] stat_wr_op_start_tag_reg = 0, stat_wr_op_start_tag_next; reg [LEN_WIDTH-1:0] stat_wr_op_start_len_reg = 0, stat_wr_op_start_len_next; reg stat_wr_op_start_valid_reg = 1'b0, stat_wr_op_start_valid_next; @@ -384,6 +395,8 @@ assign ram_rd_cmd_addr = ram_rd_cmd_addr_reg; assign ram_rd_cmd_valid = ram_rd_cmd_valid_reg; assign ram_rd_resp_ready = ram_rd_resp_ready_cmb; +assign status_busy = status_busy_reg; + assign stat_wr_op_start_tag = stat_wr_op_start_tag_reg; assign stat_wr_op_start_len = stat_wr_op_start_len_reg; assign stat_wr_op_start_valid = stat_wr_op_start_valid_reg; @@ -506,6 +519,8 @@ always @* begin op_table_start_last = 0; op_table_start_en = 1'b0; + inc_active_op = 1'b0; + // TLP segmentation case (req_state_reg) REQ_STATE_IDLE: begin @@ -590,6 +605,7 @@ always @* begin op_table_start_tag = tag_reg; op_table_start_last = op_count_reg == tr_word_count_next; op_table_start_en = 1'b1; + inc_active_op = 1'b1; stat_wr_req_start_tag_next = op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]; stat_wr_req_start_len_next = zero_len_reg ? 0 : tr_word_count_next; @@ -955,9 +971,11 @@ always @* begin // commit operations in-order op_table_finish_en = 1'b0; + dec_active_op = 1'b0; if (op_table_active[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_write_complete[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_finish_ptr_reg != op_table_tx_finish_ptr_reg) begin op_table_finish_en = 1'b1; + dec_active_op = 1'b1; if (op_table_error_code[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] != DMA_ERROR_NONE) begin m_axis_write_desc_status_error_next = op_table_error_code[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]; @@ -975,12 +993,14 @@ always @* begin end else begin // accept write completions op_table_finish_en = 1'b0; + dec_active_op = 1'b0; stat_wr_req_finish_tag_next = op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]; m_axi_bready_next = 1'b1; if (m_axi_bready && m_axi_bvalid) begin op_table_finish_en = 1'b1; + dec_active_op = 1'b1; stat_wr_req_finish_valid_next = 1'b1; if (m_axi_bresp == AXI_RESP_SLVERR) begin @@ -1066,6 +1086,8 @@ always @(posedge clk) begin m_axis_write_desc_status_error_reg <= m_axis_write_desc_status_error_next; m_axis_write_desc_status_valid_reg <= m_axis_write_desc_status_valid_next; + status_busy_reg <= active_op_count_reg != 0; + stat_wr_op_start_tag_reg <= stat_wr_op_start_tag_next; stat_wr_op_start_len_reg <= stat_wr_op_start_len_next; stat_wr_op_start_valid_reg <= stat_wr_op_start_valid_next; @@ -1085,6 +1107,8 @@ always @(posedge clk) begin ram_rd_cmd_addr_reg <= ram_rd_cmd_addr_next; ram_rd_cmd_valid_reg <= ram_rd_cmd_valid_next; + active_op_count_reg <= active_op_count_reg + inc_active_op - dec_active_op; + if (mask_fifo_we) begin mask_fifo_mask[mask_fifo_wr_ptr_reg[MASK_FIFO_ADDR_WIDTH-1:0]] <= mask_fifo_wr_mask; mask_fifo_wr_ptr_reg <= mask_fifo_wr_ptr_reg + 1; @@ -1140,6 +1164,8 @@ always @(posedge clk) begin m_axis_write_desc_status_error_reg <= 4'd0; m_axis_write_desc_status_valid_reg <= 1'b0; + status_busy_reg <= 1'b0; + stat_wr_op_start_tag_reg <= 0; stat_wr_op_start_valid_reg <= 1'b0; stat_wr_op_finish_tag_reg <= 0; @@ -1151,6 +1177,8 @@ always @(posedge clk) begin ram_rd_cmd_valid_reg <= {RAM_SEG_COUNT{1'b0}}; + active_op_count_reg <= 0; + mask_fifo_wr_ptr_reg <= 0; mask_fifo_rd_ptr_reg <= 0; diff --git a/rtl/dma_if_pcie.v b/rtl/dma_if_pcie.v index e319f3897..afabbc8e1 100644 --- a/rtl/dma_if_pcie.v +++ b/rtl/dma_if_pcie.v @@ -198,6 +198,8 @@ module dma_if_pcie # /* * Status */ + output wire status_rd_busy, + output wire status_wr_busy, output wire status_error_cor, output wire status_error_uncor, @@ -331,6 +333,7 @@ dma_if_pcie_rd_inst ( /* * Status */ + .status_busy(status_rd_busy), .status_error_cor(status_error_cor), .status_error_uncor(status_error_uncor), @@ -439,6 +442,11 @@ dma_if_pcie_wr_inst ( .requester_id(requester_id), .max_payload_size(max_payload_size), + /* + * Status + */ + .status_busy(status_wr_busy), + /* * Statistics */ diff --git a/rtl/dma_if_pcie_rd.v b/rtl/dma_if_pcie_rd.v index 18dde339c..581accc01 100644 --- a/rtl/dma_if_pcie_rd.v +++ b/rtl/dma_if_pcie_rd.v @@ -145,6 +145,7 @@ module dma_if_pcie_rd # /* * Status */ + output wire status_busy, output wire status_error_cor, output wire status_error_uncor, @@ -402,6 +403,14 @@ reg [TX_COUNT_WIDTH-1:0] active_tx_count_reg = {TX_COUNT_WIDTH{1'b0}}, active_tx reg active_tx_count_av_reg = 1'b1, active_tx_count_av_next; reg inc_active_tx; +reg [PCIE_TAG_WIDTH+1-1:0] active_tag_count_reg = 0; +reg inc_active_tag; +reg dec_active_tag; + +reg [OP_TAG_WIDTH+1-1:0] active_op_count_reg = 0; +reg inc_active_op; +reg dec_active_op; + reg rx_cpl_tlp_ready_reg = 1'b0, rx_cpl_tlp_ready_next; reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr_reg = 0, tx_rd_req_tlp_hdr_next; @@ -413,6 +422,7 @@ reg [TAG_WIDTH-1:0] m_axis_read_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_ reg [3:0] m_axis_read_desc_status_error_reg = 4'd0, m_axis_read_desc_status_error_next; reg m_axis_read_desc_status_valid_reg = 1'b0, m_axis_read_desc_status_valid_next; +reg status_busy_reg = 1'b0; reg status_error_cor_reg = 1'b0, status_error_cor_next; reg status_error_uncor_reg = 1'b0, status_error_uncor_next; @@ -459,6 +469,7 @@ assign m_axis_read_desc_status_tag = m_axis_read_desc_status_tag_reg; assign m_axis_read_desc_status_error = m_axis_read_desc_status_error_reg; assign m_axis_read_desc_status_valid = m_axis_read_desc_status_valid_reg; +assign status_busy = status_busy_reg; assign status_error_cor = status_error_cor_reg; assign status_error_uncor = status_error_uncor_reg; @@ -609,6 +620,8 @@ always @* begin req_pcie_tag_valid_next = req_pcie_tag_valid_reg; inc_active_tx = 1'b0; + inc_active_tag = 1'b0; + inc_active_op = 1'b0; op_table_start_ptr = req_op_tag_reg; op_table_start_tag = s_axis_read_desc_tag; @@ -729,6 +742,7 @@ always @* begin op_table_start_ptr = req_op_tag_reg; op_table_start_tag = s_axis_read_desc_tag; op_table_start_en = 1'b1; + inc_active_op = 1'b1; stat_rd_op_start_tag_next = req_op_tag_reg; stat_rd_op_start_len_next = s_axis_read_desc_len; stat_rd_op_start_valid_next = 1'b1; @@ -757,6 +771,7 @@ always @* begin pcie_tag_table_start_op_tag_next = req_op_tag_reg; pcie_tag_table_start_zero_len_next = req_zero_len_reg; pcie_tag_table_start_en_next = 1'b1; + inc_active_tag = 1'b1; op_table_read_start_ptr = req_op_tag_reg; op_table_read_start_commit = req_last_tlp; @@ -852,6 +867,9 @@ always @* begin out_done_ack = {RAM_SEG_COUNT{1'b0}}; + dec_active_tag = 1'b0; + dec_active_op = 1'b0; + // Write generation ram_wr_cmd_sel_pipe_next = {RAM_SEG_COUNT{ram_sel_reg}}; if (!ram_wrap_reg) begin @@ -1196,6 +1214,7 @@ always @* begin end else if (finish_tag_reg) begin pcie_tag_table_finish_ptr = pcie_tag_reg; pcie_tag_table_finish_en = 1'b1; + dec_active_tag = 1'b1; pcie_tag_fifo_wr_tag = pcie_tag_reg; if (pcie_tag_fifo_wr_tag < PCIE_TAG_COUNT_1) begin @@ -1259,6 +1278,7 @@ always @* begin if (op_table_read_commit[op_table_read_finish_ptr] && (op_table_read_count_start[op_table_read_finish_ptr] == op_table_read_count_finish[op_table_read_finish_ptr])) begin op_tag_fifo_we = 1'b1; + dec_active_op = 1'b1; stat_rd_op_finish_valid_next = 1'b1; m_axis_read_desc_status_valid_next = 1'b1; end @@ -1357,6 +1377,7 @@ always @(posedge clk) begin m_axis_read_desc_status_error_reg <= m_axis_read_desc_status_error_next; m_axis_read_desc_status_valid_reg <= m_axis_read_desc_status_valid_next; + status_busy_reg <= active_op_count_reg != 0 || active_tx_count_reg != 0; status_error_cor_reg <= status_error_cor_next; status_error_uncor_reg <= status_error_uncor_next; @@ -1408,6 +1429,9 @@ always @(posedge clk) begin active_tx_count_reg <= active_tx_count_next; active_tx_count_av_reg <= active_tx_count_av_next; + active_tag_count_reg <= active_tag_count_reg + inc_active_tag - dec_active_tag; + active_op_count_reg <= active_op_count_reg + inc_active_op - dec_active_op; + pcie_tag_table_start_ptr_reg <= pcie_tag_table_start_ptr_next; pcie_tag_table_start_ram_sel_reg <= pcie_tag_table_start_ram_sel_next; pcie_tag_table_start_ram_addr_reg <= pcie_tag_table_start_ram_addr_next; @@ -1509,6 +1533,7 @@ always @(posedge clk) begin m_axis_read_desc_status_valid_reg <= 1'b0; + status_busy_reg <= 1'b0; status_error_cor_reg <= 1'b0; status_error_uncor_reg <= 1'b0; @@ -1530,6 +1555,9 @@ always @(posedge clk) begin active_tx_count_reg <= {TX_COUNT_WIDTH{1'b0}}; active_tx_count_av_reg <= 1'b1; + active_tag_count_reg <= 0; + active_op_count_reg <= 0; + pcie_tag_table_start_en_reg <= 1'b0; pcie_tag_fifo_1_wr_ptr_reg <= 0; diff --git a/rtl/dma_if_pcie_wr.v b/rtl/dma_if_pcie_wr.v index 6cd2cbbc2..3041c9807 100644 --- a/rtl/dma_if_pcie_wr.v +++ b/rtl/dma_if_pcie_wr.v @@ -136,6 +136,11 @@ module dma_if_pcie_wr # input wire [15:0] requester_id, input wire [2:0] max_payload_size, + /* + * Status + */ + output wire status_busy, + /* * Statistics */ @@ -327,6 +332,10 @@ reg [TX_COUNT_WIDTH-1:0] active_tx_count_reg = {TX_COUNT_WIDTH{1'b0}}, active_tx reg active_tx_count_av_reg = 1'b1, active_tx_count_av_next; reg inc_active_tx; +reg [OP_TAG_WIDTH+1-1:0] active_op_count_reg = 0; +reg inc_active_op; +reg dec_active_op; + reg [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data_reg = 0, tx_wr_req_tlp_data_next; reg [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb_reg = 0, tx_wr_req_tlp_strb_next; reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr_reg = 0, tx_wr_req_tlp_hdr_next; @@ -345,6 +354,8 @@ reg [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr_reg = 0, ram_rd_cmd_a reg [RAM_SEG_COUNT-1:0] ram_rd_cmd_valid_reg = 0, ram_rd_cmd_valid_next; reg [RAM_SEG_COUNT-1:0] ram_rd_resp_ready_cmb; +reg status_busy_reg = 1'b0; + reg [OP_TAG_WIDTH-1:0] stat_wr_op_start_tag_reg = 0, stat_wr_op_start_tag_next; reg [LEN_WIDTH-1:0] stat_wr_op_start_len_reg = 0, stat_wr_op_start_len_next; reg stat_wr_op_start_valid_reg = 1'b0, stat_wr_op_start_valid_next; @@ -378,6 +389,8 @@ assign ram_rd_cmd_addr = ram_rd_cmd_addr_reg; assign ram_rd_cmd_valid = ram_rd_cmd_valid_reg; assign ram_rd_resp_ready = ram_rd_resp_ready_cmb; +assign status_busy = status_busy_reg; + assign stat_wr_op_start_tag = stat_wr_op_start_tag_reg; assign stat_wr_op_start_len = stat_wr_op_start_len_reg; assign stat_wr_op_start_valid = stat_wr_op_start_valid_reg; @@ -501,6 +514,8 @@ always @* begin op_table_start_last = op_count_reg == tlp_count_reg; op_table_start_en = 1'b0; + inc_active_op = 1'b0; + // TLP segmentation case (req_state_reg) REQ_STATE_IDLE: begin @@ -587,6 +602,7 @@ always @* begin op_table_start_tag = tag_reg; op_table_start_en = 1'b1; + inc_active_op = 1'b1; stat_wr_req_start_tag_next = op_table_start_ptr_reg; stat_wr_req_start_len_next = zero_len_reg ? 0 : tlp_count_reg; @@ -814,6 +830,7 @@ always @* begin op_table_tx_finish_en = 1'b0; inc_active_tx = 1'b0; + dec_active_op = 1'b0; tx_wr_req_tlp_data_next = tx_wr_req_tlp_data_reg; tx_wr_req_tlp_strb_next = tx_wr_req_tlp_strb_reg; @@ -965,6 +982,7 @@ always @* begin if (op_table_active[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && (!TX_SEQ_NUM_ENABLE || op_table_tx_done[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) && op_table_finish_ptr_reg != op_table_tx_finish_ptr_reg) begin op_table_finish_en = 1'b1; + dec_active_op = 1'b1; stat_wr_req_finish_valid_next = 1'b1; @@ -1072,6 +1090,8 @@ always @(posedge clk) begin ram_rd_cmd_addr_reg <= ram_rd_cmd_addr_next; ram_rd_cmd_valid_reg <= ram_rd_cmd_valid_next; + status_busy_reg <= active_op_count_reg != 0 || active_tx_count_reg != 0; + stat_wr_op_start_tag_reg <= stat_wr_op_start_tag_next; stat_wr_op_start_len_reg <= stat_wr_op_start_len_next; stat_wr_op_start_valid_reg <= stat_wr_op_start_valid_next; @@ -1091,6 +1111,8 @@ always @(posedge clk) begin active_tx_count_reg <= active_tx_count_next; active_tx_count_av_reg <= active_tx_count_av_next; + active_op_count_reg <= active_op_count_reg + inc_active_op - dec_active_op; + if (mask_fifo_we) begin mask_fifo_mask[mask_fifo_wr_ptr_reg[MASK_FIFO_ADDR_WIDTH-1:0]] <= mask_fifo_wr_mask; mask_fifo_wr_ptr_reg <= mask_fifo_wr_ptr_reg + 1; @@ -1162,6 +1184,8 @@ always @(posedge clk) begin active_tx_count_reg <= {TX_COUNT_WIDTH{1'b0}}; active_tx_count_av_reg <= 1'b1; + active_op_count_reg <= 0; + mask_fifo_wr_ptr_reg <= 0; mask_fifo_rd_ptr_reg <= 0;