diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
index 2139dcb2a..8201ea135 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
@@ -726,10 +726,10 @@ always @(posedge clk_250mhz) begin
             RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40;       // SPI flash ctrl: Next header
             RBB+8'h2C: begin
                 // SPI flash ctrl: format
-                ctrl_reg_rd_data_reg[3:0]   <= FLASH_SEG_COUNT;     // configuration
-                ctrl_reg_rd_data_reg[7:4]   <= FLASH_SEG_DEFAULT;   // default segment
-                ctrl_reg_rd_data_reg[11:8]  <= FLASH_SEG_FALLBACK;  // fallback segment
-                ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE;     // first segment size
+                ctrl_reg_rd_data_reg[3:0]   <= FLASH_SEG_COUNT;        // configuration
+                ctrl_reg_rd_data_reg[7:4]   <= FLASH_SEG_DEFAULT;      // default segment
+                ctrl_reg_rd_data_reg[11:8]  <= FLASH_SEG_FALLBACK;     // fallback segment
+                ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE >> 12;  // first segment size
             end
             RBB+8'h30: begin
                 // SPI flash ctrl: control 0
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
index c11bdf06b..97dc7ee34 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
@@ -727,10 +727,10 @@ always @(posedge clk_250mhz) begin
             RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40;       // SPI flash ctrl: Next header
             RBB+8'h2C: begin
                 // SPI flash ctrl: format
-                ctrl_reg_rd_data_reg[3:0]   <= FLASH_SEG_COUNT;     // configuration
-                ctrl_reg_rd_data_reg[7:4]   <= FLASH_SEG_DEFAULT;   // default segment
-                ctrl_reg_rd_data_reg[11:8]  <= FLASH_SEG_FALLBACK;  // fallback segment
-                ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE;     // first segment size
+                ctrl_reg_rd_data_reg[3:0]   <= FLASH_SEG_COUNT;        // configuration
+                ctrl_reg_rd_data_reg[7:4]   <= FLASH_SEG_DEFAULT;      // default segment
+                ctrl_reg_rd_data_reg[11:8]  <= FLASH_SEG_FALLBACK;     // fallback segment
+                ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE >> 12;  // first segment size
             end
             RBB+8'h30: begin
                 // SPI flash ctrl: control 0